24th week of 2020 patent applcation highlights part 69 |
Patent application number | Title | Published |
20200185278 | Selective NFET/PFET Recess of Source/Drain Regions - A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively. | 2020-06-11 |
20200185279 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers. | 2020-06-11 |
20200185280 | SEMICONDUCTOR DEVICE - A semiconductor device includes first active patterns and second active patterns on a substrate, a first source/drain region on the first active patterns, a second source/drain region on the second active patterns and a device isolation layer filling a first trench between adjacent ones of the first active patterns and a second trench between adjacent ones of the second active patterns. A liner layer is disposed on the device isolation layer between the adjacent ones of the second active patterns. The device isolation layer between the adjacent ones of the first active patterns has a recess therein under the first source/drain region and a bottom surface of the liner layer between the adjacent ones of the second active patterns is higher than the recess. | 2020-06-11 |
20200185281 | METHOD AND APPARATUS TO DETERMINE A PATTERNING PROCESS PARAMETER - A method of configuring a parameter determination process, the method including: obtaining a mathematical model of a structure, the mathematical model configured to predict an optical response when illuminating the structure with a radiation beam and the structure having geometric symmetry at a nominal physical configuration; using, by a hardware computer system, the mathematical model to simulate a perturbation in the physical configuration of the structure of a certain amount to determine a corresponding change of the optical response in each of a plurality of pixels to obtain a plurality of pixel sensitivities; and based on the pixel sensitivities, determining a plurality of weights for combination with measured pixel optical characteristic values of the structure on a substrate to yield a value of a parameter associated with change in the physical configuration, each weight corresponding to a pixel. | 2020-06-11 |
20200185282 | MANUFACTURING FLUID SENSING PACKAGES - In examples, a method of manufacturing a fluid sensing package comprises coupling a semiconductor die to a first set of conductive terminals; positioning the semiconductor die within a socket, a fluid probe extending through a probe orifice in a lid of the socket; positioning a ring of the fluid probe on a fluid sensing portion of the semiconductor die by closing the lid of the socket; and using the fluid probe to apply fluid to an area of the fluid sensing portion circumscribed by the ring. | 2020-06-11 |
20200185283 | LIGHT EMITTING DIODE (LED) TEST APPARATUS AND METHOD OF MANUFACTURE - Embodiments relate to functional test methods useful for fabricating products containing Light Emitting Diode (LED) structures. In particular, LED arrays are functionally tested by injecting current via a displacement current coupling device using a field plate comprising of an electrode and insulator placed in close proximity to the LED array. A controlled voltage waveform is then applied to the field plate electrode to excite the LED devices in parallel for high-throughput. A camera records the individual light emission resulting from the electrical excitation to yield a function test of a plurality of LED devices. Changing the voltage conditions can excite the LEDs at differing current density levels to functionally measure external quantum efficiency and other important device functional parameters. | 2020-06-11 |
20200185284 | BOTTOM EMISSION MICROLED DISPLAY AND A REPAIR METHOD THEREOF - A bottom emission microLED display includes a microLED disposed above a transparent substrate; a light guiding layer surrounding the microLED to controllably guide light generated by the microLED towards the transparent substrate; and a reflecting layer formed over the light guiding layer to reflect the light generated by the microLED downwards and to confine the light generated by the microLED to prevent the light from leaking upwards or sidewards. | 2020-06-11 |
20200185286 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package device includes a substrate, an electronic component, a ring frame, an encapsulant, a thermal conducting material and a lid. The electronic component is disposed on the substrate. The ring frame is disposed on the substrate and surrounds the electronic component. The encapsulant encapsulates the electronic component and a first portion of the ring frame. The encapsulant exposes a second portion of the ring frame. The encapsulant and the second portion of the ring frame define a space. The thermal conducting material is disposed in the space. The lid is disposed on the thermal conducting material and connects with the second portion of the ring frame. | 2020-06-11 |
20200185287 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes a case enclosing a region where a semiconductor element as a component of an electric circuit exists. A resin part is fixed to an inside of the case in contact with the region. The resin part is provided with a conductive film, which is a part of the electric circuit. The conductive film is provided in the resin part so that the conductive film comes into contact with the region. | 2020-06-11 |
20200185288 | ELECTRONIC DEVICE COMPRISING A SUPPORT SUBSTRATE AND AN ENCAPSULATING COVER FOR AN ELECTRONIC COMPONENT - A support substrate has a face above which at least one electronic component is fixed. A peripheral area of the face includes an annular local metal layer. An encapsulating cover for the electronic component includes a peripheral wall having an end edge that is mounted above the peripheral area. The annular metal local layer includes, at the periphery thereof, a series of spaced-apart teeth with notches formed therebetween. The teeth extend as far as the peripheral edge of the support substrate. | 2020-06-11 |
20200185289 | STACKED DIE CAVITY PACKAGE - An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed. | 2020-06-11 |
20200185290 | SEMICONDUCTOR PACKAGE HAVING SEALANT BRIDGE - Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package. | 2020-06-11 |
20200185291 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, a substrate having a main surface on which the semiconductor chip is arranged, a resin case which has a storage space therein and a side wall, the side wall having an injection path extending from the storage space to a device exterior, the resin case having a first opening at a bottom side thereof, connecting the storage space to the device exterior, the substrate being disposed on the resin case, at a main surface side of the substrate facing at the bottom side of the resin case, and a sealing material filling the storage space and the injection path. | 2020-06-11 |
20200185292 | INTEGRATED CIRCUIT SUBSTRATE FOR CONTAINING LIQUID ADHESIVE BLEED-OUT - Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer. | 2020-06-11 |
20200185293 | Semiconductor Package Having a Laser-Activatable Mold Compound - Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound. | 2020-06-11 |
20200185294 | SEMICONDUCTOR CHIP PACKAGE WITH SPRING BIASED LID - Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a package substrate that has a first edge and a second edge opposite to the first edge. A semiconductor chip is mounted on the package substrate. A thermal interface material is positioned on the semiconductor chip. A lid is positioned over the thermal interface material. A spring biasing mechanism is included that is operable to bias the lid away from the package substrate so that the lid, when subjected to a compressive force, can translate toward the package substrate and impart a compressive force on the thermal interface material. | 2020-06-11 |
20200185295 | SEMICONDUCTOR DEVICE AND POWER CONVERSION APPARATUS - An upper conductor portion having a thickness A larger than a thickness B of a lower conductor portion, the upper conductor portion including a circuit pattern on which semiconductor chips are disposed and an outer peripheral pattern provided on an outer peripheral side of the circuit pattern at a certain gap, the outer peripheral pattern of the upper conductor portion, an outer peripheral portion of an insulating layer, and an outer peripheral portion of the lower conductor portion are fixed to a concave portion formed in the inner peripheral portion of the peripheral wall portion of a case, a collar portion projecting outward from the outer peripheral portion of the peripheral wall portion of the case is formed, and the attachment holes, through which the radiation fins are attachable, are formed in the collar portion. | 2020-06-11 |
20200185296 | SEMICONDUCTOR PACKAGE INCLUDING ORGANIC INTERPOSER - A semiconductor package including an organic interposer includes: the organic interposer including insulating layers and wiring layers formed on the insulating layers; a stiffener disposed on the interposer and having a through-hole; a first semiconductor chip disposed in the organic through-hole on the organic interposer; a second semiconductor chips disposed adjacent to the first semiconductor chip in the through-hole on the organic interposer; and an underfill resin filling at least portions of the through-hole and fixing the first semiconductor chip and the second semiconductor chip, wherein the connection pads of the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the wiring layers of the organic interposer. | 2020-06-11 |
20200185297 | SEMICONDUCTOR DEVICE INCLUDING A PASSIVATION STRUCTURE AND MANUFACTURING METHOD - An embodiment of a semiconductor device includes a semiconductor body having a first main surface. The semiconductor body includes an active device area and an edge termination area at least partly surrounding the active device area. The semiconductor device further includes a contact electrode on the first main surface and electrically connected to the active device area. The semiconductor device further includes a passivation structure on the edge termination area and laterally extending into the active device area. The semiconductor device further includes an encapsulation structure on the passivation structure and covering a first edge of the passivation structure above the contact electrode. | 2020-06-11 |
20200185298 | SEMICONDUCTOR PACKAGES INCLUDING A HEAT INSULATION WALL - A semiconductor package includes a first semiconductor chip and a second semiconductor chip which are disposed side-by-side on a surface of a package substrate. A heat insulation wall is disposed between the first semiconductor chip and the second semiconductor chip. The heat insulation wall thermally isolates the first semiconductor chip from the second semiconductor chip. | 2020-06-11 |
20200185299 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - Various embodiments may provide a semiconductor package. The semiconductor package may include a semiconductor chip, a first mold compound layer at least partially covering the semiconductor chip, and a redistribution layer over the first mold compound layer, the redistribution layer including one or more electrically conductive lines in electrical connection with the semiconductor chip. The semiconductor package may additionally include a second mold compound layer over the redistribution layer, and an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines. | 2020-06-11 |
20200185300 | EFFECTIVE HEAT CONDUCTION FROM HOTSPOT TO HEAT SPREADER THROUGH PACKAGE SUBSTRATE - An integrated circuit (IC) package comprises a substrate comprising a dielectric and a thermal conduit that is embedded within the dielectric. The thermal conduit has a length that extends laterally within the dielectric from a first end to a second end. An IC die is thermally coupled to the first end of the thermal conduit. The IC die comprises an interconnect that is coupled to the first end of the thermal conduit. An integrated heat spreader comprises a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate that is thermally coupled to the second end of the thermal conduit. | 2020-06-11 |
20200185301 | Semiconductor Package, Metal Sheet for Use in a Semiconductor Package, and Method for Producing a Semiconductor Package - A semiconductor package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and a metal sheet having a first sheet surface and an opposite second sheet surface. The first sheet surface is exposed at the encapsulation body. The semiconductor chip is arranged at the second sheet surface. The first sheet surface has a pattern having first subdivisions having a first average roughness and second subdivisions having a second average roughness. The first average roughness is greater than the second average roughness. | 2020-06-11 |
20200185302 | POWER MODULES FOR ULTRA-FAST WIDE-BANDGAP POWER SWITCHING DEVICES - Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch. | 2020-06-11 |
20200185303 | IGBT MODULE WITH IMPROVED HEAT DISSIPATION STRUCTURE - An IGBT module with an improved heat dissipation structure includes a layer of IGBT chips, a bonding layer, a thick copper layer, a polymer composite layer, a thermal spray layer, and a heat dissipation layer. The thermal spray layer is disposed on the heat dissipation layer. The polymer composite layer is disposed on the thermal spray layer. The thick copper layer is disposed on the polymer composite layer. The bonding layer is disposed on the thick copper layer. The layer of IGBT chips is disposed on the bonding layer. | 2020-06-11 |
20200185304 | INTEGRATED CIRCUIT PACKAGE AND METHOD - In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure. | 2020-06-11 |
20200185305 | INTEGRATED CIRCUIT DIRECT COOLING SYSTEMS AND RELATED METHODS - Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough. | 2020-06-11 |
20200185306 | LIQUID COOLING SYSTEM - A liquid cooling system includes a heat dissipating device with cooling pipes and a radiation structure arranged on the cooling pipes; a pump device, integrally arranged between the cooling pipes and generating power so that a coolant circulates within the cooling pipes; a heat absorbing device, attached to a heating device and having a heat conduction effect with the heating device; and a combination means for connecting a connecting unit to the pump device. On the basis of existing products, a liquid pump main body and a radiator are integrally arranged together, and the heat absorbing device is connected to the liquid pump main body via the combination means. In addition, the leakage at the tube connector and the occupied space is significantly reduced, the heat transfer effect is significantly improved, and the production and assembly costs are reduced, so that product assembly is convenient and efficiency is high. | 2020-06-11 |
20200185307 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a first semiconductor layer, a second semiconductor layer, and a first, a second and a third bonding conductors. The first semiconductor layer includes a first top surface. The second semiconductor layer is disposed over the first semiconductor layer, and the second semiconductor layer includes a second top surface. The first bonding conductor is disposed over the first top surface. The second bonding conductor is disposed over the second top surface. The third bonding conductor is in contact with the first bonding conductor and the second bonding conductor, the first bonding conductor is different from the second bonding conductor, and the third bonding conductor includes a silicide material formed from the first bonding conductor and the second bonding conductor. | 2020-06-11 |
20200185308 | Leadframe With Vertically Spaced Die Attach Pads - A leadframe includes a first die attach pad (“DAP”) having a first longitudinally extending edge surface and a second DAP having a first longitudinally extending edge surface. The second DAP is positioned with the first longitudinally extending edge surface thereof in adjacent, laterally and vertically spaced relationship with the first longitudinally extending edge surface of the first DAP. | 2020-06-11 |
20200185309 | DIE ATTACH SURFACE COPPER LAYER WITH PROTECTIVE LAYER FOR MICROELECTRONIC DEVICES - A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed. | 2020-06-11 |
20200185310 | DUAL SIDE COOLING POWER MODULE AND MANUFACTURING METHOD OF THE SAME - A dual side cooling power module includes: a lower substrate including a recessed portion on at least one surface thereof, a semiconductor chip formed in the recessed portion, lead frames formed at both ends of the lower substrate, and an upper substrate formed on the semiconductor chip, a portion of the lead frames, and the lower substrate. | 2020-06-11 |
20200185311 | CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING CHIP PACKAGE - The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant surrounding the chip to have an increased area. A redistribution layer is formed on the package unit to draw out to and redistribute input/output terminals on a surface of the chip. The redistribution layer is then electrically coupled to a leadframe or a printed circuit board by external and electrical connectors. The method and the package structure are suitable for providing a chip package having input/output terminals with high density, reducing package cost, and improving package reliability. | 2020-06-11 |
20200185312 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a plurality of solders, and a semiconductor chip. The plurality of solders are located adjacent to each other. At least one of composition and concentration of the plurality of solders is different from each other. The semiconductor chip includes a joining surface to be joined to the substrate with the plurality of solders. The joining surface of the semiconductor chip includes a plurality of joining areas in which heat generation of the semiconductor chip or a stress on an object to be joined is different from each other. The plurality of solders are disposed to correspond to the plurality of joining areas, respectively. | 2020-06-11 |
20200185313 | INTEGRATED CIRCUIT PACKAGE ELEMENT AND LOAD BOARD THEREOF - An integrated circuit package element provided includes a chip element and a package module coupled to the chip element. The chip element includes two driving units that are electrically connected to each other. The package module includes a grounding area, two individual power distributed networks and a grounded shielding structure which is completely disposed between the individual power distributed networks, electrically connected to the chip element, and configured to block power noise coupling between the first electric power distribution network and the second electric power distribution network. The grounding area is electrically connected to the individual electric power distribution networks and the grounded shielding structure. | 2020-06-11 |
20200185314 | CONNECTION STRUCTURE AND METHOD OF FORMING THE SAME - Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern. | 2020-06-11 |
20200185315 | SEMICONDUCTOR MODULE - A semiconductor module includes: an insulating substrate; a metal pattern provided on the insulating substrate; a solder resist provided on the metal pattern; a semiconductor chip mounted on the metal pattern at an opening portion of the solder resist; and a sealing material sealing the metal pattern, the solder resist and the semiconductor chip, wherein a suction area surrounded by a groove is provided in a portion of the solder resist. | 2020-06-11 |
20200185316 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes a mounting substrate; a first wiring electrode and a second wiring electrode disposed on a main surface of a mounting substrate; an interposing member disposed between the first wiring electrode and the second wiring electrode; a semiconductor element flip-chip connected with the first wiring electrode and the second wiring electrode via a first electrical connection member and a second electrical connection member so as to at least partially overlap the interposing member in a top surface view; and a resin disposed in contact with the semiconductor element and the mounting substrate. The wettability of the interposing member to the resin is higher than that of the mounting substrate to the resin. The resin is disposed in contact with the semiconductor element and the interposing member. | 2020-06-11 |
20200185317 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant. | 2020-06-11 |
20200185318 | Semiconductor Device With Electroplated Die Attach - A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation. | 2020-06-11 |
20200185319 | HYBRID PACKAGE - A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins. | 2020-06-11 |
20200185320 | CERAMIC CIRCUIT SUBSTRATE - A ceramic circuit substrate is suitable for silver nanoparticle bonding of semiconductor elements and has excellent close adhesiveness with a power module sealing resin. A ceramic circuit substrate has a copper plate bonded, by a braze material, to both main surfaces of a ceramic substrate including aluminum nitride or silicon nitride, the copper plate of at least one of the main surfaces being subjected to silver plating, wherein: the copper plate side surfaces are not subjected to silver plating; the thickness of the silver plating is 0.1 μm to 1.5 μm; and the arithmetic mean roughness Ra of the surface roughness of the circuit substrate after silver plating is 0.1 μm to 1.5 μm. | 2020-06-11 |
20200185321 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a core layer formed of a ferromagnetic material, and includes a frame passing through the core layer and having a through-hole, a semiconductor chip disposed in the through-hole of the frame, and having an active surface on which a connection pad is disposed, and an inactive surface opposite to the active surface, an encapsulant covering at least a portion of the semiconductor chip, and a first connection structure including a first redistribution layer disposed on the active surface of the semiconductor chip and electrically connected to the connection pad. | 2020-06-11 |
20200185322 | SEMICONDUCTOR DEVICE CONNECTIONS WITH SINTERED NANOPARTICLES - In a described example, a packaged device includes a substrate having a device mounting surface with conductive lands having a first thickness spaced from one another on the device mounting surface. A first polymer layer is disposed on the device mounting surface between the conductive lands having a second thickness equal to the first thickness. The conductive lands have an outer surface not covered by the first polymer layer. A second polymer layer is disposed on the first polymer layer, the outer surface of the conductive lands not covered by the second polymer layer. Conductive nanoparticle material is disposed on the outer surface of the conductive lands. A third polymer layer is disposed on the second polymer layer between the conductive nanoparticle material on the conductive lands. At least one semiconductor device die is mounted to the third polymer layer having electrical terminals bonded to the conductive nanoparticle material. | 2020-06-11 |
20200185323 | PACKAGED SEMICONDUCTOR SYSTEM HAVING UNIDIRECTIONAL CONNECTIONS TO DISCRETE COMPONENTS - A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond wires; at least one discrete component adjacent to the at least one electronic device, a second electrode of the at least one discrete component parallel to and spaced from a first electrode by a component body; the first electrode a metal foil having a protrusion extending laterally from the body and having a surface facing towards the second electrode; bonding wires interconnecting respective terminals of the at least one electronic device, the first electrode and the second electrode, and bonded to the surface of the second electrode and to the protrusion that extend away from the respective surfaces in a same direction; and packaging compound covering portions of the at least one electronic device, the at least one discrete component, and the bonding wires. | 2020-06-11 |
20200185324 | SYSTEM FOR LAYOUT DESIGN OF STRUCTURE WITH INTER-LAYER VIAS - A system (including a processor and memory with computer program code) that is configured to execute a method which includes generating the layout diagram including: selecting a circuit cell which includes an active element; bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit; placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram; and placing a metal pattern in a second device layer of the layout diagram; and wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern. | 2020-06-11 |
20200185325 | SEMICONDUCTOR DEVICE AND METHOD TO FABRICATE THE SEMICONDUCTOR DEVICE - A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements. | 2020-06-11 |
20200185326 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a first substrate; a semiconductor chip mounted on the first substrate such that a circuit formation surface is oriented toward the first substrate; a second substrate arranged above the first substrate, the semiconductor chip being sandwiched between the first substrate and the second substrate; and a resin that seals the semiconductor chip and that is filled between the first substrate and the second substrate, wherein the second substrate includes a solder resist layer having a first surface facing a back surface that is an opposite surface of the circuit formation surface of the semiconductor chip, and wherein on an area of the first surface of the solder resist layer facing the back surface of the semiconductor chip, at least one protruding portion that protrudes towards the back surface of the semiconductor chip is provided. | 2020-06-11 |
20200185327 | SENSOR - A sensor is provided, including a substrate, a chip and a sensing element. The substrate has a plate-like shape and includes a surface and an interconnect structure disposed in the substrate. The chip is embedded in the substrate and is electrically connected to the interconnect structure. The sensing element is disposed on the surface of the substrate, and is electrically connected to the chip through the interconnect structure. | 2020-06-11 |
20200185328 | SEMICONDUCTOR DEVICE AND DATA TRANSFERRING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes a first chip, a second chip, a third chip, a fourth chip, and a substrate. The first to fourth chips are mounted on the substrate. The first chip is placed adjacent to the second chip and the fourth chip. The third chip is placed adjacent to the second chip and the fourth chip at a position different from that of the first chip. The second chip has a first transferring circuit that transfers data from the first chip to the third chip, and the fourth chip has a second transferring circuit that transfers data from the third chip to the first chip. | 2020-06-11 |
20200185329 | HETEROGENEOUS INTEGRATED CIRCUIT FOR SHORT WAVELENGTHS - A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm. | 2020-06-11 |
20200185330 | SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME - A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies. | 2020-06-11 |
20200185331 | ELECTRONIC SYSTEM COMPRISING A LOWER REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING SUCH AN ELECTRONIC SYSTEM - The invention relates to a method for producing an electronic system, comprising: a step of forming a plurality of interconnect paths obtained via metal deposition on the sacrificial member to form a lower redistribution layer defining a plurality of lower connection ports connected to a plurality of inner connection ports; a step of depositing at least one electronic component on the lower redistribution layer; and a step of forming a plurality of three-dimensional interconnect paths obtained via metal deposition in order to connect the connectors of the electronic component to the inner connection ports of the lower redistribution layer. | 2020-06-11 |
20200185332 | CIRCUIT BOARD - A circuit board includes a core layer including a plurality of metal layers laminated one over another, a bottommost metal layer of the plurality of metal layers being thickest, and a topmost metal layer of the plurality of metal layer being thinnest; an upper insulating layer and an upper conductive pattern provided over a top surface of the core layer; and a lower insulating layer and a lower conductive pattern provided below a bottom surface of the core layer, wherein the topmost metal layer of the core metal layer is patterned to have a prescribed shaped section that serves as wiring and that is connected to the upper conductive pattern, wherein a metal ratio that is defined as a ratio of an area that is formed of metal relative to an entire area in a plan view is higher in the bottommost metal layer than in the topmost metal layer. | 2020-06-11 |
20200185333 | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SAME - A semiconductor module includes a base material, an alignment mark provided on a surface of the base material and plural semiconductor elements that are individually provided on the surface of the base material while being juxtaposed to the alignment mark and that are separated from each other. Accordingly, a semiconductor module and a method for manufacturing the semiconductor module are provided which may prevent an alignment mark from being peeled off and remaining as a foreign object and may improve reliability. | 2020-06-11 |
20200185334 | THINNED SEMICONDUCTOR WAFER - A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer. | 2020-06-11 |
20200185335 | Method of Manufacturing a Semiconductor Device with Epitaxial Layers and an Alignment Mark - A semiconductor wafer includes an alignment mark contained within in a kerf region of the semiconductor wafer. The alignment mark includes a groove vertically extending from a main surface of the semiconductor wafer to a bottom surface of the groove, and at least one tin protruding from the bottom surface of the groove. The groove has a rectangular shape with four sidewalls and four inside corners, with each of the four inside corners facing the at least one fin. A minimum distance between the at least one fin and a nearest one of the four inside corners is at least 25 μm. | 2020-06-11 |
20200185336 | INTEGRATED CIRCUIT WITH INDUCTORS HAVING ELECTRICALLY SPLIT SCRIBE SEAL - An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having ≥1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing ≥2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion. | 2020-06-11 |
20200185337 | Buffer Defense Band (BDB) Outside the Seal Ring to Enhance Crack Stopping in IC's - A plurality of prime dies are fabricated on a wafer. A plurality of frame structures are fabricated in vertical scribe lines separating the prime dies from one another. A plurality of test structures are fabricated in horizontal scribe lines separating the prime dies from one another. A seal ring is fabricated surrounding each of the prime dies. A buffer defense band is provided on the outside of each seal ring and extending from the seal ring to all borders of each of the prime dies. The prime dies are diced on the vertical scribe lines and on the horizontal scribe lines wherein the buffer defense band improves the robustness of the IC packaging window to prevent any cracks, chipping, or delaminating originating from any horizontal or vertical scribe lines from propagating into any of the prime dies. | 2020-06-11 |
20200185338 | SEMICONDUCTOR PACKAGE STRUCTURE FOR IMPROVING DIE WARPAGE AND MANUFACTURING METHOD THEREOF - A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film. | 2020-06-11 |
20200185339 | INTEGRATED CIRCUIT, METHOD AND COMPUTER PROGRAM - An integrated circuit is disclosed. The integrated circuit comprises: a processing region configured to run one instruction from a plurality of instructions; a first temperature measuring region configured to measure a first temperature within the integrated circuit in response to the processing region running the one instruction; the processing region being configured to compare the measured first temperature with a predefined temperature at the first temperature measuring region when the processing region runs the one instruction and to trigger an event when the measured first temperature exceeds the predefined temperature by a threshold value. | 2020-06-11 |
20200185340 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present embedment includes a substrate having a first region provided with a semiconductor element and a second region provided from the first region to an end. A material film is provided above the first and second regions. A first metal film is provided on the material film in the second region or on the material film between the first region and the second region. A trench, which caves in toward the substrate from a surface of the material film in the first region and from a surface of the material film under the first metal film, is provided in the material film between the first metal film and the first region. | 2020-06-11 |
20200185341 | PACKAGE STRUCTURE - The present disclosure relates to a package structure. The package structure includes a semiconductor device, a first molding compound, a through-via, first and second dielectric layers, and a second molding compound in contact with a sidewall of the first dielectric layer. The first molding compound is in contact with a sidewall of the semiconductor device. The through-via is formed in the first molding compound and electrically connected to the semiconductor device. The first and second dielectric layers are formed at upper and lower sides of the semiconductor device. The at least one redistribution line is formed in the first dielectric layer and electrically connected to the semiconductor device and the through-via. The second molding compound is in contact with a sidewall of the first dielectric layer. The at least one redistribution line comprises an ESD-protection feature or is a MIM (metal-insulator-metal) feature. | 2020-06-11 |
20200185342 | PACKAGE ON ANTENNA PACKAGE - Wireless modules having a semiconductor package attached to an antenna package is disclosed. The semiconductor package may house one or more electronic components as a single die package and/or a system in a package (SiP) implementation. The antenna package may be communicatively coupled to the semiconductor package using by one or more coupling pads. The antenna package may further have one or more radiating elements for transmitting and or receiving wireless signals. The antenna package and the semiconductor package may have dissimilar number of interconnect layers and/or dissimilar materials of construct. | 2020-06-11 |
20200185343 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion. | 2020-06-11 |
20200185344 | CHIP PACKAGE STRUCTURE - A chip package structure includes a redistribution circuit layer, at least one chip and an encapsulation material. The redistribution circuit layer includes at least one transistor. The chip is arranged on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The encapsulation material is arranged on the redistribution circuit layer and covers the at least one chip. When the chip package structure includes one or more chips, a position of the chip is taken as a reference for arrangement of a position of the at least one transistor. | 2020-06-11 |
20200185345 | SEMICONDUCTOR DEVICE - The present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor substrate, a conductive through electrode, an insulating film, a bump and a connection layer, wherein the connection layer comprises a patternable material with conductive particles. The conductive through electrode penetrates through the semiconductor substrate. The patternable material comprises photosensitive material. The photosensitive material is a photoresist or polyimide. The conductive particles comprise copper (Cu), nickel (Ni), gold (Au), or silver (Ag). The connection layer is formed by spin coating, CVD (chemical vapor deposition) process or PVD (physical vapor deposition) process. The insulating film surrounds the conductive through electrode and electrically isolates the conductive through electrode from the is substrate. The bump is disposed over the conductive through electrode. The connection layer is disposed over the bump. | 2020-06-11 |
20200185346 | INTEGRATED DEVICE PACKAGES WITH PASSIVE DEVICE ASSEMBLIES - An integrated device package is disclosed. The package can include a package substrate and an integrated device die having active electronic circuitry. The integrated device die can have a first side and a second side opposite the first side. The first side can have bond pads electrically connected to the package substrate by way of bonding wires. A redistribution layer (RDL) stack can be disposed on a the first side of the integrated device die. The RDL stack can comprise an insulating layer and a conductive redistribution layer. The package can include a passive electronic device assembly mounted and electrically connected to the RDL stack. | 2020-06-11 |
20200185347 | MOUNTING STRUCTURE AND NANOPARTICLE MOUNTING MATERIAL - A mounting structure is used, which includes: a semiconductor element including an element electrode; a metal member; and a sintered body configured to bond the semiconductor element and the metal member is used, in which the sintered body contains a first metal and a second metal solid-dissolved in the first metal, the second metal is a metal having a diffusion coefficient in the first metal larger than a self-diffusion coefficient of the first metal, and a content ratio of the second metal relative to a total mass of the first metal and the second metal in the sintered body is equal to or lower than a solid solution limit of the second metal to the first metal. | 2020-06-11 |
20200185348 | SEMICONDUCTOR DEVICE - A semiconductor device may be provided with a first member, a second member joined to a first region of the first member via a first solder layer and a third member joined to a second region of the first member via a second solder layer. The first region and the second region are located on one side of the first member. The first solder layer contains a plurality of support particles that is constituted of a material having a higher melting point than the first solder layer. The second solder layer does not contain any support particles. | 2020-06-11 |
20200185349 | ULTRA-THIN EMBEDDED SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THEREOF - A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit. | 2020-06-11 |
20200185350 | IMAGE CAPTURING MODULE AND PORTABLE ELECTRONIC DEVICE - The present invention provides an image capturing module and a portable electronic device. An image capturing module includes a circuit substrate, an image sensing chip, a filter element, and a lens assembly. The circuit substrate has an upper surface, a lower surface, and a through opening. The image sensing chip is placed on the lower surface of the circuit substrate and below the through opening. The filter element is placed on the upper surface of the circuit substrate and above the through opening. The lens assembly includes a holding structure and a lens structure. The lower surface of the circuit substrate includes a first solder area, a second solder area, and a first solderless area. The upper surface of the image sensing chip includes an image sensing area, a first conductive area, a second conductive area, and a first non-conductive area. | 2020-06-11 |
20200185351 | SEMICONDUCTOR STRUCTURE AND METHOD FOR OBTAINING LIGHT EMITTING DIODES RECONSTITUTED OVER A CARRIER SUBSTRATE - A method is provided for obtaining one or more Light Emitting Diode (LED) devices reconstituted over a carrier substrate. The method includes providing a silicon-based semiconductor substrate as the carrier substrate; providing, per each of the one or more LED devices, a compound semiconductor stack including an LED layer; applying a SiCN layer to the stack and the substrate, respectively; bonding the stack to the substrate, wherein the SiCN layer applied to the stack and the SiCN layer applied to the substrate are contacted; and annealing, after bonding, the bonded stack and substrate at a temperature equal to or higher than a processing temperature for completing the LED device from the stack, wherein said temperatures are at least 400° C. A semiconductor structure including the one or more LED devices reconstituted over a carrier substrate is also provided. | 2020-06-11 |
20200185352 | SEMICONDUCTOR DEVICES HAVING A CONDUCTIVE PILLAR AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via. | 2020-06-11 |
20200185353 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - The reliability of semiconductor device is improved. The method of manufacturing a semiconductor device has a step of performing plasma treatment prior to the wire bonding step, and the surface roughness of the pads after the plasma treatment step is equal to or less than 3.3 nm. | 2020-06-11 |
20200185354 | MANUFACTURING METHOD FOR ELECTRONIC COMPONENT, AND ELECTRONIC COMPONENT - A manufacturing method for an electronic component includes forming an electrically conductive pillar on a surface of a support, forming an intermediate layer covering a side surface of the pillar, forming a conductor layer covering a side surface of the intermediate layer, and molding a resin structure covering a side surface of the conductor layer. | 2020-06-11 |
20200185355 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a method of manufacturing a semiconductor device. For example, various aspects of this disclosure provide a semiconductor device having an ultra-thin substrate, and a method of manufacturing a semiconductor device having an ultra-thin substrate. As a non-limiting example, a substrate structure comprising a carrier, an adhesive layer formed on the carrier, and an ultra-thin substrate formed on the adhesive layer may be received and/or formed, components may then be mounted to the ultra-thin substrate and encapsulated, and the carrier and adhesive layer may then be removed. | 2020-06-11 |
20200185356 | SEMICONDUCTOR SENSOR PACKAGE - A package packaged with a cap. The package features trenches, through holes, and a non-conductive coupling element forming a locking mechanism integrated embedded or integrated within a substrate. The package has a cap coupled to the non-conductive coupling element through ultrasonic plastic welding. The package protects the dice from an outside environment or external stresses or both. A method is desired to form package to reduce glue overflow defects in the package. Fabrication of the package comprises drilling holes in a substrate; forming trenches in the substrate; forming a non-conductive coupling element in the through holes and the trenches to form a locking mechanism; allowing the non-conductive coupling element to harden and cure; coupling a die or dice to the substrate; and coupling a cap to the non-conductive coupling element to protect the die or dice from an outside environment or external stresses or both. | 2020-06-11 |
20200185357 | INTERPOSER AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor package includes an interposer having multiple connection structures, each including redistribution layers electrically connected to each other, and a passivation layer covering at least a portion of each of the connection structures and filling a space between the connection structures. A first semiconductor chip is disposed on the interposer and has first connection pads, and a second semiconductor chip is disposed adjacent to the first semiconductor chip on the interposer and has second connection pads. The connection structures are independently arranged to each at least partially overlap with one or both of the first and second semiconductor chips, in a stacking direction of the first and second semiconductor chips on the interposer. The redistribution layers of each of the connection structures are electrically connected to at least one of the first and second connection pads via under bump metals. | 2020-06-11 |
20200185358 | SEMICONDUCTOR POWER MODULE - A semiconductor power module including an insulating substrate having one surface and another surface, an output side terminal arranged at a one surface side of the insulating substrate, a first power supply terminal arranged at the one surface side of the insulating substrate, a second power supply terminal to which a voltage of a magnitude different from a voltage applied to the first power supply terminal is to be applied, and arranged at another surface side of the insulating substrate so as to face the first power supply terminal across the insulating substrate, a first switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the first power supply terminal, and a second switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the second power supply terminal. | 2020-06-11 |
20200185359 | SEMICONDUCTOR MODULE AND POWER CONVERSION DEVICE - Gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern by gate wires. Sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern by source wires. The gate control pattern is disposed to interpose the source control pattern between the gate control pattern and each of the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. Hence, each of the gate wires becomes longer than each of the source wires, and has an inductance larger than the source wire. Accordingly, gate oscillation is reduced or suppressed in the plurality of semiconductor switching elements that are connected in parallel and that operate in parallel. | 2020-06-11 |
20200185360 | MICRO LED DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A micro LED display device including a display substrate, a plurality of conductive pad pairs and a plurality of micro light emitting elements is provided. The display substrate has a first arranging area, a splicing area connected to the first arranging area, and a second arranging area connected to the splicing area, wherein the splicing area is located between the first arranging area and the second arranging area. The conductive pad pairs are disposed on the display substrate in an array with the same pitch. The micro light emitting elements are disposed on the display substrate and are electrically bonded to the conductive pad pairs. A manufacturing method of the micro LED display device is also provided. | 2020-06-11 |
20200185361 | LED DISPLAY MODULE - An LED display module is disclosed. The LED display module includes: a micro-LED array including a plurality of pixel units arrayed in a matrix with rows and columns, each of the pixel units including a red LED, a green LED, and a blue LED; a substrate including a top layer on which the pixel units are mounted, a first layer located under the top layer, and a second layer located under the first layer; and pairs of electrode pads disposed on the substrate and to which first electrodes and second electrodes of the LEDs of the pixel units are connected. The distances between peripheral portions of the paired electrode pads are longer than the distances between central portions thereof. | 2020-06-11 |
20200185362 | LIGHT BULB - A light bulb includes a base, a filament coupled to the base and a cover covering the filament. The filament includes a transparent structure, optoelectronic units arranged on the transparent structure in sequence, each including a side surface, a first and second bonding pad formed on a top side of one of the optoelectronic units, a third and fourth bonding pad formed on a top side of another optoelectronic unit, conductive elements, one of the conductive elements including a bottom surface directly connecting the first and third bonding pads without covering the side surfaces of the one and the another of the optoelectronic units, and a top surface opposite to the bottom surface, the transparent structure continuously covering the optoelectronic units and the conductive elements without directly contacting the top surfaces of the conductive elements, first and seconds terminal electrically connected to the optoelectronic units. | 2020-06-11 |
20200185363 | LIGHT EMITTING DEVICE WITH LED STACK FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME - A light emitting device for a display including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, electrode pads disposed below the first LED sub-unit, and a filler disposed between the electrode pads, in which the electrode pads include a common electrode pad electrically connected in common to the first, second, and third LED sub-units, and first, second, and third electrode pads connected to the first, second, and third LED sub-units, respectively, the first, second, and third LED sub-units are independently drivable, light generated in the first LED sub-unit is configured to be emitted to the outside of the light emitting device through the second and third LED sub-units, and light generated in the second LED sub-unit is configured to be emitted to the outside through the third LED sub-unit. | 2020-06-11 |
20200185364 | THREE DIMENSIONAL INTEGRATED CIRCUIT - A method of forming a device includes providing a first substrate having a first area and a second area, forming a range compensating material over the first substrate so that the first material is disposed over the first area and not disposed over the second area, implanting ions into the first area and the second area to form first and second cleave planes at first and second depths, respectively, each of the first and second cleave planes being defined by a concentration of the implanted ions, removing the range compensating material, and cleaving the first substrate along a cleave profile including the first and second cleave planes. | 2020-06-11 |
20200185365 | PARALLELISABLE METHOD FOR INTEGRATING POWER CHIPS AND POWER ELECTRONICS - The method comprises the steps of 1) producing first and second blanks (EB | 2020-06-11 |
20200185366 | CIRCUIT BOARD WITH COMPACT PASSIVE COMPONENT ARRANGEMENT - Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board. | 2020-06-11 |
20200185367 | INTEGRATED CIRCUIT MODULE WITH INTEGRATED DISCRETE DEVICES - In at least one embodiment, an integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, and a discrete device disposed laterally with respect to the integrated circuit die and disposed above the redistribution layer. The integrated circuit product may include encapsulant mechanically coupling the redistribution layer, the integrated circuit die, and the discrete device. The integrated circuit product may include first conductive vias through the redistribution layer and second conductive vias through the redistribution layer. The first conductive vias may be electrically coupled to the integrated circuit die and the second conductive vias being electrically coupled to the discrete device. The discrete device may include a discrete capacitor device made from a ceramic material, electrolytic materials, or electrochemical materials. | 2020-06-11 |
20200185368 | LED DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention relates to an LED display device and a method for manufacturing the same. A manufacturing method, according to one embodiment of the present invention, comprises the steps of: growing a semiconductor layer on a growth substrate; forming an LED element in an asymmetrical shape from which the semiconductor layer is separated; separating the LED element from the growth substrate; forming a bonding electrode, to which the LED element is bonded, on a display substrate comprising a TFT; forming a groove by patterning the display substrate in the same shape as the LED element formed asymmetrically; seating the LED element in a pattern having the groove in the same shape as the LED element by means of a physical force; and electrically connecting by the bonding electrode of the display substrate or an adhesive conductive material formed on a bonding electrode of the LED element. | 2020-06-11 |
20200185369 | SEMICONDUCTOR STRUCTURE AND ASSOCIATED MANUFACTURING METHOD - A semiconductor structure is disclosed. The semiconductor structure includes: a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side; a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side; and a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; wherein the first color type, the second color type, and the third color type are different from each other. | 2020-06-11 |
20200185370 | Integrated Assemblies Comprising Vertically-Stacked Decks - Some embodiments include an integrated assembly having a base supporting first circuitry and first conductive lines. The first conductive lines extend along a first direction and are associated with the first circuitry. A deck is over the base and supports an array of memory cells and second conductive lines which are associated with the array of memory cells. The second conductive lines extend along a second direction which is substantially orthogonal to the first direction. Vertical interconnects extend from the deck to the base and couple the first conductive lines to the second conductive lines. Each of the vertical interconnects couples one of the first conductive lines to one of the second conductive lines. Each of the second conductive lines is coupled with only one of the first conductive lines. | 2020-06-11 |
20200185371 | Discrete Three-Dimensional Processor - A discrete 3-D processor comprises first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network. | 2020-06-11 |
20200185372 | SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE - A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than four microns, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells. | 2020-06-11 |
20200185373 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin. | 2020-06-11 |
20200185374 | WORDLINE STRAPPING FOR NON-VOLATILE MEMORY ELEMENTS - Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region. | 2020-06-11 |
20200185375 | INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING AND DESIGNING THE SAME - Provided is an integrated circuit including a semiconductor substrate, a plurality of gate lines and a plurality of metal lines. The plurality of gate lines are formed in a gate layer above the semiconductor substrate, where the plurality of gate lines are arranged in a first direction and extend in a second direction perpendicular to the second direction. The plurality of metal lines are formed in a conduction layer above the gate layer, where the plurality of metal lines are arranged in the first direction and extend in the second direction. 6N metal lines and 4N gate lines form a unit wiring structure where N is a positive integer and a plurality of unit wiring structures are arranged in the first direction. Design efficiency and performance of the integrated circuit are enhanced through the unit wiring structure. | 2020-06-11 |
20200185376 | ARRAY SUBSTRATE AND DISPLAY PANEL - The present application relates to an array substrate including a display region and a non-display region. The non-display region encapsulates the display region. The non-display region includes a first region and a second region. The first region is configured to dispose trances. The second region is configured to dispose a driving chip assembly. The first region includes a first subregion. Ground wires are disposed in the first subregion. A number of layers of an end of the ground wires close to the second region is less than a number of layers of an end of the ground wires away from the second region. | 2020-06-11 |
20200185377 | Controlled Resistance Integrated Snubber for Power Switching Device - A method includes providing a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, forming a switching device in an active region of the semiconductor substrate, the switching device having electrically conductive gate and field electrodes, forming an intermetal dielectric layer on the main surface over the active region and an inactive region that is laterally spaced apart from the active region, forming a source pad in the first metallization layer over the active region, forming a resistor trench in the inactive region, the resistor trench having a resistance section that is disposed below the main surface, and forming an electrical connection between the source pad and the field electrode that comprises the resistor. The resistor forms an exclusive current path between the source pad and the field electrode. | 2020-06-11 |
20200185378 | SWITCHING DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE - The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer. | 2020-06-11 |