24th week of 2015 patent applcation highlights part 53 |
Patent application number | Title | Published |
20150162151 | ARC CONTROL DEVICE FOR VACUUM BULB - To control the arc that forms during cut-off in a vacuum bulb, a contact device makes it possible to inflict a rotational motion on the arc, while keeping the arc diffuse. The rotating diffuse arc is obtained with each of two electrodes of the contact device including a solid wafer associated with a base of petal type, the two electrodes mirroring one another. | 2015-06-11 |
20150162152 | INTEGRATING IMPACT SWITCH - An integrating impact switch that can discriminate between accelerations due to different stimuli is provided. Embodiments of the present invention actuate only in response to an acceleration whose magnitude is equal to or greater than an acceleration threshold for a predetermined continuous period of time. Embodiments of the present invention comprise an impact switch having a throw that is operatively coupled with a viscous damper that dampens motion of the throw. As a result, a stimulus that imparts an acceleration that meets or exceeds an acceleration threshold for a time period less than a predetermined time-period threshold does not actuate the switch. A stimulus that imparts an acceleration whose magnitude is equal to or greater than the acceleration threshold for a time period equal to the time-period threshold, however, does actuate the switch. | 2015-06-11 |
20150162153 | HIGH TEMPERATURE MATERIAL COMPOSITIONS FOR HIGH TEMPERATURE THERMAL CUTOFF DEVICES - The present disclosure provides a high-temperature thermal pellet composition that maintains structural rigidity up to a transition temperature of about 240° C. The composition comprises at least one organic compound (e.g., triptycene or 1-aminoanthroquinone). The pellet can be disposed in a housing of a thermally-actuated, current cutoff device, such as a high-temperature thermal cutoff device (HTTCO). Also provided are material systems, which include the pellet composition and a high-temperature seal that provides substantial sealing up to at least the transition temperature. Methods of making such high-temperature pellet compositions and incorporating them into a thermally-actuated, current cutoff device are also provided. | 2015-06-11 |
20150162154 | CIRCUIT ARRANGEMENT FOR ACTUATING A BISTABLE RELAY - The disclosure relates to a circuit arrangement for actuating a bistable relay including a relay coil of the bistable relay being arranged in a series circuit with a capacitor, wherein the series circuit is connected to a supply voltage (V+) via a first semiconductor switch for switching on the bistable relay and is short-circuited through a second semiconductor switch for switching off the bistable relay. The circuit arrangement includes at least one voltage regulator configured to regulate the voltage present at the relay coil of the bistable relay such that a preset voltage is not exceeded. | 2015-06-11 |
20150162155 | MAGNETICALLY ACTUATED SHUT-OFF VALVE - A magnetic actuator assembly is disclosed, and includes a core, wiring, and a gate assembly. The core is constructed of a magnetic material, and includes a first end and a second end. The wiring is wound around a portion of the core. A predetermined amount of electric current is applied to the wiring to induce a magnetic field within the core. The gate assembly is positioned between the first end and a second end of the core. The gate assembly comprises a first gate member traveling between the first end and a second end of the core based on a threshold force being applied to the gate assembly. The threshold force is created by the magnetic field. | 2015-06-11 |
20150162156 | NANOTUBE BASED NANOELECTROMECHANICAL DEVICE - A nanoelectromechanical device is provided. The nanoelectromechanical device includes a nanotube, a first contact, and a first actuator. The nanotube includes a first end, the first end supported by a first structure, a second end opposite the first end, and a first portion. The first actuator is configured to apply a first force to the nanotube, the first force causing the nanotube to buckle such that the first portion couples to the first contact. | 2015-06-11 |
20150162157 | SYSTEM AND METHOD FOR ADJUSTING THE TRIP CHARACTERISTICS OF A CIRCUIT BREAKER - An electrical system includes (1) a distributed power source device structured to generate: (i) AC power, and (ii) a signal indicating an amount of current being produced by the distributed power source device, and (2) a circuit breaker having set trip characteristics coupled to distributed power source device, wherein the circuit breaker is structured to receive the signal and adjust the set trip characteristics (e.g., the trip curve) based on at least the signal from the distributed power source device. | 2015-06-11 |
20150162158 | MICRO-PLASMA FIELD EFFECT TRANSISTORS - In some aspects, a micro-plasma device comprises a plasma gas enclosure containing at least one plasma gas, and a plurality of electrodes interfaced with the plasma gas enclosure. In other aspects, a micro-plasma circuitry apparatus comprises a first layer having a cavity formed therein and a second layer having a circuit formed therein. The circuit includes a micro-plasma circuit (“MPC”) that includes one or more micro-plasma devices (“MPDs”). The first layer of the circuit is bonded to the second layer of the circuit thereby forming an enclosure that contains at least one plasma gas. An excitation voltage is applied to a drain electrode of the MPDs to generate a conductive plasma path between the drain electrode and a source electrode. | 2015-06-11 |
20150162159 | BEARING ARRANGEMENT FOR ROTATABLY MOUNTING AN ELECTRODE AND ELECTRODE ARRANGEMENT - In various embodiments, a bearing arrangement for rotatably mounting an electrode is provided. The bearing arrangement may include an outer sleeve, which is insertable into a housing for mounting a rotatable electrode; an inner element, which is received coaxially in the outer sleeve and is mounted by a first bearing and a second bearing so as to be rotatable in relation to the outer sleeve, wherein the bearings are spaced apart from one another in the axial direction; and an electrically conductive contact structure, which is positioned alongside at least one of the first bearing or the second bearing and which makes electrical contact with the inner element. | 2015-06-11 |
20150162160 | FOCUSED ION BEAM APPARATUS - A focused ion beam apparatus has an ion source chamber in which is disposed an emitter for emitting ions. The surface of the emitter is formed of a precious metal, such as platinum, palladium, iridium, rhodium or gold. A gas supply unit supplies nitrogen gas to the ion source chamber so that the nitrogen gas adsorbs on the surface of the emitter. An extracting electrode is spaced from the emitter, and a voltage is applied to the extracting electrode to ionize the adsorbed nitrogen gas and extract nitrogen ions in the form of an ion beam. A temperature control unit controls the temperature of the emitter. | 2015-06-11 |
20150162161 | TRANSMITTING-TYPE TARGET AND X-RAY GENERATION TUBE PROVIDED WITH TRANSMITTING-TYPE TARGET - A transmissive-type target includes a target layer, and a transmissive substrate configured to support the target layer. The transmissive substrate has a pair of surfaces facing each other and is formed of polycrystalline diamond. In the transmissive substrate, one of the pair of surfaces includes polycrystalline diamond having a first average crystal grain diameter which is smaller than a second average crystal grain diameter of polycrystalline diamond included on the other surface opposing thereto. The target layer is supported by any one of the pair of surfaces. | 2015-06-11 |
20150162162 | RADIATION TUBE AND RADIATION INSPECTION APPARATUS - A radiation tube includes an enclosure having an opening portion, an electron source disposed inside the enclosure, a target unit configured to generate radiation by being bombarded with electrons emitted from the electron source, and a front shield disposed on the opening portion and joined to the target unit. The front shield has a slit-shaped opening that shields some of the radiation radiated from the target unit. The radiation is radiated through the opening in the shape of a fan beam. | 2015-06-11 |
20150162163 | X-RAY TUBE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, an X-ray tube includes an envelope with an opening, an X-ray transmission assembly mounted on the envelope and vacuum-tightly blocking the opening, a cathode and an anode target. The X-ray transmission assembly includes a window frame, an X-ray transmission window, an X-ray-resistive resin film, a sealing member and a dry gas. The X-ray transmission window is formed of a beryllium thin plate, accommodated in the window frame, and configured to maintain, along with the window frame, a vacuum-tight state inside the envelope. The X-ray-resistive resin film forms a space inside along with the window frame and the X-ray transmission window. The dry gas fills the space. | 2015-06-11 |
20150162164 | ELECTRON MICROSCOPE SAMPLE HOLDER FOR FORMING A GAS OR LIQUID CELL WITH TWO SEMICONDUCTOR DEVICES - A novel sample holder for specimen support devices for insertion in electron microscopes. The novel sample holder of the invention allows for the introduction of gases or liquids to specimens for in situ imaging, as well as electrical contacts for electrochemical or thermal experiments. | 2015-06-11 |
20150162165 | CHARGED PARTICLE BEAM LITHOGRAPHY SYSTEM AND TARGET POSITIONING DEVICE - The invention relates to a charged particle beam lithography system comprising: a charged particle optical column arranged in a vacuum chamber for projecting a charged particle beam onto a target, wherein the column comprises deflecting means for deflecting the charged particle beam in a deflection direction, a target positioning device comprising a carrier for carrying the target, and a stage for carrying and moving the carrier along a first direction, wherein the first direction is different from the deflection direction, wherein the target positioning device comprises a first actuator for moving the stage in the first direction relative to the charged particle optical column, wherein the carrier is displaceably arranged on the stage and wherein the target positioning device comprises retaining means for retaining the carrier with respect to the stage in a first relative position. | 2015-06-11 |
20150162166 | SYSTEM AND METHOD FOR CONTROLLING ION IMPLANTER - A system, a method, and a non-transitory computer readable storage medium for controlling an ion implanter are disclosed herein. The system includes a sample module and a control module. The sample module is configured to generate a summarized value from process data of the ion implanter, and the process data correspond to a control parameter. The control module is configured to tune a control parameter, and the control module performs an ion implantation by releasing tools of the ion implanter in accordance with the control parameter when the summarized value meets a predetermined stability requirement. | 2015-06-11 |
20150162167 | MICROWAVE PLASMA PROCESSING APPARATUS - In accordance with example embodiments, a plasma processing apparatus includes a chamber configured to peform a plasma process, an upper plate on the chamber, an antenna under the upper plate and the antenna is configured to generate plasma in the chamber, an upper insulator between the upper plate and the antenna and the upper insulator covers a top of the antenna, a lower insulator covering a bottom of the antenna, an antenna support ring configured to fix the antenna to the upper plate, and a metal gasket adhered to the antenna support ring. | 2015-06-11 |
20150162168 | REACTOR FOR PLASMA-BASED ATOMIC LAYER ETCHING OF MATERIALS - Plasma-based atomic layer etching of materials may be of benefit to various semiconductor manufacturing and related technologies. For example, plasma-based atomic layer etching of materials may be beneficial for adding and/or removing angstrom thick layers from a surface in advanced semiconductor manufacturing and related technologies that increasingly demand atomistic surface engineering. A method may include depositing a controlled amount of a chemical precursor on an unmodified surface layer of a substrate to create a chemical precursor layer and a modified surface layer. The method may also include selectively removing a portion of the chemical precursor layer, a portion of the modified surface layer and a controlled portion of the substrate. Further, the controlled portion may be removed to a depth ranging from about 1/10 of an angstrom to about 1 nm. Additionally, the deposition and selective removal may be performed under a plasma environment. | 2015-06-11 |
20150162169 | ETCHING APPARATUS AND METHOD - An apparatus is disclosed for etching a wafer or substrate. The apparatus includes a process reaction chamber, a gas distribution plate, and an electrostatic chuck. The gas distribution plate is disposed in the process reaction chamber, and is used for entrance of a main processing gas. The electrostatic chuck is disposed in the process reaction chamber and has an adsorption surface. The wafer or substrate is disposed on the adsorption surface. The electrostatic chuck further has a plurality of first gas inlets for entrance of a plurality of auxiliary processing gases. Each of the first gas inlets is communicated with the adsorption surface and aligned with at least a part of a circumference of the wafer or substrate. The gas distribution plate and the electrostatic chuck are located at two opposite sides of the process reaction chamber, respectively. | 2015-06-11 |
20150162170 | PLASMA PROCESSING APPARATUS AND FOCUS RING - A degree of tilting caused by consumption of a focus ring can be suppressed. A plasma processing apparatus includes a chamber configured to perform a plasma process on a target object; a mounting table which is provided within the chamber and has a mounting surface on which the target object is mounted; and the focus ring, provided on the mounting table to surround the target object mounted on the mounting surface, having a first flat portion lower than the mounting surface, a second flat portion higher than the first flat portion and not higher than a target surface of the target object, and a third flat portion higher than the second flat portion and the target surface of the target object in sequence from an inner peripheral side thereof to an outer peripheral side thereof. | 2015-06-11 |
20150162171 | WAFER PROCESSING DEPOSITION SHIELDING COMPONENTS - Embodiments described herein generally relate to components for a semiconductor processing chamber, a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a process kit. In one embodiment a lower shield for encircling a sputtering target and a substrate support is provided. The lower shield comprises a cylindrical outer band having a first diameter dimensioned to encircle the sputtering surface of the sputtering target and the substrate support, the cylindrical band comprising a top wall that surrounds a sputtering surface of a sputtering target and a bottom wall that surrounds the substrate support, a support ledge comprising a resting surface and extending radially outward from the cylindrical outer band, a base plate extending radially inward from the bottom wall of the cylindrical band, and a cylindrical inner band coupled with the base plate and partially surrounding a peripheral edge of the substrate support. | 2015-06-11 |
20150162172 | MODIFIED TUNGSTEN-TITANIUM SPUTTERING TARGETS - A novel WTi target is described as having a Ti particle size similar to that of the W particle size. The target also contains controlled microstructural multi-phases characterized by an absence of a β (titanium-tungsten) alloy lamellar phase structure. The combination of controlled microstructural phases and controlled particle size improves overall sputtering performance whereby the sputtered face reduces formation of nodules which can flake off and deposit onto the resultant film to produce film defects during sputtering. | 2015-06-11 |
20150162173 | Method for Producing a Multilayer Coating and Device for Carrying Out Said Method - A method for reducing the optical loss of the multilayer coating below a predetermined value in a zone by producing coating on a displaceable substrate in a vacuum chamber with the aid of a residual gas using a sputtering device. Reactive depositing a coating on the substrate by adding a reactive component with a predetermined stoichiometric deficit in a zone of the sputtering device. Displacing the substrate with the deposited coating into the vicinity of a plasma source, which is located in the vacuum chamber at a predetermined distance from the sputtering device. The plasma action of the plasma source modifying the structure and/or stoichiometry of the coating, preferably by adding a predetermined quantity of the reactive component to reduce the optical loss of the coating. | 2015-06-11 |
20150162174 | DETECTORS AND METHODS OF USING THEM - Certain embodiments described herein are directed to detectors and systems using them. In some examples, the detector can include a plurality of dynodes, in which one or more of the dynodes are coupled to an electrometer. In some instances, an analog signal from a non-saturated dynode is measured and cross-calibrated with a pulse count signal to extend the dynamic range of the detector. | 2015-06-11 |
20150162175 | Methods for Isolation and Decomposition of Mass Spectrometric Protein Signatures - A method of analyzing a liquid mixture comprising protein or peptide molecules mixed with other molecules comprises: passing a portion of the mixture through a liquid chromatograph so as to elute the molecules; transferring the eluted portions of the molecules to an ion source of a mass spectrometer so as to generate ions comprising a plurality of ion species therefrom; transferring the generated ion species to a mass analyzer for detection thereby; generating a respective record of the intensity-versus-time variation of each of a plurality of the detected ion species; identifying and distinguishing a set of ion species corresponding to the ions generated from the eluted portion of the protein or peptide analyte molecules based on the records of the intensity-versus-time variation; and performing at least one additional operation on ions of one or more of the distinguished ion species generated from the protein or peptide analyte molecules. | 2015-06-11 |
20150162176 | MALDI SAMPLE PREPARATION METHODS AND TARGETS - The present invention is concerned with a method of preparing a MALDI sample, the method comprising the steps of: (a) mixing a solid sample precursor comprising sample and matrix to form a solid sample mixture; (b) applying the solid sample mixture to a sample cavity of a MALDI target; and (c) compressing the solid sample mixture in the sample cavity so as to form a MALDI sample surface for laser desorption. The present invention also provides a MALDI target comprising a sample cavity for receiving a MALDI sample, the sample cavity having (a) a desorption end portion comprising an aperture, such that a portion of the MALDI sample exposed at the aperture is in use subjected to laser desorption; and wherein the sample cavity also has (b) a compression end portion adapted to permit compression of a solid sample mixture towards the desorption end portion in the sample cavity by applying a compression force to the solid sample mixture via the compression end portion. | 2015-06-11 |
20150162177 | Method For Analyzing Sample Components - Described herein is a method and system for on-line coupling of capillary isoelectric focusing (cIEF) to high-resolution mass spectrometry in which a sheath flow buffer comprising polar organic solvent and organic acid is used as both an immobilization solution for (cIEF) and an ionization solution for electrospray ionization (ESI). | 2015-06-11 |
20150162178 | ION TRAP MASS SPECTROMETER USING COLD ELECTRON SOUCE - The present invention relates to an ion trap mass spectrometer using a cold electron source, in a production of a portable mass spectrometer, in which a microchannel plate (MCP) module is used, initial electrons are induced by injecting ultraviolet photons emitted from an ultraviolet diode to a front surface of the MCP module, electron beams amplified from the electrons are amplified using a channeltron electron multiplier (CEM), the amplified electron beams are accurately adjusted and injected into an ion trap, thus increasing the amplification rate, and since a quadrupole field is used as an ion filter which returns the initially injected electrons to the inside of an ion trap mass separator, the ionization rate increases. | 2015-06-11 |
20150162179 | METHOD OF CALIBRATING A SYSTEM COMPRISING A GAS-DISCHARGE LAMP AND A COOLING ARRANGEMENT - The invention describes a method of generating calibration data (ΔU | 2015-06-11 |
20150162180 | METHOD, STORAGE MEDIUM AND SYSTEM FOR CONTROLLING THE PROCESSING OF LOTS OF WORKPIECES - A method includes processing each of a plurality of lots with at least one first equipment and moving some of the plurality of lots to a first storage. For each of a plurality of second equipments, an expected dispatch time of one or more next lots for processing by the second equipment is determined Each of the lots in the first storage is assigned to one of the plurality of second equipments on the basis of at least the determined expected dispatch times and moved to one of a plurality of second storages that is associated with one of the plurality of second equipments to which the respective lot was assigned. For each of the plurality of second equipments, each of the lots in the second storage associated with the second equipment is moved to the second equipment and are processed with the second equipment. | 2015-06-11 |
20150162181 | SEMICONDUCTOR WAFER MANUFACTURING METHOD - A method of manufacturing a semiconductor wafer includes: rough-polishing front and back surfaces of the semiconductor wafer; mirror-polishing a chamfered portion of the rough-polished semiconductor wafer; performing mirror finish polishing on the front surface or both the front and back surfaces of the semiconductor wafer having the mirror-polished chamfered portion; and forming an oxide film on an entire surface of the semiconductor wafer after the mirror-polishing of the chamfered portion and before the mirror finish polishing. | 2015-06-11 |
20150162182 | SELF-LIMITING CHEMICAL VAPOR DEPOSITION AND ATOMIC LAYER DEPOSITION METHODS - Methods for depositing silicon on a semiconductor or metallic surface include cycling dosing of silane and chlorosilane precursors at a temperature between 50° C. and 300° C., and continuing cycling between three and twenty three cycles until the deposition self-limits via termination of surface sites with Si—H groups. Methods of layer formation include depositing a chlorosilane onto a substrate to form a first layer, wherein the substrate is selected from the group consisting of In | 2015-06-11 |
20150162183 | METHODS FOR FORMING CONDUCTIVE TITANIUM OXIDE THIN FILMS - The present disclosure relates to the deposition of conductive titanium oxide films by atomic layer deposition processes. Amorphous doped titanium oxide films are deposited by ALD processes comprising titanium oxide deposition cycles and dopant oxide deposition cycles and are subsequently annealed to produce a conductive crystalline anatase film. Doped titanium oxide films may also be deposited by first depositing a doped titanium nitride thin film by ALD processes comprising titanium nitride deposition cycles and dopant nitride deposition cycles and subsequently oxidizing the nitride film to form a doped titanium oxide film. The doped titanium oxide films may be used, for example, in capacitor structures. | 2015-06-11 |
20150162184 | Method of Manufacturing Semiconductor Device - A method of manufacturing a semiconductor device includes processing a substrate accommodated in a process container accommodated in a housing by supplying a process gas onto the substrate; and exhausting the process container using an exhaust system comprising a first exhaust pipe connected to the process container, the first exhaust pipe having circular or oval cross-section perpendicular to an exhausting direction thereof; and a second exhaust pipe connected to the first exhaust pipe, the second exhaust pipe having square or rectangular cross-section perpendicular to the exhausting direction, wherein at least a portion of the second exhaust pipe is disposed within the housing. | 2015-06-11 |
20150162185 | ATOMIC LAYER DEPOSITION OF SILICON CARBON NITRIDE BASED MATERIALS - A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles. | 2015-06-11 |
20150162186 | Method for producing a layer of a compound semiconductor - The invention relates to a method for producing a layer by means of MOVPE, wherein the layer comprises or consists of at least one III-V compound semiconductor and carbon, wherein the compound semiconductor comprises at least one element of main group III of the periodic table which is selected from any of gallium, aluminum, indium and/or boron, and wherein the compound semiconductor comprises at least nitrogen and wherein the compound semiconductor comprises optionally at least one further element of main group V which is selected from any of phosphorus and/or arsenic, wherein the method comprises the steps of: introducing a substrate into a vacuum chamber; evacuating the vacuum chamber to a background pressure; heating the substrate to a predefinable temperature; introducing at least one precursor gas into the vacuum chamber, said gas comprising or consisting of nitrogen; introducing at least one precursor comprising an organometallic compound into the vacuum chamber; introducing at least one hydrocarbon compound into the vacuum chamber. | 2015-06-11 |
20150162187 | SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING THE SAME - Provided is a method of manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a SiC substrate using a SiC-CVD furnace which is installed in a glove box. The method includes a SiC substrate placement step of placing the SiC substrate in the SiC-CVD furnace while circulating gas in the glove box. | 2015-06-11 |
20150162188 | Method of Forming A Dielectric Film - A method for flowable oxide deposition is provided. An oxygen source gas is increased as a function of time or film depth to change the flowable oxide properties such that the deposited film is optimized for gap fill near a substrate surface where high aspect ratio shapes are present. The oxygen gas flow rate increases as the film depth increases, such that the deposited film is optimized for planarization quality at the upper regions of the deposited film. | 2015-06-11 |
20150162189 | UV-ASSISTED PHOTOCHEMICAL VAPOR DEPOSITION FOR DAMAGED LOW K FILMS PORE SEALING - Embodiments of the invention generally provide methods for sealing pores at a surface of a dielectric layer formed on a substrate. In one embodiment, the method includes exposing a dielectric layer formed on a substrate to a first pore sealing agent, wherein the first pore sealing agent contains a compound with a general formula C | 2015-06-11 |
20150162190 | METHOD FOR FORMING SPACERS FOR A TRANSISTOR GATE - A method for forming spacers of a transistor gate having an active layer surmounted by the gate, including forming a porous layer covering the gate and having a dielectric constant equal to or less than that of silicon oxide, forming a protective layer covering the porous layer and the gate, etching the protective layer anisotropically to preserve residual portions of the protective gate only at the flanks of the gate, forming a modified layer by penetration of ions within the porous layer anisotropically to modify the porous layer over its entire thickness above the gate and above the active layer and so as not to modify the entire thickness of the porous layer on the flanks of the gate, the latter being protected by protective spacers constituting porous spacers, and removing the modified layer by etching to leave the protective spacers in place. | 2015-06-11 |
20150162191 | Substituted Silacyclopropane Precursors And Their Use For The Deposition Of Silicon-Containing Films - Provided are silacyclopropane-based compounds and methods of making the same. Also provided are methods of using said compounds in film deposition processes to deposit films comprising silicon. Certain methods comprise exposing a substrate surface to a silacyclopropane-based precursor and a co-reagent in various combinations. | 2015-06-11 |
20150162192 | Method for Forming a Semiconductor Device - A method for forming a semiconductor device includes carrying out an anodic oxidation of a surface region of a semiconductor substrate to form an oxide layer at a surface of the semiconductor substrate by generating an attracting electrical field between the semiconductor substrate and an external electrode within an electrolyte to attract oxidizing ions of the electrolyte, causing an oxidation of the surface region of the semiconductor substrate. Further, the method includes reducing the number of remaining oxidizing ions within the oxide layer, while the semiconductor substrate is within an electrolyte. | 2015-06-11 |
20150162193 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - Disclosed is a plasma processing method including: growing a polycrystalline silicon layer on a processing target base body; and exposing the polycrystalline silicon layer to hydrogen radicals by supplying a processing gas containing hydrogen into a processing container that accommodates the processing target base body including the polycrystalline silicon layer grown thereon and radiating microwaves within the processing container to generate the hydrogen radicals. | 2015-06-11 |
20150162194 | PATTERNING THROUGH IMPRINTING - Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer. | 2015-06-11 |
20150162195 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING PURIFIED BLOCK COPOLYMERS AND SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a blend solution that includes a block copolymer and an adsorbent is prepared. The block copolymer is synthesized by a copolymerization between a first polymer unit and a second polymer unit having a hydrophilicity greater than that of the first polymer unit. The adsorbent on which the block copolymer is adsorbed is extracted. The block copolymer is separated from the adsorbent. The block copolymer is collected. The block copolymer may be used to form a mask on an object layer on a substrate and the mask used to etch the object layer. | 2015-06-11 |
20150162196 | METHOD FOR FORMING PATTERNED DOPING REGIONS - A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate. | 2015-06-11 |
20150162197 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A first protective layer, a mask layer, a second protective layer and a photoresist layer are sequentially formed on a substrate. A photoresist pattern is formed by partially removing the photoresist layer. An ion implantation mask is formed by sequentially etching the second protective layer, the mask layer and the first protective layer using the photoresist pattern. The ion implantation mask exposes the substrate. Impurities are implanted in an upper portion of the substrate exposed by the ion implantation mask. | 2015-06-11 |
20150162198 | SEMICONDUCTOR DEVICE HAVING A DOUBLE DEEP WELL AND METHOD OF MANUFACTURING SAME - A method of forming a semiconductor device includes patterning a first mask over a substrate defining a first opening. The substrate includes a first dopant type. The method includes implanting ions having a second dopant type through the first opening to form a first deep well. The method includes patterning a second mask over the substrate defining a second opening. The method includes implanting ions having the second dopant type through the second opening to form a second deep well, wherein an energy for implanting ions to form the second deep well is lower than an energy for implanting ions to form the first deep well. The method includes implanting ions having the first dopant type into the substrate to form a first well, wherein the energy for implanting ions to form the second deep well is greater than an energy for implanting ions to form the first well. | 2015-06-11 |
20150162199 | AGING-BASED LEAKAGE ENERGY REDUCTION METHOD AND SYSTEM - A technique of reducing leakage energy associated with a post-silicon target circuit is generally described herein. One example method includes purposefully aging a plurality of gates in the target circuit based on a targeted metric including a timing constraint associated with the target circuit. | 2015-06-11 |
20150162200 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM OF PROCESSING SUBSTRATE - A semiconductor device includes a gate insulating film formed on a semiconductor substrate; a first conductive metal-containing film formed on the gate insulating film; a second conductive metal-containing film, formed on the first metal-containing film, to which aluminum is added; and a silicon film formed on the second metal-containing film. | 2015-06-11 |
20150162201 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor device, a dummy gate structure including a dummy gate electrode and a gate mask sequentially stacked on a substrate is formed. A spacer is formed on a sidewall of the dummy gate structure. The gate mask is formed to expose the dummy gate electrode and to form a recess on the spacer. A capping layer pattern is formed to fill the recess in the spacer. The exposed dummy gate electrode is replaced with a gate electrode. | 2015-06-11 |
20150162202 | ETCHING METHOD - An etching method is provided for performing an etching process on an etching target film arranged on a substrate. The etching method includes the steps of supplying a treatment gas including a halogen-containing gas, hydrogen gas, an inert gas, and oxygen gas; performing a treatment on a patterned mask arranged on the etching target film using a plasma generated from the treatment gas; and etching the etching target film that has undergone the treatment using a plasma generated from an etching gas. | 2015-06-11 |
20150162203 | METHOD FOR ETCHING SILICON LAYER AND PLASMA PROCESSING APPARATUS - Disclosed is a method of etching a silicon layer by removing an oxide film formed on a workpiece which includes the silicon layer and a mask provided on the silicon layer. The method includes: (a) forming a denatured region by generating plasma of a first processing gas containing hydrogen, nitrogen, and fluorine within a processing container accommodating the workpiece therein to denature an oxide film formed on a surface of the workpiece; (b1) removing the denatured region by generating plasma of a rare gas within the processing container; and (c) etching the silicon layer by generating plasma of a second processing gas within the processing container. | 2015-06-11 |
20150162204 | Method for Integrated Circuit Fabrication - Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images. | 2015-06-11 |
20150162205 | Self-Aligned Double Spacer Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask. | 2015-06-11 |
20150162206 | METHOD FOR ETCHING TARGET LAYER OF SEMICONDUCTOR DEVICE IN ETCHING APPARATUS - A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element. | 2015-06-11 |
20150162207 | METHOD OF USING SEPARATE WAFER CONTACTS DURING WAFER PROCESSING - Embodiments of the invention are directed towards improving on-wafer process performance and processing at increased processing fluid/wafer temperature while maintaining good process performance. A method for processing a wafer in a process chamber is described where the process chamber includes a wafer holder having first and second sets of edge grippers for independently securing the wafer at the wafer edge during processing, treating the wafer with a first processing fluid while securing the wafer with the first set of edge grippers, but not with the second set of edge grippers, treating the wafer with a second processing fluid while securing the wafer with the first set of edge grippers, but not with the second set of edge grippers, and treating the wafer with a third processing fluid while securing the wafer with the second set of edge grippers, but not with the first set of edge grippers. | 2015-06-11 |
20150162208 | Semiconductor Device and Manufacturing Method of the Same - There is provided a manufacturing method of a semiconductor device having an N-type semiconductor layer on a P-type semiconductor layer. The manufacturing method comprises: a dry etching process of performing dry etching to go through the N-type semiconductor layer in a thickness direction and make the plane in the thickness direction of the P-type semiconductor layer exposed; and a annealing process of annealing the P-type semiconductor layer in an atmosphere containing oxygen, after the dry etching process. This manufacturing method improves the electrical properties of the P-type semiconductor layer. | 2015-06-11 |
20150162209 | SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH PHOTOLUMINESCENCE QUENCHING - Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system for performing chemical-mechanical planarization includes: a polishing pad configured to support an article for chemical-mechanical planarization (CMP), wherein the article includes a CMP stop material, a polishing head configured to perform chemical-mechanical planarization on the article, a light source configured to provide an incident light, a polishing fluid including a plurality of luminescent particles capable of emitting a fluorescent light in response to the incident light, a fluorescence detector configured to detect the intensity of the fluorescent light, and at least one processor coupled to the fluorescent detector and the polishing head, wherein the at least one processor is configured to control the polishing head based on the detected fluorescent light. | 2015-06-11 |
20150162210 | SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH PHOTO-CURRENT DETECTION - Systems and methods are provided for performing chemical-mechanical planarization on an article. An example system includes a polishing head, a polishing pad, a light source, a polishing fluid, a current detector, and one or more processors. The polishing head is configured to perform chemical-mechanical planarization (CMP) on an article. The polishing pad is configured to support the article. The light source is configured to emit an incident light. The polishing fluid is configured to perform CMP including a plurality of light-absorption particles being capable of transferring charges to a stop layer in the article in response the incident light. The current detector is configured to detect a current in response to the light-absorption particles transferring charges to the stop layer. The one or more processors are configured to control the polishing head based on the detected current. | 2015-06-11 |
20150162211 | METHOD OF SUBSTRATE TEMPERATURE CONTROL DURING HIGH TEMPERATURE WET PROCESSING - Methods are provided for processing a substrate in single substrate tool. In one embodiment, the method includes providing the substrate in the single substrate tool, applying a first processing fluid at a first temperature greater than 100° C. to a lower surface of the substrate to heat the substrate to approximately the first temperature, and applying a second processing fluid at a second temperature greater than 100° C. to an upper surface of the substrate. | 2015-06-11 |
20150162212 | Method for Fabricating CMOS Compatible Contact Layers in Semiconductor Devices - A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer. | 2015-06-11 |
20150162213 | FORMULATIONS FOR WET ETCHING NIPT DURING SILICIDE FABRICATION - Compositions and methods for substantially and efficiently removing NiPt (1-25%) material from microelectronic devices having same thereon. The compositions are substantially compatible with other materials present on the microelectronic device such as gate metal materials. | 2015-06-11 |
20150162214 | Methods Of Selective Layer Deposition - Provided are methods for selective deposition. Certain methods describe providing a first substrate surface; providing a second substrate surface; depositing a first layer of film over the first and second substrate surfaces, wherein the deposition has an incubation delay over the second substrate surface such that the first layer of film over the first substrate surface is thicker than the first layer of film deposited over the second substrate surface; and etching the first layer of film over the first and second substrate surfaces, wherein the first layer of film over the second substrate surface is at least substantially removed, but the first layer of film over the first substrate is only partially removed. | 2015-06-11 |
20150162215 | SYSTEM AND METHOD FOR MANUFACTURING A FABRICATED CARRIER - A method and apparatus for fabricating a carrier having a top surface and a bottom surface, the method comprising combining a conductive portion at the top surface and a dielectric at the bottom surface, wherein the dielectric includes contact island cavities, filling one or more of the contact island cavities with solder metal to form solder islands, selectively metal plating the conductive portion, selectively etching a portion of the conductive portion, and applying solder resist to the selectively plated and etched top surface of said conductive portion. | 2015-06-11 |
20150162216 | TUNABLE COMPOSITE INTERPOSER - A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness. The support element can have a body of at least one of dielectric or semiconductor material exposed at a second surface of the support element, openings extending through a thickness of the body, conductive vias extending within at least some of the openings in a direction of the thickness of the body, and terminals exposed at a first surface of the support element. The second surface of the support element can be united with the second surface of the substrate element. The terminals can be electrically connected with the contacts through the conductive vias and the electrically conductive structure. | 2015-06-11 |
20150162217 | SYSTEM AND METHOD FOR MANUFACTURING A FABRICATED CARRIER - A method of fabricating a BGA carrier, the method comprising combining a conductive portion and a molded dielectric portion, the dielectric portion having a top surface, a bottom surface and an inner surface, the inner surface intersecting said top surface and said bottom surface, the inner surface forming a cavity for receiving a semiconductor die; selectively bonding the semiconductor die to a top surface of the conductive portion; selectively etching part of the conductive portion; and applying solder resist to a bottom surface of the conductive portion. | 2015-06-11 |
20150162218 | SYSTEM AND METHOD FOR MANUFACTURING A CAVITY DOWN FABRICATED CARRIER - A method of fabricating a receptacle down BGA carrier having a top surface and a bottom surface, the method comprising combining a conductive portion and a molded dielectric portion, said dielectric portion having an inner surface intersecting said top surface, said inner surface forming a cavity for receiving a die; selectively etching part of said conductive portion; and applying solder resist to a portion of a top surface of said conductive portion. | 2015-06-11 |
20150162219 | Semiconductor Device and Method of Manufacturing the Same - A plurality of semiconductor elements for power control are formed on a semiconductor substrate. A stress relaxation resin layer covering a crossing region where band-shaped dicing areas dividing the semiconductor elements adjacent to each other cross is formed. The crossing region is diced to cut the stress relaxation resin layer to obtain the separate semiconductor elements. Accordingly, even with semiconductor elements produced with a compound semiconductor substrate of SiC or the like, a semiconductor device having high adhesive strength with a sealing resin and being less likely to cause cracking or peeling of the sealing resin due to thermal stress during an operation can be obtained. | 2015-06-11 |
20150162220 | Package Structure and Methods of Forming Same - A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material. | 2015-06-11 |
20150162221 | APPARATUS FOR TREATING WAFERS USING SUPERCRITICAL FLUID - Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers. The wafer treatment method involves performing a predetermined treatment such as etching, cleaning or drying on wafers within only one of the plurality of chambers, followed by wafer treatment on the succeeding chamber, and thus allowing for sequential wafer treatment within each of the plurality of chambers. | 2015-06-11 |
20150162222 | WAFER PROCESSING APPARATUS - A wafer in which a modified layer is internally formed along planned dividing lines is placed on a placement table and a water tank allows the wafer placed on the placement table to be submerged in cleaning water. An ultrasonic supply unit supplies ultrasonic waves to the wafer submerged in the cleaning water. By the ultrasonic waves supplied by the ultrasonic supply unit, the wafer is divided along the planned dividing lines and is turned into small pieces to generate plural chips and the generated chips are cleaned. | 2015-06-11 |
20150162223 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - There are provided a substrate processing apparatus and a substrate processing method realizing an effective reduction of a voltage change of a substrate on an electrode to reduce the variation of incident energy of ions entering the substrate. The substrate processing apparatus includes: a first electrode holding a substrate on a main surface of the first electrode; a second electrode facing the first electrode; a RF power source applying to the first electrode a RF voltage whose frequency is equal to or higher than 40 MHz; and a pulse voltage applying unit applying to the first electrode a pulse voltage decreasing in accordance with a lapse of time, by superimposing the pulse voltage on the RF voltage. | 2015-06-11 |
20150162224 | SUBSTRATE TREATMENT METHOD AND SUBSTRATE TREATMENT APPARATUS - A substrate treatment method for treating a substrate including a first silicon nitride film provided on a front surface thereof and a silicon oxide film provided on the first silicon nitride film to remove the first silicon nitride film and the silicon oxide film from the substrate includes: a first phosphoric acid treatment step of supplying a phosphoric acid aqueous solution having a predetermined first concentration to the substrate held by a substrate holding unit to treat the substrate with the first concentration phosphoric acid aqueous solution for the removal of the first silicon nitride film; and a second phosphoric acid treatment step of supplying a phosphoric acid aqueous solution having a second concentration lower than the first concentration to the substrate to treat the substrate with the second concentration phosphoric acid aqueous solution for the removal of the silicon oxide film after the first phosphoric acid treatment step. | 2015-06-11 |
20150162225 | APPARATUS AND METHOD FOR WET-CHEMICAL PROCESSING OF FLAT, THIN SUBSTRATES IN A CONTINUOUS METHOD - The invention relates to a method and apparatus for wet-chemical processes (cleaning, etching, stripping, coating, dehydration) in a continuous method for flat, thin and fracture-sensitive substrates, the substrate transport and the wet process being effected by media-absorbing rollers. | 2015-06-11 |
20150162226 | Forming Charge Trap Separation in a Flash Memory Semiconductor Device - During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process. | 2015-06-11 |
20150162227 | MECHANISMS FOR ETCHING APPARATUS AND ETCHING-DETECTION METHOD - Embodiments of mechanisms of an etching apparatus are provided. The etching apparatus includes a processing chamber. The etching apparatus also includes a gas distribution plate disposed in the processing chamber and comprising a number of exhaust openings. The etching apparatus further includes a number of end-point detectors disposed on the gas distribution plate. The gas distribution plate is configured to spurt gas into the processing chamber via the exhaust openings during a semiconductor process. | 2015-06-11 |
20150162228 | METHOD FOR OVERHEAD CROSS-SYSTEM TRANSPORTATION - A method comprises transferring a wafer carrier to or from an overhead hoist transfer (OHT) system using a conveyor. The method also comprises transferring the wafer carrier between the conveyor and an overhead shuttle (OHS) system using a cross-system transport apparatus. The method further comprises generating control signals using a controller to control at least one of the cross-system transport apparatus, the conveyor, or the loading or unloading of the wafer carrier at the OHT or the OHS. The cross-system transport apparatus comprises a lifting device configured to raise or lower the wafer carrier. The transferring of the wafer carrier between the conveyor and the OHS system comprises one or more of lifting or lowering the wafer carrier. | 2015-06-11 |
20150162229 | LOAD PORT - A load port is provided with a table and a plate. The table is arranged on a side of a front wall of an atmospheric transfer unit for transferring a piece of material under processing and is adapted to mount on it a container with the piece of material received in the same. The plate serves to isolate an interior of the atmospheric transfer unit from an exterior of the atmospheric transfer unit. The load port includes an exhaust duct arranged on a rear side of the plate and a fan arranged in a lower extremity of the exhaust duct. By the exhaust duct and the fan, an internal atmosphere of the atmospheric transfer unit can be exhausted into the atmosphere. | 2015-06-11 |
20150162230 | APPARATUS FOR SELF-CENTERING PRE-HEAT RING - Embodiments described herein generally relate to an apparatus for aligning a preheat member. In one embodiment, an alignment assembly is provided for a processing chamber. The alignment assembly includes a lower liner, a preheat member; an alignment mechanism formed on a bottom surface of the preheat member; and an elongated groove formed in a top surface of the lower liner and configured to engage with the alignment mechanism. | 2015-06-11 |
20150162231 | WAFER CARRIER FOR SMALLER WAFERS AND WAFER PIECES - Embodiments described herein relate to an apparatus and method for securing and transferring substrates. A substrate carrier, having one or more electrostatic chucking electrodes disposed therein, electrostatically couples a substrate to the carrier such. Optionally, a mask may also be electrostatically coupled to the carrier and may be disposed over a region of the carrier not occupied by the substrate. In one embodiment, multiple electrode assemblies are provided such that a first electrode assembly chucks the substrate to the carrier and a second electrode assembly chucks the mask to the carrier. In another embodiment, a pocket is formed in the carrier and an electrode assembly provides chucking capability within the pocket. | 2015-06-11 |
20150162232 | SUBSTRATE HOLDING DEVICE, SEMICONDUCTOR FABRICATION DEVICE, AND SUBSTRATE CLAMPING ASCERTAINMENT METHOD - A substrate holding device is provided with an electrostatic chuck that has an electrode therein and is provided with a substrate holding surface, on one side of which a substrate is held; a displacement gauge that is disposed above or below the substrate holding surface; and a controller which, along with using the displacement gauge to measure a first distance to the substrate when a substrate is placed on the substrate holding surface, uses the displacement gauge to measure a second distance to the substrate after a predetermined voltage is applied to the electrode of the electrostatic chuck and, based on the difference between the measured distances, ascertains whether the clamping of the substrate to the electrostatic chuck has been performed in a normal manner. | 2015-06-11 |
20150162233 | METHOD FOR CALCULATING DISTANCE, METHOD FOR NEUTRALIZING ELECTROSTATIC CHUCK, AND PROCESSING APPARATUS - There are provided a method for obtaining a distance between a base portion of an electrostatic chuck and a back surface of a target object and a method for neutralizing the electrostatic chuck based on the obtained distance. The electrostatic chuck has an upper surface including the base portion and a plurality of convex portions projecting from the base portion. The target object is mounted on apexes of the convex portions of the electrostatic chuck such that the back surface is in contact with the apexes. By processing a first wavelength spectrum output from a spectroscope based on reflected light of light emitted from a light source, a distance between the back surface of the target object and the base portion of the electrostatic chuck is calculated. Based on the calculated distance, a voltage is applied to the electrostatic chuck to neutralize the electrostatic chuck. | 2015-06-11 |
20150162234 | ELECTROSTATIC CLAMPING METHOD AND APPARATUS - A method of electrostatically clamping a dielectric wafer to a processing table during plasma processing is described. The table has interdigitated electrodes embedded therein. The method comprises applying respective voltages of opposite first and second polarities to adjacent electrodes wherein polarisation charges are induced in the wafer with opposite polarity to the respective underlying electrodes thereby electrostatically clamping the wafer to the table; and, after a predetermined time (t | 2015-06-11 |
20150162235 | CARRIER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - Provided are a carrier and a method of fabricating a semiconductor device using the same. The carrier may include a recess region provided adjacent to an edge thereof. The recess region may be configured to confine an adhesive layer within a desired region including the recess region. The recess region makes it possible to reduce a process failure in a process of fabricating a semiconductor device. | 2015-06-11 |
20150162236 | FILM FOR SEMICONDUCTOR DEVICE PRODUCTION, METHOD FOR PRODUCING FILM FOR SEMICONDUCTOR DEVICE PRODUCTION, AND METHOD FOR SEMICONDUCTOR DEVICE PRODUCTION - The present invention relates to a film for semiconductor device production, which includes: a separator; and a plurality of adhesive layer-attached dicing tapes each including a dicing tape and an adhesive layer laminated on the dicing tape, which are laminated on the separator at a predetermined interval in such a manner that the adhesive layer attaches to the separator, in which the separator has a cut formed along the outer periphery of the dicing tape, and the depth of the cut is at most ⅔ of the thickness of the separator. | 2015-06-11 |
20150162237 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench and a second oxide layer formed over the first oxide layer, wherein the first oxide layer and the second oxide layer have a same composition. | 2015-06-11 |
20150162238 | Trench Formation using Horn Shaped Spacer - A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than respective bottom widths, and the mandrels define a first opening in the mandrel layer. The first opening has an I-shape and includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. Portions of the first opening that are unfilled by the spacers are extended into the target layer. | 2015-06-11 |
20150162239 | TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING - A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern. Alternately, the titanium nitride layer, with or without a titanium oxynitride layer thereupon, may be patterned with a line pattern, and physically exposed surface portions of the titanium nitride layer may be converted into titanium oxynitride. Titanium oxynitride provides etch resistance during transfer of a combined first and second pattern, but can be readily removed by a wet etch without causing surface damages to copper surfaces. A chamfer may be formed in the interconnect-level dielectric material layer by an anisotropic etch that employs any remnant portion of titanium nitride as an etch mask. | 2015-06-11 |
20150162240 | TRENCH FORMATION USING ROUNDED HARD MASK - A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer. | 2015-06-11 |
20150162241 | METAL PVD-FREE CONDUCTING STRUCTURES - Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd). | 2015-06-11 |
20150162242 | RADIO-FREQUENCY DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a electronic device package provides a electronic device chip, wherein the electronic device chip includes a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate has a first thickness, an electronic component disposed on the front side of the semiconductor substrate, and an interconnect structure disposed on the electronic component. The method further performs a thinning process to remove a portion of the semiconductor substrate from the back side thereof The method then removes a portion of the thinned semiconductor substrate and a portion of a dielectric layer of the interconnect structure from a back side of the thinned semiconductor substrate until a first metal layer pattern of the interconnect structure is exposed, thereby forming a through hole. Finally, the method forms a TSV structure in the through hole, and mounts the electronic device chip on a base. | 2015-06-11 |
20150162243 | SCREEN PRINT MASK FOR LASER SCRIBE AND PLASMA ETCH WAFER DICING PROCESS - Methods of using a screen-print mask for hybrid wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits separated by streets involves screen-printing a patterned mask above the semiconductor wafer, the patterned mask covering the integrated circuits and exposing the streets of the semiconductor wafer. The method also involves laser ablating the streets with a laser scribing process to expose regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the exposed regions of the semiconductor wafer to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching. | 2015-06-11 |
20150162244 | METHOD AND CARRIER FOR DICING A WAFER - Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a carrier for supporting a wafer or substrate in an etch process includes a frame having a perimeter surrounding an inner opening. The carrier also includes a tape coupled to the frame and disposed below the inner opening of the frame, the tape comprising an etch stop layer disposed above a support layer. | 2015-06-11 |
20150162245 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other. | 2015-06-11 |
20150162246 | SEMICONDUCTOR DEVICES INCLUDING WISX - Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices. | 2015-06-11 |
20150162247 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME AND MANUFACTURING METHODS THEREOF - The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed. | 2015-06-11 |
20150162248 | METHOD FOR THE FORMATION OF DIELECTRIC ISOLATED FIN STRUCTURES FOR USE, FOR EXAMPLE, IN FINFET DEVICES - On a substrate formed of a first semiconductor material, a first overlying layer formed of a second semiconductor material is deposited. A second overlying layer formed of a third semiconductor material is deposited over the first overlying layer. The first and second overlying layers are patterned to define fins, wherein each fin includes a first region formed of the third material over a second region formed of the second material. An oxide material fills the space between the fins. A thermal oxidation is then performed to convert the second region to a material insulating the first region formed of the third material from the substrate. As an optional step, the second region formed of the second material is horizontally thinned before the oxide material is deposited and the thermal oxidation is performed. Once the fins are formed and insulated from the substrate, conventional FinFET fabrication is performed. | 2015-06-11 |
20150162249 | FABRICATION OF LITHOGRAPHIC IMAGE FIELDS USING A PROXIMITY STITCH METROLOGY - A method of determining stitching errors in multiple lithographically exposed fields on a semiconductor layer during a semiconductor manufacturing process is provided. The method may include receiving a predetermined design distance corresponding to a plurality of petals associated with the multiple lithographically exposed fields and identifying a blossom within a single field-of-view (FOV) of a metrology tool, where the blossom is formed by a non-overlapping abutment of corners corresponding to the multiple lithographically exposed fields. The blossom may include the plurality of petals associated with the multiple lithographically exposed fields. Petal position errors may then be calculated based on both a coordinate position for each of the plurality of petals within the blossom and the predetermined design distance, whereby the calculated petal position errors are indicative of stitching errors for the multiple lithographically exposed fields. | 2015-06-11 |
20150162250 | INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK - An integrated circuit (IC) stack device for thermal management is disclosed. The IC stack device can include a primary IC having a first set of cores with a ratio of first enabled cores and first disabled cores. The IC stack device can also have a supplementary IC interfaced with the primary IC, and having a second set of cores with a second ratio of second enabled cores and second disabled cores, with the second ratio being less than the first ratio. The integrated circuit stack device can also include a cooling element located such that the primary integrated circuit is between the cooling element and the supplementary integrated circuit. The cooling element can be designed to facilitate heat dissipation of the first and second enabled cores of the primary integrated circuit and the supplementary integrated circuit. | 2015-06-11 |