24th week of 2009 patent applcation highlights part 28 |
Patent application number | Title | Published |
20090147575 | NOR FLASH MEMORY DEVICE WITH A SERIAL SENSING OPERATION AND METHOD OF SENSING DATA BITS IN A NOR FLASH MEMORY DEVICE - In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed. | 2009-06-11 |
20090147576 | FLOATING GATE WITH UNIVERSAL ETCH STOP LAYER - Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example. | 2009-06-11 |
20090147577 | NON-VOLATILE SEMICONDUCTOR LATCH USING HOT-ELECTRON INJECTION DEVICES - The invention concerns semiconductor latches capable of memorizing any programmed information even after power supply has been removed. Used is a 0.6 m BiCMOS EPROM process but it is applicable in any other process having hot electron injection devices like EPROM, Flash EEPROM. Suggested is a bi-stable latch circuit having a pair of cross-coupled branches (I,II), each branch including a complementary driver and a load connected between a drain line and a source line and a non-volatile memory cell having a program transistor and a read transistor, at least one of said drivers and loads including said read transistor, said driver and load of said branch connected in series at a respective output node, said read transistor and program transistor having a common floating gate and separate control gates, said control gate of said program transistor connected to a program voltage, the drain of said program transistor connected to a respective input node, said control gate of said read transistor in said branch connected to said output node of the other branch (II). | 2009-06-11 |
20090147578 | Combined volatile nonvolatile array - A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines. | 2009-06-11 |
20090147579 | NON-VOLATILE MEMORY SYSTEMS AND METHODS INCLUDING PAGE READ AND/OR CONFIGURATION FEATURES - A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described. | 2009-06-11 |
20090147580 | One-transistor floating-body dram cell device with non-volatile function - Disclosed herein is a one-transistor (1T) floating-body Dynamic Random Access Memory (DRAM) cell device with a non-volatile function for implementing the high integration/high performance DRAM. The 1T floating-body DRAM cell device includes a floating body for storing information of the DRAM cell device, a source and a drain formed on respective sides of the floating body, a gate insulating layer formed on a top of the floating body, a gate electrode formed on a top of the gate insulating layer, a gate stack formed under the floating body and configured to have a charge storage node for storing electric charges, and a control electrode formed on a lower side of the gate stack or partially or completely surrounded by the gate stack. The DRAM cell device performs “write0” and “write1” operations or a read operation. The DRAM cell device performs a non-volatile program operation or a non-volatile erase operation. | 2009-06-11 |
20090147581 | NAND FLASH MEMORY AND MEMORY SYSTEM - A NAND flash memory comprising blocks which are units of writing and deletion of data, the block comprising: memory cells from which data corresponding to values of held threshold voltages can be read by applying a reading voltage to control gates of the memory cells; source-side selection gate transistors connected between a common source line and the memory cells; drain-side selection gate transistors connected between a bit line and the memory cells; and monitor cells which are configured as the memory cells and have a threshold voltage set according to monitor data, and from which data corresponding to values of held threshold voltages can be read by applying a decision voltage to control gates of the monitor cells. | 2009-06-11 |
20090147582 | Adjusting program and erase voltages in a memory device - There is provided a method and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string. | 2009-06-11 |
20090147583 | SEMICONDUCTOR MEMORY DEVICE HAVING MAT STRUCTURE - A semiconductor memory device having a mat structure. The semiconductor memory device may comprise a first mat having a plurality of first memory cells and a second mat having a plurality of second memory cells. The first and second mats are formed in a single well region. The first and second mats may share a first well of a first conductivity type, and the first well may be formed in a second well of a second conductivity type. The second well may be formed in a semiconductor substrate of the first conductivity type. As a result, the semiconductor memory device according to embodiments of the present invention provide for higher integration density. | 2009-06-11 |
20090147584 | NAND ARCHITECTURE MEMORY DEVICES AND OPERATION - Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device. | 2009-06-11 |
20090147585 | FLEXIBLE WORD LINE BOOSTING ACROSS VCC SUPPLY - Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up table has a list of trim codes that indicates desired boosting ratios. The boosting ratio can vary depending on a level of a supply voltage to provide a sufficient word line voltage, thereby preventing and/or mitigating delay in reading operations. The number of the capacitors in the boosting circuit can be predetermined to be turned on or off according to the trim code. Accordingly, the voltage boost circuit provides a sufficient boosted word line voltage to a core cell gate with flexibility despite fluctuation of the supply voltage level. | 2009-06-11 |
20090147586 | Non-Volatile Memory and Method With Improved Sensing Having Bit-Line Lockout Control - In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level. | 2009-06-11 |
20090147587 | CIRCUIT PRE-CHARGE TO SENSE A MEMORY LINE - Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass. | 2009-06-11 |
20090147588 | MEMORY DEVICES HAVING REDUCED WORD LINE CURRENT AND METHOD OF OPERATING AND MANUFACTURING THE SAME - There is provided a memory array and methods for manufacturing the same. In one embodiment, there is provided a string comprising a plurality of transistors. Each of the plurality of transistors includes: a charge storage node, a control gate, and at least one resistive element coupled to the string. The control gate of at least one of the plurality of transistors can be selectively coupled to a reference potential via a corresponding one of the at least one resistive element. | 2009-06-11 |
20090147589 | Selective Application Of Word Line Bias To Minimize Fringe Effects In Electromagnetic Fields During Erase Of Nonvolatile Memory - A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase. | 2009-06-11 |
20090147590 | APPARATUS FOR REDUCING LEAKAGE IN GLOBAL BIT-LINE ARCHITECTURES - A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the cells; an output latch having transistors, the output latch selectively coupled to a global bit-line of the sense amplifier having a logical state, the output latch configured for selectively reading out stored data from one of the cells through the global bit-line; and a transmission gating device coupled between the sense amplifier and the output latch for selectively coupling the sense amplifier to the output latch correspondingly eliminating a first leakage path and forming a second leakage path, the first leakage path being between the sense amplifier and the output latch, the second leakage path formed within the sense amplifier. | 2009-06-11 |
20090147591 | MEMORY CIRCUIT WITH HIGH READING SPEED AND LOW SWITCHING NOISE - A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level. | 2009-06-11 |
20090147592 | Memory Circuit with Decoupled Read and Write Bit Lines and Improved Write Stability - In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed. | 2009-06-11 |
20090147593 | OUTPUT DRIVER OF SEMICONDUCTOR MEMORY APPARATUS - An output driver of a semiconductor memory apparatus comprises a voltage dividing block configured to generate divide voltages by dividing an internal voltage, a threshold voltage detecting block configured to generate a detecting voltage corresponding to a change in a threshold voltage of a transistor, a drive capability control signal generating block | 2009-06-11 |
20090147594 | VOLTAGE REGULATOR FOR SEMICONDUCTOR MEMORY - A voltage regulator in a semiconductor memory has: a comparing unit including first and second bias current sources, for comparing an output voltage with first and second reference voltages under control of a first signal, the second bias current source being ON under control of a second signal; and a driver active element, coupled to the comparing unit, for outputting the output voltage. Before sensing operations, the output voltage is reset to the second reference voltage. During the sensing operations, the output voltage is maintained at the first reference voltage and the second signal is asserted for turning ON the second bias current source for raising speed of the comparing unit. After the sensing operations, the output voltage is reset to the second reference voltage. | 2009-06-11 |
20090147595 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a memory cell array composed of electrically rewritable memory cells; an internal voltage generating circuit having a boosting circuit for generating a voltage boosted from a supply voltage, and a voltage detecting circuit for detecting an output voltage of the boosting circuit as a monitor voltage and controlling on/off of the boosting circuit for holding the output voltage of the boosting circuit at a specified level, the internal voltage generating circuit outputting the output voltage of the boosting circuit as an internal voltage; a control circuit for controlling the internal voltage generating circuit; and a writing circuit for applying the internal voltage to the memory cell as a writing voltage when writing data into the memory cell, wherein the control circuit controls the internal voltage to a first voltage necessary for writing data into the memory cell when writing data into the memory cell, and to a second voltage lower than the first voltage in a write verify operation following the data write operation. | 2009-06-11 |
20090147596 | Method to improve the write speed for memory products - A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write speed and wherein the layout area of the BS FET-switches and thus also the die size is minimized. This is achieved by using a two thickness technique of oxide layers for crucial internal circuit parts of the chip. | 2009-06-11 |
20090147597 | SEMICONDUCTOR MEMORY DEVICE - A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives sequentially inputted second data in accordance with the data input mode. A second data selector selectively transfers the data of the first input buffer or of the second input buffer, in accordance with the data input mode. A first data alignment circuit aligns and outputs the data from the second data selector. | 2009-06-11 |
20090147598 | Integrated circuits and methods to compensate for defective memory in multiple layers of memory - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods to compensate for defective memory in third dimension memory technology. In a specific embodiment, an integrated circuit is configured to compensate for defective memory cells. For example, the integrated circuit can include a memory having memory cells that are disposed in multiple layers of memory. It can also include a memory reclamation circuit configured to substitute a subset of the memory cells for one or more defective memory cells. At least one memory cell in the subset of the memory cells resides in a different plane in the memory than at least one of the one or more defective memory cells. | 2009-06-11 |
20090147599 | Column/Row Redundancy Architecture Using Latches Programmed From A Look Up Table - A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. | 2009-06-11 |
20090147600 | APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY - An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address. | 2009-06-11 |
20090147601 | Non-volatile memory structure - A non-volatile memory array structure includes N bit lines, M first word lines, M×N first memory cells, a second word line, n repair circuits and a sense amplifier. The N bit lines and M first word lines are interlaced to control the M×N first memory cell. The second word line is placed across the n bit lines. Each of the repair circuits is electrically connected between the corresponding bit line and the sense amplifier. M and N are natural number. | 2009-06-11 |
20090147602 | SENSE AMPLIFIER FOR CONTROLLING FLIP ERROR AND DRVING METHOD THEREOF - A sense amplifier and a driving method is described for resolving a flip failure occurrence where the voltage applied across the bit line is within an acceptable threshold range when the data is delivered to the data bus. The driving method includes disconnecting a bit line from a sense amplifying circuit according to a bit line select control signal after performing a read operation according to a read request. Then, connecting the sense amplifying circuit to a data bus according to a column select control signal after the bit line is disconnected from the sense amplifying circuit and deactivating an output terminal of the sense amplifier circuit that is disconnected from the bit line and connected to the data bus during a restore section synchronized to a command following the read command. Finally, delivering the data on the bit line to the output terminal of the sense amplifying circuit to update the output terminal of the sense amplifying circuit by connecting the sense amplifying circuit to to the bit line according to the bit line select control signal. | 2009-06-11 |
20090147603 | MEMORY WITH LOW POWER MODE FOR WRITE - The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode control circuitry coupled to the array and configured to alter a supply voltage level to the SRAM array based on a mode of operation. The circuitry also includes control inputs coupled to the mode control circuitry for selecting one of the low power write mode, the full active mode, and optionally a retention mode of operation. The mode control circuitry is configured to receive the control inputs to select one of the three modes of operation, and to alter one or more supply voltage levels to the array, for example, the Vss supply voltage using a Vss supply circuit and the Vdd supply voltage using a Vdd supply circuit, based on the selected mode of operation. The mode control circuitry may also comprise a bitline precharge circuit configured to alter a bitline precharge voltage. | 2009-06-11 |
20090147604 | SENSE AMPLIFIER AND DRIVING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SENSE AMPLIFIER - The semiconductor memory device includes a bank having a cell array and a sense amplifier. A back bias voltage generating unit supplies a back bias voltage to the cell array of the bank. A negative drive voltage generating unit generates negative driving voltages including a normal pull-up voltage, an overdrive voltage, a normal pull-down voltage, and a negative voltage and supplies the negative driving voltages to the sense amplifier of the bank. A switching unit opens a connection between the back bias voltage generating unit and the negative drive voltage generating unit when in active mode and shares the back bias voltage between the back bias voltage generating unit and the negative drive voltage generating unit when in a refresh mode, in response to an external command. | 2009-06-11 |
20090147605 | NOVEL HIGH PERFORMANCE, AREA EFFICIENT DIRECT BITLINE SENSING CIRCUIT - In a method and apparatus for reading a logic state stored in an 8 transistor memory cell (8TMC), a differential sense circuit includes a differential input circuit having a pair of differential inputs and an output. An output signal is provided at the output and is indicative of a difference between two signals received at the pair of differential inputs. The difference is in accordance with the logic state read from the 8TMC. A sense amplifier is coupled to the output, the sense amplifier being operable to amplify the output signal that is greater than a threshold and switch the output signal to a voltage level corresponding to the logic state. The difference between the two signals measurable over a configurable time period is greater than a corresponding change in any one of the two signals measured over the same period, thereby improving the performance of the 8TMC. | 2009-06-11 |
20090147606 | MEMORY REFRESH METHOD AND APPARATUS - An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows selectable through a row address. The refresh controller is configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation. | 2009-06-11 |
20090147607 | RANDOM ACCESS MEMORY AND DATA REFRESHING METHOD THEREOF - A random access memory and a data refreshing method thereof are provided. The random access memory includes a memory array having a plurality of word lines; a control logic unit which is used for outputting a refreshment indicating signal, a thermal sensor which is used for outputting a temperature indicating signal; a refresh counter which is used for outputting a row address counting signal; and a row address decoder which is used for performing a decoding operation on the row address counting signal in response to the refreshment indicating signal and the temperature indicating signal, and simultaneously enabling the plurality of word lines of the memory array based on a result of the decoding operation. | 2009-06-11 |
20090147608 | POWER MANAGEMENT CONTROL AND CONTROLLING MEMORY REFRESH OPERATIONS - A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation. | 2009-06-11 |
20090147609 | TECHNIQUES FOR CONFIGURING MEMORY SYSTEMS USING ACCURATE OPERATING PARAMETERS - Techniques are disclosed for reading operating parameters from programmable elements on memory devices to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, or voltage and timing parameters. The memory device may be incorporated into a memory module that is incorporated into a system. Once the memory module is incorporated into a system, the programmable elements may be accessed such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for each memory device in the system. | 2009-06-11 |
20090147610 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second memory circuits that are disposed in different power source blocks and operate in synchronization with a clock, first and second delay circuits that are connected between output terminals of one memory circuits and input terminals of the other memory circuits, and a determination circuit that determines whether it is a situation that can cause malfunction based on an input signal and an output signal in the memory circuits and outputs a determination result as an error detection signal. To the first and second memory circuits, different initial values are given, and it is monitored whether a signal is sent and received between the memory circuits in a toggle state or not. Thus, occurrence of a situation that can cause malfunction can be simply and quickly detected. | 2009-06-11 |
20090147611 | BULK VOLTAGE DETECTOR - A bulk voltage detector comprises a voltage sensor configured to receive a bulk voltage and compare the received bulk voltage with a target level to provide a first detection signal having a voltage gain that is increased within a predetermined voltage range around the target level, and an amplifier coupled with the voltage sensor, the amplifier configured to receive the first detection signal and invert and amplify the first detection signal. | 2009-06-11 |
20090147612 | SYSTEM FOR CONTROLLING MEMORY POWER CONSUMPTION IN INTEGRATED DEVICES - A method for reducing power consumption in integrated devices is provided. The method comprising: locating a plurality of unused blocks of memory and a plurality of used blocks of memory in a memory device tlhrough a tracking mechanism; performing a refresh operation on the plurality of used blocks of memory at a constant frequency and suppressing the refresh operation on the plurality of unused blocks of memory through a memory controller; and suppressing error correction codes or parity errors on at least one of the plurality of unused blocks of memory when the at least one of the plurality of unused blocks of memory is accessed through the memory controller. | 2009-06-11 |
20090147613 | DEVICE FOR PROTECTING SRAM DATA - A device for protecting data stored in a static random access memory (SRAM) is provided. More particularly, a device for protecting SRAM data including an SRAM data erasing circuit, which erases memory stored in an SRAM at once when illegal separation from a system is detected. The device for protecting SRAM data includes: a power switching circuit for outputting electrical power supplied from an external power supply or a back-up battery power supply depending on whether the external power supply is supplying the electrical power or not; and an SRAM data erasing circuit for supplying the electrical power output from the power switching circuit to a power input terminal of a SRAM or grounding the power input terminal of the SRAM, in response to a connecter connection signal. The device can prevent illegal leakage of SRAM data by erasing the data stored in the SRAM when the SRAM is illegally separated from a system according to the switch setting of the SRAM data erasing circuit. | 2009-06-11 |
20090147614 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory includes a cell mat configured to include a plurality of memory cells to which a first bit line pair or a second bit line pair is connected; a sense amplifier configured to amplify a positive sensing line and a negative sensing line in response to a first bit line equalize signal; a column selecting unit configured to connect the positive sensing line and the negative sensing line to a first data bus and a second data bus, respectively, in response to a column selection signal; and a share control unit configured to connect the positive sensing line and a positive first bit line of the first bit line pair or a positive second bit line of the second bit line pair in response to a second bit line equalize signal, a positive share control signal and a negative share control signal. | 2009-06-11 |
20090147615 | DISPOSABLE CUP WITH A ROTATING SPOON - The invention relates to a disposable cup with a rotating spoon comprising a container ( | 2009-06-11 |
20090147616 | Method of and Apparatus For Controlling The Efficiency of Mixing - A method of and apparatus for controlling the efficiency of mixing of a mixer, comprising injecting a chemical into a process fluid flowing in a pipe, mixing the chemical with the process fluid with a mixer operating at a first operation rate, wherein the method comprises further steps of measuring an efficiency of mixing of the chemical and the process fluid within the pipe downstream of the mixer, comparing the measured efficiency of mixing with a predetermined efficiency of mixing range, controlling the operation rate of the mixer so as to adjust the efficiency of mixing to the predetermined efficiency of mixing range. The efficiency of mixing is preferably measured by using a set of electrodes disposed on the periphery of the pipe, and the efficiency of mixing is preferably obtained by the use of electrical impedance tomography. | 2009-06-11 |
20090147617 | Container and method for the mixing of media - Container and method for the mixing of media, in particular as a disposable container, which has at least one closable opening for the introduction and/or removal of the media and has a first sensor for measurement of at least one parameter of the mixture, in which at least one second sensor for measurement of the same parameter is arranged at a distance from the first sensor. | 2009-06-11 |
20090147618 | Kitchen appliance provided with a reinforced electric motor-gear stage arrangement and method for producing an electric motor-driven kitchen appliance - An electric motor-driven kitchen appliance includes an electric motor having a motor housing and a gear stage having a gear case fastened to the electric motor. A removable reinforcement frame is around the motor housing and gear case. The electric motor-gear stage arrangement can be tested outside of the housing of the kitchen appliance and produced in a cost effective manner, being particularly torsionally rigid due to the removable reinforcement frame, thereby exhibiting an operation reliability. | 2009-06-11 |
20090147619 | In-Sea Power Generation for Marine Seismic Operations - A method for conducting seismic operations includes the steps of deploying a seismic streamer carrying an electrically powered device from a vessel into water having waves, providing an in-sea generator in electrical connection with the device, producing electricity from the in-sea generator by harvesting mechanical energy from the waves, and providing the produced electricity to the device. | 2009-06-11 |
20090147620 | Method for processing marine towed streamer seismic data from regular multi-azimuth surveys - Marine towed streamer seismic data are combined from a first survey and a second survey, wherein the first survey and the second survey are shot with a bin size of L×L and the second survey is shot with a shooting direction rotated 90° relative to the shooting direction of the first survey. The combined seismic data from the first and second surveys are binned on a bin grid with a bin size of | 2009-06-11 |
20090147621 | Method of attenuating noise in marine seismic streamers utilizing varied sensor spacing and position-dependent band-pass filters - The invention comprises a system for attenuating noise in seismic signals detected in a marine seismic streamer. In a particular implementation the system may comprise seismic detectors positioned in the streamer and interconnected to form a plurality of wavenumber filters, with each of the wavenumber filters attenuating signals within a range of wavenumbers. The output signals from the wavenumber filters are operatively connected to a plurality of band-pass filters, and the output signals of the band-pass filters are combined by summation means. The range of wavenumbers attenuated by the wavenumber filters and the passbands of the band-pass filters are selected so that in the output signal of the summation means, signals within a selected frequency range of interest propagating along the cable within a selected velocity range are attenuated and signals within the selected frequency range of interest having a velocity range outside the selected velocity range are preserved. | 2009-06-11 |
20090147622 | Side scan sonar imaging system with enhancement - A system for use with a boat to provide underwater sonar images, includes a left side scan sonar transducer for transmitting left side scan sonar pulses and for receiving left side scan sonar return signals, a right side scan sonar transducer for transmitting right side scan sonar pulses and for receiving right side scan sonar return signals, and signal processing circuitry for processing the left and right side scan sonar return signals to produce side scan image data. The system further includes a user interface including user inputs and a display and a digital processor for providing signals to the display to show an underwater image based upon the side scan image data, wherein the digital processor, in response to a user command, performs an image enhancement algorithm to enhance the underwater image. | 2009-06-11 |
20090147623 | Side scan sonar imaging system with associated GPS data - A system for use with a boat to provide underwater sonar images includes a GPS receiver for providing GPS position data, a left side scan sonar transducer for transmitting left side scan sonar pulses and for receiving left side scan sonar return signals, and a right side scan sonar transducer for transmitting right side scan sonar pulses and for receiving right side scan sonar return signals. The system further includes signal processing circuitry for processing the left and right side scan sonar return signals to produce side scan image data and a digital processor for causing a display to display an underwater image based upon the side scan image data, wherein the digital processor associates GPS position and side scan image data. | 2009-06-11 |
20090147624 | Sound Collection Environment Deciding Device, Sound Processing Device, Electronic Appliance, Sound Collection Environment Deciding Method and Sound Processing Method - A sound collection environment deciding device for deciding whether the sound was collected in air or in water by utilizing an audio signal of collected sound is provided. Methods of Utilizing the audio signal of collected sound include, for instance, utilizing a difference of frequency characteristics between in-air and in-water of the audio signal of collected sound, utilizing a difference of propagation characteristics between in-air and in-water of the audio signal of collected sound, or the like. | 2009-06-11 |
20090147625 | EFFICIENT METHODS FOR WIDEBAND CIRCULAR AND LINEAR ARRAY PROCESSING - The objective of this patent is to develop new signal processing algorithms for a wide-band circular electronically scanned array (CESA) or a wideband linear electronically scanned array (LESA) for use in surveillance and communications applications, where a sequence of pulses are transmitted and their returns are collected by the array for further processing. Instead of partitioning the entire wideband frequency into various subbands and then processing them separately using narrowband schemes, a frequency focusing method is proposed here to compensate and focus the wideband spatio-temporal data into a single narrow frequency band. This is made possible by operating with a pre-computed frequency focusing matrix that transforms the data from various frequency slots that are spread across the entire wideband region into a common narrowband frequency for the array outputs. Finally the focused narrowband data can be processed using conventional space-time adaptive processing methods to suppress the clutter/noise returns and detect any targets present. | 2009-06-11 |
20090147626 | Foldable marine seismic source - The invention relates to a source device for the emission of seismic waves designed to operate by being towed by a vessel. | 2009-06-11 |
20090147627 | MULTILAYER BACKING ABSORBER FOR ULTRASONIC TRANSDUCER - A multilayer backing absorber for use with an ultrasonic transducer comprises an elemental multilayer having at least one metal layer and at least one adhesive layer, wherein the backing absorber is adapted to be coupled to a vibrating layer of the ultrasonic transducer. | 2009-06-11 |
20090147628 | MOBILE TERMINAL AND METHOD OF SETTING ALARM THEREIN - A mobile terminal and a method of setting an alarm therein are provided. The mobile terminal includes a controller, a display unit, and a memory unit. The controller controls the display unit to display an alarm setting screen on which alarm dates are arranged in a first direction and alarm time points are arranged in a second direction, the alarm screen being displayed in an alarm setting mode and sets an alarm at a selected time point of each alarm date in response to selection of the alarm time point. The controller also controls the memory unit to store a set alarm on an alarm date and alarm time point. The display unit displays an alarm image at an intersection of an alarm date and an alarm time point of each set alarm. | 2009-06-11 |
20090147629 | CHRONOGRAPH CONTROL DEVICE - The present invention concerns a chronograph control device including a first, pivotably mounted lever, which is activated by a first push-button and whose movement in the direction of the first push-button is limited by a first stop member, and a second, pivotably mounted lever, which is activated by a second push-button and whose movement is limited in the direction of the second push-button by a second stop member. A spring is mounted on the second lever. | 2009-06-11 |
20090147630 | PUSH-BUTTON CONTROL DEVICE - The present invention concerns a push-button control device for a timepiece, including a push-button head secured to a push-button stem that is fixed to a timepiece case, said stem being able to move axially between at least a rest position and an active position, against a return member, to control at least one function of said timepiece, and water-resistant sealing means, said device being characterized in that the water-resistant sealing means include a cap made of flexible, water-resistant material which covers the push-button head and which is secured to the timepiece case. | 2009-06-11 |
20090147631 | Optical Disk Image Forming Device, Optical Disk Image Forming Method and Optical Disk - When an image is formed on an optical disk, an optical disk image forming device reads information written in an information area of the optical disk. When a reflection preventing process is applied to an image forming area of the optical disk, the optical disk image forming device corrects at least one of a laser power or a focus gain in accordance with information about the image forming areawritten in the information area. Thus, the optical disk image forming device can form the image with a clear brightness and a good visibility on the image forming area of the optical disk without allowing a rainbow-color to appear or a face or a background to be reflected due to the interference of light. | 2009-06-11 |
20090147632 | OPTICAL DISC DRIVE APPARATUS - In an optical disc drive apparatus, when a start time of a tracking pull-in operation is adjusted according to the eccentricity amount of the optical disc, a suitable starting point of the tracking pull-in operation can be always captured and the pull-in operation of the tracking control can be stably performed, without depending on the eccentricity amount of the optical disc. Further, the eccentricity amount and an eccentricity phase are detected from a track zero crossing signal before the tracking pull-in, and an eccentricity compensation signal of the track is added to the tracking control signal. As a result, also in the optical disc with the large eccentricity amount, the tracking pull-in operation can be stably performed. | 2009-06-11 |
20090147633 | OPTICAL DISK APPARATUS, SIGNAL PROCESSING SEMICONDUCTOR INTEGRATED CIRCUIT CONSTITUTING THE SAME, AND OPERATION METHOD - In order to cancel an offset caused by a variation of a signal inputted from an optical pickup, variations of elements in an integrated circuit, etc., a calibration circuit which generates and feeds back an offset adjustment amount that makes the offset zero by a comparison with a reference value, and an offset adjustment circuit that makes the offset zero using the fed-back control signal are provided in an analog front-end LSI. The offset adjustment by the calibration circuit is automatically done in response to commands supplied from a digital signal processing LSI, a host control device, etc. On the other hand, as for a signal on which arithmetic processing such as gain control, addition and subtraction, is performed, the offset adjustment is performed by sending the offset adjustment amount obtained by an arithmetic operation performed by software processing of the digital signal processing LSI to the analog front-end. | 2009-06-11 |
20090147634 | OPTICAL PICKUP APPARATUS AND INFORMATION RECORDING AND REPRODUCING APPARATUS - A light quantity adjusting apparatus, to adjust a light quantity of a light beam emitted from a light source, including a transmission element, including a first transmission portion, formed on a plane, having a first transmittance and a second transmission portion, formed on the same plane as the first transmission portion, having a second transmittance, a support element to support the transmission element, and a rotation shaft, connected to the support element, with a center axis extending in a direction perpendicular to an optical axis of the light beam, to rotate the transmission element, supported by the support element, about the center axis, to selectively insert into a path of the light beam one of the first transmission portion and the second transmission portion to adjust the light quantity of the light beam passing through a respective transmission portion. | 2009-06-11 |
20090147635 | DIGITAL VIDEO RECORDER WIDE DYNAMIC RANGE OPTICAL POWER CALIBRATION - A method and apparatus are presented for optimizing write operations for optical storage media. A determination is made, at least in part by iteration, of a next power range and a current score for a current power range. If it is determined that the current score is relatively equivalent to a maximum score, a plurality of final parameters is updated and provided, including an optimal power range and a final score. If it is determined that the current score is relatively greater than the final score, then the plurality of final parameters is updated. If it is determined that a maximum number of iterations has been performed, the plurality of final parameters is provided. Otherwise, the current power range is updated with the next power range. One or more of the returned plurality of final parameters are employed to optimize write operations for optical storage media. Determination of the score may also include determining validity of test data segments, selecting a score calculation criterion, and calculating the score based at least in part on the score calculation criterion and on a number and a sequence of valid test data segments. The score calculation criterion may be based on such criterion as beta criterion or modulation amplitude. | 2009-06-11 |
20090147636 | ACTUATOR, OPTICAL HEAD DEVICE, AND OPTICAL INFORMATION DEVICE - An optical head device according to the present invention includes: a light source for outputting laser light; an optical system for allowing the laser light to be radiated onto an optical disk medium; and an aberration correction section for correcting an aberration of the laser light. The aberration correction section includes: a plurality of mirror sections for reflecting the laser light; a plurality of mirror driving sections for displacing the plurality of mirror sections; and a detection section for detecting a physical condition within the optical head device. | 2009-06-11 |
20090147637 | OPTICAL DISK REPRODUCING DEVICE AND PHASE-LOCKED LOOP CIRCUIT - Provided is an optical disk reproducing device for controlling false detection of synchronization signals due to intersymbol interference, and stably improving accuracy of frequency acquisition of a PLL even when offset and so on occur. A signal width close to an original mark length is obtained to use for frequency acquisition of the PLL by, for example, using two different slice thresholds and taking a width between a rising of a result of slicing at one threshold and a falling of a result of slicing at the other threshold as a synchronization signal width. When asymmetric properties due to offset, asymmetry, etc. occur, an amount of corrections on the slice threshold is calculated, and it is reflected on a threshold previously set to always obtain a correct synchronization signal width. | 2009-06-11 |
20090147638 | OPTICAL DISC REPRODUCING APPARATUS - In an optical disc reproducing apparatus, when an amount of light received by an optical pick-up varies or leakage light enters a light receiving portion due to the tilt of the optical pick-up or the like, a tracking control signal generation circuit adds an offset in accordance with a control value outputted from a tracking actuator controller to an output of a tracking servo filter. As a result, a tracking servo pull-in operation is performed in a state where the optical pick-up is forcibly tilted. The direction in which the optical pick-up mentioned above is forcibly tilted is determined from the result of, e.g., measuring the duty ratio of a DPD off-track signal. Therefore, a reproduction signal, a focus error signal, and a tracking error signal are correctly generated without providing a tilt mechanism in the optical pick-up. | 2009-06-11 |
20090147639 | OPTICAL DISK UNIT AND DRIVING METHOD THEREFOR - An optical disk drive according to the present invention has the ability to read data from multiple types of optical disks, each of which includes at least one information storage layer. The drive includes: a driving mechanism | 2009-06-11 |
20090147640 | Recording medium, and method and apparatus of controlling access to the recording medium - A recording medium, and a method and apparatus of controlling an access to the recording medium are disclosed. Physical access control (PAC) information that is pre-recorded on a recording medium is extracted. Then, a PAC identification is extracted from the PAC information. An access to the recording medium is controlled using first control information that is included in the PAC information, when the PAC identification is known. Alternatively, the access to the recording medium is controlled using second control information that is included in the PAC information, when the PAC identification is unknown. | 2009-06-11 |
20090147641 | Optical disc recording and reproducing apparatus - An optical disc recording and reproducing apparatus for recording and reproducing data in and from an optical disc by the use of the optical disc as a recording medium, comprises analog processing means including a binarization unit for subjecting a signal read from the optical disc to binarization and a servo unit for controlling recording and reproducing a signal in and from the optical disc; synchronous clock generating means for generating a synchronous clock signal which is synchronized with the signal read from the optical disc; address detecting means for detecting address information indicating a physical position on the optical disc based on the signal read from the optical disc, and outputting a signal indicating the address information and a signal indicating that the address has been detected when the address information has been detected; a sector counter for holding a sector count value of a sector as a recording unit on the optical disc, and updating the sector count value according to the synchronous clock signal and the signal output from the address detecting means; and gate signal generation switching means for generating gate a signal which controls the analog processing means, based on one of the sector count value held in the sector counter and information obtained from the analog processing means, according to the signal indicating that the address has been detected, which is output from the address detecting means. | 2009-06-11 |
20090147642 | APPARATUS FOR AND METHOD OF DETECTING TRACKING ERROR SIGNALS - An apparatus for detecting a tracking error signal includes an optical detector to receive light beams reflected from an optical disc and having a plurality of detecting regions; and a phase difference extracting unit to extract a phase difference between a pair of optical signals output from the optical detector, wherein the phase difference extracting unit repeatedly moves a first graph representing one optical signal from among the pair of optical signals by a predetermined distance with respect to a second graph representing another optical signal from among the pair of optical signals, the first and second graph represent optical signal values with respect to t-axis, adds differences between optical signal values of the first graph and optical signal values of the second graph corresponding to predetermined positions of the t-axis, the adding differences is repeated for each of the repeatedly moved positions of the first graph, and outputs a moved distance of a position where the added value is smallest as a phase difference. | 2009-06-11 |
20090147643 | MULTI-LAYER DATA STORAGE MEDIUM AND RECORDING LAYER IDENTIFICATION METHOD THEREOF - A multi-layer data storage medium includes a plurality of recording layers in which a guide groove, where data is stored, is formed in a spiral manner, and each center of the plurality of the recording layers is eccentric to a center of the multi-layer data storage medium in a different direction. | 2009-06-11 |
20090147644 | INFORMATION RECORDING METHOD, INFORMATION RECORDING APPARATUS, INFORMATION RECORDING PROGRAM AND RECORDING MEDIUM STORING INFORMATION RECORDING PROGRAM - An information recording apparatus and method can prevent an information recording medium having a plurality of recording layers from being incompatible with a reproduction-only information recording medium due to an unrecorded area, which is produced by completion of recording in a middle of a data area of the recording layer. The recording layers include at least a first recording layer and a second recording layer, the first recording layer providing a reference with respect to a position of said data area in each of the recording layers. The user data is recorded in response to a recording request. After recording the user data, predetermined data is recorded in a predetermined unrecorded area in the second recording layer. | 2009-06-11 |
20090147645 | METHOD FOR INSPECTING OPTICAL INFORMATION RECORDING MEDIUM, INSPECTION APPARATUS, OPTICAL INFORMATION RECORDING MEDIUM AND RECORDING METHOD - A method for inspecting an optical information storage medium includes the steps of: irradiating the storage medium with a laser beam and rotating the medium by a constant linear velocity control technique by reference to the radial location at which the laser beam forms a spot on the medium; changing the rotational velocities according to the radial location on the medium between at least two linear velocities that include a first linear velocity Lv | 2009-06-11 |
20090147646 | APPARATUS AND METHOD TO VISUALLY INDICATE THE STATUS OF A DATA STORAGE DEVICE - A data storage and retrieval system that comprises a data storage device is disclosed. The data storage and retrieval system further comprises a first LED, a second LED, a third LED, and a fourth LED, interconnected with the data storage device. The data storage device causes the first LED and the second LED to emit first light comprising a first color if the data storage device detects an internal failure. Alternatively, the storage device causes the third LED and the fourth LED to emit second light comprising a second color if the data storage device remains operative. | 2009-06-11 |
20090147647 | INFORMATION RECORDING METHOD AND INFORMATION RECORDING/REPRODUCING APPARATUS - To make the adjustment of a write-pulse parameter on the basis of a phase error between a readout signal and a clock signal applicable also to high-density optical discs. The channel bit length during trial writing is made larger than that during user-data recording. Then, a write-pulse parameter adjusted by the trial writing is applied as it is or with a predetermined correction to user-data recording. | 2009-06-11 |
20090147648 | MAXIMUM LIKELIHOOD SEQUENCE ESTIMATION DECODING - A Maximum Likelihood Sequence Estimator comprises a signal receiver ( | 2009-06-11 |
20090147649 | Sound Playback and Editing Through Physical Interaction - The disclosure relates to sound playback and editing apparatus. The editing apparatus uses user interaction to allow the user to instinctively modify recorded sound. This can be achieved by converting a quality of the user's physical interactions with the editing apparatus into instructions for processing the sound. For example, in one embodiment the user can mix sound files by ‘mixing’, i.e. shaking, physical representations of those sound files (such as the recording medium on which the files are stored) alone or together. | 2009-06-11 |
20090147650 | RECORDING APPARATUS AND RECORDING METHOD, AND COMPUTER PROGRAM - A recording apparatus for recording record data onto a recording medium on which a plurality of recording layers are formed in a thickness direction, is provided with: a recording device for recording the record data into each of the plurality of recording layers by emitting each of a plurality of recording light beams to be focused on a corresponding one of the plurality of recording layers; a calculating device for calculating a leaked beam feature of another recording light beam, which is emitted to be focused on another recording layer other than one recording layer of the plurality of recording layers, leaking to the one recording layer; and an adjusting device for adjusting an emission condition of at least one of the plurality of recording light beams, on the basis of the calculated leaked beam feature. | 2009-06-11 |
20090147651 | SINGLE BEAM SYSTEM FOR WRITING DATA USING ENERGY DISTRIBUTION PATTERNS - A system for creating microstructures for data storage on a substrate employs a single modulated beam to write the data. The microstructures created can be in the form of lines created by a stylus constituted by a laser beam. Using the subject system, the individual microstructures can be configured to varying depths to achieve greater data storage capacity for the same surface area of substrate. | 2009-06-11 |
20090147652 | OPTICAL DISC DEVICE AND OPTICAL INFORMATION RECORDING METHOD - An optical disc device that irradiates a light beam on an optical disc having a recording layer in which information is recorded and a positioning layer in which tracks for specifying a recording position of the information in the recording layer are provided includes an information recording unit that irradiates a light beam for information on a target position in the recording layer to record the information by shifting a position in an optical axis direction of the light beam for information, a terminal-end recognizing unit that recognizes, when new information is recorded in a recording layer having a recorded area in which information is already recorded, a terminal end of the recorded area, and a target-position setting unit that sets the target position to separate the terminal end of the recorded area and a start end of a recording planned area in which information is recorded anew. | 2009-06-11 |
20090147653 | Holographic content search engine for rapid information retrieval - An apparatus for information retrieval comprising a first holographic drive, configured to content-search holographic recording media (HRM), and to generate an address, and at least one data storage system, configured to receive the address generated by the first holographic drive and operable to retrieve information from said data storage system corresponding to the address received from said first holographic drive. | 2009-06-11 |
20090147654 | Sync mark correction for holographic data pages - The presented invention relates to a method for reading data from a data page from an optical data storage medium, e.g. a holographic storage medium and to an apparatus for performing this method. At least one missing or wrong positioned sync mark on a read data page is identified and its corrected position is estimated. The estimated corrected sync mark position is used for further processing. | 2009-06-11 |
20090147655 | Miniaturized disc drive containing DVD-compatible optical controller - A miniature optical disc drive includes a DVD-compatible optical controller and a cartridge load module designed to hold a cartridge containing a 32 mm optical data storage disc. | 2009-06-11 |
20090147656 | OPTICAL PICK UP AND OPTICAL DISC DEVICE - An optical pickup according to the present invention includes: a light source | 2009-06-11 |
20090147657 | Optical pickup device and objective lens used in the same - An optical system has an optical functional surface including a common region used for conducting information recording and/or reproducing for both of a first optical information recording medium and a second optical information recording medium. The common region comprises a refractive surface of an imaginary basic aspherical surface and a optical path difference providing structure in which plural ring-shapes zones are separated around the center of an optical axis and neighboring ring-shaped zones are displaced to each other in a direction of an optical axis so as to cause an optical path difference obtained by multiplying a predetermined wavelength λs (λ | 2009-06-11 |
20090147658 | OPTICAL HEAD AND OPTICAL INFORMATION RECORDER/REPRODUCER EMPLOYING IT - To provide an optical head capable of detecting tilt with high sensitivity for two kinds of optical recording media having different groove pitches, and to provide an optical information recording/reproducing device, diffraction optical elements split emitted light from a light source into a main beam, a first sub-beam (diffracted light from a region of the diffraction optical element, and a second sub-beam (diffracted light from a region of the diffraction optical element). The region of the diffraction optical element has a diameter larger than that of the region of the diffraction optical element. A push-pull signal by the first sub-beam under track-servo is employed as a radial tilt error signal for an optical recording medium having a narrow groove pitch, and a push-pull signal by the second sub-beam under track-servo is employed as a radial tilt error signal for an optical recording medium having a wide groove pitch. | 2009-06-11 |
20090147659 | OBJECTIVE LENS UNIT, OPTICAL PICKUP, AND OPTICAL INFORMATION DEVICE - An objective lens unit according to the present invention includes a first objective lens | 2009-06-11 |
20090147660 | OPTICAL DISC APPARATUS, POSITION CONTROL METHOD AND OPTICAL PICKUP - An optical disc apparatus can make the focus of an information light beam converged by an objective lens agree with a target track of a target mark layer of an optical disc by appropriately predefining the distance between the focus of a servo light beam and that of the information light beam with regard to the direction of the thickness and a radial direction of the optical disc by means of the optical pickup of the apparatus and then operating for focus control and tracking control of the objective lens so as to make focus of the servo light beam converged by the objective lens agree with a reference track of a reference mark layer. | 2009-06-11 |
20090147661 | Optical Information Processing Apparatus, Optical Pick-Up Device And Optical Recording Disc System - An optical pick-up device includes a laser source enabling emission of at least two light beams with different wavelengths, an objective lens which focuses the light beams emitted from the laser source on an optical disc, an optical detector which receives a light reflected from the optical disc, a front monitor which receives a part of the light beams emitted from the laser source, a front monitor light-guiding plate which guides part of the light beams emitted from the laser source to the front monitor. The front monitor light-guiding plate is arranged between the laser source and the objective lens, at least a part of a region of the front monitor light-guiding plate illuminated by the light beams emitted from the laser source has a predetermined shape which causes the light beams to change traveling direction thereof by refraction and then be guided to the front monitor. | 2009-06-11 |
20090147662 | DISK DEVICE - A disk device includes a frame, an optical pickup and a shock absorbing component. The frame has a receiving component. The optical pickup is slidable with respect to the frame. The shock absorbing component is fixedly coupled to the optical pickup and arranged to selectively contact the receiving component of the frame. The shock absorbing component includes a support portion and a spring piece. The spring piece has a first end portion that is fixedly coupled to the optical pickup and a second end portion that is spaced from the support portion in an unloaded rest state and that contacts the support portion to support the spring piece at both the first and second end portions with respect to the optical pickup when the spring piece is pushed by the receiving component of the frame to a loaded state. | 2009-06-11 |
20090147663 | METHOD AND APPARATUS FOR READING OPTICAL DISCS HAVING DIFFERENT CONFIGURATIONS - A player is provided that is capable of playing discs of either a first or a second configuration. Both types of discs can be double-sided optical discs formed with data tracks. In one configuration, the tracks on one side follow one spiral while the tracks on the other side follow a second spiral, the two spirals being oriented in opposite directions as viewed from the respective sides, and therefore being mirror images of each other. This allows data to be read by a player seamlessly from both sides of the disc without changing the direction of rotation of the disc. In the other configuration, the tracks follow identical spirals. The disc is then rotated in one direction for one side and the other direction for the other side. | 2009-06-11 |
20090147664 | OPTICAL DISK READ ONLY MEMORY - An optical disk read only memory having an information recording surface with a concave-convex pattern formed on the basis of a first signal and a reflective film covering the surface. The disc medium includes: an additional information recording section formed on a recording track of a first data string; and a second data string including a mark of removing or reducing the reflective film. The modulation methods of the first and the second data strings are identical, and Lh(n)>Lp | 2009-06-11 |
20090147665 | OPTICAL DISC RECORDING DEVICE AND OPTICAL DISC RECORDING SYSTEM - When recording is carried out in a DVD-RAM, if at least one address mark could have been detected at the header section, after a test light emission for a laser power control is carried out at a GAP section, normal recording is carried out from GUARD | 2009-06-11 |
20090147666 | METHOD, SYSTEM AND DEVICE FOR xDSL CROSSTALK CANCELLATION - A method and system for xDSL crosstalk cancellation is provided. The method includes dividing xDSL signals into a plurality of signal sets; and connecting signals from a same signal set to a same processing unit to be processed. A digital subscriber line access multiplexer (DSLAM) includes a line switching control module and at least one processing unit. | 2009-06-11 |
20090147667 | APPARATUS AND METHOD FOR DETECTING PACKET OF ZERO-PADDED OFDM SIGNAL - Provided is an apparatus and method for detecting a packet of a zero-padded OFDM signal, which are capable of determining if a packet exists in a reception (RX) signal by comparing a cross-correlation value of an OFDM signal delayed by a predetermined sample time, e.g., a zero-padded sample time, with a power value of the RX signal, thereby increasing a packet detection probability and preventing a false alarm. The packet detecting apparatus includes: a cross-correlation calculator for calculating a cross-correlation value of a reception signal received from the outside and delaying the calculated cross-correlation value by a predetermined sample time; a power calculator for calculating a power value of the reception signal; and a packet detector for determining if a packet exists in the reception signal by comparing the delayed cross-correlation value with the calculated power value, and detecting the corresponding packet. | 2009-06-11 |
20090147668 | Orthogonal pilot code construction - A method, system and apparatus for communication in an Orthogonal Frequency Division Multiplexing (OFDM) communication system is provided. The method includes allocating a plurality of sequences to a plurality of sectors in the OFDMA communication system. The plurality of sequences are orthogonal to each other. The method further includes communicating one or more OFDM tiles between one or more MSs in one or more sectors of the plurality of sectors and one or more BSs of the one or more sectors. The one or more OFDM tiles include one or more sequences of the plurality of sequences allocated to the one or more sectors. | 2009-06-11 |
20090147669 | CONTINUOUS PHASE MODULATION ENCODER FOR WIRELESS NETWORKS - Various example embodiments are disclosed herein. According to an example embodiment, an apparatus for use in a wireless transmitter may include a phase encoder adapted to generate a continuous time signal based on a symbol and a corresponding modulation index for a current symbol interval and one or more previous symbol intervals and based on a continuous phase modulation (CPM) phase response function, a filter and symbol-rate sampler adapted to filter and then symbol rate sample the continuous time signal to generate a symbol-rate statistic that is representative of the continuous time signal for each of the symbol intervals; a mapping circuit adapted to map each of the plurality of symbol-rate statistics to a corresponding constant modulus CPM symbol, and a transmitter circuit adapted to transmit a signal based on the constant modulus CPM symbols. | 2009-06-11 |
20090147670 | METHOD, SYSTEM AND DEVICE FOR RECOVERING INVALID DOWNLINK DATA TUNNEL BETWEEN NETWORKS - Described herein is a method for processing an invalidation of a downlink data tunnel between networks. The method includes the following steps: (1) a core network user plane anchor receives an error indication of data tunnel sent from an access network device, (2) after deciding that the user plane corresponding to the error indication uses a One Tunnel technology, the core network user plane anchor notifies a relevant core network control plane to request recovering the downlink data tunnel, (3) the core network control plane recovers the downlink data tunnel and notifies the core network user plane anchor to update information of the user plane. In addition, a communication system and a communication device are also provided. The method, system, and device can improve the speed of recovering data transmission after the downlink data tunnel becomes invalid. | 2009-06-11 |
20090147671 | SYSTEM FOR TESTING THE UPSTREAM CHANNEL OF A CABLE NETWORK - A system for testing a portion of a cable network provides a pattern generator, Addresser, forward error corrector, and comparator. The system is particularly adapted to testing the upstream channel in a cable network. The pattern generator generates a test signal. The addresser addresses the signal to a known server and also instructs the known server to return the test signal to the test system. The forward error corrector corrects errors introduced in the test signal in transmission from the known server to the test system. The comparator then compares the returned test signal to the originally transmitted test signal to determine the performance of the back channel. Preferably, the comparator uses a bit error rate test to determine the performance of the back channel. | 2009-06-11 |
20090147672 | PROTECTION SWITCHING METHOD AND APPARATUS FOR USE IN RING NETWORK - A protection switching method and apparatus for use in a ring network are provided. At least two switching request signals are received from a network device neighboring a link in which a failure occurs. A switching operation is performed in response to a first received signal of the at least two received switching request signals. When a network failure occurs, fast protection switching can be performed. | 2009-06-11 |
20090147673 | STORAGE SYSTEM AND ROUTE SWITCH - A storage system includes a route switch, connected to at least two different communication lines different in path between each of switches and the route switch. Upon detecting a fault on a communication line extending to the switch, the route switch converts a destination address of a frame into a modified address in accordance with an address conversion table. The route switch thus controls a frame exchanged between a calculation device and each of the switches. | 2009-06-11 |
20090147674 | LOOP PREVENTION TECHNIQUES USING ENCAPSULATION MANIPULATION OF IP/MPLS FIELD - In one embodiment, an edge device communicates with a neighboring routing domain. A failure that prevents communication between the edge device and the neighboring routing is detected. When the edge device thereafter receives a data packet that is directed to the neighboring routing domain, it determines if the received data packet was rerouted to the edge device from another edge device coupled to the neighboring routing domain. If the received data packet was not rerouted to the edge device from another edge device coupled to the neighboring routing domain, the edge device reroutes the received data packet to another edge device for forwarding to the neighboring routing domain. However, if the received data packet was rerouted to the edge device from another edge device coupled to the neighboring routing domain, the edge device prevents the received data packet from being rerouted a second time to prevent loops. | 2009-06-11 |