24th week of 2009 patent applcation highlights part 19 |
Patent application number | Title | Published |
20090146675 | PLANARIZING PROBE CARD - A novel planarizing probe card for testing a semiconductor device is presented. The probe card is adapted to come into contact with a probe card mount that is in adjustable contact with the prober. The probe card includes a printed circuit board affixed to a stiffener and a probe head that is in electrical contact with the printed circuit board. The probe head also includes a plurality of probe contactor tips that define a first plane. The stiffener further contains at least two planarizing adjusters that comes into contact with the probe card mount. The adjusters may be actuated to alter the position of first plane. A surface of the semiconductor device under test may define a second plane, and the adjusters may be adjusted to position the first plane to be substantially parallel to the second plane. | 2009-06-11 |
20090146676 | Measuring module for rapid measurement of electrical, electronic and mechanical components at cryogenic temperatures and measuring device having such a module - Measuring module for the measurement of an object ( | 2009-06-11 |
20090146677 | TEST APPARATUS AND PIN ELECTRONICS CARD - There is provided a test apparatus including a driver that outputs a test signal to a device under test, a first switch that switches whether to connect the driver to the device under test, a comparator that receives an output signal from the device under test via the first switch, and compares a voltage of the output signal with a predetermined reference voltage, a reference voltage input section that inputs the reference voltage into the comparator, a second switch that is provided between the reference voltage input section and the comparator, and a dummy resistance that is connected at one end thereof to a connection point between the comparator and the second switch and at the other end thereof to a predetermined potential. Here, a resistance ratio between an output resistance of the driver and an on-resistance of the first switch is substantially equal to a resistance ratio between the dummy resistance and an on-resistance of the second switch. | 2009-06-11 |
20090146678 | SUBSTRATE TESTING CIRCUIT - The present invention relates to a substrate testing circuit comprising a testing bus and a testing signal terminal connected to the testing bus, a signal line to be tested in the substrate being connected to the testing bus via a signal connecting terminal, wherein a plurality of signal access terminals are provided on the testing bus; one testing branch is connected between each the signal access terminal and the testing signal terminal; and resistance values of the testing branches are the same. By means of the present invention, since a plurality of signal access terminals are introduced and the testing branches with the same resistance are added so that input resistances and impedances of testing signals across the display screen are substantially identical without making changes to process flow and device hardware structure, input resistances and impedances of respective signal lines are well averaged, thereby no obvious regional attenuation occurs in the testing signals within the pixel area to be tested irrespective of limitation in size of panel, so as to realize tests for panels with greater sizes. | 2009-06-11 |
20090146679 | Method for testing liquid crystal display - An LCD test method and apparatus for reducing the number of channels of a probe unit is provided. An apparatus for testing a liquid crystal display including: a stage on which a liquid crystal panel is placed; a plurality of vertically divided blocks, wherein each of the vertically divided blocks include a plurality of adjacent data lines; a data probe unit that provides test pattern signals respectively to groups of at least two of the plurality of vertically divided blocks of the liquid crystal panel; a plurality of horizontally divided blocks, wherein each of the horizontally divided blocks include a plurality of adjacent gate lines; a gate probe unit that provides scanning signals respectively to the plurality of horizontally divided blocks of the liquid crystal panel; and a controller that provides test pattern signals to the data probe unit and provides scanning signals to the gate probe unit. | 2009-06-11 |
20090146680 | SELF-GUIDING INSTRUMENT CARRIER FOR IN-SITU OPERATION IN A GENERATOR - Removal of the rotor of a large electrical machine is costly and time consuming, and in particular the outage time of a power plant, which is needed for the removal of a generator rotor, is very expensive and should be minimized. To avoid opening of the generator for inspection and maintenance instrument carriages can be used. A method allows the reliable guidance for an in-situ instrument carrier inside the annular gap of a generator and a corresponding instrument carrier. The method avoids the use of sensors and active control systems for the guidance of the instrument carrier. A passively self-guiding system and method takes advantage of the internal structure of a generator and uses the passive centering properties of magnets to guide the instrument carrier through the annular gap of a generator. | 2009-06-11 |
20090146681 | METHOD AND APPARATUS FOR ESTIMATING RESISTANCE AND CAPACITANCE OF METAL INTERCONNECTS - Techniques for estimating resistance and capacitance of metal interconnects are described. An apparatus may include an interconnect, a set of pads, a set of isolation circuits, and a test circuit. The set of pads may be coupled to the interconnect and used for simultaneously applying a current through the interconnect and measuring a voltage across the interconnect. The current and voltage may be used to estimate the resistance of the interconnect. The test circuit may charge and discharge the interconnect to estimate the capacitance of the interconnect. The isolation circuits may isolate the pads from the interconnect when the test circuit charges and discharges the interconnect. The apparatus may further include another interconnect, another set of pads, and another set of isolation circuits that may be coupled in a mirror manner. Resistance and/or capacitance mismatch between the two interconnects may be accurately estimated. | 2009-06-11 |
20090146682 | DATA OUTPUT DRIVING CIRCUIT AND METHOD FOR CONTROLLING SLEW RATE THEREOF - A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control signals by using a code signal, and a plurality of drivers configured to output data by driving the data at a slew rate set according to the slew rate control signals. | 2009-06-11 |
20090146683 | CALIBRATION CIRCUIT OF ON-DIE TERMINATION DEVICE - A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node and a reference voltage, to generate calibration codes. The calibration unit also includes a calibration resistor unit having parallel resistors which are turned on/off in response to each of the calibration codes and connected to the calibration node, a turn-on strength of at least one of the parallel resistors being controlled by a control signal. | 2009-06-11 |
20090146684 | CIRCUIT FOR CONTROLLING DRIVER OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - A circuit for controlling a driver of a semiconductor memory apparatus includes a driving unit having an impedance that is set according to a code value; a driving reinforcing control unit configured to output an adjustment code for a predetermined time; and a driving reinforcing unit configured to output a reinforcing code obtained by adjusting the code value using the adjustment code, wherein the reinforcing code reinforce a driving capability of the driving unit. | 2009-06-11 |
20090146685 | CALIBRATION CIRCUIT OF ON-DIE TERMINATION DEVICE - A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node connected to an external resistor and a reference voltage to generate pull-up calibration codes. The calibration circuit also includes a pull-up calibration resistor unit configured to pull up the calibration node in response to the pull-up calibration codes. The pull-up calibration resistor unit is calibrated such that its resistance becomes higher as a power supply voltage increases. | 2009-06-11 |
20090146686 | Configuration Context Switcher with a Latch - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 2009-06-11 |
20090146687 | INTEGRATED CIRCUIT FEATURE DEFINITION USING ONE-TIME-PROGRAMMABLE (OTP) MEMORY - In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser. | 2009-06-11 |
20090146688 | Methods of reducing power in programmable devices using low voltage swing for routing signals - Reduced voltage swing signal path circuitry is provided that lowers the internal signaling power consumption of the interconnection resources of a programmable logic device. The reduced voltage swing signal path circuitry includes a reversed routing driver circuitry to limit the voltage range of the output signal of the driver circuitry. | 2009-06-11 |
20090146689 | Configuration Context Switcher with a Clocked Storage Element - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 2009-06-11 |
20090146690 | RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL - A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers. | 2009-06-11 |
20090146691 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 2009-06-11 |
20090146692 | Structure for apparatus for reduced loading of signal transmission elements - A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. A signal-handling apparatus may include an isolating circuit coupled to a first conductor, a second conductor to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. A signal-handling circuit can perform a signal-handling function in response to the output of the isolating circuit. The signal-handling circuit and the first circuit may be isolated from the second conductor and the signal-handling circuit such that a communication signal may be conducted with less capacitance and be subject to less return loss. | 2009-06-11 |
20090146693 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential. | 2009-06-11 |
20090146694 | CIRCUIT AND METHOD FOR PREVENTING BANG-BANG ERROR, CALIBRATION CIRCUIT INCLUDING THE CIRCUIT, AND ANALOG-TO-DIGITAL CONVERTER INCLUDING THE CIRCUIT - A circuit including a comparing unit for comparing a target voltage with a stepwise-varying tracking voltage, a counting unit for counting a code according to the comparison result of the comparing unit and a control signal generating unit for generating a signal for controlling a counting operation of the counting unit. | 2009-06-11 |
20090146695 | HYBRID IC FOR ULTRASOUND BEAMFORMER PROBE - A hybrid integrated circuit package for a microbeamformer in an ultrasound probe includes a substrate, a driver circuit for generating transmit pulses to be transmitted to the transducer elements of the probe for producing a transmit beam, and a beamformer circuit including time delay circuits and a summation circuit, the time delay circuits being operatively arranged for receiving a plurality of reflected pulses from the transducer elements and delaying the reflected pulses and the summation circuit operatively arranged summing groups of the delayed reflected pulses for producing beamformed signals. The driver circuit is part of a high voltage integrated circuit device including said driver circuit. At least a portion of the beamformer circuit is part of a low voltage integrated circuit device, wherein the high voltage integrated circuit and the low voltage integrated circuit are mounted on the substrate. | 2009-06-11 |
20090146696 | CLASS-AB DRIVER DESIGN WITH IMPROVED FREQUENCY RESPONSE - A class-AB driver design with improved frequency response is disclosed. In one embodiment, the class-AB driver includes a push-pull output stage, a trans-linear loop, an input stage, a current biasing and enabling circuit. Further, the trans-linear loop is coupled to a signal input terminal AB | 2009-06-11 |
20090146697 | CIRCUIT FOR BUFFERING HAVING A COUPLER - The buffer circuit includes a differential amplifier differentially amplifying a reference node corresponding to a reference voltage and an input node corresponding to the input signal by sensing a potential difference of the reference voltage and the input signal. A coupling unit couples the input signal to the reference node, making it possible to improve the operating speed of the buffer circuit and operate normally when a level of the input signal or the reference voltage becomes low. | 2009-06-11 |
20090146698 | DRIVING CIRCUIT AND A PIXEL CIRCUIT INCORPORATING THE SAME - A driving circuit includes: a switch unit operable according to a scan signal, and adapted for permitting transfer of a data signal when operating in an on state; a capacitor having a first end that is coupled to the switch unit, and a second end; a first transistor having a first terminal that is adapted for coupling to a voltage source, a second terminal that is coupled to the second end of the capacitor and that is adapted to be coupled to a load, and a control terminal that is coupled to the first end of the capacitor; and a second transistor having a first terminal that is adapted for coupling to the voltage source, a second terminal coupled to the second terminal of the first transistor, and a control terminal that is adapted for receiving a bias voltage. Each of the first and second transistors operates in the linear region. | 2009-06-11 |
20090146699 | DUAL-MODULUS PRESCALER CIRCUIT OPERATING AT A VERY HIGH FREQUENCY - The dual-modulus prescaler circuit ( | 2009-06-11 |
20090146700 | DUTY RATIO CORRECTION CIRCUIT - A duty ratio correction circuit including a reference clock generation block configured to generate first and second reference clocks that synchronize with rising and falling edges of an external clock and have a primarily corrected duty ratio, and a duty ratio adjustment block for generating first and second internal clocks in response to the first and second reference clocks, and secondarily correcting a duty ratio of the first and second reference clocks by adjusting phases of the first and second reference clocks by means of plural digital control signals generated according to phase difference between the first and second internal clocks. | 2009-06-11 |
20090146701 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER - A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection. | 2009-06-11 |
20090146702 | CHARGE PUMP AND METHOD FOR OPERATING THE SAME - A charge pump comprises a ring oscillator and a pumping circuit. The ring oscillator provides a plurality of oscillating clocks. The pumping circuit includes a plurality of pumping blocks coupled to each other for outputting a boosted voltage, and each pumping block is connected to a corresponding oscillating clock. | 2009-06-11 |
20090146703 | OSCILLATION CIRCUIT, TEST APPARATUS AND ELECTRONIC DEVICE - Provided is an oscillation circuit for generating an oscillation signal synchronized with a supplied reference clock, including: a voltage control oscillation section that, when triggered by each edge of the reference clock, stops oscillation of the oscillation signal having a frequency in accordance with a supplied control voltage to start new oscillation; a phase comparing section that compares a phase of a comparison signal that is in accordance with the oscillation signal outputted from the voltage control oscillation section and a phase of a signal that is in accordance with the reference clock; and a voltage control section that supplies the control voltage in accordance with a comparison result of the phase comparing section, to the voltage control oscillation section. | 2009-06-11 |
20090146704 | DELAY LOCKED LOOP CIRCUIT AND METHOD FOR ELIMINATING JITTER AND OFFSET THEREIN - A delay locked loop (DLL) circuit is provided. The DLL circuit includes a divider, a shift register, a digital-to-analog converter and a voltage controlled delay line. The divider divides an input clock signal to output a reference clock signal. The shift register is triggered by the reference clock signal and outputs a digital signal corresponding to the reference clock signal in accordance with a phase difference between the input clock signal and a feedback clock signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback clock signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed. | 2009-06-11 |
20090146705 | DELAY LOCKED LOOP CIRCUIT AND METHOD FOR ELIMINATING JITTER AND OFFSET THEREIN - A delay locked loop circuit (DLL) is provided. The delay locked loop circuit includes a shift register, a digital-to-analog converter and a voltage controlled delay line. The shift register outputs a digital signal in accordance with a phase difference between an input signal and a feedback signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input signal and an output signal in a delay locked loop circuit is also disclosed. | 2009-06-11 |
20090146706 | DLL CLOCK SIGNAL GENERATING CIRCUIT CAPABLE OF CORRECTING A DISTORTED DUTY RATIO - A DLL (Delay Locked Loop) clock signal generating circuit includes a duty correction buffer for receiving a first clock signal and a second clock signal, producing a first internal clock signal and a second internal clock signal, and correcting duty ratios of the first and second internal clock signals based on a reference signal which is controlled by a duty ratio of the first internal clock signal, and an edge trigger unit for a DLL clock signal which has a first level when the first internal clock signal is activated and which has a second level when the second internal clock signal is activated. | 2009-06-11 |
20090146707 | DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes an initial operation setting unit configured to generate an initial operation signal in response to a reference clock signal and an operation start signal; a shift register configured to generate a delay control code in response to the initial operation signal, a phase comparison signal, and an initial setting code; a delay line configured to delay the reference clock signal or a feedback clock signal in response to the initial operation signal and the delay control code, thereby generating a plurality of unit delay clock signals; and an initial delay monitoring unit configured to generate the initial setting code in response to the reference clock signal and the plurality of unit delay clock signals. | 2009-06-11 |
20090146708 | DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of a first delay line and to output a first delay amount information signal, a second delay control unit configured to generate a second delay control signal in response to a second phase detection signal to control a delay amount of a second delay line and to output a second delay amount information signal, and to control the delay amount of the second delay line again in response to the first delay control signal and a half cycle information signal, a half cycle detecting unit configured to receive the first delay amount information signal and the second delay amount information signal to extract half cycle information of a reference clock signal, thereby generating the half cycle information signal, and a duty cycle correcting unit configured to combine an output clock signal from the first delay line and an output clock signal from the second delay line, thereby outputting a duty ratio correction clock signal. | 2009-06-11 |
20090146709 | DELAY CIRCUIT OF DELAY LOCKED LOOP HAVING SINGLE AND DUAL DELAY LINES AND CONTROL METHOD OF THE SAME - A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal. | 2009-06-11 |
20090146710 | Signal generating circuit - A signal generating circuit includes an input stage delay circuit which can switch a state of outputting a reference clock and a state of outputting a signal delaying the reference clock by a first time which is shorter than one cycle of the reference clock, a control section including a gate circuit holding the output of the input stage delay circuit for a second time which is shorter than one cycle of the reference clock from a point at which the output of the input stage delay circuit is changed to output a signal corresponding to the output of the gate circuit, and an output stage delay circuit outputting a signal delaying the output signal of the control section by the second time, in which the input stage delay circuit switches an output state in response to change of the output signal of the control section. | 2009-06-11 |
20090146711 | CLOCK SIGNAL GENERATING CIRCUIT, DISPLAY PANEL MODULE, IMAGING DEVICE, AND ELECTRONIC EQUIPMENT - A delay synchronization loop type clock signal generating circuit includes: a delay line for delaying a first clock signal by a set delay amount and outputting; a delay time length setting unit for setting a delay time length of the delay line, based on phase difference between a second clock signal output from an output terminal and the first clock signal; a phase relation determining unit for determining whether or not the phase relation of the first clock signal and the second clock signal are in a particular phase relation; and a phase inversion/non-inversion unit for performing phase inversion of the first clock signal on a transmission path including the delay line, at the time of detecting the particular phase relation. | 2009-06-11 |
20090146712 | DELAY-LOCKED LOOP (DLL) SYSTEM FOR DETERMINING FORWARD CLOCK PATH DELAY - A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line having a plurality of delay stages. The DLL system also includes a measure shot device configured to determine a forward clock path delay of the DLL system. The measure shot device is configured to provide a calibration sequence into the DLL loop and to detect the calibration sequence after the calibration sequence has passed through the DLL loop. The measure shot device is further configured to count the number of clocks for a period of time between providing and detecting the calibration sequence. The number of clocks can be used to calibrate components of the DLL system. | 2009-06-11 |
20090146713 | CLOCK SIGNAL GENERATING CIRCUIT, DISPLAY PANEL MODULE, IMAGING DEVICE, AND ELECTRONIC EQUIPMENT - A delay synchronization loop type clock signal generating circuit includes: a digital delay line for delaying a first clock signal and generating a second clock signal; a ring-type shift register for setting the delay time length of the digital delay line by flip-flop output of each stage thereof; and a delay amount control unit for controlling supply of shift clocks to the ring-type shift register, based on phase relation between the first clock signal and the second clock signal. | 2009-06-11 |
20090146714 | DRIVER CIRCUIT - A driver circuit facilitates reducing noises and losses and improving the driving performances thereof without connecting a series circuit of capacitor and a resistor to the gate of IGBT. The driver circuit includes a slope setting circuit that sets the gate voltage waveform of IGBT; and an operational amplifier that includes a non-inverting input terminal, to which an output voltage V* from slope setting circuit is inputted, and an inverting input terminal, to which a divided voltage Vgsf divided by resistors is inputted; and the operational amplifier outputs an output voltage Vout, proportional to the difference between the output voltage V* and the divided voltage Vgsf, to the gate of IGBT. | 2009-06-11 |
20090146715 | DUTY CYCLE CALIBRATION FOR RECEIVER CLOCK - Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed. | 2009-06-11 |
20090146716 | Timing control circuit, timing generation system, timing control method and semiconductor memory device - A timing control circuit DLY | 2009-06-11 |
20090146717 | INCREASING CHARGE CAPACITY OF CHARGE TRANSFER CIRCUITS WITHOUT ALTERING THEIR CHARGE TRANSFER CHARACTERISTICS - A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers. | 2009-06-11 |
20090146718 | DELAY CIRCUIT - A delay circuit is disclosed for providing highly stable delay time in digital signal processing. The delay circuit includes a preliminary charging/discharging circuit, a signal processing circuit and an output circuit. The preliminary charging/discharging circuit performs charging and discharging operations based on a logic input signal for generating a voltage signal. The signal processing circuit performs signal processing on the voltage signal for generating a first delay signal and a second delay signal. The output circuit performs logic signal processing on the first and second delay signals for generating a logic output signal lagging behind the logic input signal by a delay time. The delay time is independent of any supply voltage. That is, even though the supply voltage is unstable, the delay circuit is capable of generating a stable logic output signal by performing a signal delay process on a logic input signal regardless of the unstable supply voltage. | 2009-06-11 |
20090146719 | Control Voltage Generator for a Clock, Frequency Reference, and Other Reference Signal Generator - Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, a control voltage generator adapted to provide a temperature-dependent control voltage; and a plurality of variable reactance modules. The reference resonator generates a first reference signal having a resonant frequency, and each reactance module is adapted to modify a corresponding reactance in response to the control voltage to maintain the resonant frequency substantially constant or within a predetermined variance over a predetermined temperature range. A frequency controller may also be included to maintain substantially constant a magnitude of a peak amplitude of the first reference signal and maintains substantially constant a common mode voltage level of the reference resonator. | 2009-06-11 |
20090146720 | PULSE GENERATOR - A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent. | 2009-06-11 |
20090146721 | OOB (OUT OF BAND) DETECTION CIRCUIT AND SERIAL ATA SYSTEM - The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register. | 2009-06-11 |
20090146722 | Systems and Arrangements to Provide Input Offset Voltage Compensation - In one embodiment a method is disclosed that includes applying a series of voltages to an input of an offset evaluation latch, detecting an offset voltage from the offset evaluation latch in response to the application of the series of voltages, and applying an offset compensation voltage to the input of a plurality of sampling latch in response to the detected offset voltage. In some embodiments a digital value can be assigned to the applied offset voltage. When the offset voltage is determined, it can be applied to a plurality sampling latches and a data stream can be received and clock and data recovery can be performed. | 2009-06-11 |
20090146723 | BUFFER CIRCUIT - Disclosed is a buffer circuit including a source follower circuit comprising a MOS transistor which is driven by a current source. The MOS transistor has a gate to which an input voltage is supplied, a source from which an output voltage is output and a back gate supplied with a back gate voltage for being controlled to provide for a desired value of the source voltage. There is provided a second MOS transistor, to a gate of which a bias voltage is supplied, and a source of which is connected to a non-inverting input terminal of an OP amp. An output voltage of the OP amp is supplied as the back gate voltage | 2009-06-11 |
20090146724 | SWITCHING CIRCUIT FOR MILLIMETER WAVEBAND CONTROL CIRCUIT - Provided is a switching circuit for a millimeter waveband control circuit. The switching circuit for a millimeter waveband control circuit includes a switching cell disposed on a signal port path to match an interested frequency and including at least one transistor coupled vertically to an input/output transmission line and a plurality of ground via holes disposed symmetrically in an upper portion and a lower portion of the input/output transmission line; capacitors for stabilizing a bias of the switching cell; and bias pads coupled in parallel to the capacitor to control the switching cell. Therefore, the switching circuit may be useful to improve its isolation by simplifying its design and layout through the use of symmetrical structure of optimized switching cells without the separate use of different switch elements, and also to reduce its manufacturing cost through the improved yield of the manufacturing process and the enhanced integration since it is possible to reduce a chip size of an integrated circuit in addition to its low insertion loss. | 2009-06-11 |
20090146725 | TEMPERATURE SENSOR CIRCUIT - Disclosed is a temperature sensor circuit including a bipolar differential pair driven by a constant current and having an emitter area ratio of 1:N (N>1) and two MOS transistors having the transistor size ratio of K:1 (K>1) connected as an active load to the bipolar differential pair. A reference voltage is applied to one of the transistors of the bipolar differential pair. The other transistor has a base and a collector connected together. A desired voltage is output between the bases of the two transistors of the bipolar differential pair. A plural number of the temperature sensor circuits may be connected in cascade ( | 2009-06-11 |
20090146726 | DELAY CIRCUIT WITH CONSTANT TIME DELAY INDEPENDENT OF TEMPERATURE VARIATIONS - A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting receiver and the resistive element; a first transistor, having lower turned ON voltage at higher temperature; a second transistor, used for generating a rail to rail signals on a terminal of the first transistor; and an output inverter, having an input node coupled to the first transistor and an output node for outputting an output signal of the delay circuit. Further, a third transistor is used for enhancing pulling low of the output signal of the delay circuit. | 2009-06-11 |
20090146727 | VOLTAGE GENERATING APPARATUS - A voltage generating apparatus including a current source, a first voltage source, a second voltage source, a first differential pair, a second differential pair, a voltage divider and a current mirror is provided. The voltage divider is used for reducing a voltage with a negative temperature coefficient, so as to reduce the amplification ratio of the voltage with a positive temperature coefficient used for compensating the negative temperature coefficient. | 2009-06-11 |
20090146728 | GENERIC VOLTAGE TOLERANT LOW POWER STARTUP CIRCUIT AND APPLICATIONS THEREOF - Circuits and systems including a startup circuit coupled to a reference source for providing startup current to the reference source wherein no transistor of the startup circuit experiences a stress condition and wherein the startup circuit consumes no static current following stabilized, steady-state operation of the reference source. | 2009-06-11 |
20090146729 | CONSTANT VOLTAGE CIRCUIT, CONSTANT VOLTAGE SUPPLY SYSTEM AND CONSTANT VOLTAGE SUPPLY METHOD - An input voltage signal VIN to be inputted to a gate terminal of a PMOS transistor M1 is converted to a voltage value which was level shifted at the source terminal by an inter-terminal voltage between the gate and source of the PMOS transistor M1. This conversion is carried out in accordance with a bias current I1 flowing from the constant current source IS through the source terminal of the PMOS transistor M1. The voltage thus converted is outputted from a source follower circuit through a capacitative element C1. A low-pass filter is constituted of the impedance of the PMOS transistor M1 and the capacitative element C1 in a signal path extending from the input voltage signal VIN to the source follower circuit. | 2009-06-11 |
20090146730 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit generating bandgap reference voltage/current. The bandgap reference circuit generates a negative temperature coefficient current (I | 2009-06-11 |
20090146731 | REFERENCE VOLTAGE GENERATING CIRCUIT AND POWER SUPPLY DEVICE USING THE SAME - A disclosed reference voltage generating circuit for generating a reference voltage includes MOSFETs connected in series or in parallel. At least one of the MOSFETs includes a control gate and a floating gate that is made hole-rich or discharged by ultraviolet irradiation, and the reference voltage generating circuit is configured to output the difference between threshold voltages of a pair of the MOSFETs as the reference voltage. | 2009-06-11 |
20090146732 | Constant Current Source Circuit - The present invention discloses a constant current source circuit with energy saving and over voltage protection to provide a constant current source circuit with less elements, simple circuitry, energy saving and over voltage protection. The present invention includes a regulating circuit ( | 2009-06-11 |
20090146733 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit provided with: a transistor M | 2009-06-11 |
20090146734 | Charge Recycling (CR) in Power Gated Complementary Metal-Oxide-Semiconductor (CMOS) Circuits and in Super Cutoff CMOS (SCCMOS) Circuits - In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a first virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to ground via a second sleep transistor, a second virtual ground node between the second circuit block and the second sleep transistor, and a transmission gate (TG) or a pass transistor connecting the first virtual ground node to the second virtual ground node to enable charge recycling between the first circuit block and the second circuit block during transitions by the first circuit block from active mode to sleep mode and the second circuit block from sleep mode to active mode or vice versa. | 2009-06-11 |
20090146735 | SWITCHED CAPACITOR RESONATOR AND SIGMA-DELTA MODULATOR USING THE SAME - Provided is a switched capacitor resonator including at least one integrator circuit having a differential operational amplifier and a sub feedback circuit configured with a switched capacitor circuit. A main feedback circuit connecting main input and output terminals of the switched capacitor resonator to each other may be configured with the switched capacitor circuit. The main feedback circuit may be connected to the sub feedback circuit included in one of the integrator circuits. A capacitor of the main feedback circuit can serve as an integration capacitor connected between the input and output terminals of the differential operational amplifier. Consequently, it is possible to improve an operating speed by reducing a settling time constant of the integrator circuit. | 2009-06-11 |
20090146736 | Baseband-Derived RF Digital Predistortion - A baseband-derived RF predistortion system using a lookup table having coefficients extracted at baseband and then applied at RF by means of a vector modulator. The architecture combines the narrowband advantage of envelope predistortion with the accuracy of baseband predistortion, and including compensation for memory effects. A polynomial-based alternative is also described. | 2009-06-11 |
20090146737 | CLASS-D AMPLIFIER AND MULTI-LEVEL OUTPUT SIGNAL GENERATED METHOD THEREOF - A class-D amplifier and a method of generating a multi-level output signal thereof are provided. The class-D amplifier includes a controlling logic circuit and an output module. The controlling logic circuit analyzes the amplitude of an input signal to generate a voltage modifying signal. A power supply provides a voltage according to the voltage modifying signal. The controlling logic circuit generates controlling signals according to the input signal. The output module generates an output signal to drive a load according to the voltage and the controlling signals. In other words, the resolution of the amplitude of the output signal is increased by modifying the voltage, and a signal to noise ratio is then increased. | 2009-06-11 |
20090146738 | OPERATIONAL AMPLIFIER - The operational amplifier adapting to a source driver is provided herein. The operational amplifier includes the input module, the first and the second current mirror module, the switch control module and output stage module, wherein the input module includes the first and the second differential pairs. The first current mirror module provides the first bias current to the first differential pairs and outputs the first mirrored current. The second current mirror module receives the second bias currents and the second mirrored current from the second differential pairs. The first and the second mirrored currents are respectively generated by mirroring the first and the second bias currents. The switch control module adjusts the first and the second bias currents for controlling the operation of the output stage module. The output stage module generates an output voltage terminal to a panel load according to the first and the second mirrored currents. | 2009-06-11 |
20090146739 | OPTICAL RECEIVER AND AMPLIFIER AND PHOTOCOUPLER USING THE SAME - In an optical receiver and amplifier and an optical coupler, a technique for stabilize operations at turning on/off of a power supply by a simple configuration is desired. An optical receiver and amplifier includes: a photodiode generates a photocurrent in response to a light input; an output section outputs output voltage being a low level or a high level in response to a magnitude of the photocurrent by using a power supply voltage supplied from a power supply; and an output control circuit controls an input voltage of the output section such that the output voltage is set to the low level when the power supply is turned on or off during a period where the power supply voltage is lower than a predetermined value. The output voltage can be set to the low level so that an additional circuit for preventing malfunction is not needed. | 2009-06-11 |
20090146740 | Average power efficiency enhancement and linearity improvement of microwave power amplifiers - A biasing circuit is used to provide low distortion and high efficiency operation of a microwave power amplifier. The biasing circuit utilizes the nonlinear rectified current of a microwave diode or transistor for biasing the amplifying transistor self-adaptively. The biasing current not only reduces the DC bias power during low-power operation and increases self-adaptively during high-power operation, but also manipulates the intermodulation distortion minimum dynamically. Meanwhile, the biasing circuit distorts the input signals with positive gain and negative phase deviations. Therefore, the average power efficiency of the operation is enhanced, the linearity of the input-output characteristic is improved and the radiated level of adjacent channel power is suppressed. | 2009-06-11 |
20090146741 | High-frequency amplifier, high-frequency module, and mobile wireless apparatus using the same - A high-frequency amplifier with high linearity is provided that is easy to integrate and is resistant to variations in transistor characteristics due to process variation. The high-frequency amplifier includes a bias circuit to bias an amplifying element that amplifies high frequencies. The bias circuit has a feedback circuit including a feedback loop in which a circuit with low pass characteristics and having a capacitor one end of which is grounded is inserted. A stable bias voltage is thus provided, which makes it possible to improve the linearity of the high-frequency amplifier. | 2009-06-11 |
20090146742 | PLL Apparatus - It is an object of the present invention to provide a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a trouble. | 2009-06-11 |
20090146743 | Systems and Methods for PLL Linearity Measurement, PLL Output Duty Cycle Measurement and Duty Cycle Correction - Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%. | 2009-06-11 |
20090146744 | SYSTEM AND METHOD OF CALIBRATING REAL TIME CLOCK UTILIZING AVERAGE CALIBRATION - A system for real time clock (RTC) calibration includes: a timer counter; a clock generator; and a clock calibration unit coupled between the clock generator and the timer counter. The clock calibration unit receives calibration parameters comprising an average calibration value, a remainder calibration value and a calibration period, counts a plurality of clock cycles generated by the clock generator, calibrates a number of the counted clock cycles according to the average calibration value and remainder calibration value in the calibration period, and increments the timer counter by one second when a predetermined number of clock cycles have been reached. | 2009-06-11 |
20090146745 | NOISE REDUCING DIELECTRIC RESONATOR OSCILLATOR - Systems, devices, and methods are provided for reducing noise in communication systems. An example resonator system comprises: a housing comprising a top portion and a floor portion, a dielectric resonator positioned with the housing, a substrate, and a stripline transmission line adjacent the substrate. In this exemplary embodiment, the stripline transmission line within the housing is electromagnetically coupled to the dielectric resonator, the substrate is positioned away from the floor portion and top portion of the housing, and the dielectric resonator coupled with the suspended stripline transmission line is connected to an active device to form an oscillator. The positioning of the substrate relative to the housing may reduce the amount of the electromagnetic field from the stripline transmission line that is absorbed into the housing. In a further embodiment, the board has no metallic backing on at least a portion of the back of the board. | 2009-06-11 |
20090146746 | SELF-CALIBRATING TEMPERATURE-COMPENSATED OSCILLATOR - A self-calibrating temperature compensated oscillator includes a monolithic structure having a first resonator, a second resonator, and a heating element to heat the first and second resonators. The temperature coefficient of the second resonator is substantially greater than the temperature coefficient of the first resonator. A first oscillator circuit operates with the first resonator and outputs a first oscillator output signal having a first oscillating frequency. A second oscillator circuit operates with the second resonator and outputs a second oscillator output signal having a second oscillating frequency. A temperature determining circuit determines the temperature of the first resonator using the second oscillating frequency. A temperature compensator provides a control signal to the first oscillator in response to the determined temperature to adjust the first oscillating frequency and maintain it at a desired operating frequency. | 2009-06-11 |
20090146747 | NOVEL METHOD OF FREQUENCY SYNTHESIS FOR FAST SWITCHING - A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL). | 2009-06-11 |
20090146748 | Amplitude Controller for a Clock, Frequency Reference, and Other Reference Signal Generator - Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, and an amplitude controller. The reference resonator generates a first reference signal having a resonant frequency, and the amplitude controller maintains substantially constant a magnitude of a peak amplitude of the first reference signal. A common mode controller may also be included to maintain substantially constant a common mode voltage level of the reference resonator. A temperature-dependent control voltage also may be generated and utilized to maintain the resonant frequency substantially constant or within a predetermined variance of a calibrated or selected frequency. | 2009-06-11 |
20090146749 | Low-Voltage Oscillator with Capacitor-Ratio Selectable Duty Cycle and Single-Input Sub-Threshold-Conducting Comparators to S-R Latch - An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage. | 2009-06-11 |
20090146750 | Common Mode Controller for a Clock, Frequency Reference, and Other Reference Signal Generator - Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, and a common mode controller. The reference resonator generates a first reference signal having a resonant frequency, and the common mode controller maintains substantially constant a common mode voltage level of the reference resonator. An amplitude controller may also be included to maintain substantially constant a magnitude of a peak amplitude of the first reference signal. A temperature-dependent control voltage also may be generated and utilized to maintain the resonant frequency substantially constant or within a predetermined variance of a calibrated or selected frequency. | 2009-06-11 |
20090146751 | Clock, Frequency Reference, and Other Reference Signal Generator - Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, and a frequency controller. The reference resonator generates a first reference signal having a resonant frequency, and the frequency controller maintains substantially constant a magnitude of a peak amplitude of the first reference signal and maintains substantially constant a common mode voltage level of the reference resonator. A temperature-dependent control voltage is also generated and utilized to maintain the resonant frequency substantially constant or within a predetermined variance of a calibrated or selected frequency. | 2009-06-11 |
20090146752 | Clock, Frequency Reference, and Other Reference Signal Generator with a Controlled Quality Factor - Exemplary embodiments of the invention provide a reference signal generator having a controlled quality (“Q”) factor. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, which generates a first reference signal having a resonant frequency, and a plurality of reactance modules couplable to the reference resonator. Each reactance module comprises one or more reactance unit cells, and each reactance unit cell comprises a reactance element coupled in series to a switching element. In exemplary embodiments, the reactance element is a capacitor having a predetermined unit of capacitance, and the switching element is a transistor having a predetermined resistance when in an off state. The ratio of capacitance to resistance is substantially constant for all reactance modules of the plurality of reactance modules. | 2009-06-11 |
20090146753 | OSCILLATOR VOLTAGE SOURCE CIRCUITS - An oscillator voltage source circuit is provided comprising a multiplexer, a plurality of transmission gates, a plurality of resistors, a voltage source circuit, and an output circuit. The multiplexer inputs a digital signal. The transmission gates is individually coupled to the multiplexer and receives the digital signal, wherein the plurality of transmission gate are turned on or off according to the digital signal. The plurality of resistors is coupled in series and individually coupled to the plurality of transmission gates. The voltage source circuit is coupled to the plurality of resistors and provides a first voltage source. The output circuit is coupled to the voltage source and outputs an oscillator voltage source according to the first voltage source and the turned-on or turned-off transmission gates. | 2009-06-11 |
20090146754 | Pulse-Width Modulator Methods and Apparatus - Otherwise conventional pulse-width modulators (PWMs) generate signals that can be converted into other forms by reshapers, and thereby overcome many of the problems of conventional PWMs in applications that demand high performance, such as switched-mode amplifiers and radio-frequency transmitters in modern communication systems. With a suitable reshaper, a conventional PWM differential signal can be converted into a signal more typical of linear amplification with nonlinear components (LINC) and still retain low-frequency information, such as the information needed for linearization of a switched-mode amplifier. Apparatus and methods of transforming signals are disclosed. | 2009-06-11 |
20090146755 | PLANAR EMI FILTER - An EMI filter for use between a power source and an electronic product is formed of at least one planar element including a pair of opposed coreless spiral planar windings, and a planar capacitor. This enables the integration of common mode and differential mode filters into integrated planar structures. Furthermore the planar EMI filter may be combined with an active filter element to provide a hybrid EMI filter comprising both passive and active elements with superior performance. | 2009-06-11 |
20090146756 | OUTPUT CIRCUIT FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE HAVING OUTPUT CIRCUIT, AND METHOD OF ADJUSTING CHARACTERISTICS OF OUTPUT CIRCUIT - To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased. | 2009-06-11 |
20090146757 | Coaxial automatic impedance adaptor - The invention concerns a coaxial automatic impedance adaptor characterized in that it comprises two slugs and has only a lateral translational movement along an axis Ox. The double slug tuner principle is based on the movement of two line segments of different characteristics of 50 O inside a closed cylinder on either side of standard connectors. | 2009-06-11 |
20090146758 | DIRECTIONAL COUPLER - A directional coupler ( | 2009-06-11 |
20090146759 | CIRCUIT TOPOLOGY FOR MULTIPLE LOADS - A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal via a main transmission line, a second node coupled to the first node via a first branch transmission line, a first receiving terminal coupled to the first node via a second branch transmission line, a third node coupled to the second node via a third branch transmission line, and a second receiving terminal coupled to the second node via a fourth branch transmission line. The second branch transmission line is longer than the first transmission line, and a first resistor is connected in the second branch transmission line. The third branch transmission line is longer than the fourth branch transmission line, and a second resistor is connected in the third branch transmission line. | 2009-06-11 |
20090146760 | ASSEMBLY, CHIP AND METHOD OF OPERATING | 2009-06-11 |
20090146761 | RF monoblock filter with recessed top pattern and cavity providing improved attenuation - An electrical signal filter defined by a block of dielectric material with a top surface, a bottom surface, side surfaces, and through-holes extending between the top and bottom surfaces. In one embodiment, a plurality of walls extend outwardly from the top surface to define a peripheral rim and filter cavity. A pattern of metallized and unmetallized areas is defined on selected surfaces of the block including an area of metallization that covers at least a portion of the top surface and at least one of the walls to define at least one input/output electrode on the wall. In one embodiment, a pair of input/output electrodes are formed on a pair of posts defined on one of the walls and the filter is adapted for mounting to a printed circuit board with the rim of the walls against the board and the posts coupled to respective input and output pads on the board. | 2009-06-11 |
20090146762 | RESONATOR AND FILTER - According to an aspect of the present invention, there is provided a resonator including: a transmission line including a conductor line with a bent portion, wherein the conductor line has a plurality of slits formed therein, the slits being formed in an extending direction of the conductor line to pass through the bent portion, and wherein the slits are formed to have intervals that become narrower from an outer-side toward an inner-side of the bent portion. | 2009-06-11 |
20090146763 | High Q Surface Mount Technology Cavity Filter - A cavity filter device includes a micro-strip structure comprising a low dielectric organic material forming a printed wiring board. The printed wiring board may be soldered, welded, or adhered to the base of one or more cavity filters. The cavity filter may include a coupling pin such as a RF pin positioned at the base of the filter. The micro-strip structure may be configured to carry a RF signal from the input, across the micro-strip structure to the RF pin positioned at the base of the filter. | 2009-06-11 |
20090146764 | Down-converter Having 90-Degree Hybrid Coupler with Open-circuited Transmission line(s) or Short-circuited Transmission line(s) Included Therein - A down-converter includes two low-noise amplifiers, a 90-degree hybrid coupler, and a down-converting circuit. The 90-degree hybrid coupler is coupled to the two low-noise amplifiers for transforming a first amplified signal and a second amplified signal into a first coupler output signal and a second coupler output signal. The 90-degree hybrid coupler includes a coupler main body, a first transmission line, and a second transmission line, wherein the first and the second transmission lines are coupled to the coupler main body. The coupler main body includes two input ports respectively coupled to the two low-noise amplifiers and two output ports for respectively outputting the first and the second coupler output signals. The first and the second transmission lines are each an open-circuited transmission line or a short-circuited transmission line. The down-converting circuit is coupled to the two output ports of the 90-degree hybrid coupler. | 2009-06-11 |
20090146765 | Down-converter Having Matching Circuits with Tuning Mechanism Coupled to 90-Degree Hybrid Coupler Included Therein - A down-converter includes two low-noise amplifiers, a 90-degree hybrid coupler, two first matching circuits, and a down-converting circuit. The two low-noise amplifiers respectively amplify a first beacon signal and a second beacon signal to generate a first amplified signal and a second amplified signal. The 90-degree hybrid coupler includes two input ports and two output ports for transforming the first amplified signal and the second amplified signal into a first coupler output signal and a second coupler output signal. The two first matching circuits are respectively coupled to the two input ports or the two output ports of the 90-degree hybrid coupler and each first matching circuit has a first tuning mechanism disposed in one side of the first matching circuit and not contacting the first matching circuit. The down-converting circuit performs a frequency down-conversion on the first coupler output signal and the second coupler output signal. | 2009-06-11 |
20090146766 | Protection Switch - A protection switch, particularly for fast switching, includes at least one single-pole protection switch module having a housing, a movable contact mounted on a switching arm for pivoting against a fixed contact between closed and open positions, a manual operating mechanism manually setting the switching arm between the closed and open positions, and a tripping mechanism automatically resetting the switching arm into the open position upon a tripping condition. The switching arm is spring-loaded in direction of the open position and includes a latch lever latching with the manual operating mechanism, and a contact lever carrying the moveable contact. The latch lever is pivotably mounted on the housing and joined to the contact lever by a hinge. The tripping mechanism includes a trip slider to be displaced by a trip device from a ready position towards a tripping position, to load the switching arm for rotationally fixing the contact lever. | 2009-06-11 |
20090146767 | Ferromagnetic Nanorings, Mediums Embodying Same Including Devices and Methods Related Thereto - Featured is a magnetic ring structure including at least a vortex magnetic state such as symmetrically and asymmetrically shaped nanorings, having small diameters (e.g., on the order of 100 nm). In particular embodiments, the width and thickness of the asymmetrical nanorings varies as a function of the locations on the circumference so that maxima and minima thereof are located on opposite sides of the nanoring. Also featured are methods for fabricating such symmetrically and asymmetrically shaped nanorings. Also featured are methods for controlling the reversal process so as to thereby create vortex states in such asymmetric nanorings by controlling the field angle. | 2009-06-11 |
20090146768 | MAGNETIC DEVICE UNIT AND FIXING COMPONENT THEREOF - A magnetic device unit disposed on a circuit board is disclosed. The magnetic device comprises a magnetic device and a fixing component. The magnetic device has a conductive wire wound thereon. The conductive wire has a terminal. The fixing component is disposed on the circuit board and comprises a main body and a pin. The pin comprises a first conductive portion, a second conductive portion and a connection portion connecting the first and second conductive portions, wherein the connection portion is embedded in the main body and the second conductive portion is connected to the circuit board. The magnetic device is carried by the main body of the fixing component and the terminal of the conductive wire is connected to the first conductive portion of the pin for the magnetic device to be electrically connected to the circuit board via the pin. | 2009-06-11 |
20090146769 | Light-weight, conduction-cooled inductor - A lightweight inductor for the motor controller of an aircraft starter includes a toroidal inductor core divided into multiple sections that are separated by a thermally conductive, but electrically insulating, material. The inductor core is wound with wire and positioned inside of an electrically and thermally conductive container, which acts as a heat sink and EMI shield, while also reducing eddy currents within the inductor core. | 2009-06-11 |
20090146770 | PLANAR-LIKE INDUCTOR COUPLING STRUCTURE - A planar-like inductor coupling structure includes a first planar inductor embedded in an insulating material layer and a second planar inductor also embedded in the insulating material layer. The first planar inductor and the second planar inductor are substantially at the same height, and have a portion in a horizontal distribution serving as a coupled overlapping region with electric insulation from each other. In addition, the first planar inductor and the second planar inductor may be at different heights. | 2009-06-11 |
20090146771 | Apparatus for Generating Secondary Electricity from an Electromagnetic Field Around a Wire - Disclosed is an apparatus for generating secondary electricity from an electromagnetic field around a wire. The apparatus includes a coil unit, a wire and a rectifier. The coil unit comprising a highly magnetically conductive ring and a coil provided wound around the highly magnetically conductive ring. The wire is wound around the highly magnetically conductive ring. The rectifier is connected to the coil. | 2009-06-11 |
20090146772 | INDUCTIVE DEVICE INCLUDING PERMANENT MAGNET AND ASSOCIATED METHODS - The radio frequency (RF) inductor includes a core being electrically non-conductive and ferrimagnetic, and having a toroidal shape, and a wire coil thereupon. At least one permanent magnet body is at a fixed position within the interior of the core, and an electrically conductive RF shielding layer is on the at least one permanent magnet body. The core may be ferrite for example. The electrically conductive RF shielding layer may be a conductive plating layer or a metal foil surrounding the permanent magnet body, for example. A magnetic field from the permanent magnet is applied to the inductor core to reduce losses, and the permanent magnet may be enclosed within the conductive shield to keep RF fields out. The inductor may be made small and have increased Q and resulting efficiency. The RF inductor may be applicable to RF communication circuits, for example, as an antenna coupler. | 2009-06-11 |
20090146773 | LATERAL SNAP ACTING MEMS MICRO SWITCH - A MEMS micro-switch with a lateral snap action includes a laterally bowed beam and an electro thermal actuator. The electro thermal actuator can be activated in response to the application of an actuation voltage and a push rod pushes the laterally bowed beam to a transition point through a push-pull connector. The bowed beam can be snapped to an opposite position at the transition point and a moving electrode makes strong contact to fixed electrodes, which makes the switch turn on with strong contact force. The actuator can be deactivated and the push rod pulls the bowed beam back to the transition point and snapped back to an original position, which makes the switch turn off. The switch can be fabricated utilizing glass and SOI wafer bonding technique. | 2009-06-11 |
20090146774 | PTC-RESISTOR - A PTC-resistor includes a base body made of a ceramic material with a positive temperature coefficient of resistance. The base body extends along a median plane, and is confined by surfaces. At least one surface is configured to electrically connect the base body. An area of the at least one surface is larger than an area of a parallel projection of the base body in a direction perpendicular to the median plane. | 2009-06-11 |