23rd week of 2022 patent applcation highlights part 64 |
Patent application number | Title | Published |
20220181167 | MANUFACTURING METHOD OF PACKAGE STRUCTURE | 2022-06-09 |
20220181168 | SUPPORTING UNIT AND SUBSTRATE TREATING APPARATUS INCLUDING THE SAME | 2022-06-09 |
20220181169 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD INCLUDING PROCESSING LIQUID SUPPLY UNIT | 2022-06-09 |
20220181170 | WAFER PROCESSING APPARATUS AND METHOD FOR PROCESSING WAFER | 2022-06-09 |
20220181171 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS | 2022-06-09 |
20220181172 | CONTROL DEVICE AND SUBSTRATE PROCESSING METHOD | 2022-06-09 |
20220181173 | SYSTEM FOR FRACTURING A PLURALITY OF WAFER ASSEMBLIES | 2022-06-09 |
20220181174 | WAFER MANUFACTURING APPARATUS | 2022-06-09 |
20220181175 | COOLING SHEET ATTACHMENT APPARATUS TO FOCUSING RING FOR SEMICONDUCTOR MANUFACTURING APPARATUS | 2022-06-09 |
20220181176 | SUBSTRATE PROCESSING TOOL WITH INTEGRATED METROLOGY AND METHOD OF USING | 2022-06-09 |
20220181177 | APPARATUS HAVING CLOSED LOOP IR CAMERA HEAT DETECTION SYSTEM AND METHOD | 2022-06-09 |
20220181178 | CORRECTION METHOD AND SUBSTRATE TRANSFER APPARATUS | 2022-06-09 |
20220181179 | In-Situ Metrology And Process Control | 2022-06-09 |
20220181180 | SEMICONDUCTOR MANUFACTURING APPARATUS, FAILURE PREDICTION METHOD FOR SEMICONDUCTOR MANUFACTURING APPARATUS, AND FAILURE PREDICTION PROGRAM FOR SEMICONDUCTOR MANUFACTURING APPARATUS | 2022-06-09 |
20220181181 | SEMICONDUCTOR MANUFACTURING APPARATUS, METHOD OF READING POSITION OF CARRIER, AND METHOD OF ATTACHING SEMICONDUCTOR DIE ON CARRIER USING SEMICONDUCTOR MANUFACTURING APPARATUS | 2022-06-09 |
20220181182 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | 2022-06-09 |
20220181183 | GAS PLUG, ELECTROSTATIC ATTRACTION MEMBER, AND PLASMA TREATMENT DEVICE | 2022-06-09 |
20220181184 | ELECTROSTATIC CHUCK FOR USE IN SEMICONDUCTOR PROCESSING | 2022-06-09 |
20220181185 | HYBRID TETHERS FOR MICRO-TRANSFER PRINTING | 2022-06-09 |
20220181186 | 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE | 2022-06-09 |
20220181187 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REPLACEMENT GATES | 2022-06-09 |
20220181188 | PLASMA PROCESSING METHOD | 2022-06-09 |
20220181189 | MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE | 2022-06-09 |
20220181190 | WAFER FIXING MECHANISM AND WAFER PRE-CLEANING MACHINE USING THE WAFER FIXING MECHANISM | 2022-06-09 |
20220181191 | CIRCULAR WAFER LATERAL POSITIONING DEVICE | 2022-06-09 |
20220181192 | SOLDER BUMP FORMATION USING WAFER WITH RING | 2022-06-09 |
20220181193 | HIGH PERFORMANCE SUSCEPTOR APPARATUS | 2022-06-09 |
20220181194 | SEMICONDUCTOR FLIPPER | 2022-06-09 |
20220181195 | WAFER HOLDER FOR GENERATING STABLE BIAS VOLTAGE AND THIN FILM DEPOSITION EQUIPMENT USING THE SAME | 2022-06-09 |
20220181196 | DEPOSITION APPARATUS AND DISPLAY PANEL MANUFACTURING APPARATUS INCLUDING THE SAME | 2022-06-09 |
20220181197 | BURIED POWER RAIL CONTACT FORMATION | 2022-06-09 |
20220181198 | SELF ALIGNED BURIED POWER RAIL | 2022-06-09 |
20220181199 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | 2022-06-09 |
20220181200 | SILICON ON INSULATOR STRUCTURE AND METHOD OF MAKING THE SAME | 2022-06-09 |
20220181201 | SELECTIVE TUNGSTEN DEPOSITION WITHIN TRENCH STRUCTURES | 2022-06-09 |
20220181202 | AIR-REPLACED SPACER FOR SELF-ALIGNED CONTACT SCHEME | 2022-06-09 |
20220181203 | ELECTRON MIGRATION CONTROL IN INTERCONNECT STRUCTURES | 2022-06-09 |
20220181204 | REVERSE SELECTIVE ETCH STOP LAYER | 2022-06-09 |
20220181205 | SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA | 2022-06-09 |
20220181206 | SEMICONDUCTOR STRUCTURE WITH A LAMINATED LAYER | 2022-06-09 |
20220181207 | SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS | 2022-06-09 |
20220181208 | SEMICONDUCTOR DEVICE WITH REDUCED STRESS DIE PICK AND PLACE | 2022-06-09 |
20220181209 | ELEMENT CHIP MANUFACTURING METHOD | 2022-06-09 |
20220181210 | METHOD FOR REMOVING A BAR OF ONE OR MORE DEVICES USING SUPPORTING PLATES | 2022-06-09 |
20220181211 | Composite Wafer, Semiconductor Device and Electronic Component | 2022-06-09 |
20220181212 | SEMICONDUCTOR DEVICE WITH REDUCED LOADING EFFECT | 2022-06-09 |
20220181213 | TRANSISTOR HAVING SOURCE OR DRAIN FORMATION ASSISTANCE REGIONS WITH IMPROVED BOTTOM ISOLATION | 2022-06-09 |
20220181214 | Multi-Channel Devices and Methods of Manufacture | 2022-06-09 |
20220181215 | GATE FORMATION PROCESS | 2022-06-09 |
20220181216 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | 2022-06-09 |
20220181217 | SEMICONDUCTOR DEVICE WITH CUT METAL GATE AND METHOD OF MANUFACTURE | 2022-06-09 |
20220181218 | GATE STRUCTURE AND PATTERNING METHOD | 2022-06-09 |
20220181219 | PLASMA TREATMENT APPARATUS, A METHOD OF MONITORING A PROCESS OF MANUFACTURING A SEMICONDUCTOR DEVICE BY USING THE SAME, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE MONITORING METHOD | 2022-06-09 |
20220181220 | SEMICONDUCTOR PACKAGE | 2022-06-09 |
20220181221 | SEMICONDUCTOR MODULE AND POWER CONVERTER | 2022-06-09 |
20220181222 | FLEXIBLE COMPONENT SUPPORT AND DISPLAY DEVICE | 2022-06-09 |
20220181223 | COVERS FOR SEMICONDUCTOR PACKAGE COMPONENTS | 2022-06-09 |
20220181224 | FILM COVERS FOR SENSOR PACKAGES | 2022-06-09 |
20220181225 | ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF | 2022-06-09 |
20220181226 | SEMICONDUCTOR DEVICE | 2022-06-09 |
20220181227 | MULTI-USE PACKAGE ARCHITECTURE | 2022-06-09 |
20220181228 | SEMICONDUCTOR PACKAGE WITH IMPROVED RELIABILITY | 2022-06-09 |
20220181229 | SEMICONDUCTOR MODULE | 2022-06-09 |
20220181230 | SEMICONDUCTOR DEVICE PACKAGE HAVING THERMAL DISSIPATION FEATURE AND METHOD THEREFOR | 2022-06-09 |
20220181231 | HEAT DISSIPATION PLATE AND SEMICONDUCTOR DEVICE | 2022-06-09 |
20220181232 | METHOD FOR FORMING PACKAGE STRUCTURE WITH LID | 2022-06-09 |
20220181233 | POWER CONVERTER | 2022-06-09 |
20220181234 | POWER ELECTRONICS SYSTEM WITH A SWITCHING DEVICE AND A LIQUID COOLING DEVICE | 2022-06-09 |
20220181235 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | 2022-06-09 |
20220181236 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC APPARATUS | 2022-06-09 |
20220181237 | CHIP PACKAGING METHOD AND CHIP PACKAGE UNIT | 2022-06-09 |
20220181238 | CHIP PACKAGING METHOD AND CHIP PACKAGE UNIT | 2022-06-09 |
20220181239 | SEMICONDUCTOR PACKAGE HAVING SIDE WALL PLATING | 2022-06-09 |
20220181240 | LAMINATE STACKED ON DIE FOR HIGH VOLTAGE ISOLATION CAPACITOR | 2022-06-09 |
20220181241 | PLATED METAL LAYER IN POWER PACKAGES | 2022-06-09 |
20220181242 | REDISTRIBUTION LAYER STRUCTURE AND MANUFACTURING METHOD THEREOF | 2022-06-09 |
20220181243 | Component Carrier With a Photoimageable Dielectric Layer and a Structured Conductive Layer Being Used as a Mask for Selectively Exposing the Photoimageable Dielectric Layer With Electromagnetic Radiation | 2022-06-09 |
20220181244 | PACKAGE SUBSTRATE AND PACKAGE STRUCTURE | 2022-06-09 |
20220181245 | PRINTED CIRCUIT BOARD | 2022-06-09 |
20220181246 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THEREOF | 2022-06-09 |
20220181247 | Chip Module, Use of Chip Module, Test Arrangement and Test Method | 2022-06-09 |
20220181248 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME | 2022-06-09 |
20220181249 | LAYOUT OF WORDLINE AND METHOD OF FORMING THE SAME | 2022-06-09 |
20220181250 | BACKSIDE CONNECTION STRUCTURES FOR NANOSTRUCTURES AND METHODS OF FORMING THE SAME | 2022-06-09 |
20220181251 | METHODS & STRUCTURES FOR IMPROVED ELECTRICAL CONTACT BETWEEN BONDED INTEGRATED CIRCUIT INTERFACES | 2022-06-09 |
20220181252 | DECOUPLING CAPACITOR INSIDE GATE CUT TRENCH | 2022-06-09 |
20220181253 | CAPACITOR NETWORKS FOR HARMONIC CONTROL IN POWER DEVICES | 2022-06-09 |
20220181254 | Integrated Assemblies Having Conductive-Shield-Structures Between Linear-Conductive-Structures | 2022-06-09 |
20220181255 | CONDUCTIVE LINES WITH SUBTRACTIVE CUTS | 2022-06-09 |
20220181256 | HYBRID MANUFACTURING FOR INTEGRATED CIRCUIT DEVICES AND ASSEMBLIES | 2022-06-09 |
20220181257 | ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF | 2022-06-09 |
20220181258 | POWER-TAP PASS-THROUGH TO CONNECT A BURIED POWER RAIL TO FRONT-SIDE POWER DISTRIBUTION NETWORK | 2022-06-09 |
20220181259 | Backside Power Rail Structure and Methods of Forming Same | 2022-06-09 |
20220181260 | SEMICONDUCTOR DEVICE STRUCTURE WITH MANGANESE-CONTAINING CONDUCTIVE PLUG AND METHOD FOR FORMING THE SAME | 2022-06-09 |
20220181261 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURE WITH MANGANESE-CONTAINING CONDUCTIVE PLUG | 2022-06-09 |
20220181262 | MICROELECTRONIC COMPONENT HAVING MOLDED REGIONS WITH THROUGH-MOLD VIAS | 2022-06-09 |
20220181263 | INTER-TIER POWER DELIVERY NETWORK (PDN) FOR DENSE GATE-ON-GATE 3D LOGIC INTEGRATION | 2022-06-09 |
20220181264 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME | 2022-06-09 |
20220181265 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES | 2022-06-09 |
20220181266 | OPTOELECTRONIC COMPONENT, SYSTEM AND METHOD FOR PRODUCING SAME | 2022-06-09 |