23rd week of 2016 patent applcation highlights part 62 |
Patent application number | Title | Published |
20160163524 | ZERO VOLTAGE MASS SPECTROMETRY PROBES AND SYSTEMS - The invention generally relates to zero volt mass spectrometry probes and systems. In certain embodiments, the invention provides a system including a mass spectrometry probe including a porous material, and a mass spectrometer (bench-top or miniature mass spectrometer). The system operates without an application of voltage to the probe. In certain embodiments, the probe is oriented such that a distal end faces an inlet of the mass spectrometer. In other embodiments, the distal end of the probe is 5 mm or less from an inlet of the mass spectrometer. | 2016-06-09 |
20160163525 | Mass Spectrometer Device and Method Using Scanned Phase Applied Potentials in Ion Guidance - An ion guide or mass analyser is disclosed comprising a plurality of electrodes having apertures through which ions are transmitted in use. A pseudo-potential barrier is created at the exit of the ion guide or mass analyser. The amplitude or depth of the pseudo-potential barrier is inversely proportional to the mass to charge ratio of an ion. One or more transient DC voltages are applied to the electrodes of the ion guide or mass analyser in order to urge ions along the length of the ion guides or mass analyser. The amplitude of the transient DC voltage applied to the electrode may be increased with time so that ions are caused to be emitted from the ion guide or mass analyser in reverse order of their mass to charge ratio. | 2016-06-09 |
20160163526 | Mass Spectrometer - A mass spectrometer is disclosed comprising a time of flight mass analyser. The time of flight mass analyser comprises an ion guide comprising a plurality of electrodes which are interconnected by a series of resistors forming a potential divider. Ions are confined radially within the ion guide by the application of a two-phase RF voltage to the electrodes. A single phase additional RF voltage is applied across the potential divider so that an inhomogeneous pseudo-potential force is maintained along the length of the ion guide. | 2016-06-09 |
20160163527 | IONIZER AND MASS SPECTROMETER - In the ionizer of the present invention, a stream of gas spouted from a nozzle ( | 2016-06-09 |
20160163528 | INTERFACE FOR AN ATMOSPHERIC PRESSURE ION SOURCE IN A MASS SPECTROMETER - The invention relates to a mass spectrometer having an ion source region at substantially atmospheric pressure in which ions are formed from a liquid sample. The mass spectrometer further has an interface for transmitting the formed ions from the ion source region into a vacuum region which is held at a pressure level substantially below the atmospheric pressure and where the formed ions are further processed. The interface comprises a wall dividing the ion source region and the vacuum region and has a central orifice formed therein for letting pass gaseous and particulate matter from the ion source region into the vacuum region following the pressure gradient, wherein the central orifice is surrounded at least section-wise by a plurality of lateral orifices. | 2016-06-09 |
20160163529 | FREQUENCY SCAN LINEAR ION TRAP MASS SPECTROMETRY - An ion trap mass spectrometer and methods for obtaining a mass spectrum of ions by scanning an RF frequency applied to the linear ion trap for mass selective ejection of the ions by using two power amplifiers to apply opposite phases of the RF to x and y electrodes. | 2016-06-09 |
20160163530 | SYSTEMS FOR SEPARATING IONS AND NEUTRALS AND METHODS OF OPERATING THE SAME - A mass spectrometer system includes a pulsed ion source configured to generate ionized molecules and neutral molecules. The system also includes a first enclosure coupled in flow communication with the pulsed ion source. The first enclosure defines a first vacuum chamber and an ion inlet aperture. The system further includes a detector positioned within said first enclosure and a plurality of ion transmission devices positioned within the first vacuum chamber and aligned with the ion inlet aperture. The plurality of ion transmission devices is configured to channel and accelerate ionized molecules through a first transmission path such that the ionized molecules and the neutral molecules are physically separated in space and temporally separated. | 2016-06-09 |
20160163531 | COOLING APPARATUS, ILLUMINATION OPTICAL SYSTEM, EXPOSURE APPARATUS, AND METHOD OF MANUFACTURING ARTICLE - A cooling apparatus for cooling a light source unit is provided. The cooling apparatus includes a cooling unit provided outside a path of light from the light source unit, and a heat pipe configured to connect a heat generating portion of the light source unit and the cooling unit. The heat pipe also serves as an electrode wire of the light source unit. | 2016-06-09 |
20160163532 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N | 2016-06-09 |
20160163533 | TANTALUM OXIDE FILM REMOVAL METHOD AND APPARATUS - In a tantalum oxide film removal method and apparatus, a silicon substrate having a tantalum oxide film is supported on a spin chuck. A mixed aqueous solution including hydrofluoric acid and organic acid is supplied to the silicon substrate while rotating the silicon substrate together with the spin chuck. The mixed aqueous solution comes into contact with the tantalum oxide film existing on the silicon substrate to remove the tantalum oxide film by the chemical reaction therebetween. | 2016-06-09 |
20160163534 | SUBSTRATE CLEANING APPARATUS, SUBSTRATE CLEANING SYSTEM, SUBSTRATE CLEANING METHOD AND MEMORY MEDIUM - A method for cleaning a substrate includes setting a substrate inside a cleaning chamber, supplying on a surface of the substrate a treatment solution which includes a volatile component and forms a treatment film, vaporizing the volatile component of the treatment solution supplied on the surface of the substrate such that the treatment solution solidifies or is cured on the surface of the substrate and the treatment film is formed on the surface of the substrate, and supplying onto the treatment film formed on the surface of the substrate a removal solution which removes the treatment film. | 2016-06-09 |
20160163535 | LAYER TRANSFERRING PROCESS - A process for transferring a useful layer to a receiver substrate includes providing a donor substrate comprising an intermediate layer, a carrier substrate, and a useful layer. The intermediate layer is free of species liable to degas during a subsequent heat treatment, and is configured to become soft at a temperature. The receiver substrate and the donor substrate are assembled. An additional layer is provided between the receiver substrate and the carrier substrate that comprises chemical species that are susceptible to diffuse into the intermediate layer during the subsequent heat treatment so as to form a weak zone. The heat treatment is carried out on the receiver substrate and the donor substrate at a second temperature higher than the first temperature. | 2016-06-09 |
20160163536 | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING METAL OXIDE STRUCTURES - Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described. | 2016-06-09 |
20160163537 | SEMICONDUCTOR DEVICE INCLUDING h-BN INSULATING LAYER AND ITS MANUFACTURING METHOD - A semiconductor device includes a support substrate, an insulating layer provided on the support substrate, and a semiconductor element provided on the insulating layer. The insulating layer has a lower insulating layer consisting of amorphous boron nitride, and an upper insulating layer provided on the lower insulating layer and including amorphous boron nitride and an hexagonal system boron nitride (h-BN) particles. | 2016-06-09 |
20160163538 | METHOD FOR PRODUCING METAL OXIDE FILM AND METHOD FOR PRODUCING TRANSISTOR - Provided is a technology for efficiently obtaining a metal oxide film having good adhesiveness. A method of producing a metal oxide film includes: an application step of applying a solution containing an organic metal complex onto a substrate; an ozone exposure step of exposing the resultant coating film to ozone; and a heating step of heating the coating film. | 2016-06-09 |
20160163539 | METHODS FOR DEPOSITING SILICON OXIDE - The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes. Conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls. The disclosed embodiments achieve more uniform film quality as evidenced by more uniform wet etch rates and electrical properties throughout the film. The disclosed embodiments may use one or more of a relatively high deposition temperature, a relatively high RF power for generating the plasma, and/or relatively long RF plasma exposure duration during each cycle of the PEALD reaction. | 2016-06-09 |
20160163540 | METHOD FOR CURING FLOWABLE LAYER - Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a flowable layer over a substrate and heating the flowable layer to form a cured layer in a curing process. In addition, the curing process is performed under a pressure of over 2 atmospheres, and the flowable layer reacts with precursors in the flowable layer during the curing process. | 2016-06-09 |
20160163541 | GROUP III NITRIDE SUBSTRATES AND THEIR FABRICATION METHOD - Group III nitride substrate having a first side of nonpolar or semipolar plane and a second side has more than one stripe of metal buried, wherein the stripes are perpendicular to group III nitride's c-axis. More than 90% of stacking faults exist over metal stripes. Second side may expose a nonpolar or semipolar plane. Also disclosed is a group III nitride substrate having a first side of nonpolar or semipolar plane and a second side with exposed nonpolar or semipolar plane. The substrate contains bundles of stacking faults with spacing larger than 1 mm. The invention also provides methods of fabricating the group III nitride substrates above. | 2016-06-09 |
20160163542 | OXIDE SEMICONDUCTOR FILM, FILM FORMATION METHOD THEREOF, AND SEMICONDUCTOR DEVICE - An oxide semiconductor film with high crystallinity is formed. An oxide semiconductor film having a single crystal region, which is formed by a sputtering method using a sputtering target including a polycrystalline oxide containing a plurality of crystal grains, is provided. The plurality of crystal grains contained in the sputtering target has a plane that is cleaved or is likely to be cleaved because of a weak crystal bond; therefore, the cleavage planes in the plurality of crystal grains are cleaved when an ion collides with the sputtering target, whereby flat plate-like sputtered particles can be obtained. The obtained flat plate-like sputtered particles are deposited on a deposition surface; accordingly, an oxide semiconductor film is formed. The flat plate-like sputtered particle is formed by separation of part of the crystal grain and therefore the oxide semiconductor film can have high crystallinity. | 2016-06-09 |
20160163543 | ACTIVE STRUCTURES OF A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns and a first trench, each of the first preliminary active patterns having a first width, and the first trench having a second width of about 2 to 3 times the first width; forming an insulating spacer on each sidewall of the first trench to form a second trench having the first width; forming a second preliminary active pattern in the second trench, the second preliminary active pattern having the first width; partially etching the first and second preliminary active patterns to form a plurality of first active patterns and a plurality of second active patterns and an opening between the plurality of first and second active patterns; and forming an insulation pattern to fill the opening. | 2016-06-09 |
20160163544 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed. | 2016-06-09 |
20160163545 | SILICON CARBIDE SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; an epitaxial layer formed on the main surface; and a deformation suppression layer formed on a backside surface of the base substrate opposite to the main surface. In this way, the deformation suppression layer suppresses the substrate from being deformed (for example, warped during high-temperature treatment). This can reduce a risk of causing defects such as crack in the silicon carbide semiconductor substrate during the manufacturing process in performing a method for manufacturing a silicon carbide semiconductor device using the silicon carbide semiconductor substrate. | 2016-06-09 |
20160163546 | 3D MATERIAL MODIFICATION FOR ADVANCED PROCESSING - Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes. | 2016-06-09 |
20160163547 | METHODS OF FORMING FINE PATTERNS AND METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES USING THE METHODS - The present inventive concept provides a method of forming a fine pattern including forming a plurality of pillar-shaped guides that are regularly arranged on a feature layer. | 2016-06-09 |
20160163548 | Masking Process and Structures Formed Thereby - A method, e.g., of forming and using a mask, includes forming an inverse mask over a dielectric layer; forming a mask layer conformally over the inverse mask; removing horizontal portions of the mask layer; and after removing the horizontal portions, simultaneously etching the inverse mask and vertical portions of the mask layer. The etching the inverse mask is at a greater rate than the etching the vertical portions of the mask layer. The etching the inverse mask removes the inverse mask, and the etching the vertical portions of the mask layer forms a mask comprising rounded surfaces distal from the dielectric layer. Recesses are formed in the dielectric layer using the mask. Locations of the inverse mask correspond to fewer than all locations of the recesses. | 2016-06-09 |
20160163549 | LASER PROCESSING METHOD - A planar object to be processed | 2016-06-09 |
20160163550 | Gate Electrodes with Notches and Methods for Forming the Same - A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region. | 2016-06-09 |
20160163551 | METHODS OF FORMING METAL SILICIDE REGIONS ON SEMICONDUCTOR DEVICES USING AN ORGANIC CHELATING MATERIAL DURING A METAL ETCH PROCESS - A method includes forming a refractory metal alloy layer above a silicon-containing material, performing a first heating process to form a metal silicide region in at least a portion of the silicon-containing material using the refractory metal alloy layer, and removing at least a first portion of an unreacted portion of the refractory metal alloy layer using a first solution comprising a solvent and an organic chelator. | 2016-06-09 |
20160163552 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory including a substrate, a first stacked structure, a second stacked structure, a fifth conductive layer, a first doped region, and a second doped region is provided. The first stacked structure includes a first conductive layer and a second conductive layer stacked on the substrate in order and isolated from each other. The second stacked structure is separately disposed from the first stacked structure and includes a third conductive layer and a fourth conductive layer stacked on the substrate in order and connected to each other. The fifth conductive layer is disposed on the substrate at one side of the first stacked structure away from the second stacked structure. The first doped region is disposed in the substrate below the fifth conductive layer. The second doped region is disposed in the substrate at one side of the second stacked structure away from the first stacked structure. | 2016-06-09 |
20160163553 | METHOD FOR IMPROVING QUALITY OF SPALLED MATERIAL LAYERS - Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling. | 2016-06-09 |
20160163554 | PLASMA ETCHING METHOD - A plasma etching method is provided to perform a desired etching by switching a process condition while maintaining plasma by supplying high frequency power. A first plasma etching process is performed based on a first process condition. A second plasma etching process different from the first process conditions is performed based on a second process condition while supplying first high frequency power having first effective power. Second high frequency power having second effective power is intermittently supplied between the first plasma etching process and the second plasma etching process during a switch from the first plasma etching process to the second plasma etching process. The second effective power of the second high frequency power is equal to or lower than the first effective power of the first high frequency power in the second plasma etching process. | 2016-06-09 |
20160163555 | METHODS OF FORMING FEATURES HAVING DIFFERING PITCH SPACING AND CRITICAL DIMENSIONS - Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer. | 2016-06-09 |
20160163556 | TECHNIQUE TO DEPOSIT SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH - Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants having low sticking coefficients in some embodiments. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition or plasma assisted chemical vapor deposition. | 2016-06-09 |
20160163557 | TECHNIQUE TO DEPOSIT SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH - Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in substantial preservation of a mask layer on the substrate. The protective coating may be deposited using particular reactants and/or reaction conditions that are unlikely to damage the mask layer. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition, a modified plasma assisted atomic layer deposition, or plasma assisted chemical vapor deposition. | 2016-06-09 |
20160163558 | TECHNIQUE TO DEPOSIT METAL-CONTAINING SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH - Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation. In some cases, a bilayer approach may be used to deposit the protective coating on sidewalls of partially etched features. | 2016-06-09 |
20160163559 | METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE - Semiconductor structure and methods of fabrication thereof are provided which includes, for instance, providing a carbon-doped material layer within a recess of a semiconductor structure; removing, in part, carbon from the carbon-doped material layer to obtain, at least in part, a carbon-depleted region thereof, the carbon-depleted region having a modified etch property with an increased etch rate compared to an etch rate of the carbon-doped material layer; and recessing the carbon-depleted region of the carbon-doped material layer by an etching process, with the carbon-depleted region being recessed based upon, in part, the modified etch property of the carbon-depleted region. | 2016-06-09 |
20160163560 | SUBSTRATE PROCESSING METHOD, STORAGE MEDIUM AND SUBSTRATE PROCESSING SYSTEM - There is provided a method of processing a substrate using a block copolymer composed of a first polymer containing an oxygen atom and a second polymer containing no oxygen atom, the method including: coating the block copolymer onto the substrate on which a predetermined pattern is formed; phase-separating the block copolymer into the first polymer and the second polymer; and heating the substrate in a low oxygen atmosphere to selectively remove the first polymer from the phase-separated block copolymer. | 2016-06-09 |
20160163561 | TECHNIQUE TO DEPOSIT SIDEWALL PASSIVATION FOR HIGH ASPECT RATIO CYLINDER ETCH - Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants and/or reaction mechanisms that result in substantially complete sidewall coating at relatively low temperatures without the use of plasma. In some cases the protective coating is deposited using molecular layer deposition techniques. | 2016-06-09 |
20160163562 | Etching Method, and Recording Medium - An etching method includes a modification process of supplying a mixture gas to a surface of a silicon oxide film, modifying the silicon oxide film to generate a reaction product, and a heating process of heating and removing the reaction product. The modification process includes a first modification process of supplying the mixture gas containing a gas including a halogen element and an alkaline gas to the surface of the silicon oxide film, and a second modification process of stopping supplying the alkaline gas and supplying the mixture gas containing the gas including the halogen element to the surface of the silicon oxide film. | 2016-06-09 |
20160163563 | ETCHING METHOD - There is provided an etching method for etching an object to be processed by using a substrate processing apparatus including a process chamber including a first electrode and a second electrode disposed opposite to the first electrode to receive the object to be processed thereon. The etching method includes a process of removing at least one of a first polymer and a second polymer by etching the object to be processed on which a pattern of the first polymer and the second polymer is formed by phase separation of a block copolymer containing the first polymer and the second polymer at a temperature lower than or equal to 10 degrees C. by using plasma of a process gas. | 2016-06-09 |
20160163564 | Semiconductor Packages and Methods of Forming the Same - A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias. | 2016-06-09 |
20160163565 | MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE - When a plating layer is formed on through holes in semiconductor packages, first and second stacked bodies are stacked with first and second cavities formed in the first and second stacked bodies facing the inner side and are bonded together by applying adhesive to peripheral regions so that the cavities of the first and second stacked bodies form sealed spaces, and the through holes are formed such that part of the first and second stacked bodies including the bonding surface remains. Then, the through holes are plated to form the plating layer, the peripheral regions are removed as cutting allowances, i.e., removal regions, and the first and second stacked bodies are divided into a plurality of pieces along dicing lines to form semiconductor packages. | 2016-06-09 |
20160163566 | INTEGRATED CIRCUIT PACKAGE PAD AND METHODS OF FORMING - A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias. | 2016-06-09 |
20160163567 | SUBSTRATE SURFACE METALLIZATION METHOD AND SUBSTRATE HAVING METALLIZED SURFACE MANUFACTURED BY THE SAME - A coating device for coating a coating liquid onto a substrate includes: a coating head having a coating-liquid outlet, adapted to move with respect to the substrate along a first axial direction and capable of coating the substrate with coating liquid through the coating-liquid outlet; and adjustment unit connected to the coating head and including a movable pad disposed proximal to the coating-liquid outlet and adapted to move along a second axial direction for adjusting the size of the opening of the coating-liquid outlet; and a drive assembly connected to the adjustment unit for controlling the adjustment unit to move along the second axial direction. Additionally a coating method is provided. | 2016-06-09 |
20160163568 | METHODOLOGIES FOR RINSING TOOL SURFACES IN TOOLS USED TO PROCESS MICROELECTRONIC WORKPIECES - Rinsing methodologies and components to accomplish rinsing of tool surfaces in tools that are used to process one or more microelectronic workpieces. The invention can be used to rinse structures that overlie a workpiece being treated in such a manner to function in part as a lid over the process chamber while also defining a tapering flow channel over the workpiece. Rather than spray rinsing liquid onto the surface in a manner that generates undue splashing, droplet, or mist generation, a swirling flow of rinse liquid is generated on a surface of at least one fluid passage upstream from the surface to be rinsed. The swirling flow then provides smooth, uniform wetting and sheeting action to accomplish rinsing with a significantly reduced risk of generating particle contamination. | 2016-06-09 |
20160163569 | Faraday Shield Having Plasma Density Decoupling Structure Between TCP Coil Zones - A Faraday shield and a plasma processing chamber incorporating the Faraday shield is are provided. The plasma chamber includes an electrostatic chuck for receiving a substrate, a dielectric window connected to a top portion of the chamber, the dielectric window disposed over the electrostatic chuck, and a Faraday shield. The Faraday shield is disposed inside of the chamber and defined between the electrostatic chuck and the dielectric window. The Faraday shield includes an inner zone having an inner radius range that includes a first and second plurality of slots and an outer zone having an outer radius range that includes a third plurality of slots. The inner zone is adjacent to the outer zone. The Faraday shield also includes a band ring separating the inner zone and the outer zone, such that the first and second plurality of slots do not connect with the third plurality of slots. | 2016-06-09 |
20160163570 | SYSTEM AND METHOD FOR FORMING A SEALED CHAMBER - According to an embodiment of the invention, there is provided a system, comprising: a first chamber; a second chamber; a chuck; a movement system; wherein the first chamber comprises: a first element that has a first surface; a first chamber housing that comprises a second surface; wherein the first surface and the second surface come into proximity with each other at a first interface; a supporting element for supporting the chuck when the chuck is positioned within the first chamber; and a first dynamic seal formed at the first interface and is arranged to seal the first chamber from the movement system; wherein the second chamber comprises: a second chamber housing; a movement system that is arranged to introduce movement between (a) the first chamber housing and (b) the first element and the chuck; and a movement control element for mechanically coupling the first element to the movement system. | 2016-06-09 |
20160163571 | APPARATUS FOR REMOVING A RING-SHAPED REINFORCEMENT EDGE FROM A GROUND SEMICONDUCTOR WAFER - An apparatus for removing a ring-shaped reinforcement, edge from a ground semiconductor wafer, which is cohesively connected to an elastic carrier film and is fixed to a circumferential wafer frame via the carrier film, includes a holding device, which has a support having suction openings for holding the semiconductor wafer on the support surface of the support, and a separating device, which includes a device for integrally detaching the reinforcement edge from the carrier film. In order to be able to detach the reinforcement edge from the carrier film without damage, the holder device has a clamping device encompassing the support and serving for clamping the wafer frame and/or the carrier film, wherein the clamping device interacts with the support to stretch the carrier film, and the separating device has a tool guide with a dividing tool for moving the dividing tool between carrier film and reinforcement edge in order to detach the reinforcement edge in one piece from the carrier film stretched by interaction of clamping device and support. | 2016-06-09 |
20160163572 | METHOD AND SYSTEM RELATED TO SEMICONDUCTOR PROCESSING EQUIPMENT - A system including a first linear bearing, a second linear bearing, a first shuttle, and a second shuttle. The first linear bearing is mounted in and disposed along a linear path of a transfer chamber. The second linear bearing is mounted on a same side of the transfer chamber as the first linear bearing and disposed along the linear path. The first shuttle rides on the first linear bearing and carries a first wafer. The second shuttle rides on the second linear bearing and carries a second wafer. The second shuttle moves independent of the first shuttle. During movement of the first shuttle and the second shuttle and during a first period of time, a first portion of the second shuttle is above the first shuttle such that the first portion of the second shuttle is vertically overlapping the first shuttle. During movement of the first shuttle and the second shuttle and during a second period of time, the first portion of the second shuttle is not above the first shuttle such that the first portion of the second shuttle is not vertically overlapping the first shuttle. | 2016-06-09 |
20160163573 | SUBSTRATE TREATING APPARATUS WITH PARALLEL SUBSTRATE TREATMENT LINES - A substrate treating apparatus for treating substrates includes a plurality of substrate treatment lines arranged vertically for carrying out plural types of treatment on the substrates while transporting the substrates substantially horizontally, and a controller for changing processes of treatment carried out on the substrates for each of the substrate treatment lines. By changing the processes of treatment carried out for the substrates for each substrate treatment line, the processes of treatment carried out for the substrates can be changed for each substrate conveniently. Thus, a plurality of different processes of treatment corresponding to the number of substrate treatment lines can be carried out in parallel for the respective substrates. | 2016-06-09 |
20160163574 | DETERMINING CRITICAL PARAMETERS USING A HIGH-DIMENSIONAL VARIABLE SELECTION MODEL - A high-dimensional variable selection unit determines a list of critical parameters from sensor data and parametric tool measurements from a semiconductor manufacturing tool, such as a semiconductor inspection tool or other types of semiconductor manufacturing tools. The high-dimensional variable selection model can be, for example, elastic net, forward-stagewise regression, or least angle regression. The list of critical parameters may be used to design a next generation semiconductor manufacturing tool, to bring the semiconductor manufacturing tool back to a normal status, to match a semiconductor manufacturing tool's results with that of another semiconductor manufacturing tool, or to develop a specification for the semiconductor manufacturing tool. | 2016-06-09 |
20160163575 | DOOR FOR THIN PLATE CONTAINER - A door which closes an opening in a container body of a thin plate container. A door body has latch passage holes in the circumference thereof, which correspond to latch recesses in an inner circumferential surface of the opening, and a component installation space. A rotary cam is received in the component installation space and is rotated by manipulation. Latch arms, each having one end connected to the rotary cam in the component installation space, reciprocate depending on a direction of rotation of the rotary cam so that free end areas thereof enter or exit the latch recesses through the latch passage holes. When the rotary cam rotates in a locking direction, the latch arms move along straight lines until at least portions of the free end areas are inserted into the latch recesses and then pivot so that the free end areas are pressed toward the container body. | 2016-06-09 |
20160163576 | PROCESSING OBJECT TRANSPORT SYSTEM, AND SUBSTRATE INSPECTION SYSTEM - A substrate inspection system includes a plurality of processing units, and each processing unit is provided with a transport mechanism configured to transport an substrate to be inspected along a transport passage which extends substantially horizontally, a lift mechanism configured to lift the substrate to be inspected to a height position, at a set position on the transport passage, and processors each configured to perform a predetermined process on the substrate to be inspected positioned at the height position. The processing units are arranged such that transport passages thereof are aligned and such that the transport directions thereof are the same direction. Between two adjacent transport passages, the substrate to be inspected is delivered from the transport passage on an upstream side to the transport passage on a downstream side. | 2016-06-09 |
20160163577 | ELECTROSTATIC CHUCK HAVING REDUCED POWER LOSS - Embodiments of the invention generally relate to an electrostatic chuck having reduced power loss, and methods and apparatus for reducing power loss in an electrostatic chuck, as well as methods for testing and manufacture thereof. In one embodiment, an electrostatic chuck is provided. The electrostatic chuck includes a conductive base, and a ceramic body disposed on the conductive base, the ceramic body comprising an electrode and one or more heating elements embedded therein, wherein the ceramic body comprises a dissipation factor of about 0.11 to about 0.16 and a capacitance of about 750 picoFarads to about 950 picoFarads between the electrode and the one or more heating elements. | 2016-06-09 |
20160163578 | Semiconductor Packages and Methods of Forming the Same - A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer and protrude from the patterned layer to expose tapered sidewalls. | 2016-06-09 |
20160163579 | METHOD FOR MANUFACTURING LAMINATE, METHOD FOR MANUFACTURING SEALED SUBSTRATE LAMINATE, SEALED SUBSTRATE LAMINATE, AND SEALED SUBSTRATE - A laminate manufactured by forming a step difference in a substrate by grinding a periphery edge portion to have such a size that a surface on the inner side of the step difference can be housed in a cavity of a die, and then laminating the substrate, an adhesive layer, a release layer, and a support plate in this order such that the surface on the inner side of the step difference of the substrate faces the support plate. | 2016-06-09 |
20160163580 | CHUCKING WARPED WAFER WITH BELLOWS - A vacuum chuck has at least one suction assembly that pulls a wafer surface toward a chucking surface. The suction assembly may be used with a wafer that is warped. A suction force engages a pad of a suction assembly with the wafer surface and retracts a bellows of the suction assembly. As the bellows retracts and draws the wafer surface closer to the chucking surface, the suction force provided by the vacuum chuck can pull the wafer flat. | 2016-06-09 |
20160163581 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first insulator, and conductors and second insulators alternately provided on the first insulator. Each second insulator of the second insulators has a first side face adjacent to one of the conductors via a first air gap, a second side face adjacent to one of the conductors via a second air gap, first lower faces in contact with the first insulator, and second lower faces provided above the first insulator via third air gaps. | 2016-06-09 |
20160163582 | FORMATION OF ISOLATION SURROUNDING WELL IMPLANTATION - Embodiments of present invention provide a method of making well isolations. The method includes forming a hard-mask layer on top of said substrate; forming a first resist-mask on top of a first portion of the hard-mask layer and applying the first resist-mask in forming a first type of wells in a first region of the substrate; forming a second resist-mask on top of a second portion of the hard-mask layer and applying the second resist-mask in forming a second type of wells in a second region of the substrate; applying the first and second resist-masks in transforming the hard-mask layer into a hard-mask, the hard-mask having openings aligned to areas overlapped by the first and second regions of the substrate; etching at least the areas of the substrate in creating deep trenches that separate the first and second types of wells; and filling the deep trenches with insulating materials. | 2016-06-09 |
20160163583 | ISOLATION SCHEME FOR HIGH VOLTAGE DEVICE - Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage. | 2016-06-09 |
20160163584 | SELF-ALIGNED DOUBLE PATTERNING PROCESS FOR TWO DIMENSIONAL PATTERNS - One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material. | 2016-06-09 |
20160163585 | METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate structures above the source/drain region and under a masking layer feature of a patterned masking layer, forming a liner layer that contacts the island of insulating material and the masking layer feature, selectively removing the masking layer feature to thereby form an initial opening that is defined by the liner layer, performing at least one isotropic etching process through the initial opening to remove the island of first insulating material and thereby define a contact opening that exposes the source/drain region, and forming a conductive contact structure in the contact opening that is conductively coupled to the source/drain region. | 2016-06-09 |
20160163586 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A VIA STRUCTURE AND AN INTERCONNECTION STRUCTURE - Methods of fabricating a semiconductor device include forming a lower interlayer insulating layer and a conductive base structure, forming a middle interlayer insulating layer covering the lower interlayer insulating layer and the conductive base structure, etching the middle interlayer insulating layer to form a via hole, and an interconnection trench vertically aligned with the via hole, forming a via barrier layer on inner walls of the via hole, and an interconnection barrier layer on inner walls and a bottom of the interconnection trench, the via barrier layer not being formed on an upper surface of the conductive base structure, forming a via plug on the via barrier layer to fill the via hole, forming a seed layer on the interconnection trench and the via plug, forming an interconnection electrode on the seed layer, and forming an interconnection capping layer on the interconnection electrode. | 2016-06-09 |
20160163587 | SELF-ALIGNED VIA INTERCONNECT STRUCTURES - A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure. | 2016-06-09 |
20160163588 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. Disclosed is a semiconductor device including a substrate, a conductive line on the substrate, and a seed layer between the substrate and the conductive line, the seed layer including cobalt titanium nitride. | 2016-06-09 |
20160163589 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE STRUCTURES - A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level. | 2016-06-09 |
20160163590 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Disclosed is a method of manufacturing a semiconductor device. A preliminary wafer-carrier assembly is formed in such a way that a wafer structure having a plurality of via structures is adhered to a light-penetrating carrier by a photodegradable adhesive. A wafer-carrier assembly having an optical shielding layer for inhibiting or preventing a light penetration is formed such that the wafer structure, the carrier and the adhesive are covered with the optical shielding layer except for the backside of the wafer structure through which the via structures are exposed. An interconnector is formed on the backside of the wafer structure such that the via structures make contact with the interconnector, and the wafer structure and the carrier are separated from each other by irradiating a light to the wafer-carrier assembly. Accordingly, the adhesive is inhibited or prevented from being dissolved during a plasma process on the wafer-carrier assembly. | 2016-06-09 |
20160163591 | COPPER WIRING FORMING METHOD, FILM FORMING SYSTEM, AND STORAGE MEDIUM - A Cu wiring forming method of forming Cu wiring that is to be arranged in contact with tungsten wiring, by filling Cu into a recess formed in a substrate, includes: removing a tungsten oxide formed on a surface of the tungsten wiring; forming a nitriding preventing film at least on the surface of the tungsten wiring in the recess; forming a barrier film that prevents diffusion of Cu, on a surface in the recess from above the nitriding preventing film; forming a liner film on the barrier film; and filling a Cu film on the liner film. | 2016-06-09 |
20160163592 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices. | 2016-06-09 |
20160163593 | METHOD FOR FORMING A SELF-ALIGNED CONTACT IN A DAMASCENE STRUCTURE USED TO FORM A MEMORY DEVICE - Exemplary embodiments of the present invention are directed towards a method for fabricating a self-aligned contact under a bitline in a damascene structure for a memory device comprising forming a dummy pattern, forming dielectric sidewalls using a first dielectric film around the dummy pattern, forming a second dielectric film around the dielectric sidewalls, removing the dummy pattern forming a plurality of trenches, depositing active cell material in each of the plurality of trenches, forming a third dielectric film atop the active cell material; and creating a self-aligned contact hole using etch selectivity between the dielectric sidewalls and the second dielectric film. | 2016-06-09 |
20160163594 | METHOD FOR FORMING VOID-FREE POLYSILICON AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. A sacrificial spacer is formed on sidewalls of the insulating layer defining the contact hole. A polysilicon layer pattern is formed in the contact hole. The sacrificial spacer is removed to form an air gap around the polysilicon layer pattern. A thermal process is performed to remove a seam existing in the polysilicon layer pattern. | 2016-06-09 |
20160163595 | METHOD FOR MANUFACTURING THROUGH-HOLE SILICON VIA - A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon. | 2016-06-09 |
20160163596 | PROCESS AND MATERIAL FOR PREVENTING DELETERIOUS EXPANSION OF HIGH ASPECT RATIO COPPER FILLED THROUGH SILICON VIAS (TSVS) - Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW | 2016-06-09 |
20160163597 | WAFER PROCESSING METHOD - A wafer processing method for dividing a wafer into individual device chips along division lines is disclosed. The wafer processing method includes a back grinding step of grinding the back side of the wafer in the condition where a protective tape is attached to the front side of the wafer, thereby reducing the thickness of the wafer to a predetermined thickness, and a reinforcing insulation seal mounting step of mounting a reinforcing insulation seal capable of transmitting infrared light on the back side of the wafer. The wafer processing method further includes a modified layer forming step of applying a laser beam along each division line to thereby form a modified layer inside the wafer along each division line and a wafer dividing step of applying an external force to the wafer to thereby divide the wafer into the individual device chips along each division line. | 2016-06-09 |
20160163598 | METHOD OF FORMING A BICMOS SEMICONDUCTOR CHIP THAT INCREASES THE BETAS OF THE BIPOLAR TRANSISTORS - The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant. | 2016-06-09 |
20160163599 | PERFORMANCE OPTIMIZED GATE STRUCTURES - A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device. | 2016-06-09 |
20160163600 | SELF-ALIGNED QUADRUPLE PATTERNING PROCESS - Methods for modifying a spacer and/or spaces between spacers to enable a fin cut mask to be dropped between the spacers are provided. A first set of second mandrel structures having a first width is formed on facing sidewall surfaces of a neighboring pair of first mandrel structures and a second set of second mandrel structures having a second width less than the first width are formed on non-facing sidewall surfaces of the neighboring pair of first mandrel structures. Each first mandrel structure is removed and a spacer is formed on a sidewall surface of the first and second sets of second mandrel structures. In the region between the neighboring pair of first mandrel structure, a merged spacer is formed. The first and second sets of second mandrel structures are removed. A portion of an underlying substrate can be patterned utilizing each spacer and the merged spacer as etch masks. | 2016-06-09 |
20160163601 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities. | 2016-06-09 |
20160163602 | VERTICAL FIELD EFFECT TRANSISTORS - Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin. | 2016-06-09 |
20160163603 | PFET GATE STACK MATERIALS HAVING IMPROVED THRESHOLD VOLTAGE, MOBILITY AND NBTI PERFORMANCE - A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a p-type field effect transistor (PFET) workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a lower titanium nitride (TiN) first layer and a second layer including one of titanium-aluminum-carbide (TiAlC) and tantalum-aluminum-carbide (TaAlC) formed on the lower TiN first layer. | 2016-06-09 |
20160163604 | METHODS OF FORMING DIFFUSION BREAKS ON INTEGRATED CIRCUIT PRODUCTS COMPRISED OF FINFET DEVICES AND THE RESULTING PRODUCTS - One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin. | 2016-06-09 |
20160163605 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor structure is provided. The method includes providing a semiconductor substrate; and forming a plurality of semiconductor devices on the semiconductor substrate. The method also includes forming a dielectric layer covering the plurality of the semiconductor devices on the semiconductor substrate; and forming an optical auxiliary layer configured to reflect a portion of a levelness-detecting light and absorb a portion of the levelness detecting light transmitting through the optical auxiliary layer during a levelness-detecting process over the dielectric layer. Further, the method includes forming a photoresist layer over the optical auxiliary layer; and detecting a levelness of the semiconductor substrate and exposing the photoresist layer to form a patterned photoresist layer. | 2016-06-09 |
20160163606 | Generating a Wafer Inspection Process Using Bit Failures and Virtual Inspection - Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during scanning of a wafer regardless of whether the output corresponds to defects detected on the wafer and separating physical locations on the wafer that correspond to bit failures detected by testing of the water into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected. In addition, the method includes applying defect detection method(s) to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations and generating a wafer inspection process based on the defects detected by the defect detection method(s) at the first portion of the physical locations. | 2016-06-09 |
20160163607 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND METHOD OF TESTING SEMICONDUCTOR DEVICE - A semiconductor device may include a semiconductor substrate doped with a first type impurity; a through electrode inserted in the semiconductor substrate; an active area formed in the semiconductor substrate to surround an upper portion of sidewalls of the through electrode, and doped with a second type impurity; an insulating layer formed between the semiconductor substrate and the through electrode, and between the active area and the through electrode; a drive circuit suitable for applying a first voltage to the through electrode in a test operation; and a test pad connected to the active area electrically in the test operation, to which a voltage is applied from outside. | 2016-06-09 |
20160163608 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pad including a connection pad and a measurement pad; and a chip bump including a first bump provided between the package substrate and the connection pad and a second bump provided between the package substrate and the measurement pad. An interconnection disposed within the package substrate is not connected to the second bump to be electrically isolated from the second bump. | 2016-06-09 |
20160163609 | METHODS AND APPARATUS FOR TESTING AUXILIARY COMPONENTS IN A MULTICHIP PACKAGE - Ways for testing a multichip package while reducing the required test pin count are provided. The multichip package may include a main die coupled to multiple daughter components. During testing, one of the daughter components may be selected for testing while other daughter components sit idle. The daughter components may receive test signals via a shared path. Dedicated select pins may be used to activate the selected daughter component while placing the unselected components in tristate mode. The selection of daughter components during testing can also be controlled directly using the main die. If desired, general-purpose input-output (GPIO) pins of the main die may be borrowed from the main die to convey the test signals to the selected daughter component during testing. If desired, multiplexing circuitry may also be used to selectively route signals to the daughter components during testing. | 2016-06-09 |
20160163610 | SEMICONDUCTOR DIE AND PACKAGE JIGSAW SUBMOUNT - A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and having relatively narrow edge surfaces and first and second relatively large face surfaces; at least one recess formed along an edge surface; a layer of a conducting material formed on a surface of each of the at least one recess; a first plurality of soldering pads on the first face surface configured to make electrical contact with a semiconductor device; and electrically conducting connections each of which electrically connects a soldering pad in the first plurality of soldering pads to the layer of conducting material of a recess of the at least one recess. | 2016-06-09 |
20160163611 | LAMINATE SUBSTRATES HAVING RADIAL CUT METALLIC PLANES - A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a core that includes particle-filled epoxy and a metallic layer on the core. At least one laminate layer has a radial cut through the metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer. The radial cut cuts only through the metallic layer and does not cut through the core. | 2016-06-09 |
20160163612 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to semiconductor packages and methods of manufacturing the same. In an embodiment, the semiconductor package includes a substrate, a semiconductor element, at least one connecting element, and an encapsulant. The semiconductor element is mounted to the substrate. The connecting element is disposed on the substrate and adjacent to the semiconductor element. The encapsulant covers at least a portion of the semiconductor element and at least a portion of the connecting element and defines at least one first groove surrounding the connecting element. | 2016-06-09 |
20160163613 | ELECTRONIC APPARATUS - An electronic apparatus includes a board, a first electronic component, a mold resin and a second electronic component. The board has a first surface and a second surface opposite to the first surface. The first electronic component is mounted on the first surface of the board. The mold resin seals the first electronic component and the first surface of the board. The second electronic component is arranged on the mold resin. | 2016-06-09 |
20160163614 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes a first substrate, a patterned solder mask, first thermal-conductive posts, a chip and a second substrate. The first substrate includes a first patterned metal layer, a second patterned metal layer, a first surface and a second surface. The first and second patterned metal layers are disposed on the first and second surfaces. The patterned solder mask disposed on the first and second patterned metal layers exposes part of the first and second patterned metal layers. The first thermal-conductive posts are disposed on the exposed first patterned metal layer and thermally coupled thereto. The chip is disposed on the first surface. The chip electrically connected to the first patterned metal layer is thermally coupled to the first thermal-conductive posts. Two opposite ends of each first thermal-conductive post are connected to the first and second substrates, and the first thermal-conductive posts are thermally coupled to the second substrate. | 2016-06-09 |
20160163615 | SEMICONDUCTOR DEVICE - For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device. | 2016-06-09 |
20160163616 | Heat Spreader, Electronic Module Comprising a Heat Spreader and Method of Fabrication Thereof - An electronic module includes a semiconductor package, a heat spreader attached to the semiconductor package and an electrically insulating layer disposed on the heat spreader remote from the semiconductor package. | 2016-06-09 |
20160163617 | CERAMIC CIRCUIT BOARD AND ELECTRONIC DEVICE - A ceramic circuit board includes a ceramic substrate, a first metal plate bonded to a front surface of the ceramic substrate, and a member bonded to a front surface side of the metal plate. The member is made up from a material which exhibits a lower coefficient of thermal expansion than that of the first metal plate, and which exhibits a higher Young's modulus than that of the first metal plate. | 2016-06-09 |
20160163618 | HEAT DISSIPATING CIRCUIT BOARD AND ELECTRONIC DEVICE - A heat dissipating circuit board for a power semiconductor includes an electrode material on which a power semiconductor is mounted on a front surface thereof, and a member bonded to a front surface side of the electrode material. The member is made up from a material which exhibits a lower coefficient of thermal expansion than that of the electrode material, and which exhibits a higher Young's modulus than that of the electrode material. | 2016-06-09 |
20160163619 | SEMICONDUCTOR CHIP AND STACK TYPE SEMICONDUCTOR APPARATUS USING THE SAME - A semiconductor may include a core block configured to store and output data, and may be configured to output internal information. The semiconductor may include a through via configured for signal transfer with another semiconductor chip. The semiconductor may include an internal information processing circuit configured to transmit internal information selected from the internal information to the through via, or may be configured to output internal information of the other semiconductor chip, which has been transmitted through the through via, to an exterior through a special purpose pin, in response to test signals. | 2016-06-09 |
20160163620 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP - A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad. | 2016-06-09 |
20160163621 | SINGLE-LAYER WIRING PACKAGE SUBSTRATE, SINGLE-LAYER WIRING PACKAGE STRUCTURE HAVING THE PACKAGE SUBSTRATE, AND METHOD OF FABRICATING THE SAME - A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced. | 2016-06-09 |
20160163622 | PACKAGING-BEFORE-ETCHING FLIP CHIP 3D SYSTEM-LEVEL METAL CIRCUIT BOARD STRUCTURE AND TECHNIQUE THEREOF - Provided are a packaging-before-etching flip chip 3D system-level metal circuit board structure and technique thereof. The metal circuit board structure comprises a metal substrate frame; the front face of the metal substrate frame is provided with pins; the front faces of the pins are provided with conductive posts; chips are installed in a flip manner between the pins via underfills; the peripheral areas of the pins, the conductive posts and the chip are encapsulated with molding compound, the top of the molding compound being parallel to the tops of the conductive posts; and the surfaces of the metal substrate frame, the pins and the conductive posts exposing out of the molding compounds are provided with an anti-oxidation layer, thus solving the problem of limited functionality and application of a traditional metal lead frame due to the fact that objects cannot be embedded therein. | 2016-06-09 |
20160163623 | SYSTEM, METHOD AND APPARATUS FOR LEADLESS SURFACE MOUNTED SEMICONDUCTOR PACKAGE - A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body. | 2016-06-09 |