23rd week of 2016 patent applcation highlights part 60 |
Patent application number | Title | Published |
20160163324 | APPARATUS AND METHOD FOR PROCESSING AN AUDIO SIGNAL USING AN ALIASING ERROR SIGNAL - An apparatus for processing an audio signal including a sequence of blocks of spectral values, includes: a processor for calculating an aliasing-affected signal using at least one first modification value for a first block of the sequence of blocks and using at least one different second modification value for a second block of the sequence of blocks and for estimating an aliasing-error signal representing an aliasing-error in the aliasing-affected signal; and a combiner for combining the aliasing-affected signal and the aliasing-error signal such that a processed signal obtained by the combining is an aliasing-reduced or aliasing-free signal. | 2016-06-09 |
20160163325 | METHOD FOR SPEECH CODING, METHOD FOR SPEECH DECODING AND THEIR APPARATUSES - A high quality speech is reproduced with a small data amount in speech coding and decoding for performing compression coding and decoding of a speech signal to a digital signal. In speech coding method according to a code-excited linear prediction (CELP) speech coding, a noise level of a speech in a concerning coding period is evaluated by using a code or coding result of at least one of spectrum information, power information, and pitch information, and various excitation codebooks are used based on an evaluation result | 2016-06-09 |
20160163326 | PITCH FILTER FOR AUDIO SIGNALS - In some embodiments, a pitch filter for filtering a preliminary audio signal generated from an audio bitstream is disclosed. The pitch filter has an operating mode selected from one of either: (i) an active mode where the preliminary audio signal is filtered using filtering information to obtain a filtered audio signal, and (ii) an inactive mode where the pitch filter is disabled. The preliminary audio signal is generated in an audio encoder or audio decoder having a coding mode selected from at least two distinct coding modes, and the pitch filter is capable of being selectively operated in either the active mode or the inactive mode while operating in the coding mode based on control information. | 2016-06-09 |
20160163327 | AUTOMATIC TIMBRE CONTROL - A system and method for automatically controlling the timbre of a sound signal in a listening room are also disclosed, which include the following: producing sound in the time domain from a re-transformed electrical sound signal in the time domain, in which an electrical sound signal in the time domain being transformed into electrical sound signal in the frequency domain and the electrical sound signal in the frequency domain being re-transformed into the re-transformed electrical sound signal; generating a total sound signal representative of the total sound in the room, processing the total sound signal to extract an estimated ambient noise signal representing the ambient noise in the room; and adjusting the spectral gain of the electrical sound signal in the frequency domain dependent on the estimated ambient noise signal, the electrical sound signal and a room dependent gain signal. | 2016-06-09 |
20160163328 | TERMINAL, AUDIO DEVICE COMMUNICATING WITH TERMINAL, AND VEHICLE - A terminal includes: a communication unit configured to communicate with a hands-free device and an audio device provided in a place in which speech is produced; and a control unit configured to perform control such that: i) when a filter generation mode is selected, a test signal is generated, ii) when a microphone signal transmitted from the hands-free device is received, the received microphone signal and the generated test signal are mixed, and the mixed signal is transmitted to the audio device, and iii) when a feedback signal transmitted from the hands-free device is received, a sound feedback removing filter is generated based on the received feedback signal, and the generated sound feedback removing filter is transmitted to the audio device. | 2016-06-09 |
20160163329 | METHOD AND APPARATUS FOR MANAGING AUDIO SIGNALS - A method comprising: detect a first acoustic signal by using a microphone array; detecting a first angle associated with a first incident direction of the first acoustic signal; and storing, in a memory, a representation of the first acoustic signal and a representation of the first angle. | 2016-06-09 |
20160163330 | ELECTRONIC DEVICE AND CONTROL METHOD - According to one embodiment, an electronic device includes a receiver and a hardware processor. The receiver is configured to receive an audio signal. The hardware processor is configured to enable a first function comprising separating the audio signal into a voice signal and a background sound signal and emphasizing or suppressing either the voice signal or the background sound signal and enable a second function comprising giving an acoustic effect to the audio signal. The hardware processor is further configured to receive an user operation to turn on either the first function or the second function and restrict the second function, if the first function is turned on. | 2016-06-09 |
20160163331 | ELECTRONIC DEVICE AND METHOD FOR VISUALIZING AUDIO DATA - According to one embodiment, an electronic displays a first block including speech segments, wherein a main speaker of the first block is visually distinguishable. When the first block includes a first speech segment of a first speaker and a second speech segment of a second speaker, the first speech segment is longer than the second speech segment, and the second speaker is not a speaker whose amount of speech of the sequence of the audio data is smaller than that of the first speaker or a first amount, the first speaker is determined as a main speaker of the first block. | 2016-06-09 |
20160163332 | EMOTION TYPE CLASSIFICATION FOR INTERACTIVE DIALOG SYSTEM - Techniques for selecting an emotion type code associated with semantic content in an interactive dialog system. In an aspect, fact or profile inputs are provided to an emotion classification algorithm, which selects an emotion type based on the specific combination of fact or profile inputs. The emotion classification algorithm may be rules-based or derived from machine learning. A previous user input may be further specified as input to the emotion classification algorithm. The techniques are especially applicable in mobile communications devices such as smartphones, wherein the fact or profile inputs may be derived from usage of the diverse function set of the device, including online access, text or voice communications, scheduling functions, etc. | 2016-06-09 |
20160163333 | CONFERENCING SYSTEM AND METHOD FOR CONTROLLING THE CONFERENCING SYSTEM - A communication system and a method can be configured to facilitate the performance of a conference. The system can include a conference organizer terminal and at least two participants' terminals each assigned to respective conference participants who each log in to start a conference on the communication system. The communication system can be configured to calculate a decision situation at a particular point in time of the ongoing conference by analyzing the views expressed by the conference participants during the conference and send data relating to the decision situation for that point in time to the conference organizer's terminal and/or other conference participant terminals for use in facilitating the conference. IN some embodiments, such data can be used to assist the conference participants' in recognizing when there is a consensus made on at least one decision to be made during the conference. | 2016-06-09 |
20160163334 | VOICE SIGNAL PROCESSING DEVICE AND VOICE SIGNAL PROCESSING METHOD - Up-sampler generates an up-sampled sound signal from the sound signal. From the up-sampled sound signal, odd-ordered high-harmonic generator generates an odd-ordered high-harmonic, and even-ordered high-harmonic generator generates an even-ordered high-harmonic. Vowel sound detector identifies whether or not the sound signal is vowel sound, and generates a first gain value and a second gain value. First gain controller amplifies or attenuates the odd-ordered high-harmonic based on the first gain value, and outputs the resultant odd-ordered high-harmonic. Second gain controller amplifies or attenuates the even-ordered high-harmonic based on the second gain value, and outputs the resultant even-ordered high-harmonic. Sound signal processing device adds the gain-adjusted odd-ordered high-harmonic and the gain-adjusted even-ordered high-harmonic to the up-sampled sound signal, and outputs the up-sampled sound signal having the high-harmonics added. | 2016-06-09 |
20160163335 | METHOD AND DEVICE FOR PROCESSING A SOUND SIGNAL - A method of processing a sound signal is disclosed. The method of processing a sound signal includes receiving a sound signal from the outside of a device, converting the sound signal into a first frequency domain signal, determining whether or not the sound signal is a voice signal using the first frequency domain signal acquired through the conversion, converting the first frequency domain signal into a second frequency domain signal based on the determination, and recognizing the sound signal using the second frequency domain signal acquired through the conversion. | 2016-06-09 |
20160163336 | DEVICES INCLUDING AT LEAST ONE INTERMIXING LAYER - Devices that include a near field transducer (NFT), the NFT including a peg having five surfaces, the peg including a first material, the first material including gold (Au), silver (Ag), aluminum (Al), copper (Cu), ruthenium (Ru), rhodium (Rh), iridium (Ir), or combinations thereof; an overlying structure; and at least one intermixing layer, positioned between the peg and the overlying structure, the at least one intermixing layer positioned on at least one of the five surfaces of the peg, the intermixing layer including at least the first material and a second material. | 2016-06-09 |
20160163337 | MAGNETIC STACK INCLUDING COOLING ELEMENT - Various embodiments of a magnetic stack are disclosed. In one or more embodiments, the magnetic stack includes first and second shield layers, and a magnetically responsive lamination disposed between the first and second shield layers. The magnetically responsive lamination can be configured to receive a sense current I | 2016-06-09 |
20160163338 | TUNNELING MAGNETORESISTIVE (TMR) SENSOR WITH A SOFT BIAS LAYER - An apparatus according to one embodiment includes a read sensor. The read sensor has an antiferromagnetic layer (AFM), a first antiparallel magnetic layer (AP1 ) positioned above the AFM layer in a first direction oriented along a media-facing surface and perpendicular to a track width direction, a non-magnetic layer positioned above the AP1 in the first direction, a second antiparallel magnetic layer (AP2) positioned above the non-magnetic layer in the first direction, a harrier layer positioned above the AP2 in the first direction, and a free layer positioned above the barrier layer in the first direction. A soft bias layer is positioned behind at least a portion of the free layer in an element height direction normal to the media-facing surface, the soft bias layer including a soft magnetic material configured to compensate for a magnetic coupling of the free layer with the AP2. | 2016-06-09 |
20160163339 | Slider With Aluminum Compound Fill - Embodiments disclosed herein generally relate to a magnetic device. The magnetic head of the magnetic device includes structure for protecting the media facing surface (MFS). The protective structure, which may be referred to as an air bearing surface overcoat (ABSOC) structure, includes an aluminum containing compound that is disposed on the slider and head. The ABSOC also includes a silicon containing compound and a carbon layer disposed thereover. | 2016-06-09 |
20160163340 | MICROWAVE-ASSISTED MAGNETIC HEAD AND MAGNETIC RECORDING/REPRODUCING APPARATUS - According to one embodiment, a microwave-assisted magnetic head includes a main magnetic pole configured to apply a recording magnetic field to a magnetic recording medium, an auxiliary magnetic pole configured to constitute a magnetic circuit together with the main magnetic pole, and a domain propagation element including a domain propagation path having two ends and a magnetic anisotropy perpendicular to a domain propagation direction, and a domain input portion configured to write a magnetic domain in the domain propagation path, and a current supply mechanism connected to the domain propagation path, and at least part of the domain propagation path passes between the main magnetic pole and the auxiliary magnetic pole. | 2016-06-09 |
20160163341 | Angled Waveguide - An apparatus has an input surface configured to receive energy emitted from an energy source in a first mode. A mode order converter is configured to convert the energy from the first mode to a second mode. The waveguide of the apparatus has an input end disposed proximate the input surface and configured to receive the energy in the first mode. The waveguide has an output end disposed proximate a media-facing surface and configured to deliver energy in the second mode. The output end is at an oblique angle to a cross-track line at an intersection of the media-facing surface and a substrate-parallel plane. | 2016-06-09 |
20160163342 | APPARATUS, SYSTEMS AND PROCESSES FOR REDUCING A HARD DISK DRIVE'S ACCESS TIME AND CONCOMITANT POWER OPTIMIZATION - Rotational latency is reduced in a standard conventional form factor HDD system by replacing, for example, the prior art rotary arm actuator of a conventional HDD, with one or more belts and pulleys and one or more read/write heads mounted on, or otherwise associated with the belts. Multiple scaled iterations facilitate energy savings and power optimized systems, without compromise to data access performance. | 2016-06-09 |
20160163343 | APPARATUS AND METHOD FOR SETTING SLIDER SURFACE POTENTIAL - An apparatus includes a slider body of a disk drive. The slider body is electrically coupled to a plurality of end bond pads. A voltage applied to one more of the end bond pads sets a surface potential of the slider body. | 2016-06-09 |
20160163344 | DISK-SHAPED GLASS SUBSTRATE, MAGNETIC-DISK GLASS SUBSTRATE, METHOD FOR MANUFACTURING MAGNETIC-DISK GLASS SUBSTRATE, AND MAGNETIC DISK - A disk-shaped glass substrate for a magnetic-disk glass substrate includes an outer circumference having a roundness of 1.3 μm or less. A first reference circle is obtained with a least squares method from a first outline corresponding to a shape of a lap around the outer circumference. A second reference circle is obtained with a least squares method from a second outline obtained by performing low-pass filtering using a period in which the number of peaks per lap is 150 as a cut-off value on the first outline. A ratio of the second peak count value defined by the number of peaks of the second outline that project outward in a radial direction from the second reference circle to the first peak count value defined by the number of peaks of the first outline that project outward in a radial direction from the first reference circle is 0.2 or less. | 2016-06-09 |
20160163345 | MAGNETIC RECORDING MEDIUM AND PRODUCTION METHOD OF MAGNETIC RECORDING MEDIUM - The present invention provides: a method of producing, at low temperature, a magnetic recording medium comprising an L1 | 2016-06-09 |
20160163346 | IN-SITU ANNEALING OF A TMR SENSOR - A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions area executable by a data processing system having at least one processor to cause the data processing system to apply, by the data processing system, a current to a lead of a tunneling magnetoresistance (TMR) sensor for inducing joule heating of the lead or a heating layer, the level of joule heating being sufficient to anneal a magnetic layer of the sensor; and maintain, by the data processing system, the current at the level for an amount of time sufficient to anneal the sensor. | 2016-06-09 |
20160163347 | INFORMATION RECORDING AND PLAYBACK DEVICE - An information recording and playback device includes a recording and playback unit, and a controller. The controller divides a recording area of an optical disk into a first recording area which is at an inner circumference side, and a second recording area which is at an outer circumference side. The controller controls the recording and playback unit such that the unit records or plays back data in the first recording area at a first speed, and records or plays back data in the second recording area at a second speed slower than the first speed. The predetermined radius is set to a boundary between an area in which a control residual exceeds a predetermined reference value when servo control related to focusing and tracking is performed on the recording area of the optical disk, and an area in which the control residual does not exceed the predetermined reference value. | 2016-06-09 |
20160163348 | DRIVE DEVICE FOR THE BIO-DISC DETECTION - A driver device and a method for bio-disc detection are provided. A spindle motor rotates a bio-disc by a central hole at a high speed. A step motor rotates a periphery of a clamper to rotate the bio-disc at a low speed. When the spindle motor and the step motor work together in conjunction with the separation, mixing and detection process, various rotation modes such as high speed mode, braking mode, direction switching mode and low speed rotation mode can be provided to increase the detection efficiency of the bio-disc. | 2016-06-09 |
20160163349 | SPINDLE MOTOR, DISK DRIVE APPARATUS, AND METHOD OF MANUFACTURING BASE UNIT OF SPINDLE MOTOR - A method of manufacturing a base unit of a spindle motor includes the steps of: defining a base plate including a support fitting portion; fitting a support to a hole portion passing through the support fitting portion; measuring an inclination of the support fitting portion; calculating a laser irradiation area and a laser irradiation output based on the inclination; irradiating the support fitting portion with a laser beam; and measuring the inclination of the support fitting portion again. The base plate is made of a metal, and is defined by press working, casting, or forging. The support is fitted to the hole portion by crimping, press fitting, or welding. This method reduces the inclination of the support fitting portion, thereby reducing a distortion of the support, which serves as a rotation center of an access portion. | 2016-06-09 |
20160163350 | SPINDLE MOTOR FOR DRIVING A HARD DISK DRIVE - The invention relates to the spindle motor for driving a hard disk drive, comprising: a fixed engine component ( | 2016-06-09 |
20160163351 | WRITE INTERFERENCE REDUCTION WHEN READING WHILE WRITING TO A HARD DISK DRIVE MEDIA - A hard disk drive device and a method and apparatus for control of the hard disk drive is provided. The hard disk drive includes disk media, a slider head, a head gimbal assembly and a control means. The disk media includes at least two layers for data storage. The slider head flies above the disk media and includes a writer and a reader, and a head gimbal assembly supports the slider head above the disk media. The control means is physically coupled to the head gimbal assembly and electrically coupled to the writer and the reader for reducing write interference from the writer when the writer is writing to the disk media while the reader is reading from the disk media, wherein write interference is reduced in one or more of a time domain and a frequency domain. | 2016-06-09 |
20160163352 | Systems and Methods for Multi-Dimensional Equalization Constraint - Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for multi-dimensional signal equalization. In one case, a data processing system is discussed that includes: a first equalizer governed at least in part by a first coefficient; a second equalizer circuit governed at least in part by a second coefficient; and a constraint circuit operable to force a sum of at least the first coefficient and the second coefficient to equal a defined value. | 2016-06-09 |
20160163353 | VIDEO EDITING WITH CONNECTED HIGH-RESOLUTION VIDEO CAMERA AND VIDEO CLOUD SERVER - An apparatus having a server is disclosed. The server may be configured to (i) receive via a network a first clip of video generated by a camera, (ii) receive via the network first information to edit the first clip, (iii) receive via the network one or more segments of a second clip of video generated by the camera as identified by the first information and (iv) create a third clip of video by editing the segments according to the first information. The second clip is generally a higher resolution version of the first clip. The third clip may have the higher resolution. | 2016-06-09 |
20160163354 | Programme Control - A system for controlling the presentation of audio-video programmes has an input for receiving audio-video programmes. A data comparison unit is arranged to produce at intervals throughout the programme a value for each of f features of the audio-video and then to derive from the features a metadata value, the metadata value having M dimensions, the number of dimensions being smaller than the number of features. A threshold is applied to the metadata value to determine points of interest within the audio-video programmes and a controller is arranged to control retrieval and playback of the programmes using the interesting points. | 2016-06-09 |
20160163355 | FILE GENERATION DEVICE AND METHOD, AND CONTENT PLAYBACK DEVICE AND METHOD - The present disclosure relates to a file generation device and method, and a content playback device, enabling efficient access to arbitrary subsamples within a sample. Information for acquiring arbitrary subsamples (tiles) is disposed not by extending the sidx and the ssix, but by defining a separate box, a general subsegment index box (gsix), after the sidx and the ssix at the beginning of the segment file. The present disclosure may be applied to a content playback system equipped with a content server and a content playback device, for example. | 2016-06-09 |
20160163356 | HDR METADATA TRANSPORT - A video distribution system transfers a formatted video signal ( | 2016-06-09 |
20160163357 | SEMICONDUCTOR MEMORY - A semiconductor memory including a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair in which the sense amplifier includes; precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors each having a diffusion layer formed integrally with the diffusion layer of the precharging transistor for selectively connecting the plurality of the bit line pairs to a common bus line. | 2016-06-09 |
20160163358 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - In a configuration including a memory cell that retains multilevel data by controlling the on/off state of a transistor, correct data can be read out even if a potential of data retained by turning off the transistor is changed. The memory cell controls writing or retention of data corresponding to one of a plurality of potentials by controlling an on/off state of the transistor. The write voltage generator circuit outputs a first write voltage of data to be written to the memory cell. The write voltage generator circuit obtains a read voltage of the data by reading the first write voltage written to the memory cell. The write voltage generator circuit generates a second write voltage by correcting a change of the first write voltage caused by turning off the transistor, and outputs the second write voltage to the memory cell. | 2016-06-09 |
20160163359 | DATA SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME - A data sense amplifier may include: first and second external nodes, wherein a potential difference occurs between the first and second external nodes when a memory cell is selected; an amplification unit suitable for generating and amplifying a potential difference between first and second nodes in response to the potential difference between the first and second external nodes; and a switching unit suitable for electrically coupling the first and second external nodes to the first and second nodes, respectively, after a predetermined time elapses from when the memory cell is selected. | 2016-06-09 |
20160163360 | LATCH CIRCUIT AND LATCH CIRCUIT ARRAY INCLUDING THE SAME - A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a PMOS transistor and an NMOS transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a K | 2016-06-09 |
20160163361 | DATA OUTPUT CIRCUIT - A data output circuit includes a first trigger unit and a signal generation unit. The first trigger unit is inputted with first data in a first mode and a second mode, and outputs the first data in response to a first trigger signal. The signal generation unit, in the first mode, outputs the first trigger signal in response to a first clock signal, and, in the second mode, retains the first trigger signal in a first state regardless of the first clock signal. | 2016-06-09 |
20160163362 | INPUT CIRCUIT OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME - An input circuit of a semiconductor apparatus may include a first input buffer configured to receive a signal through a test input terminal and to output a first input signal, a second input buffer configured to receive a signal through a normal input terminal and to output a second input signal. The input circuit of the semiconductor apparatus may include a switching unit configured to transfer the signal inputted through the test input terminal to the second input buffer according to a test mode signal. The input circuit of the to semiconductor apparatus may include a comparison unit configured to compare the first input signal with the second input signal and to generate a comparison signal, and a storage unit configured to store the comparison signal. | 2016-06-09 |
20160163363 | SEMICONDUCTOR MEMORY APPARATUS AND INPUT BUFFER THEREFOR - A semiconductor memory apparatus may include an input buffer configured to receive an external signal, boost the external signal to a frequency according to an operation mode signal, and generate an internal signal; and an internal circuit configured to operate by receiving the internal signal. | 2016-06-09 |
20160163364 | SEMICONDUCTOR MEMORY DEVICE - Disclosed is a semiconductor memory device including: a sense amplifier capable of sensing and amplifying data loaded on a data-line pair based on a pull-up driving voltage and a pull-down driving voltage; a pull-up driving unit capable of supplying a first voltage as the pull-up driving voltage for first and third active sections of an active mode, and supplying a second voltage having a voltage level lower than the first voltage as the pull-up driving voltage for a second active section of the active mode, between the first and third active sections of the active mode; and a pull-down driving unit capable of supplying a third voltage as the pull-down driving voltage for the first to third active sections of the active mode and for an initial section of a precharge mode after the active mode. | 2016-06-09 |
20160163365 | SEMICONDUCTOR DEVICE - A semiconductor device may include a mat array, and a plurality of memory cell mats each including bit lines. The memory cell mats may be included in the mat array. The semiconductor device may include edge sense amplifier blocks comprising edge sense amplifiers coupled to half of the bit lines of the outermost memory cell mats among the memory cell mats. The half of the bit lines of the outermost memory cell mats may be coupled to the edge sense amplifiers, respectively, and may be configured for a first input. The semiconductor device may include half dummy mats each having an area corresponding to half of the area of a memory cell mat of the plurality of memory cell mats and configured to provide reference bit lines for a second input to the edge sense amplifiers, respectively. | 2016-06-09 |
20160163366 | MEMORY DEVICE, RELATED METHOD, AND RELATED ELECTRONIC DEVICE - A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor. | 2016-06-09 |
20160163367 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may include a decoding control block configured to generate a first decoding control signal and a second decoding control signal in response to a double enable signal and a first address. The semiconductor memory apparatus may include a decoding block configured to enable only one word line among a plurality of word lines or may simultaneously enable at least two word lines among the plurality of word lines, in response to the first and second decoding control signals and a second address. | 2016-06-09 |
20160163368 | ADDRESS COMPARATOR CIRCUIT, MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - An address comparator circuit includes a first determination unit suitable for activating a first control signal when a first address corresponding to a previous read command is identical with a second address corresponding to a current read command; a second determination unit suitable for activating a second control signal when the previous and current read commands are consecutively inputted to the address comparator circuit with an interval of a specific number of clocks or less; and a blocking signal generation unit suitable for generating a blocking signal that blocks data transmission between a memory array and an external device based on the first and the second control signals. | 2016-06-09 |
20160163369 | MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device including magnetic tunnel junctions, which are spaced apart from each other on a substrate, and each of which includes a free magnetic pattern, a first pinned magnetic pattern, and a tunnel barrier pattern therebetween. The semiconductor device further includes a separation structure interposed between the magnetic tunnel junctions. The separation structure includes a second pinned magnetic pattern and a first insulating pattern stacked to each other. | 2016-06-09 |
20160163370 | MEMORY DEVICE - According to one embodiment, a memory device includes a first memory element being able to store data, and a second memory element storing information relating to the first memory element, wherein the information of the second memory element is rewritten by a power amount, which is greater than a power amount at a time when the data is written in the first memory element, being supplied to the second memory element. | 2016-06-09 |
20160163371 | NON-DESTRUCTIVE WRITE/READ LEVELING - In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device. | 2016-06-09 |
20160163372 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD THEREOF - A semiconductor memory device includes a memory bank including a plurality of word lines, and a refresh operation control unit suitable for performing a first refresh operation for a first adjacent word line group of a target word line of the plurality of word lines, and performing a second refresh operation for a second adjacent word line group of the target word line after the first refresh operation, in response to a smart refresh command. | 2016-06-09 |
20160163373 | MEMORY DEVICE FOR CONTROLLING REFRESH OPERATION BY USING CELL CHARACTERISTIC FLAGS - A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows. | 2016-06-09 |
20160163374 | MEMORY DEVICE - In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured. | 2016-06-09 |
20160163375 | MEMORY DEVICE - A memory device may include: first to Nth cell blocks; first to (N−1)th bit line sense amplifiers, of which a Kth bit line sense amplifier amplifies a potential difference between a bit line of a Kth cell block and a bit line of a (K+1)th cell block; one or more first outermost bit line sense amplifiers suitable for amplifying a potential difference between a first node and a bit line of the first cell block, wherein drivability for driving the first node is different from drivability for driving the bit line of the first cell block; and one or more second outermost bit line sense amplifiers suitable for amplifying a potential difference between a second node and a bit line of the Nth cell block, wherein drivability for driving the second node is different from drivability for driving the bit line of the Nth cell block. | 2016-06-09 |
20160163376 | APPARATUS, METHOD AND SYSTEM FOR PERFORMING SUCCESSIVE WRITES TO A BANK OF A DYNAMIC RANDOM ACCESS MEMORY - Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data. | 2016-06-09 |
20160163377 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING SAME - A method of operating a semiconductor memory device is provided as follows. The semiconductor memory device receive a bank address for a first bank including a first word line, a second word line and a third word line. The semiconductor memory device receive a first row address to activate the first world line for a read operation or a write operation. The semiconductor memory device generates a second row address to refresh a plurality of memory cells associated with the second word line. | 2016-06-09 |
20160163378 | TIME DIVISION MULTIPLEXED MULTIPORT MEMORY - In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal. | 2016-06-09 |
20160163379 | CIRCUITS AND METHODS FOR PERFORMANCE OPTIMIZATION OF SRAM MEMORY - In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed. | 2016-06-09 |
20160163380 | MEMORY DEVICE - A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data, third bit data, and fourth bit data, in which the first bit data and the fourth bit data are configured to be a high logic state, and the second bit data and the third bit data are configured to be a low logic state. The sensing unit is configured to read bit data stored in one of the memory cells according to the first bit data, the second bit data, the third bit data, and the fourth bit data. | 2016-06-09 |
20160163381 | MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The method includes determining the number of valid pages of a first memory block as a first count value, determining the number of valid pages of a second memory block as a second count value, applying a weight to the first count value and generating a comparison count value which is greater than the first count value, and defining the first and second memory blocks as a victim block by comparing the comparison count value and the second count value with a threshold value. | 2016-06-09 |
20160163382 | Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization - A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements. | 2016-06-09 |
20160163383 | APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE - The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse. | 2016-06-09 |
20160163384 | PAGE PROGRAMMING SEQUENCES AND ASSIGNMENT SCHEMES FOR A MEMORY DEVICE - Embodiments of the invention are directed towards a memory device comprising a plurality of wordlines each coupled to a row of memory cells in a subtile of the memory device, a plurality of level one column select circuits coupled to each cell in a plurality of groups of cells in a subtile, a plurality of level two column select circuits coupled to each of the plurality of groups of cells in the subtile, a common bit line coupled to the plurality of level one column select circuits and the plurality of level two column select circuits, the common bit line also coupled to a sense and program circuit, wherein the sense and program circuit addresses each first cell in each of the groups of cells to form a single page of memory. | 2016-06-09 |
20160163385 | DUO CONTENT ADDRESSABLE MEMORY (CAM) USING A SINGLE CAM - Disclosed is a content addressable memory (CAM). The content addressable memory array includes a memory array and a data match module. The memory array includes multiple memory rows. Each memory row is configured to store a first data word and a second data word. The data match module includes a first match circuitry configured to compare a first match word to the first data word of a memory row, and to generate a first match output based on the comparison between the first match word and the first data word of the memory row. The data match module further includes a second match circuitry configured to compare a second match word to the second data word of the memory row, and to generate a second match output based on the comparison between the second match word and the second data word of the memory row. | 2016-06-09 |
20160163386 | NONVOLATILE MEMORY DEVICE INCLUDING MULTI-PLANE - A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group. | 2016-06-09 |
20160163387 | REUSE OF ELECTRICAL CHARGE AT A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having a plurality of decoders, wherein each decoder is assigned to a select line, wherein no other decoder is assigned to the select line, each decoder has an output configured to charge the select line to when the decoder is activated and to discharge the select line when said decoder is deactivated. Also, each decoder is configured such that, in case that a first decoder gets deactivated after being activated and a second decoder of the decoders gets activated after being deactivated, the output of the first decoder and the output of the second decoder get connected to a common node for a predefined time interval, so that an electrical charge may be transferred from the select line, to the first decoder is assigned to, to the select line, to which the second decoder is assigned to, before the output of the first decoder gets connected to a reference voltage and the output of the second decoder gets connected to a supply voltage. | 2016-06-09 |
20160163388 | APPLYING SUBSTANTIALLY THE SAME VOLTAGE DIFFERENCES ACROSS MEMORY CELLS AT DIFFERENT LOCATIONS ALONG AN ACCESS LINE WHILE PROGRAMMING - An embodiment of a method of programing might include applying a first voltage difference across a first memory cell to be programed, where applying the first voltage difference comprises applying a first channel bias voltage to a channel of the first memory cell, and applying a second voltage difference, substantially equal to the first voltage difference, across a second memory cell to be programed while applying the first voltage difference across the first memory-cell, where applying the second voltage difference comprises applying a second channel bias voltage to a channel of the second memory cell. The first channel bias voltage is different than the second channel bias voltage, and the first memory cell and the second memory cell are commonly coupled to an access line and are at different locations along a length of the access line. | 2016-06-09 |
20160163389 | THREE-DIMENSIONAL MEMORY STRUCTURE HAVING A BACK GATE ELECTRODE - A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell. | 2016-06-09 |
20160163390 | SEMICONDUCTOR DEVICE - A semiconductor device includes a memory array including a plurality of memory blocks. Each memory block includes a pipe transistor, a drain select transistor and a first memory cell connected between the pipe transistor and a bit line, and a source select transistor and a second memory cell connected between the pipe transistor and a common source line. The semiconductor device further includes an operation circuit configured to apply an operating voltage to a memory block selected to perform program and read operations, and a gate control circuit configured to control a gate of the pipe transistor included in an unselected memory block. | 2016-06-09 |
20160163391 | FLASH MEMORY AND PROGRAMMING METHOD THEREOF - A programming method of an NAND flash memory is provided, for narrowing a distribution width of a threshold voltage. The method includes a step of verification reading for verifying a threshold voltage of a selected memory cell after a programming voltage is applied to a selected word line. The verification reading further includes a step of pre-charging a voltage to a bit line, a step of discharging the pre-charged bit line to a source line, and a step of reading the voltage of the bit line after the discharging step. Regarding the discharge period from starting the discharging of the bit line to starting the read out, the discharge period of the verification reading after the initial programming voltage is applied is set longer than the discharge period of the verification reading after the subsequent programming voltage is applied. | 2016-06-09 |
20160163392 | DATA RETENTION FLAGS IN SOLID-STATE DRIVES - Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory. | 2016-06-09 |
20160163393 | PARTIAL BLOCK ERASE FOR DATA REFRESHING AND OPEN-BLOCK PROGRAMMING - Systems and methods for performing partial block erase operations on a subset of word lines within a memory array prior to performing data refreshing or open-block programming are described. In some cases, data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells, performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. The one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line. | 2016-06-09 |
20160163394 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR READING DATA FROM THE SAME - A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state. | 2016-06-09 |
20160163395 | NAND FLASH MEMORY AND READING METHOD THEREOF - The disclosure provides a NAND flash memory and a reading method thereof, which may read a negative threshold value of a memory cell without using a negative-voltage-generating circuit. The disclosed NAND flash memory includes a sense amplifier, a bit line selecting circuit and an array having a plurality of NAND string units. The disclosed NAND flash memory includes a ΔV supplying portion element that applies a positive voltage to a source line, a P well formed with a selected memory cell, and a non-selected bit line which is adjacent to a selected bit line, within a predetermined time period, after the selected bit line is pre-charged and during a reading process. | 2016-06-09 |
20160163396 | PEAK CURRENT CONTRL - A low-dropout regulator includes an error amplifier to provide a control signal, a first transistor, and a second transistor. The first transistor receives the control signal and has a source-drain path electrically coupled between a supply voltage node and a load, the first transistor to power the load in response to a voltage on the supply voltage node rising above an absolute value of a threshold voltage of the first transistor. The second transistor has a source-drain path electrically coupled between the supply voltage node and the load, the second transistor to receive the control signal in response to the voltage on the supply voltage node rising above a particular voltage. | 2016-06-09 |
20160163397 | INTRINSIC MEMORY BLOCK HEALTH MONITORING - A memory system or flash card may monitor the health of memory and the user data stored by detecting and storing a number of bits in error for each block. This detection can be used to determine where user data should be programmed and which blocks should be cycled. The erratic bits are detected after a programming and the listing for each block is updated. When the erratic bits exceed a threshold for a particular block, that block may be cycled or retired. | 2016-06-09 |
20160163398 | METHOD FOR CREATING AN OTPROM ARRAY POSSESSING MULTI-BIT CAPACITY WITH TDDB STRESS RELIABILITY MECHANISM - A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level. | 2016-06-09 |
20160163399 | NON-VOLATILE MEMORY, SEMICONDUCTOR DEVICE AND READING METHOD - There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector. | 2016-06-09 |
20160163400 | LIQUID CRYSTAL DISPLAY AND SHIFT REGISTER THEREOF - The present invention provides a liquid crystal display and a shift register thereof. Each shift register unit of the shift register comprises a storage circuit, receiving and temporarily storing a former stage signal, a voltage level control circuit and an inverter circuit, charging and discharging scan lines of a liquid crystal display panel, and a first node exists between the voltage level control circuit and the inverter circuit, and a second node exists between the storage circuit and the voltage level control circuit, and the storage circuit is employed to selectively invert and output received level signals to the second node under control of a first sequence signal, and the voltage level control circuit is employed to provide a low level signal to the first node, and the inverter circuit is employed to selectively invert and output the low level signal provided by the voltage level control circuit under control of a second sequence signal. With the aforementioned arrangement, the present is beneficial to the narrow frame or non frame design of the liquid crystal display panel and promote the process yield. | 2016-06-09 |
20160163401 | SHIFT REGISTER CIRCUIT, GATE DRIVER AND DISPLAY APPARATUS - Provided is a shift register circuit including a single conductive transistor which performs overlap scanning without increasing the number of clock signals and reduces power consumption by avoiding an ineffective through current, a gate driver, and a display apparatus. The shift register circuit includes: a shift register unit having a first output transistor which connects an output terminal and a first power supply; and a first gate control circuit of which an output terminal is connected to a gate terminal of the first output transistor, wherein the first gate control circuit includes a timing generation unit and a buffer unit, the buffer unit is a bootstrap circuit, and an output of the timing generation unit to which an input signal is inputted is used as an input of the buffer unit and an output of the buffer unit is used as an output of the first gate control circuit. | 2016-06-09 |
20160163402 | NUCLEAR FUEL ASSEMBLY SUPPORT GRID - A nuclear fuel assembly grid having a torpedo-shaped mixing vane assembly supported at each intersection of the grid straps that surrounds a fuel rod support location. The torpedo-shaped stem supports mixing vanes that extend over each of the fuel rod support locations. | 2016-06-09 |
20160163403 | LEAD-FREE POLYMER-BASED COMPOSITE MATERIALS - The present invention relates to a lead-free, non-toxic and arc resistant composite material having a thermosetting polymer, at least one heavy particulate filler, at least one light particulate filler and, optionally, at least one arc resistant filler. The composite material may be utilized in manufacturing articles used in radiation shielding and other applications where arc resistant and dielectric strength are desired. | 2016-06-09 |
20160163404 | METHOD OF STORING HIGH LEVEL RADIOACTIVE WASTE - Method for storing high level radioactive waste. In one embodiment, the invention comprises: (a) providing a body portion comprising a floor, an open top end, an inner shell forming a cavity having, an outer shell surrounding the inner shell so as to form a space therebetween, and at least one opening in the inner shell that forms a passageway from the space into a bottom of the cavity; (b) placing a canister containing high level radioactive waste into the cavity; and (c) positioning a lid having at least one outlet vent atop the inner and outer shells so as to enclose the open top end of the body portion and the at least one outlet vent forming a passageway from a top of the cavity to the ambient atmosphere; and wherein at least one inlet vent forms a passageway from an ambient atmosphere to the space. | 2016-06-09 |
20160163405 | METHOD FOR TREATING AN ABSORBER PIN CONTAINING CONTAMINATED BORON CARBIDE AND SODIUM - Disclosed is a method for treating an absorber pin, wherein the pin comprises a cladding in which a sintered boron carbide-based material having cracks is located, the material having porosity less than 1% of the volume of the material, the cracks containing sodium and at least one radioactive material. The method includes contacting the material with a treatment reaction mixture including carbon dioxide and water, in such a manner that the production of sodium carbonate and the expansion thereof cause the opening of cracks and of the sheath from at least one slit provided in the sheath as well as the propagation of the treatment process within the material. The process overcomes the physical-chemical properties of a sintered boron carbide-based material as much as possible. These properties prevent an easy treatment of the sodium and radioactive material contained in the cracks of the material. | 2016-06-09 |
20160163406 | METHOD FOR LONG-TERM STORAGE OF WASTE NUCLEAR FUEL - The method for the long-term storage of waste nuclear fuel of a nuclear reactor consists in that, first, prior to the waste fuel assembly of the nuclear reactor being disposed in a steel case and the latter being hermetically sealed with a cover, a material which is chemically inert in relation to the material of the casing of the fuel elements of the waste fuel assemblies, to the material of the body of the case, to air and to water, is arranged in the steel case, the steel case is mounted in a heating device, the steel case is heated along with the material arranged in said steel case until said material passes into a liquid state, and then the waste fuel assembly which has been extracted from the nuclear reactor is arranged in the steel case in such a way that the fuel part of the fuel elements of the waste fuel assemblies is lower than the level of the liquid material in the steel case, the waste fuel assembly is fixed in this position, and the case is hermetically sealed by the cover, whereupon the hermetically sealed steel case is extracted from the heating device and mounted in a storage facility which is cooled by atmospheric air. This technical solution makes it possible to ensure long-term safe storage of waste fuel assemblies of a nuclear reactor in storage facilities with cooling using atmospheric air, in particular with natural circulation of atmospheric air, and also to transport the waste fuel assemblies to a factory for processing so as to ensure an increased level of safety. | 2016-06-09 |
20160163407 | ROBUST RAMSEY SEQUENCES WITH RAMAN ADIABATIC RAPID PASSAGE - Methods and apparatus provide for inertial sensing and atomic time-keeping based on atom interferometry. According to one example a method for inertial sensing includes trapping and cooling a cloud of atoms, applying a first beam splitter pulse sequence to the cloud of atoms, applying a mirror sequence to the cloud of atoms subsequent to applying the first beam splitter pulse sequence, applying a second beam splitter pulse sequence to the cloud of atoms subsequent to applying the mirror sequence, modulating at least one of a phase and an intensity of at least one of the first and the second beam splitter pulse sequences, performing at least one measurement subsequent to applying the second beam splitter pulse on the cloud of atoms during an interrogation time, and generating a control signal based on the at least one measurement. | 2016-06-09 |
20160163408 | MICROSTRUCTURE MANUFACTURING METHOD - A microstructure manufacturing method includes forming a first insulating film on an Si substrate, exposing an Si surface by removing a part of the first insulating film, forming a recessed portion by etching the Si substrate from the exposed Si surface, forming a second insulating film on a sidewall and a bottom of the recessed portion, forming an Si exposed surface by removing at least a part of the second insulating film formed on the bottom of the recessed portion, and filling the recessed portion with a metal from the Si exposed surface by electrolytic plating. | 2016-06-09 |
20160163409 | OPTICAL DESIGN METHOD FOR X-RAY FOCUSING SYSTEM USING ROTATING MIRROR, AND X-RAY FOCUSING SYSTEM - An object of the invention is to provide a novel optical design method for an X-ray focusing system capable of collecting all the fluxes, while applying an X-ray of a very small divergence angle to the entire surface of a rotating mirror. The method includes a step of determining the shape of a rotating mirror ( | 2016-06-09 |
20160163410 | ELECTRICALLY CONDUCTIVE THIN FILMS - An electrically conductive thin film including a plurality of nanosheets including a doped titanium oxide represented by Chemical Formula 1 and having a layered crystal structure: | 2016-06-09 |
20160163411 | METHOD FOR MANUFACTURING CARBON CARRIER-METAL NANOPARTICLE COMPOSITE AND CARBON CARRIER-METAL NANOPARTICLE COMPOSITE MANUFACTURED THEREBY - The present application relates to a method for preparing a carbon carrier-metal nanoparticle composite and a carbon carrier-metal nanoparticle composite prepared thereby, and has an advantage in that it is possible to improve dispersibility and supporting ratio of metal nanoparticles with respect to a carbon carrier by efficiently supporting metal nanoparticles having a uniform size of several nanometers on evenly dispersed carbon carriers. | 2016-06-09 |
20160163412 | DIELECTRIC OR HEAT-TRANSFER FLUID COMPOSITIONS AND USES OF SAME - A composition including: (a) from 30 to 70% by weight of a mixture of benzyltoluene and dibenzyltoluene, and (b) from 70 to 30% by weight of at least one compound chosen from the C4-C8 aromatic compounds enclosing two benzene rings condensed or bonded to each other by a bond or by a spacer group other than —CH2-, the oligomers of same and the mixtures of same, excluding phenylxylylethane. Also, the use of this composition, with or without phenylxylylethane, depending on the case, as a dielectric and/or heat-transfer fluid, in particular in use conditions at very low temperatures, such as temperatures lower than −40° C., or indeed lower than −60° C. Also, mixtures of these compositions with mineral oils and/or natural or synthetic esters. Finally, devices, in particular electrical devices, incorporating this composition. | 2016-06-09 |
20160163413 | THERMOPLASTIC RESIN COMPOSITION, AND MOLDED ARTICLE THEREOF - The present invention aims to provide a resin composition which can provide a molded article excellent in insulation and showing a low relative permittivity and which causes no melt fracture even when extrusion-molded at a high shear rate. The resin composition of the present invention includes an aromatic polyether ketone resin (I) and a fluororesin (II). The fluororesin (II) is a copolymer of tetrafluoroethylene and a perfluoro ethylenically unsaturated compound represented by the following formula (1): | 2016-06-09 |
20160163414 | CROSSLINKABLE HALOGEN-FREE RESIN COMPOSITION, CROSS-LINKED INSULATED WIRE AND CABLE - A crosslinkable halogen-free resin composition includes a polymer blend, and a metal hydroxide mixed in an amount of 120 to 200 parts by mass per 100 parts by mass of the polymer blend. The polymer blend includes a maleic anhydride-modified high-density polyethylene, 30 to 50 parts by mass of an ethylene-acrylic ester-maleic anhydride terpolymer, 5 to 20 parts by mass of a maleic anhydride modified ethylene-α-olefin copolymer and 10 to 30 parts by mass of an ethylene-acrylic ester copolymer. | 2016-06-09 |
20160163415 | Conductor Joint and Conductor Joint Component - A conductor joint for joining a copper conductor to a fiber-structured heating element whose dimensions are length (L)>>width (W)>>thickness (T), and which heating element comprises carbon fiber strands, wherein the copper conductor is transversely disposed to the longitudinal direction (L) of the heating element to form a layered structure in the thickness direction (T), on both sides of the heating element, the copper conductor comprising strands separable from each other. The strands of the copper conductor, the number and diameter of which are suitable for transferring a power of more than ten kW, are quantitatively substantially evenly distributed on both sides of the heating element, the strands are disposed in a planar manner in such a way that the strands substantially lie in one plane, adjacent to each other, and the ends of the strands extend, in the width direction (W) of the heating element, beyond the heating element, wherein the portions of the ends of the strands extending beyond the heating element overlap each other, and an electric joint is formed between the lateral faces of these overlapping strands. | 2016-06-09 |
20160163416 | WIRE HARNESS AND WIRE HARNESS MANUFACTURING METHOD - A wire harness having high productivity and a portion of an electrical line group configured to be easily housed in a protector without requiring the task of opening an overlapping portion of the protector, and a method for manufacturing said wire harness are provided. The protector includes a shape-memory panel having a shape-memory polymer sheet and noise suppression metal coating films formed on two surfaces thereof and are electrically conductive with each other. The shape-memory polymer sheet is molded in a shape-memory state for covering a portion of the electrical line group in a scroll-like manner, and then opened into a flat plate shape. The portion of the electrical line group is placed on the flat plate-shaped shape-memory panel, and then heated so that the shape-memory panel returns to the shape-memory state and covers the portion of the electrical line group in a scroll-like manner. | 2016-06-09 |
20160163417 | CROSSLINKABLE HALOGEN-FREE RESIN COMPOSITION, CROSS-LINKED INSULATED WIRE AND CABLE - A crosslinkable halogen-free resin composition includes a polymer blend, and a metal hydroxide mixed in an amount of 120 to 200 parts by mass per 100 parts by mass of the polymer blend. The polymer blend includes a high-density polyethylene, 30 to 50 parts by mass of an ethylene-acrylic ester-maleic anhydride terpolymer, 5 to 20 parts by mass of a maleic anhydride modified ethylene-α-olefin copolymer and 10 to 30 parts by mass of an ethylene-vinyl acetate copolymer. | 2016-06-09 |
20160163418 | SYSTEMS AND METHODS FOR APPLYING METALLIC LAMINATES TO CABLES - A laminated cable includes a metal laminate surrounding a cable core having first and second ends. Solder is applied adjacent the ends of the laminate, and is heated and subsequently cooled to form a metal seal. The solder can be melted in a plastic jacketing extruder as the extruder applies a plastic jacket over the metal laminate. | 2016-06-09 |
20160163419 | CORROSION PROTECTION OF BURIED METALLIC CONDUCTORS - A method for protecting a conductive metal from corrosion, including coating the conductive metal with a water impermeable carbonaceous conductive material to protect the conductive metal from corrosion. | 2016-06-09 |
20160163420 | Insulated Wire and Dynamo-Electric Machine Using the Same - An insulated wire producible at low cost and excellent in heat resistance and voltage resistance and a dynamo-electric machine using the insulated wire are provided. The insulated wire includes a conductor and a resin laminated body covering the conductor and formed by a plurality of resin layers being stacked, wherein the resin layer of an outermost layer in the resin laminated body is formed from a resin having maximum heat resistance among resins forming the plurality of resin layers. | 2016-06-09 |
20160163421 | INSULATING WINDING WIRE HAVING CORONA RESISTANCE - Disclosed is an insulating winding wire having corona resistance, including a conductor and an insulation coating. The insulation coating includes a basal layer applied to cover the conductor and an outer layer applied to cover the basal layer. The basal layer includes at least one resin selected from the group consisting of polyvinylformal resin, polyurethane resin, heat-resistant polyurethane resin, polyester resin, polyester imide resin, polyamide imide resin, polyimide resin and polyamide resin. The basal layer includes 5 to 15 parts by weight of inorganic insulation particles and 1 to 3 parts by weight of an adhesive agent with respect to 100 parts by weight of the resin and the basal layer has a thickness 70 to 80% of the thickness of the insulation coating. | 2016-06-09 |
20160163422 | HARNESS EXTERIOR PROTECTION MEMBER AND WIRE HARNESS USING THE SAME - A harness exterior protection member with an electric wire bundle inserted therein includes a bent portion and a straight portion which are formed in a cylindrical shape in an integrated manner formed of a flame-retardant polyamide resin composition. A thickness of the straight portion is set to be twice to four times of a thickness of the bent portion. A bending radius of the bent portion is 10 mm or larger, and a bending strength of the straight portion is 15 to 25 N. | 2016-06-09 |
20160163423 | SHIELDED WIRE AND WIRE HARNESS - A wire harness includes a surface treated shielded wire and a counterpart connection portion provided at an end of the surface treated shielded wire. The surface treated shielded wire includes a conductor, an insulative coating provided on an outer side of the conductor, an electrically-conductive surface treatment portion applied on a surface of the insulative coating from one end to the other end, in an extending direction of the conductor, of a predetermined range on the insulative coating, and a metal wire having electrical conductivity. | 2016-06-09 |