| 23rd week of 2011 patent applcation highlights part 22 |
| Patent application number | Title | Published |
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| 20110133795 | DIGITAL PHASE-LOCKED LOOP WITH REDUCED LOOP DELAY - There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively. | 2011-06-09 |
| 20110133796 | CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE PROVIDED THEREWITH - It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal. | 2011-06-09 |
| 20110133797 | NOVEL METHOD OF FREQUENCY SYNTHESIS FOR FAST SWITCHING - A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL). | 2011-06-09 |
| 20110133798 | SYNTHESIZER AND RECEPTION DEVICE AND ELECTRONIC DEVICE USING THE SAME - A synthesizer includes: a synthesizer unit that outputs an oscillation signal based on a reference oscillation signal; a temperature detecting unit that detects a temperature; a time variation detecting unit that detects a time variation in frequency of the reference oscillation signal based on a result of temperature detection by the temperature detecting unit; and a control unit that adjusts a frequency of the oscillation signal outputted from the synthesizer unit based on a result of detection by the time variation detecting unit. With such a configuration, frequency compensation control is performed on a transducer having a large temperature coefficient. | 2011-06-09 |
| 20110133799 | CONFIGURABLE DIGITAL-ANALOG PHASE LOCKED LOOP - A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop. | 2011-06-09 |
| 20110133800 | CHARGE PUMPING CIRCUIT AND CLOCK GENERATOR - A charge pumping circuit comprises: a charging pump capacitance; a charging unit; a discharging unit; a detection resistor having one terminal and the other terminal, the one terminal being connected between a first node and a second node in a second mode; a voltage source for supplying a reference voltage to the other terminal of the detection resistor; a correction unit for correcting a charging current output from the charging unit and a discharging current that is to be sunk by the discharging unit to equalize the charging current and the discharging current in the second mode, based on a difference between a voltage of the one terminal of the detection resistor and the reference voltage when the charging unit outputs the charging current to the one terminal of the detection resistor and the discharging unit sinks the discharging current from the one terminal of the detection resistor. | 2011-06-09 |
| 20110133801 | PULSE WIDTH DIGITIZING METHOD AND PULSE WIDTH DIGITIZER USING THEREOF - A pulse width (PW) digitizer comprises a current pump, a capacitor, a quantizer, a feedback controller, and a digital filter. The current pump provides a current signal in response to a PW signal. The capacitor obtains a voltage signal in response to the current signal. The quantizer obtains a digital signal in response to the voltage signal. The feedback controller determines a feedback PW signal in response to the digital signal. The feedback PW signal is fed back to the current pump for controlling the current signal converging to a specific value and controlling the digital signal switching between a first code and a second code. The digital filter counts times that the digital signal indicating the first code/the second code and accordingly obtains the PW of the PW signal. | 2011-06-09 |
| 20110133802 | INTEGRATED CIRCUIT DEVICE, ELECTRONIC EQUIPMENT AND CONTROL METHOD - An integrated circuit device includes a first rectangular wave signal generation section that outputs a first rectangular wave signal when an amplitude of an oscillation signal inputted is greater than a first amplitude, and a second rectangular wave signal generation section that outputs a second rectangular wave signal when the amplitude of the oscillation signal is greater than a second amplitude that is greater than the first amplitude, and that controls the power supply voltage of an oscillation circuit by the first and second rectangular wave signals so as to maintain an appropriate potential difference with respect to a stop voltage against changes in the oscillation stop voltage associated with changes in a temperature condition. | 2011-06-09 |
| 20110133803 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area. | 2011-06-09 |
| 20110133804 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 2011-06-09 |
| 20110133805 | DIFFERENTIAL LATCH, DIFFERENTIAL FLIP-FLOP, LSI, DIFFERENTIAL LATCH CONFIGURATION METHOD, AND DIFFERENTIAL FLIP-FLOP CONFIGURATION METHOD - A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is controlled by a reset signal; and a switching transistor that is connected to the gate electrode of the data holding transistor and is controlled by a switch signal, being an inverted version of the reset signal. | 2011-06-09 |
| 20110133806 | INTEGRATED CLOCK GATING CELL FOR CIRCUITS WITH DOUBLE EDGE TRIGGERED FLIP-FLOPS - A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock gater switches the gated clock signal from the first logic value at a next clock edge when the enable signal is at a second logic state. | 2011-06-09 |
| 20110133807 | DIFFERENTIAL LATCH, DIFFERENTIAL FLIP-FLOP, LSI, DIFFERENTIAL LATCH CONFIGURATION METHOD, AND DIFFERENTIAL FLIP-FLOP CONFIGURATION METHOD - A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is controlled by a reset signal; and a switching transistor that is connected to the gate electrode of the data holding transistor and is controlled by a switch signal, being an inverted version of the reset signal. | 2011-06-09 |
| 20110133808 | APPARATUS - An apparatus has a delay circuit, a delay control circuit which detects the delay time of the delay circuit and generates a delay adjustment signal based upon the detection result, and a delay adjustment circuit operable to adjust delay time of the delay circuit in response to the delay adjustment signal. | 2011-06-09 |
| 20110133809 | Semiconductor device and method for cancelling offset voltage of sense amplifier - A semiconductor device includes first and second signal lines; a sense amplifier amplifying potential difference occurring in the first and second signal lines; a cancel charge generator circuit producing cancel charge that corresponds to offset voltage in the sense amplifier; a cancel charge storage circuit storing the cancel charge; and a cancel charge feed circuit feeding the cancel charge that has been stored in the cancel charge storage circuit to the first and second signal lines to cancel the offset voltage. | 2011-06-09 |
| 20110133810 | System and Method for a Semiconductor Switch - In one embodiment, a semiconductor circuit for coupling a first node to a second node includes a first transistor having a first terminal coupled to the first node, a second terminal coupled to the second node, and a control terminal coupled to a control node. The circuit also includes a level shifting circuit having a series diode for coupling a bulk terminal of the first transistor to the control node, and a supply coupling circuit coupled between a first power supply node and the control node. | 2011-06-09 |
| 20110133811 | CLOCK DISTRIBUTION NETWORK - Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components. | 2011-06-09 |
| 20110133812 | PHYSICAL QUANTITY SENSOR - Provided is a physical quantity sensor capable of improving physical quantity detection precision thereof. The physical quantity sensor includes a bridge resistance type physical quantity detection element for generating a voltage based on a bias current and a physical quantity, a current supply circuit for supplying the bias current to the physical quantity detection element, and a leakage current control circuit for causing leakage currents flowing when switches of the current supply circuit are in an off state to flow into a ground terminal. | 2011-06-09 |
| 20110133813 | ANALOG SWITCH WITH A LOW FLATNESS OPERATING CHARACTERISTIC - An analog switch includes a transistor whose source connected to a signal input and whose drain is connected to a signal output. An output of a gate control circuit is connected to the transistor gate. A first input of the gate control circuit is connected to the source of the transistor. The gate control circuit responds to a logic transition of an enable signal received at a second input by pre-charging a substantially constant gate-to-source voltage across the transistor. This voltage is stored by a gate-to-source connected capacitor. In one steady-state logic condition of the enable signal, the gate control circuit operates to turn off the transistor. In another steady-state logic condition of the enable signal, the gate control circuit permits the signal received at the signal input to drive the gate of the transistor with a voltage offset by the substantially constant gate-to-source voltage stored on the capacitor. | 2011-06-09 |
| 20110133814 | TX OUTPUT COMBINING METHOD BETWEEN DIFFERENT BANDS - An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational voltage is lower than the first operational voltage. The third switch includes a first terminal connected to the bulk of the first output transistor, a control terminal connected to the first switch, and a second terminal connected to the first operational voltage. | 2011-06-09 |
| 20110133815 | TOUCH SWITCHES AND PRACTICAL APPLICATIONS THEREFOR - A touch switch apparatus emulating a mechanical switch includes a field effect sensor and an electric field stimulator mechanically associated with the field effect sensor. A field generation signal applied to the field effect sensor causes an electric field to be generated thereabout. The electric field stimulator can be moved between first and second positions with respect to the field effect sensor. When moved into proximity with the field effect sensor, the electric field stimulator disturbs the electric field. A detection circuit coupled to the field effect sensor detects and responds to the disturbance to the electric field. | 2011-06-09 |
| 20110133816 | SWITCH-BODY PMOS SWITCH WITH SWITCH-BODY DUMMIES - An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. | 2011-06-09 |
| 20110133817 | TAP SWITCH WITH SEMICONDUCTOR SWITCHING ELEMENTS - The invention relates to a tap switch for uninterrupted changeover between two winding taps (tap n, tap n+1) of a tapped transformer, wherein each of the two winding taps is connected to the common outgoing load line via in each case a mechanical switch (Ds) and a series circuit which is arranged in series therewith and which is composed of two oppositely connected IGBTs (Ip, In). According to the invention, each IGBT is bridged by in each case a specially dimensioned varistor (Vp, Vn) connected in parallel therewith. | 2011-06-09 |
| 20110133818 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer. | 2011-06-09 |
| 20110133819 | LOW POWER CHARGE PUMP AND METHOD OF OPERATION - A charge pump and method for starting up a charge pump are provided. The charge pump comprises a plurality of charge pump cells and a start-up control circuit. Each charge pump cell has a clock terminal for receiving a delayed clock signal, an input terminal for receiving an input voltage, and an output terminal for providing a boosted voltage in response to receiving the clock signal and the input voltage. The start-up control circuit is coupled to the clock terminals of each of the plurality of charge pump cells. The start-up control circuit is for delaying the delayed clock signal provided to each charge pump cell of the plurality of charge pump cells. Each of the charge pump cells receives the delayed clock signal having a different predetermined delay so that each of the plurality of charge pump cells are enabled in a predetermined sequence during start-up of the charge pump. | 2011-06-09 |
| 20110133820 | Multi-Stage Charge Pump with Variable Number of Boosting Stages - A charge pump circuit for generating an output voltage is described. The charge pump includes multiple output generation stages connected in series, where the number of stages operating in a boosting mode is variable in order to regulate the pump. The number of stages arranged in series stays the same, but the last one or more of the stages can be operated in a filtering mode, with the number of boosting stages being lower as the regulation level goes lower. This improves the power consumption and reduces noise at lower regulated output levels. | 2011-06-09 |
| 20110133821 | CHARGE PUMP CIRCUIT - A charge pump circuit has: first and second charge pump circuits alternately performing boosting operations; and a control circuit. The first (second) charge pump circuit has: plural stages of first (second) switch transistors connected in series; plural stages of first (second) connection nodes respectively connected to sources of the first (second) switch transistors; and plural stages of first (second) capacitors respectively connected to the first (second) connection nodes. The control circuit has: plural stages of first inverters and plural stages of second inverters. The n-th-stage first (second) inverter is supplied with a positive-side power supply voltage from the (n−1)-th-stage second (first) connection node, is supplied with a negative-side power supply voltage from the n-th-stage first (second) connection node, is supplied with an input voltage from the (n−1)-th-stage first (second) connection node, and outputs an output voltage to a gate of the n-th-stage first (second) switch transistor. | 2011-06-09 |
| 20110133822 | DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER - This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures. | 2011-06-09 |
| 20110133823 | Booster Circuit, Semiconductor Device, and Electronic Apparatus - A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current. The invention provides a booster circuit including a first transistor, a second transistor, a first capacitor element, a second capacitor element, a diode, and an inverter, wherein one electrode of the first transistor is maintained at a predetermined potential, the output of the inverter is connected to the gate electrode of the first transistor and one electrode of the second transistor through the second capacitor element, the input of the inverter is connected to the other electrode of the first transistor through the first capacitor element and connected to the gate electrode of the second transistor, and the diode is connected between the other electrode of the first transistor and the other electrode of the second transistor so as to be forwardly biased. | 2011-06-09 |
| 20110133824 | MICROPROCESSOR DIE WITH INTEGRATED VOLTAGE REGULATION CONTROL CIRCUIT - An integrated circuit die includes a microprocessor and a control circuit to control elements of a voltage regulator to supply power to the microprocessor. | 2011-06-09 |
| 20110133825 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND SAMPLED CONTROL SIGNALS - A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal. | 2011-06-09 |
| 20110133826 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND QUEUE ALLOCATION - A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies. | 2011-06-09 |
| 20110133827 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK | 2011-06-09 |
| 20110133828 | Semiconductor Device - A semiconductor device is provided in which a transistor which supplies a current to a load (an EL pixel and a signal line) can supply an accurate current without being affected by a variation. A voltage of each terminal of a transistor is controlled by using a feedback circuit using an amplifier circuit. A current Idata is inputted from a current source circuit to a transistor and a gate-source voltage (a source potential) required for the transistor to flow the current Idata is set by using the feedback circuit. The feedback circuit is controlled to operate so that a drain potential of the transistor becomes a predetermined potential. Then, a gate voltage required to flow the current Idata is set. By using the set transistor, an accurate current can be supplied to the load (an EL element and a signal line). As a drain potential can be controlled, the kink effect can be reduced. | 2011-06-09 |
| 20110133829 | FEEDBACK CIRCUIT WITH FEEDBACK IMPEDANCE MODULATION FOR IMPROVING POWER SAVING - A feedback circuit with feedback impedance modulation according to the present invention comprises a compare circuit, a counter and a switching resistor circuit. The compare circuit receives a feedback signal of a power converter to compare the feedback signal with a threshold signal for generating a control signal. The feedback signal is correlated to a load condition of the power converter. The counter is coupled to the compare circuit and generates a modulation signal in response to the control signal. The switching resistor circuit is coupled to the counter and a feedback loop of the power converter for modulating a feedback impedance of the power converter in response to the modulation signal. The feedback impedance is directly modulated from a lower resistance to a higher resistance when the load condition is reduced from a half/full-load to a no/light-load. The feedback impedance is gradually modulated from a higher resistance to a lower resistance when the load condition is increased from the no/light-load to the half/full-load. | 2011-06-09 |
| 20110133830 | DEMODULATION CIRCUIT - The circuit ( | 2011-06-09 |
| 20110133831 | Demodulator for Simultaneous Multi-Node Receiving and the Method Thereof - The present invention relates to a demodulator for simultaneous multi-node receiving and a method therof; and, more particularly, a demodulator in a wireless communication system for receiving signals from multi nodes simultaneously and a method thereof. | 2011-06-09 |
| 20110133832 | DIGITAL AMPLIFIER WITH FEEDFORWARD AND FEEDBACK CONTROL - The invention relates to a digital amplifier for providing a desired electrical output power, the amplifier comprising a power source ( | 2011-06-09 |
| 20110133833 | Systems and methods providing multi-path low noise amplifiers with seamless switching - Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable. | 2011-06-09 |
| 20110133834 | POWER AMPLIFIER - There is provided a power amplifier with a variable supply of bias power according to a look-up table having a voltage value determined based on a level of an RF signal being input to the power amplifier to thereby increase power efficiency. A power amplifier according to an aspect of the invention may include an amplification section amplifying an input signal according to a bias voltage being supplied; and a bias supply section comparing a level of the input signal with a look-up table set in advance and supplying a bias voltage to the amplification section according to a result of the comparison. | 2011-06-09 |
| 20110133835 | DOUBLE TRANSFORMER BALUN FOR MAXIMUM POWER AMPLIFIER POWER - Double transformer balun for maximum PA (Power Amplifier) power. A novel approach is presented herein by which conversion from a differential signal to single-ended signal may be achieved using a double transformer balun design. The secondary coils of the double transformer balun also operate as a choke for the PA supply voltage. The secondary coils can operate as an RF (Radio Frequency) trap or choke to keep any AC (Alternating Current) signal components and to pass any DC (Direct Current) components. By using a double transformer balun design, relatively thinner tracks may be employed thereby ensuring a high degree of electromagnetic coupling efficiency and high performance. Also, these relatively thinner tracks consume a relatively small amount of space on the die. The double transformer balun design also includes a matching Z (impedance) block that is operable to match the Z of an antenna or line that the PA is driving. | 2011-06-09 |
| 20110133836 | CLASS-D AMPLIFIER - Class D amplifier is provided. The class D amplifier includes at least a block; each block includes an input circuit, an integrator, a comparator, a driving circuit and two feedback circuits. The input circuit receives a digital input to provide a differential pair of a positive and a negative input signals. The integrator receives the positive and negative input signals and a pair of positive and negative feedback signals for providing a positive error signal according to the positive input signal and the negative feedback signal, and providing a negative error signal according to the negative input signal and the positive feedback signal. The comparator compares between the positive and the negative error signals such that the driving circuit generates a driving output signal according to comparison result. The two feedback circuits respectively providing said positive and negative feedback signals according to the driving output signal. | 2011-06-09 |
| 20110133837 | VARIABLE GAIN AMPLIFIER - A gain variable range of a variable gain amplifier is increase and a non-linear distortion is reduced at the same time. The variable gain amplifier includes an operational amplifier, a variable resistive circuit which includes a plurality of variable resistive elements connected together in series, each having a resistance value corresponding to a given control voltage, and is connected between an input terminal and an output terminal of the operational amplifier, and a control circuit configured to generate a plurality of control voltages each corresponding to a gain control signal, having an offset corresponding to a DC voltage difference between input and output of the operational amplifier, and apply the plurality of control voltages to the plurality of the variable resistive elements, respectively. | 2011-06-09 |
| 20110133838 | LOW OUTPUT IMPEDANCE RF AMPLIFIER - A radio frequency (RF) power amplifier includes a low impedance pre-driver driving the input of a common-source output amplifier stage. The preamplifier includes a first transistor that has a first terminal coupled to a preamplifier RF input node, a second terminal coupled to a preamplifier RF output node, and a third terminal coupled to a supply voltage node. A first inductor is coupled between the RF output node and a bias voltage node. A voltage difference between respective first and second voltages on the RF input node and the RF output node that are substantially in phase, determines current through the first transistor. | 2011-06-09 |
| 20110133839 | ARRANGEMENT FOR CALIBRATING THE QUIESCENT OPERATING POINT OF A PUSH-PULL AMPLIFIER - A signal processing arrangement comprises an amplifier (AMP V | 2011-06-09 |
| 20110133840 | PRE AND POST FILTER AUTOMATIC GAIN CONTROL WITH BOUNDED PRE-FILTER GAIN CONTROL - An electronic circuit includes a first variable gain amplifier for amplifying a signal at an input to provide a first amplified signal; a filter receiving the first amplified signal to provide a filtered signal; a second variable gain amplifier for receiving and amplifying the filtered signal; a second gain control bock, to provide at least one gain control signal derived from the filtered signal, one of the at least one gain control signal to control the gain of the second variable gain amplifier; and a bounding block for receiving one of the at least one gain control signal from the second gain control block, and for generating therefrom a bounded gain control signal to control gain of the first variable gain amplifier. | 2011-06-09 |
| 20110133841 | Low Noise Binary-Coded Gain Amplifier And Method For Time-Gain Compensation In Medical Ultrasound Imaging - A low noise variable gain amplifier and method for processing received signals in an ultrasound medical imaging system is disclosed. Unlike solutions known from the prior art, the signals are amplified by a binary-coded gain amplifier having its amplification factor progressively increased during the penetration of the transmitted pulse into a patient's body. This allows enhancing both the system dynamic range and Signal to Noise Ratio. | 2011-06-09 |
| 20110133842 | RADIO-FREQUENCY AMPLIFIER - A radio-frequency amplifier includes a common gate amplification stage configured to be biased in a saturation condition with a first current and configured to receive an input signal as a gate-source voltage and to generate an output voltage as an amplified replica of the input signal. A feedback transistor is configured to be biased in a saturation condition with a second current and coupled to the common gate amplification stage so as to have a gate-drain voltage corresponding to a difference between the output voltage and the input signal. | 2011-06-09 |
| 20110133843 | POWER AMPLIFIER DEVICE - Provided is a power amplifier device. The power amplifier device includes: a cutoff unit cutting off a direct current (DC) component of a signal delivered from a signal input terminal; a circuit protecting unit connected to the cutoff unit and stabilizing a signal delivered from the cutoff unit; and an amplification unit connected to the circuit protecting unit and amplifying a signal delivered from the circuit protecting unit, wherein the amplification unit comprises a plurality of transistors connected in parallel to the circuit protecting unit and the circuit protecting unit comprises resistors connected to between bases of the plurality of transistors. | 2011-06-09 |
| 20110133844 | Surface mount crystal oscillator and manufacturing method of the same - There are disclosed a surface mount crystal oscillator which can enhance a product quality and improve productivity while realizing miniaturization and a manufacturing method of the crystal oscillator. On wall faces of through holes formed in corner portions of a rectangular ceramic base, through terminals are formed; on the front surface of the ceramic base, leading terminals of crystal holding terminals which hold a crystal piece are connected to the diagonal through terminals; on the back surface of the ceramic base, mount terminals connected to the through terminals are formed; and the opening end face of a metal cover joined onto the ceramic base via the molten resin comprises a flange having an inclined face in the surface mount crystal oscillator. | 2011-06-09 |
| 20110133845 | OSCILLATOR CIRCUIT - The present invention provides an oscillator circuit that can decrease consumed current. Namely, a second PMOS transistor is provided between a first PMOS transistor in which a constant current flows and an NMOS transistor for amplifying an oscillating signal, in order to interrupt the constant current flowing in the first PMOS transistor MP | 2011-06-09 |
| 20110133846 | Temperature Invariant Circuit and Method Thereof - A temperature invariant digitally controlled oscillator is disclosed. The digitally controlled oscillator is configured to generate an output clock with stable frequency. The temperature invariant digitally controlled oscillator comprises a digitally controlled oscillator, a temperature sensor, a temperature decision logic circuit, and a temperature conditioner. The digitally controlled signal is provided to adjust the oscillation frequency of the digitally controlled oscillator by changing its capacitances. The stabilization of the silicon temperature is achieved with the temperature sensor, the temperature decision logic circuit, and the temperature conditioner. | 2011-06-09 |
| 20110133847 | PACKAGE AND VIBRATING DEVICE USING THE SAME - A vibrating device includes: a package having an internal space; and a vibrating reed housed in the internal space of the package, wherein the package has a porous portion formed of a communication hole communicating between the internal space and the outside and a porous body buried in the communication hole, and a metal film closing the internal space is arranged on the outside side of the porous portion. | 2011-06-09 |
| 20110133848 | Thin-Film Piezoelectric-on-Insulator Resonators Having Perforated Resonator Bodies Therein - A micro-electromechanical resonator self-compensates for process-induced dimensional variations by using a resonator body having a plurality of perforations therein. These perforations may be spaced along a longitudinal axis of the resonator body, which extends orthogonal to a nodal line of the resonator body. These perforations, which may be square or similarly-shaped polygonal slots, may extend partially or entirely though the resonator body and may be defined by the same processes that are used to define the outer dimensions (e.g., length, width) of the resonator body. | 2011-06-09 |
| 20110133849 | LOW PHASE NOISE VOLTAGE-CONTROLLED OSCILLATOR (VCO) USING HIGH QUALITY FACTOR METAMATERIAL TRANSMISSION LINES - A voltage-controlled oscillator (VCO), specifically, a low phase noise VCO using metamaterial transmission lines including a signal plane on which transmission lines are etched in an interdigital fashion is provided. Though high quality resonators based on a metamaterial structure, improvement of the phase noise of the VCO and circuit miniaturization are achieved. | 2011-06-09 |
| 20110133850 | HIGH-FREQUENCY MODULE - A high frequency module includes RF terminal lands at a first layer that is a surface layer of a multilayer substrate on which RF terminal electrodes of a switch IC are mounted that are arranged in a line. Each of the RF terminal lands is electrically connected to one end of a lead electrode at a second layer via a via hole. Some of the lead electrodes extend from corresponding ones of the RF terminal lands in an outward direction away from a side of the switch IC. The remaining ones of the lead electrodes extend from corresponding ones of the RF terminal lands in an inward direction that is opposite to the outward direction. | 2011-06-09 |
| 20110133851 | ELECTROSTATIC SWITCH FOR HIGH FREQUENCY AND METHOD FOR MANUFACTURING THE SAME - An electrostatic switch for high frequency and a method for manufacturing the same are disclosed. The electrostatic switch for high frequency in accordance with an embodiment includes: a first substrate module including a first substrate, an electrode part and a pair of CoPlanar Waveguides (CPWs), the electrode part being installed on the first substrate, the pair of CPWs being formed on either side of the electrode part and guiding an RF signal to travel; and a second substrate module being joined to the first substrate module, the second substrate module including a membrane and a bias line, the membrane being installed on a second substrate and bent by bias voltage supplied to the electrode part and being coupled to the pair of CPWs across an upper area of the electrode part in order to be short-circuited to the electrode part, the bias line being connected to the electrode part. | 2011-06-09 |
| 20110133852 | MULTIPLEXED SERIAL CONTROL BUS - A signal line sharing protocol and hardware permit control of a remotely located active device configured to provide different load configurations to an antenna. As an example, the communication system may include a master device. The master device may include a general purpose output and a radio frequency port. The communication system may further include a first duplexer and a second duplexer. The first duplexer may include a first port, a second port, and a third port, where the second port is coupled to the radio frequency port and the third port is coupled to the general purpose output of the master device. The second duplexer may include a first port, a second port, and a third port, where the first port of the second duplexer is in communication with the first port of the first duplexer, wherein the second port is coupled to an antenna, and where the third port is in communication with a slave device. The slave device may be coupled to the antenna. In response to commencement of a command from the master device, the slave device may clamp the antenna to ground. | 2011-06-09 |
| 20110133853 | SEMICONDUCTOR DEVICE WITH FILTER CIRCUIT - A filter circuit formed on a semiconductor chip, includes an input node provided to input an input signal; an output bonding pad provided to output an output signal; a ground bonding pad provided to be connected a ground through a bonding wire; a parallel resonant circuit provided between the input node and the output bonding pad and having one end connected to the output bonding pad; and a serial resonant circuit having one end which is provided between the input node and the other end of the parallel resonant circuit and the other end connected with the ground bonding pad. The serial resonant circuit includes a capacitor and an inductor which are connected in serial, and the parallel resonant circuit includes a capacitor and an inductor which are connected in parallel. | 2011-06-09 |
| 20110133854 | METHOD OF MANUFACTURING AN INSTANT PULSE FILTER USING ANODIC OXIDATION AND INSTANT PULSE FILTER MANUFACTURED BY SAID METHOD - The instant pulse filter according to the present invention, which may cause a malfunction or a short life span of a semiconductor device, is made using an aluminum anodic oxidation, comprising—a first step for forming an aluminum thin film layer on an upper side of an insulator substrate; a second step for forming an aluminum oxide thin film layer having a pore by oxidizing the aluminum thin film layer by means of an anodic oxidation; a third step for depositing a metallic material on an upper side of the aluminum thin film layer for filling the pore; a fourth step for forming a nano rod in the interior of the aluminum oxide thin film layer by eliminating the metallic material deposited except in the pore; a fifth step for forming an internal electrode on an upper side of the aluminum oxide thin film layer having the nano rod; a sixth step for forming a protective film layer on an upper side of the same in order to protect the aluminum oxide thin film layer and the internal electrode from the external environment; and a seventh step for forming an external electrode on both sides of the substrate in which the protective film layer is formed. | 2011-06-09 |
| 20110133855 | RESONATOR, ELASTIC WAVE TRANSMISSION ELEMENT AND FABRICATION METHOD THEREOF - A resonator, an elastic wave transmission element and a method for fabricating the transmission element are provided. The elastic wave transmission element has a first side and a second side. The elastic wave transmission element includes a plurality of structures sequentially arranged along a direction from the first side toward the second side. Each of the structures has a different defect which is different to each other. The impedance of the structures decreases gradually along the direction. As such, the elastic wave transmission element has an impedance match function. | 2011-06-09 |
| 20110133856 | Contour-Mode Piezoelectric Micromechanical Resonators - A contour mode micromechanical piezoelectric resonator. The resonator has a bottom electrode; a top electrode; and a piezoelectric layer disposed between the bottom electrode and the top electrode. The piezoelectric resonator has a planar surface with a cantilevered periphery, dimensioned to undergo in-plane lateral displacement at the periphery. The resonator also includes means for applying an alternating electric field across the thickness of the piezoelectric resonator. The electric field is configured to cause the resonator to have a contour mode in-plane lateral displacement that is substantially in the plane of the planar surface of the resonator, wherein the fundamental frequency for the displacement of the piezoelectric resonator is set in part lithographically by the planar dimension of the bottom electrode, the top electrode or the piezoelectric layer. | 2011-06-09 |
| 20110133857 | INTERFACE ACOUSTIC WAVE DEVICE - The present invention relates to the field of acoustic wave devices, and particularly to that of transducers capable of operating at very high frequencies, from a few hundred MHz to several gigahertz, and its subject is more particularly an interface acoustic wave device including at least two substrates and a layer of ferroelectric material, the latter being contained between a first electrode and a second electrode and having first positive-polarization domains and second negative-polarization domains, the first and second domains being alternated, wherein the assembly constituted by the first electrode, the layer of ferroelectric material, and the second electrode is contained between a first substrate and a second substrate. | 2011-06-09 |
| 20110133858 | ELASTIC WAVE ELEMENT AND ELECTRONIC DEVICE USING THE SAME - An elastic wave device includes a piezoelectric substrate, an IDT electrode disposed on a piezoelectric device, a first dielectric layer disposed on the piezoelectric substrate such that it covers the IDT electrode, and a second dielectric layer disposed over the first dielectric layer. The second dielectric layer propagates transverse waves faster than that on the first dielectric layer. When a film thickness of the second dielectric layer is greater than a wave length of a major wave excited by the IDT electrode, a cut angle of the piezoelectric substrate in indication of Euler angles (φ, θ, Φ) is set to φ≠0°, θ≠0°, and Φ≠0°. This suppresses deterioration of device characteristics. | 2011-06-09 |
| 20110133859 | HIGH-FREQUENCY ACOUSTIC WAVE DEVICE - An acoustic wave device comprising a piezoelectric layer on an omnidirectional acoustic mirror and excitation and/or reception means on a surface of said piezoelectric layer, capable of exciting waves in a band gap of the acoustic mirror. | 2011-06-09 |
| 20110133860 | BANDPASS FILTER, HIGH-FREQUENCY DEVICE AND COMMUNICATIONS APPARATUS - A bandpass filter comprising two or more resonators arranged between two input/output terminals in a laminate substrate comprising pluralities of dielectric layers; each resonator being constituted by a resonance line and a resonance capacitance connected to one end of the resonance line; capacitance electrodes forming said resonance capacitances and said resonance lines being arranged on different dielectric layers, via a planar ground electrode covering the entire structural portion of the bandpass filter when viewed in a lamination direction; and in each of the resonators connected to said two input/output terminals, the junctions of said input/output terminals to said paths between said resonance lines and said resonance capacitances being closer to said resonance capacitances than said resonance lines in a lamination direction. | 2011-06-09 |
| 20110133861 | TUNABLE FILTER FOR EXPANDING THE TUNING RANGE - A tunable filter for expanding tuning range includes: a housing, which has multiple cavities defined by partitions; a resonator contained in the cavity; at least one sliding member installed over the resonator; a main cover coupled to an upper portion of the housing; and at least one tuning element coupled to a lower portion of the sliding member and made of a metallic material. Tuning is accomplished by a sliding motion of the sliding member, and the resonator includes a cylindrical first conductor and a second conductor coupled to an upper portion of the cylindrical conductor, where a cross section of the second conductor is shaped as a circle with a portion removed such that an area of overlap between the tuning element and the second conductor is varied according to a sliding of the tuning element. | 2011-06-09 |
| 20110133862 | TUNABLE FILTER CAPABLE OF CONTROLLING TUNING CHARACTERISTICS - A tunable filter for enabling the adjustment of tuning characteristics includes: a housing, in which multiple cavities are defined by partitions; a resonator contained in the cavity; at least one sliding member installed over the resonator; a main cover coupled to an upper portion of the housing; and at least one tuning element coupled to a lower portion of the sliding member and made of a metallic material. The tuning element is coupled to the sliding member by a rotatable bolt, and the bolt is coupled to the tuning element at a point that is a particular distance away from a center of the tuning element. The tunable filter using a sliding system according to certain embodiments of the present invention has the advantage of enabling adjustment of tuning characteristics by way of the rotation of the tuning element, and accordingly, can be used adaptively in various environments. | 2011-06-09 |
| 20110133863 | High Power Waveguide Polarizer With Broad Bandwidth and Low Loss, and Methods of Making and Using Same - Embodiments of the invention provide high power waveguide polarizers with broad bandwidth and low loss, and methods of making and using the same. Under one aspect of the present invention, a waveguide polarizer includes a hollow waveguide body having an interior surface; a first ridge disposed on the interior surface of the hollow waveguide body and having an inward-facing surface; and a first plurality of projections disposed on the inward-facing surface of the first ridge. The projections may have a width that is narrower than that of the ridge, and a length that is tunable. The length of the projections may be selected to induce about a 90-degree phase delay in a first mode propagating in a plane parallel to the first ridge relative to a second mode propagating in a plane perpendicular to the first ridge. | 2011-06-09 |
| 20110133864 | MODE SUPPRESSION RESONATOR - The present disclosed technique pertains to high Q mode resonators, and, more particularly, to a technique for separating a high Q mode from masking low Q modes. In a first aspect, it includes a high Q mode resonator, comprising: a housing defining a clover-shaped resonating cavity; a dielectric material filling the cavity; an input to the cavity; and an output from the cavity. In a second aspect, it includes a high Q mode resonator, comprising: a housing defining a clover-shaped resonating cavity, the cavity comprising four intersecting right angle, cylindrical chambers; a fluid dielectric material filling the cavity; an input to the cavity; and an output from the cavity. In a third aspect, it includes a method, comprising: introducing a signal to a resonating cavity; resonating the signal within a chamber, the resonating cavity shifting the resonance of the low Q mode higher in frequency than it shifts the high Q mode; and permitting egress of the signal from the resonating cavity. In a fourth aspect, it includes a method for use in designing a high Q mode resonator, comprising: calculating the dimensions of the simple cylindrical cavity for the frequency desired for the high Q mode; and decreasing the outer radius of the simple cylindrical cavity while holding the sum of the inner and outer radius equal to the initial simple cylindrical radius. | 2011-06-09 |
| 20110133865 | Technique for conveying a wireless-standard signal through a barrier - The RF signal generated by a ZigBee radio on the outside of a building structure is conveyed to the interior of the building by guiding it along an electric cable bundle that passes through the building's wall to supply domestic electric power to the interior of the structure. The RF signal is launched by a unique coupler comprising a pair of insulated foil conductors. | 2011-06-09 |
| 20110133866 | COUPLER AND WIRELESS COMMUNICATION DEVICE USING COUPLER - A coupler is provided on a printed board including a feeder circuit and a grounded circuit. The coupler includes a first line, a short-circuited line and an open-ended line. The first line has two ends. One of the ends is a feed point of the coupler connected to the feeder circuit, and another one of the ends is a node of the coupler. The short-circuited line is extended from the node to an end short-circuited to the grounded circuit. The open-ended line is extended from the node. | 2011-06-09 |
| 20110133867 | Surface wave coupler - The RF signal generated by a ZigBee radio on the outside of a building structure is conveyed to the interior of the building by guiding it along an electric cable bundle that passes through the building's wall to supply domestic electric power to the interior of the structure. The RF signal is launched by a unique coupler comprising a pair of insulated foil conductors. | 2011-06-09 |
| 20110133868 | Thermometer Coded Attenuator - Techniques are disclosed that allow for programmable attenuation using thermometer code steps. By thermometer coding the attenuator structure, monotonicity is guaranteed or otherwise greatly improved, which eliminates instability problems with automatic gain control loops and without the need for compensation or trimming. In addition, the thermometer coding technique also greatly reduces phase discontinuity between adjacent gain states. | 2011-06-09 |
| 20110133869 | DYNAMIC SEALING DEVICE FOR MIDDLE- OR HIGH-VOLTAGE POWER SWITCH EQUIPMENT - Disclosed is a dynamic sealing device for a middle- or high-voltage power switch equipment, comprising: a housing ( | 2011-06-09 |
| 20110133870 | Contactor Assembly With Arc Steering System - A contactor assembly includes a stationary contact, an arc contact, an arc arrestor, and a magnetic intensifier. The magnetic intensifier is constructed to be secured in generally close proximity to the stationary contact. During communication of power through the contactor assembly, the magnetic intensifier accentuates a magnetic field associated with the stationary contact and increases the magnitude of a magnetic force directed to the arc arrestor. A pair of arc guides extend along the magnetic intensifier and, cooperatively with the magnetic force, ensure efficient, repeatable, and expedient transfer of a circuit termination arc to the arc arrestor. Such a construction increases the operable range and lifecycle of the contactor by reducing the damage associated with propagation of the circuit termination arc. | 2011-06-09 |
| 20110133871 | SUPERCONDUCTING MAGNETIZER - A superconducting magnetizer includes a thermal shield disposed within a vacuum chamber. A superconducting magnet is disposed within the thermal shield and configured to generate a magnetic field in response to an electric current supplied to the superconducting magnet. A heat transfer device comprising at least one of a thermal conduction device, and a heat pipe is disposed contacting the superconducting magnet. A cryocooler is coupled to the heat transfer device and configured to cool the superconducting magnet via the heat transfer device. | 2011-06-09 |
| 20110133872 | THERAPEUTIC MAGNET APPARATUS - A reconfigurable magnetic therapy apparatus is formed by multiple magnetic magnetic components which are maintained in a stable planar array by either mutual magnetic attraction or mechanical fixtures which may include a ferromagnetic backing plate to which the elements are magnetically attached. The array can be separated and reconfigured by the user to provide different magnetic patterns that favor either high surface strength, or deep penetration, or multiple smaller sub arrays to treat multiple sites. | 2011-06-09 |
| 20110133873 | Chip Type Wire Wound Choke Coil - A chip type wire wound choke coil with a fixed shape and size provides different electrical characteristics by, with various standardized chip sizes, changing a diameter or a thickness of an insulation film of an insulated conductor of the choke coil, or changing a cross sectional shape of the insulated conductor of the choke coil, or changing a turn number of the choke coil with respect to turn numbers of both terminals, or changing the core material of the choke coil, or changing a height of the choke coil. | 2011-06-09 |
| 20110133874 | MAGNETIC COMPONENTS AND METHODS FOR MAKING THE SAME - A method for making a magnetic component is provided. The method comprises providing a core with one or more ridges protruding from one or more surfaces of the core, depositing one or more electrically conductive materials on the core, and removing at least a portion of the one or more ridges to form one or more continuous conductors wound around the core. Each of the one or more continuous conductors defines at least one insulating gap. Further, a magnetic component and methods for making the magnetic component are also presented. | 2011-06-09 |
| 20110133875 | Stack inductor with different metal thickness and metal width - A stacked inductor with different metal thickness and metal width is represented in this invention, this structure comprise: top and bottom metal trace, which is aligned with each other. The thickness and width of top and bottom metal trace are different. The top and bottom metal trace are connected at the end of metal trace with via holes. The inductance is increased with the use of the mutual inductance between top and bottom metal layers, and the parasitic resistor is reduced by means of different top and bottom metal width. This stacked inductor possesses larger inductance than single layer spiral inductor with relatively higher Q factor. | 2011-06-09 |
| 20110133876 | Manufacture method for IC process with TOP and TOP-1 metal layers thickened and stacked inductor manufactured by this method - A manufacture method for IC process with top and top-1 metal layers thickened and stacked inductor manufactured by this method is represented in this invention. This method includes: with multi metal layers, and the thickness of top and top-1 metal layers are more than 2.8 um. Thickened top and top-1 metal layers can reduce the resistance of top and top-1 metal layers, so can increase the Q factor of inductor. | 2011-06-09 |
| 20110133877 | Stacked inductor with multi paths for current compensation - A multi-path stacked inductor for current compensation is represented in this invention. This structure includes top and bottom metal trace, which are aligned with each other. Each metal trace consists of multi paths. The inner path in top metal flips over to the outer path in the bottom metal, while the outer path in top metal flips over to the inner path in the bottom metal. These paths join together at the end of the metal trace with via holes. Skin effect and current crowding effect are reduced by means of this method. This stacked inductor possesses larger inductance than single layer spiral inductor, with relatively higher Q factor. | 2011-06-09 |
| 20110133878 | Stacked differential inductor - A structure of stack differential inductor is represented in this invention; this structure includes top and bottom metal traces, which are aligned with each other and symmetric. Starting from one port and after half turn, the top metal trace is connected to bottom metal trace through via holes. Meanwhile, after another half turn, the bottom trace is connected to top trace through via holes. The inductance is increased by means of this method. With the same chip area, this stack differential inductor possesses larger inductance and higher Q factor because of the larger mutual inductance between top and bottom metal than conventional differential inductor. | 2011-06-09 |
| 20110133879 | STACKED INDUCTOR - A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance. | 2011-06-09 |
| 20110133880 | INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS - Integrated circuit inductors ( | 2011-06-09 |
| 20110133881 | LAMINATED INDUCTOR, METHOD FOR MANUFACTURING THE LAMINATED INDUCTOR, AND LAMINATED CHOKE COIL - Disclosed is a laminated inductor that has good direct current superimposition characteristics, does not cause a variation in temperature characteristics, suppresses the occurrence of delamination, and can be stably manufactured. Also disclosed are a method for manufacturing the laminated inductor and a laminated choke coil. A laminated inductor ( | 2011-06-09 |
| 20110133882 | Apparatus for detecting coordinates of an event within interest region, display device, security device and electronic blackboard including the same - There is provided an apparatus for detecting the coordinates of an event within an interest region including: a light source limiting an interest region; at least two light receiving units receiving reflected light of an event within the interest region; a reflector refracting the reflected light received in the light receiving units; and one image sensor on which the reflected light refracted on the reflector is image-formed, wherein the apparatus for detecting coordinates is configured of one module. | 2011-06-09 |
| 20110133883 | ANONYMOUS AUTHENTICATION METHOD BASED ON PRE-SHARED CIPHER KEY, READER-WRITER, ELECTRONIC TAG AND SYSTEM THEREOF - An anonymous authentication method based on a pre-shared key, a reader-writer, an electronic tag and an anonymous bidirectional authentication system are disclosed. The method comprises the following steps: 1) a reader-writer sends an accessing authentication requirement group to the electronic tag; 2) after the electronic tag receives the accessing authentication requirement group, an accessing authentication response group is constructed and sent to the reader-writer; 3) after the reader-writer receives the accessing authentication response group, an accessing authentication confirmation group is constructed and sent to the electronic tag; 4) the electronic tag carries out confirmation according to the accessing authentication confirmation group. | 2011-06-09 |
| 20110133884 | METHOD AND APPARATUS FOR CONFIGURING AN ACCESS CONTROL SYSTEM - A method and apparatus is provided for configuring a security system. The method includes the steps of providing a plurality of configuration files on a computer readable medium where each configuration file defines an access control system or integrated security system and each configuration file is different than any other configuration file of the plurality of configuration files, presenting the plurality of configuration files to a person on a display, a configuration processor receiving a selection of a configuration file of the plurality of configuration files from the person and the processor automatically configuring an access control system or integrated security system in accordance with the selected configuration file. | 2011-06-09 |
| 20110133885 | REMOTE CONTROL DEVICES AND METHOD FOR PREVENTING ACCIDENTAL OPERATION THEREOF - A remote control device and method, the remote control being changeable between an unlocked state and a locked state includes a communicating unit for allowing the remote control device to communicate with and remotely control a controlled apparatus and a processor electronically connected with the communicating unit. The processor is configured for unlocking the remote control device from the locked state, such that the remote control device communicates with and remotely control the controlled apparatus, and is configured for locking the remote control device into the locked state, such that communication between the remote control device and the controlled apparatus is disabled the remote control device cannot remotely control the controller apparatus. A method for preventing accidental operations of the remote control device is also disclosed. | 2011-06-09 |
| 20110133886 | MOBILE IDENTIFICATION TRANSMITTER IN A SAFETY SYSTEM - The invention relates to a mobile identification transmitter ( | 2011-06-09 |
| 20110133887 | IMAGE REGISTRATION METHOD FOR IMAGE COMPARISON AND DOCUMENT AUTHENTICATION - A method for authenticating a printed document is disclosed. Barcode stamps are added to an original document image near the corners of the page to act as registration markers. The original document image bearing the barcode stamps is printed and circulated, while the original document image is stored in a database. To authenticate a printed document, the printed document is scanned into a target document image, which is compared to the stored original document image. The barcode stamps are used as registration markers to perform a global image registration. Then, the target image and the original image are divided into multiple sub-images, and local image registration is performed on the sub-images before performing an image comparison. Difference sub-images are generated from the pairs of sub-images, and merged into a global difference image for the purpose of detecting any alterations in the printed document. | 2011-06-09 |
| 20110133888 | CONTEXTUALLY AWARE MONITORING OF ASSETS - An apparatus, method and system for contextually aware monitoring of a supply chain are disclosed. In some implementations, contextually aware monitoring can include monitoring of the supply chain tradelane with tracking devices including sensors for determining location, velocity, heading, vibration, acceleration (e.g., 3D acceleration), or any other sensor that can monitor the environment of the shipping container to provide contextual awareness. The contextual awareness can be enabled by geofencing and recursive algorithms, which allow dynamic modification of the tracking device behavior. Dynamic modification can reduce performance to save power (e.g., save battery usage) and lower costs. Dynamic modification can increase performance where it matters in the supply chain for improved reporting accuracy or frequency or recognition of supply chain events. Dynamic modification can adapt performance such as wireless communications to the region or location of the tracking device. | 2011-06-09 |
| 20110133889 | DEVICE FOR LOCATING OBJECTS BY RFID COMMUNICATION - The invention relates to the locating and identifying of objects with radiofrequency communication by inductive coupling, without electrical contact, between a reader and a tag. The device includes an array of N fixed RFID markers of RFID tag type, with inductive antennas placed at known positions, N being an integer greater than 1 and an RFID tag reader provided with a fixed reading inductive antenna passing in proximity to the N markers. The position of the N markers with respect to the inductive reading antenna is such that the mutual inductance between the inductive antenna of any marker and the inductive reading antenna is zero when no object to be located is present in the vicinity of the array of markers, and nonzero when an RFID tag is present in the vicinity of the marker considered. A coupling is established in the presence of a mobile tag in proximity to a marker. | 2011-06-09 |
| 20110133890 | METHOD AND DEVICE FOR IMPROVING THE SIGNAL TO NOISE RATIO (SNR) OF A BACKSCATTER SIGNAL RECEIVED FROM A RADIO FREQUENCY IDENTIFICATION (RFID) TAG - A method and device enables improving a signal to noise ratio (SNR) of a backscatter signal received from a radio frequency identification (RFID) tag. The method includes generating a continuous wave (CW) carrier signal at the reader device (step | 2011-06-09 |
| 20110133891 | METHODS AND SYSTEMS FOR REAL TIME RFID LOCATING ONBOARD AN AIRCRAFT - An aircraft communications and item tracking system is described. The system includes an RFID reader and a communications device located at fixed locations within the aircraft, a plurality of passive RFID tags operable for association with items within the aircraft, and a distributed antenna system comprising a plurality of antenna units and a wireless distribution system. The wireless distribution system is communicatively coupled to an aircraft communications network. The antenna units are communicatively coupled to the wireless distribution system and disbursed about the aircraft such that the RFID tags within the aircraft may be activated by signals output by at least one of the antenna units. The RFID reader and communications device are communicatively coupled to the wireless distribution system. The distributed antenna system is operable for transmission and reception of signals associated with the RFID reader and RFID tags. The distributed antenna system is further operable for transmission and reception of signals associated with the communications device. | 2011-06-09 |
| 20110133892 | IDENTIFICATIONS AND COMMUNICATIONS METHODS - The invention relates to improved methods and forms for automatically and non-unobtrusively to detect, without human interpretation, the identification of people(s), object(s), and other, with various methods utilized in connection to creating, storing, adding, connecting, modifying, sharing, inputting, recalling, authorizing, approving, tracking, generating, formatting, monitoring, accessing, locating, deleting, controlling, linking, collecting all types of data and information, and generating at least one type of identifiable communications information related to anyone or anything, and in and/or around any type of environment, such as an airport(s), airline(s), and/or other aviation location(s), theme park, amusement park, aquarium, cruise ships, tourist location, hospitals, buildings, government complex, malls, customs boards, sports events, parking, manufacturing, hotels, resorts, clubs, retail, elevators, utilities, museums, libraries, as well as other types of location(s), among other environments. | 2011-06-09 |
| 20110133893 | Recycle bag identification tag - A recycle identification (ID) tag and method for organizing and labeling a recycle ID tag connected by an attachment mechanism to an aperture in a flat body at a first end, and the attachment mechanism connected to a recycle bag at a second end. A first identifying inscription of an association to a specific user is provided on a space for inscribing an identification inscription on a first side of the ID tag. An image is provided on a second side of the ID tag. The first identifying inscription may be at least one of a chronological numbering or alphabetizing adapted to identify to the user of the quantity of recycle bags in, or missing from, her possession. | 2011-06-09 |
| 20110133894 | PASSIVE TRANSPONDER FOR AN RFID SYSTEM, AND METHOD OF TRANSMITTING DATA FROM/TO A DATA SOURCE OF SUCH A PASSIVE TRANSPONDER - A passive transponder includes an antenna, an antenna oscillator circuit and a data source. The antenna oscillator circuit is configured to operate at a first resonant frequency or at a second resonant frequency, depending on reception of energy at the transponder or on a data transmission from/to the data source. | 2011-06-09 |
