| 23rd week of 2011 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20110133195 | Thin film transistor, display device including the same, and method of manufacturing the display device - A thin film transistor, a display device including the same, and a method of manufacturing the display device, the thin film transistor including a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer; and source/drain electrodes electrically connected with the semiconductor layer, wherein the gate electrode has a thickness of about 500 Å to about 1500 Å and the gate insulating layer has a thickness of about 1600 Å to about 2500 Å. | 2011-06-09 |
| 20110133196 | SEMICONDUCTOR DEVICE - An object is to provide a highly reliable transistor and a semiconductor device including the transistor. A semiconductor device including a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film over the gate insulating film; and a source electrode and a drain electrode over the oxide semiconductor film, in which activation energy of the oxide semiconductor film obtained from temperature dependence of a current (on-state current) flowing between the source electrode and the drain electrode when a voltage greater than or equal to a threshold voltage is applied to the gate electrode is greater than or equal to 0 meV and less than or equal to 25 meV, is provided. | 2011-06-09 |
| 20110133197 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A bottom gate-type thin film transistor includes a gate insulating film, an interlayer insulating film formed on the gate insulating film, having an opening which is formed in a formation region of a gate electrode, and a semiconductor film formed on the interlayer insulating film so as to cover the opening. The interlayer insulating film contains nitrides in an amount larger than that in the gate insulating film, and the semiconductor film includes a microcrystalline semiconductor film or a polycrystalline semiconductor film formed on semiconductor crystalline nuclei which are formed on the gate insulating film and the interlayer insulating film and contain at least Ge. | 2011-06-09 |
| 20110133198 | THIN FILM TRANSISTOR, DISPLAY DEVICE INCLUDING THE SAME AND MANUFACTURING METHOD THEREOF - A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first portion disposed between the input electrode and the output electrode and having a first crystallinity, and a second portion connected with the first portion, which overlaps the input electrode or the output electrode, and having a second crystallinity. The first crystallinity is higher than the second crystallinity. | 2011-06-09 |
| 20110133199 | ARRRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An array substrate for an LCD device includes a first TFT including a first semiconductor layer, a first gate electrode, wherein the first gate electrode is directly over the first semiconductor layer; a first protrusion extending from the first gate electrode along an edge of the first semiconductor layer; a second TFT including a second semiconductor layer, a second gate electrode, wherein the second gate electrode is directly over the second semiconductor layer; a second protrusion extending from the second gate electrode along an edge of the second semiconductor layer; a third TFT connected to crossed data and gate lines including a third semiconductor layer, a third gate electrode, wherein the third gate electrode is directly over the third semiconductor layer; a third protrusion extending from the third gate electrode along an edge of the third semiconductor layer; and a pixel electrode. | 2011-06-09 |
| 20110133200 | Dual Gate Layout for Thin Film Transistor - A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact. | 2011-06-09 |
| 20110133201 | ELECTRONIC CIRCUIT - An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 Å, e.g., between 100 and 750 Å. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting of aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer. | 2011-06-09 |
| 20110133202 | HIGH THROUGHPUT RECRYSTALLIZATION OF SEMICONDUCTING MATERIALS - Methods for making and/or treating articles of semiconducting material are disclosed. In various methods, a first article of semiconducting material is provided, the first article of semiconducting material is heated sufficiently to melt the semiconducting material, and the melted semiconducting material is solidified in a direction substantially parallel to a shortest dimension of the melted article of semiconducting material. Articles of semiconducting materials made by methods described herein are also disclosed. | 2011-06-09 |
| 20110133203 | TRANSPARENT CERAMIC PHOTO-OPTICAL SEMICONDUCTOR HIGH POWER SWITCHES - A photoconductive semiconductor switch according to one embodiment includes a structure of sintered nanoparticles of a high band gap material exhibiting a lower electrical resistance when excited by light relative to an electrical resistance thereof when not exposed to the light. A method according to one embodiment includes creating a mixture comprising particles, at least one dopant, and at least one solvent; adding the mixture to a mold; forming a green structure in the mold; and sintering the green structure to form a transparent ceramic. Additional system, methods and products are also presented. | 2011-06-09 |
| 20110133204 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a thermal conductive substrate, an p-type GaN layer, an active layer and an n-type GaN layer sequentially stacked above the substrate and an electrode pad deposited on the n-type GaN layer. A surface of n-type GaN layer away from the active layer has a first diffusing section and a second diffusing section. The first diffusing section is adjacent to the electrode pad and the second diffusing section is located at the other side of the first diffusing section opposite to the electrode pad, wherein the doping concentration of the first diffusing section is less than that of the second diffusing section. The n-type GaN layer has an electrical resistance larger than that of the first diffusing section which in turn is larger than that of the second diffusing section. | 2011-06-09 |
| 20110133205 | FIELD-EFFECT TRANSISTOR - A field-effect transistor provided with a channel layer, a carrier supply layer forming a heterojunction with the channel layer, a recessed portion recessed from a surface of the carrier supply layer, a first insulating layer formed at least along the recessed portion, a first gate electrode formed on the first insulating layer, a source electrode formed on one side of the recessed portion in a channel lengthwise direction, and a drain electrode formed on an opposite side of the recessed portion in the channel lengthwise direction. The recessed portion snakes in a direction intersecting the channel lengthwise direction, in the range of a channel length between the source electrode and the drain electrode. | 2011-06-09 |
| 20110133206 | Compound semiconductor device - At a gate electrode formed on a compound semiconductor layer with a Schottky junction, a diffusion preventing layer made of Ti | 2011-06-09 |
| 20110133207 | GROUP III NITRIDE SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A group III nitride substrate on which an epitaxially grown layer of good quality can be formed, and a method of manufacturing the same are obtained. A GaN substrate ( | 2011-06-09 |
| 20110133208 | SEMICONDUCTOR ELEMENT - Light extraction efficiency of a semiconductor light-emitting element is improved. A buffer layer, an n-type GaN layer, an InGaN emission layer, and a p-type GaN layer are laminated on a sapphire substrate in a semiconductor light-emitting element. A ZnO layer functioning as a transparent electrode is provided on the p-type GaN layer and concave portions are formed on a surface of the ZnO layer at two-dimensional periodic intervals. If a wavelength of light from the InGaN emission layer in the air is λ, an index of refraction of the ZnO layer at the wavelength λ is n | 2011-06-09 |
| 20110133209 | GaN SUBSTRATE, EPITAXIAL LAYER-PROVIDED SUBSTRATE, METHODS OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A GaN substrate on which an epitaxially grown layer of good quality can be formed is obtained. A GaN substrate as a group III nitride substrate has a surface in which the number of chlorine atoms per square centimeter of the surface is not more than 2×10 | 2011-06-09 |
| 20110133210 | SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING SCHOTTKY BARRIER DIODE - A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×10 | 2011-06-09 |
| 20110133211 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth. | 2011-06-09 |
| 20110133212 | METHODS OF MAKING SEMICONDUCTOR DEVICES HAVING IMPLANTED SIDEWALLS AND DEVICES MADE THEREBY - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications. | 2011-06-09 |
| 20110133213 | GETTER COMPOSITION AND ORGANIC LIGHT EMITTING DIODE DEVICE INCLUDING THE SAME - A getter composition including a moisture absorbing material and a binder having a volatility of 400 ppm or less when heated to a temperature in the range of 60° C. to 120° C. for 2 hours and an organic light emitting diode device including the getter composition | 2011-06-09 |
| 20110133214 | LIGHT SENSOR DEVICE AND MANUFACTURING METHOD - A light sensor device comprises a substrate ( | 2011-06-09 |
| 20110133215 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an organic light emitting diode (OLED) display includes forming an upper electrode power source line outside of a pixel area over a substrate, forming a lower electrode in the pixel area, forming at least one layer of an organic material layer in the pixel area and areas outside of the pixel area, forming an upper electrode in the pixel area, selectively removing portions of the organic material layer that are exposed outside of the upper electrode, thereby exposing the upper electrode power source line, and coating a conductive material between the upper electrode and the upper electrode power source line in a normal pressure condition such that the conductive material overlaps the upper electrode and the upper electrode power source line, thereby forming a connection portion. | 2011-06-09 |
| 20110133216 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE AND STACKED STRUCTURE BODY - According to one embodiment, a method is disclosed for manufacturing a semiconductor light emitting device. The method can include forming a plurality of semiconductor stacked bodies on a first major surface of a support substrate with a gap between two neighboring semiconductor stacked bodies. The semiconductor stacked bodies includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The method can bond the plurality of semiconductor stacked bodies to one other support substrate with a bonding member. In addition, the method can remove the support substrate from the plurality of semiconductor stacked bodies by irradiating the plurality of semiconductor stacked bodies with a laser light from a second major surface of the support substrate on a side opposite to the first major substrate. The bonding member is not irradiated with the laser light. | 2011-06-09 |
| 20110133217 | Led light emitting apparatus and vehicle headlamp using the same - Four LED chips are mounted on a sub-mount substrate so as to be parallel thereto. A wire | 2011-06-09 |
| 20110133218 | LIGHT EMITTING APPARATUS, METHOD OF MANUFACTURING THE SAME, AND LIGHTING SYSTEM - Disclosed are a light emitting apparatus, a method of manufacturing the same, and a lighting system. The light emitting apparatus includes a body, a light emitting device on the body, a conductive member electrically connected with the light emitting device on the body, a resin member surrounding the light emitting device, and an inorganic oxide layer having a refractive index less than a refractive index of the resin member on the resin member. | 2011-06-09 |
| 20110133219 | LIGHT EMITTING ELEMENT ARRAY - A method of fabricating a light emitting diode array, comprising: providing a temporary substrate; forming a first light emitting stack and a second light emitting stack on the temporary substrate; forming a first insulating layer covering partial of the first light emitting stack; forming a wire on the first insulating layer and electrically connecting to the first light emitting stack and the second light emitting stack; forming a second insulating layer fully covering the first light emitting stack, the wire and partial of the second light emitting stack; forming a metal connecting layer on the second insulating layer and electrically connecting to the second light emitting stack; forming a conductive substrate on the metal connecting layer; removing the temporary substrate; and forming a first electrode connecting to the first light emitting stack. | 2011-06-09 |
| 20110133220 | LIGHT EMITTING DIODE, METHOD FOR FABRICATING PHOSPHOR LAYER, AND LIGHTING APPARATUS - A light emitting diode includes: a light emitting diode chip including a substrate and a light emission structure disposed on the substrate; and a phosphor layer formed to cover at least one surface of a diode upper surface and a diode lower surface, when a surface formed by the light emitting diode chip, when viewed from above the light emission structure, is defined as the diode upper surface and a surface formed by the light emitting diode chip, when viewed from below the substrate is defined as the diode lower surface. The phosphor layer is formed in a manner such that the phosphor layer does not deviate from the diode upper surface or the diode lower surface and has a flat surface parallel to the diode upper surface or the diode lower surface and a curved surface connecting the flat surface to corners of the diode upper surface or the diode lower surface. | 2011-06-09 |
| 20110133221 | LED AND LED PACKAGE - A light emitting device (LED) and Package of the same are provided. The LED comprises a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, a first dielectric layer, and a first electrode layer. The first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer are on a substrate. The first dielectric layer covers the edges of the second conductivity type semiconductor layer and the active layer. The first electrode layer covers the edge of the first conductivity type semiconductor layer. | 2011-06-09 |
| 20110133222 | LED LAMP WITH REMOTE PHOSPHOR COATING AND METHOD OF MAKING THE LAMP - A light emitting diode (LED) lamp includes a base with one or more LED chips, an internal cover over the LED chips, where the cover is a translucent ceramic whose thermal conductivity is greater than glass, where the cover has an interior surface separated from the LED chips by a gap, and where an exterior surface of the cover is coated with a phosphor. The ceramic cover preferably has a bulk thermal conductivity of at least 5 W/(m·K), such as polycrystalline alumina. The LED chips preferably are blue LEDs and the phosphor is selected so that the lamp emits white light. In the method of making the lamp, the phosphor may be applied to the exterior surface of the cover as a preformed sheet or in a coating. | 2011-06-09 |
| 20110133223 | SOLID STATE EMITTER PACKAGES - A solid state emitter package may include at least one electrically conductive path associated with the solid state emitter package that is not in electrical communication with any solid state emitter of the solid state emitter package, with such electrically conductive path being susceptible to inclusion of a jumper or a control element. A solid state emitter package includes a principally red solid state emitter having peak emissions within 590 nm to 680 nm, a principally blue solid state emitter having peak emissions within 400 nm to 480 nm, and at least one of a common leadframe, common substrate, and common reflector, with the package being devoid of any principally green solid state emitters having peak emissions between 510 nm and 575 nm. | 2011-06-09 |
| 20110133224 | THERMALLY OPTIMISED LED CHIP-ON-BOARD MODULE - A LED Chip-on-Board (COB) module comprises a plurality of LED die arranged on a substrate in one or more radially concentric rings about a centre point such that each LED die is azimuthally offset from neighbouring LED die. The module includes thermal conduction pads each having lateral dimensions at least as large as the combined lateral dimensions of the LED die attached to it and a total surface area at least five times larger than the total surface area of all the LED die attached to it. At the same time, the total light emission area of the module is no greater than four times larger than the combined total surface emission area of all the individual LED die disposed on the substrate. A variety of configurations are possible subject to these criteria, which permit good packing density for enhanced brightness whilst ensuring optimal heat transfer. A method of manufacturing the module is also provided. | 2011-06-09 |
| 20110133225 | LIGHT COLLECTION SYSTEM FOR AN LED LUMINAIRE - A light beam collection engine | 2011-06-09 |
| 20110133226 | Organic light emitting diode device - An organic light emitting diode device including an anode, a cathode facing the anode, and a light emitting member between the anode and cathode, wherein the light emitting member includes at least two light emitting units displaying the same or different color as one another, and a charge-generation layer between the at least two light emitting units, the charge-generation layer including a first charge-generation layer and a second charge-generation layer that each include an undoped material, and wherein the first charge-generation layer has an ionization energy that is about the same as or less than an electron affinity of the second charge-generation layer. | 2011-06-09 |
| 20110133227 | ORGANIC LIGHT EMITTING DIODE DEVICE - An organic light emitting diode device is disclosed. The organic light emitting diode device includes a light emitting layer which includes at least two blue light emitting units and at least one orange light emitting unit. Such a device exhibits excellent color characteristic and high luminance and efficiency, as well as a longer life span due to the materials used. In particular, the white light represents color of high color purity after it passes through a color filter. | 2011-06-09 |
| 20110133228 | LED STRUCTURE AND THE LED PACKAGE THEREOF - Disclosed is a light-emitting diode structure comprises a substrate, a plurality of light-emitting diodes on the substrate, and a conductive layer laid on the surface thereof. Each light-emitting diode comprises at least an electrical coupling side close to another electrical coupling side of an adjacent light-emitting diode. Each light-emitting diode comprises at least a first and a second electrode on the surface along the electrical coupling side, so that two close first or second electrodes can be soldered at the same time in wire soldering process, so as to make the light-emitting diodes connect in parallel. One end of the conductive layer is connected to the first electrode of a light-emitting diode and the other end is close to the second electrode of another light-emitting diode, so that the second electrode and the conductive layer can be soldered at the same time in wire soldering process, so as to make the light-emitting diodes connect in series. | 2011-06-09 |
| 20110133229 | Light Emitting Diode Structure, LED Packaging Structure Using the Same and Method of Forming the Same - A light emitting diode (LED) structure and a LED packaging structure are disclosed. The LED structure includes a sub-mount, a stacked structure, an electrode, an isolation layer and a conductive thin film layer. The sub-mount has a first surface and a second surface opposite the first surface. The stacked structure has a first semiconductor layer, an active layer and a second semiconductor layer that are laminated on the first surface. The electrode is disposed apart from the stacked structure on the first surface. The isolation layer is disposed on the first surface to surround the stacked structure as well as cover the lateral sides of the active layer. The conductive thin film layer connects the electrode to the stacked structure and covers the stacked structure. | 2011-06-09 |
| 20110133230 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a substrate, in which concave-convex patterns are in at least a portion of a backside of the substrate, and a light emitting structure on the substrate and comprising a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer. | 2011-06-09 |
| 20110133231 | EXTENSIVE AREA LED HAVING ROUGNESS SURFACE - The structure for fixing packing of a lid ( | 2011-06-09 |
| 20110133232 | Lead frame, its manufacturing method, and semiconductor light emitting device using the same - A lead frame comprises on a same plane, a pad part including an LED chip mounting upper surface A on which at least an LED chip is to be mounted, and a lead part including an electric connection area C in which an electric connection with the LED chip is made. A relationship between an area S | 2011-06-09 |
| 20110133233 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - A light emitting device may include a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer. A first electrode including a plurality of openings may be provided on the light emitting structure. A filling factor, which is an area ratio of the first electrode relative to an area of a top surface of the light emitting structure, may be 20% or less. | 2011-06-09 |
| 20110133234 | LIGHT EMITTING DEVICE - A light emitting device according to the embodiment includes a first electrode; a light emitting structure including a first semiconductor layer over the first electrode, an active layer over the first semiconductor layer, and a second semiconductor layer over the second semiconductor layer; a second electrode over the second semiconductor layer; and a connection member having one end making contact with the first semiconductor layer and the other end making contact with the second semiconductor layer to form a schottky contact with respect to one of the first and second semiconductor layers. | 2011-06-09 |
| 20110133235 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device including a sapphire layer and a light emitting layer formed on the sapphire layer. The sapphire layer has a polygonal sectional shape whose internal angle is an obtuse angle, such as a regular hexagonal shape. Light emitted from the light emitting layer is totally reflected on one side surface of the sapphire layer and next transmitted through another side surface of the sapphire layer. | 2011-06-09 |
| 20110133236 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A light emitting device that can radiate heat generated by a semiconductor light emitting element and/or a resin layer at not only a position directly under the light emitting element, but also a position remote from such a position with respect to the main plane direction is provided. In the light emitting device, a light emitting element is carried on a substrate, and a resin covers the light emitting element. An anisotropic heat conduction material showing a heat conductivity for the substrate main plane direction larger than that for the substrate thickness direction is carried on the substrate. A side of the anisotropic heat conduction material contacts with the resin. Thereby, the anisotropic heat conduction material can receive heat of the resin, conduct it along the main plane direction, and radiate it to the substrate at a position remote from the light emitting element and/or the resin. As the anisotropic heat conduction material, for example, one or more laminated layers of graphite in the form of sheet are used. | 2011-06-09 |
| 20110133237 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device | 2011-06-09 |
| 20110133238 | LIGHT-EMITTING DIODE AND METHOD FOR FABRICATION THEREOF - A transparent-substrate light-emitting diode ( | 2011-06-09 |
| 20110133239 | Substrate structrue for light-emitting diode - Disclosed is a substrate structure for light-emitting diode (LED), including an upper layer substrate, a flexible printed circuit, a lower layer substrate, and an isolation substance. The upper layer substrate has forming a conductor pattern to provide a bonding zone and a plurality of electrode zones. The flexible printed circuit is bonded under the upper layer substrate. The lower layer substrate is bonded under the flexible printed circuit and has forming conductor lines. The isolation substance is coated on the top surface of the upper layer substrate and the bottom surface of the lower layer substrate. As such, a substrate structure comprised of upper and lower layers made of the upper-layer and lower-layer substrates interposing a core made of the flexible printed circuit is formed. | 2011-06-09 |
| 20110133240 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT HAVING THE SAME - Discussed is an LED package The LED package includes a body having a cavity at one side thereof, at least one of lead frames having a bottom frame and a sidewall frame in the cavity, and a light emitting device electrically connected with the lead frames. | 2011-06-09 |
| 20110133241 | LIGHT EMITTING DEVICE - Disclosed are a light emitting device, a light emitting device package, a lighting system and a manufacturing method of light emitting device. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; a first ohmic layer over the light emitting structure; and a second ohmic layer including a pattern over the first ohmic layer. | 2011-06-09 |
| 20110133242 | LIGHT EMITTING APPARATUS - A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer. | 2011-06-09 |
| 20110133243 | LIGHT EMITTING ELEMENT AND A PRODUCTION METHOD THEREFOR - Disclosed are a light emitting device and a method of manufacturing the same. The light emitting device includes a growth substrate, a first conductive semiconductor layer on the growth substrate, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, and an ohmic contact layer having a concavo-convex structure on the second conductive semiconductor layer. | 2011-06-09 |
| 20110133244 | LIGHT EMITTING ELEMENT - A heat radiation structure of a light emitting element has leads, each lead having a plurality of leg sections, and a light emitting chip mounted on any one of the leads. The present invention can provide a high-efficiency light emitting element, in which a thermal load is reduced by widening a connecting section through which a lead and a chip seating section of the light emitting element are connected, and the heat generated from a heat source can be more rapidly radiated to the outside. Further, the present invention can also provide a high-efficiency light emitting element, in which heat radiation fins are formed between a stopper and a molding portion of a lead of the light emitting element so that natural convection can occur between the heat radiation fins, and an area in which heat radiation can occur is widened to maximize a heat radiation effect. | 2011-06-09 |
| 20110133245 | MELT-PROCESSABLE, INJECTION-MOLDABLE THERMOPLASTIC POLYMER COMPOSITION AND SEMI-CONDUCTIVE DEVICES FABRICATED THEREWITH - A thermoplastic, hydrogenated vinyl aromatic/conjugated diene block polymer composition, especially a hydrogenated styrene/butadiene triblock composition, functions well as a LED encapsulating material in that it provides one or more of optical clarity, thermal stability, ultraviolet light resistance, melt-processability and injection-moldability. The resulting LED resists deformation after setting or hardening under typical solder reflow conditions. | 2011-06-09 |
| 20110133246 | INTERNAL COMBUSTION ENGINE IGNITER SEMICONDUCTOR DEVICE - An internal combustion engine igniter semiconductor device is disclosed which is low cost yet secures energy withstand and reverse surge withstand capability. An IGBT includes a clamping diode between a collector electrode and a gate electrode. The IGBT has two n-type buffer layers of differing impurity concentrations between a p | 2011-06-09 |
| 20110133247 | Zener-Triggered SCR-Based Electrostatic Discharge Protection Devices For CDM And HBM Stress Conditions - SCR device is modified to improve turn-on speed for CDM stress conditions. A zener diode is integrated inside SCR device to create an internal feedback and improve turn-on speed. The zener diode is designed as a p | 2011-06-09 |
| 20110133248 | VERTICAL PMOS FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure. | 2011-06-09 |
| 20110133249 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor includes first, second and third compound semiconductor layers. The second compound semiconductor layer has a first interface with the first compound semiconductor layer. The third compound semiconductor layer is disposed over the first compound semiconductor layer. The third compound semiconductor layer has at least one of lower crystallinity and relaxed crystal structure as compared to the second compound semiconductor layer. The gate electrode is disposed over the third compound semiconductor layer. Source and drain electrodes are disposed over the second compound semiconductor layer. The two-dimensional carrier gas layer is generated in the first compound semiconductor layer. The two-dimensional carrier gas layer is adjacent to the first interface. The two-dimensional carrier gas layer either is absent under the third compound semiconductor layer or is reduced in at least one of thickens and carrier gas concentration under the third compound semiconductor layer. | 2011-06-09 |
| 20110133250 | MONOLITHIC MICROWAVE INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME - Provided are a monolithic microwave integrated circuit device and a method for forming the same. The method include: forming an HBT on a substrate; forming a wiring of the HBT and a bottom electrode of a capacitor on the substrate, with a first metal, the bottom electrode being spaced apart from the HBT; forming a first insulation layer on the substrate to cover the HBT and the bottom electrode; and forming a top electrode of the capacitor on the first insulation layer and forming a resistance pattern on the substrate, with a second metal, the resistance pattern being spaced apart from the capacitor, wherein an edge of the top electrode is spaced apart from an edge of the bottom electrode. | 2011-06-09 |
| 20110133251 | Gated algan/gan heterojunction schottky device - Some exemplary embodiments of a semiconductor device using a III-nitride heterojunction and a novel Schottky structure and related method resulting in such a semiconductor device, suitable for high voltage circuit designs, have been disclosed. One exemplary structure comprises a first layer comprising a first III-nitride material, a second layer comprising a second III-nitride material forming a heterojunction with said first layer to generate a two dimensional electron gas (2DEG) within said first layer, an anode comprising at least a first metal section forming a Schottky contact on a surface of said second layer, a cathode forming an ohmic contact on said surface of said second layer, a field dielectric layer on said surface of said second layer for isolating said anode and said cathode, and an insulating material on said surface of said second layer and in contact with said anode. | 2011-06-09 |
| 20110133252 | SEMICONDUCTOR DEVICE WITH INTERFACE CIRCUIT AND METHOD OF CONFIGURING SEMICONDUCTOR DEVICES - Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell. | 2011-06-09 |
| 20110133253 | SEMICONDUCTOR DEVICE - A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G | 2011-06-09 |
| 20110133254 | CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING - An electrical device includes a plurality of interconnects passing through a plane. The interconnects have a longitudinal axis substantially perpendicular to the plane and including an arrangement pattern which reduces or eliminates cross-talk between nearest neighboring interconnects, wherein the interconnects include a first differentially driven signal conductor pair and at least one other signal conductor, and the arrangement includes the at least one other signal conductor disposed at a substantially same distance from each conductor of the first differentially driven signal conductor pair. | 2011-06-09 |
| 20110133255 | APPARATUS AND METHOD FOR MOLECULE DETECTION USING NANOPORES - A detector device: a source region (S), a drain region (D) and a gate contact ( | 2011-06-09 |
| 20110133256 | CMOS-MEMS Cantilever Structure - The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity. | 2011-06-09 |
| 20110133257 | TRANSFERRED THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Provided are a transferred thin film transistor and a method of manufacturing the same. The method includes: forming a source region and a drain region that extend in a first direction in a first substrate and a channel region between the source region and the drain region; forming trenches that extend in a second direction in the first substrate to define an active layer between the trenches, the second direction intersecting the first direction; separating the active layer between the trenches from the first substrate by performing an anisotropic etching process on the first substrate inside the trenches; attaching the active layer on a second substrate; and forming a gate electrode in the first direction on the channel region of the active layer. | 2011-06-09 |
| 20110133258 | SHIELDED GATE TRENCH MOSFET WITH INCREASED SOURCE-METAL CONTACT - A semiconductor device formed on a semiconductor substrate having a substrate top surface, includes: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region, at least a portion of the source region extending above the dielectric material; a contact trench that allows contact such as electrical contact between the source region and the body region; and a metal layer disposed over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench. | 2011-06-09 |
| 20110133259 | STRESSED BARRIER PLUG SLOT CONTACT STRUCTURE FOR TRANSISTOR PERFORMANCE ENHANCEMENT - A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices. | 2011-06-09 |
| 20110133260 | METHOD AND DEVICE TO REDUCE DARK CURRENT IN IMAGE SENSORS - A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area. | 2011-06-09 |
| 20110133261 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an active region defined by an isolation region formed in a cell area, buried gates disposed in the active region and the isolation region, conduction layers disposed on the active region and having the same heights as an surface of the isolation region, and a line type storage node contact connected with one of the conduction layers. | 2011-06-09 |
| 20110133262 | Power Semiconductor Component with Plate Capacitor Structure and Edge Termination - A semiconductor component includes a body with a drift zone, a source zone, a body zone, and a drain zone. A gate forms a MOS structure with the drift zone, with the source zone and with the body zone. An edge termination between the lateral edge and the MOS structure includes a plurality of field rings which enclose the MOS structure. The lateral edge is at the same potential as the drift zone, and the edge termination reduces voltage between the lateral edge and the source zone. A horizontally extending edge plate is disposed at the front side between the lateral edge and the edge termination. The edge plate is at the same potential as the drift zone and forms a plate capacitor structure including a field plate lying above the edge plate. | 2011-06-09 |
| 20110133263 | SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 2011-06-09 |
| 20110133264 | SYSTEM AND METHOD FOR EEPROM ARCHITECTURE - A method for manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) device includes providing a substrate and forming a gate oxide over the substrate. Also, the method includes providing a mask overlying the gate oxide layer, the mask defining a tunnel opening. The method additionally includes performing selective etching over the mask to form a tunnel oxide layer. The method includes forming a floating gate over the tunnel oxide layer and a selective gate over the gate oxide layer. The method includes angle doping a region of the substrate using the floating gate as a mask to obtain a first doped region. The method further includes forming a dielectric layer over the floating gate and a control gate over the dielectric layer. The method additionally includes angle doping a second region of the substrate using the selective gate as a mask to obtain a second doped region, wherein the first and second doped regions partially overlap. | 2011-06-09 |
| 20110133265 | MEMORY CELL - A memory cell has a tunnel dielectric over a first silicon-containing material, a second silicon-containing material over the tunnel dielectric, a first silicon oxide layer on an edge of the second silicon-containing material and extending across a first portion of an edge of the tunnel dielectric, and a second silicon oxide layer on a side of the first silicon-containing material and extending across a second portion of the edge of the tunnel dielectric. The first and second silicon oxide layers are two distinct layers and are in contact with the tunnel dielectric layer. | 2011-06-09 |
| 20110133266 | Flash Memory Having a Floating Gate in the Shape of a Curved Section - The floating gate of a flash memory may be formed with a flat lower surface facing a substrate and a curved upper surface facing the control gate. In some embodiments, such a device has improved capacitive coupling to the control gate and reduced capacitive coupling to its neighbors. | 2011-06-09 |
| 20110133267 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a charge accumulation layer, an intermediate insulating film and a conductive layer sequentially on the gate insulating film, forming an electrode isolating trench in the conductive layer, the intermediate insulating film and the charge accumulation layer, forming a nitride film on upper and side surfaces of the conductive layer, side surfaces of the intermediate insulating film, side surfaces of the charge accumulation layer and an upper surface of the gate insulating film, removing the nitride film formed on the upper surface of the gate insulating film, and filling the electrode isolating trench with an insulating film. | 2011-06-09 |
| 20110133268 | Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones. | 2011-06-09 |
| 20110133269 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes, below a high-voltage wiring, a p | 2011-06-09 |
| 20110133270 | MEMORY DEVICE WITH RECESSED CONSTRUCTION BETWEEN MEMORY CONSTRUCTIONS - A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell. | 2011-06-09 |
| 20110133271 | Trench MOS Device with Schottky Diode and Method for Manufacturing Same - In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction. | 2011-06-09 |
| 20110133272 | SEMICONDUCTOR DEVICE WITH IMPROVED ON-RESISTANCE - A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone. | 2011-06-09 |
| 20110133273 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific offset from the gate electrode and a sidewall insulating film. The semiconductor device enables the drain breakdown voltage to be sufficient and the on-resistance to decrease. A silicide layer is also formed on the surface of the gate electrode, thereby achieving gate resistance reduction and high frequency characteristics improvement. | 2011-06-09 |
| 20110133274 | LATERAL DOUBLE-DIFFUSED MOSFET - A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain. | 2011-06-09 |
| 20110133275 | STRUCTURE AND METHOD FOR SEMICONDUCTOR POWER DEVICES - A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element. | 2011-06-09 |
| 20110133276 | Gate Dielectric Formation for High-Voltage MOS Devices - An integrated circuit structure includes a semiconductor substrate and a high-voltage metal-oxide-semiconductor (HVMOS) device, which includes a first high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate; a drain region of a second conductivity type opposite the first conductivity type in the semiconductor substrate and spaced apart from the first HVW region; a gate dielectric with at least a portion directly over the first HVW region; and a gate electrode over the gate dielectric. The gate dielectric includes a bottom gate oxide region; and a silicon nitride region over the bottom gate oxide region. | 2011-06-09 |
| 20110133277 | SEMICONDUCTOR DEVICE - A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode. | 2011-06-09 |
| 20110133278 | SEMICONDUCTOR DEVICE - A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion. | 2011-06-09 |
| 20110133279 | SEMICONDUCTOR DEVICE - The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate. | 2011-06-09 |
| 20110133280 | DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS - A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire. | 2011-06-09 |
| 20110133281 | Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof - Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer. | 2011-06-09 |
| 20110133282 | Semiconductor device - A semiconductor device includes a power supply line supplied with a power supply voltage; a power supply node connected with the power supply line; a ground line; a ground pad connected with the ground line; a signal input pad; a main protection circuit section configured to discharge an ESD surge applied to a first pad as one of the power supply node, the signal input pad and the ground pad to a second pad as another thereof; a protection object circuit; a connection node connected with the protection object circuit; a first resistance element connected between the signal input pad and the connection node; and a sub protection circuit section. The sub protection circuit section includes a least one of a first PMOS transistor having a source connected with the connection node, a drain connected with the ground line and a gate and a back gate connected with the power supply line, and a first NMOS transistor having a source connected with the connection node, a drain connected with the power supply line and a gate and a back gate connected with the ground line. | 2011-06-09 |
| 20110133283 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a structure in which a difference in height between a cell region and a peripheral region are formed so that a buried gate structure of the cell region is substantially equal in height to the gate of the peripheral region, whereby a bit line and a storage node contact can be more easily formed in the cell region and parasitic capacitance can be decreased decreased. The semiconductor device includes a cell region including a gate buried in a substrate, and a peripheral region adjacent to the cell region, where a step height between a surface of the cell and a surface of the peripheral region is generated. | 2011-06-09 |
| 20110133284 | MULTIPLE CARBON NANOTUBE TRANSFER AND ITS APPLICATIONS FOR MAKING HIGH-PERFORMANCE CARBON NANOTUBE FIELD-EFFECT TRANSISTOR (CNFET), TRANSPARENT ELECTRODES, AND THREE-DIMENSIONAL INTEGRATION OF CNFETS - A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications. Further, three-dimensional CNFETs can be provided by utilizing the subject plasma exposure processes. | 2011-06-09 |
| 20110133285 | SRAM Structure with FinFETs Having Multiple Fins - A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor. | 2011-06-09 |
| 20110133286 | INTEGRIERTER SCHALTUNGSTEIL - An integrated circuit part containing at least one MOS transistor with a trace system, with a source region having a source contact, and with a drain region having a drain contact, and with a gate region having a gate contact, and with a first cover layer lying on the gate, source, and drain regions and a first trace level formed thereupon, and with a second cover layer, lying above the first trace level, with a second trace level lying thereupon, and with a trace formed and connected with the source contact, and with a trace formed and connected with the drain contact, whereby a first metal region, arranged at least partially between the trace, connected to the source contact, and the trace, connected to the drain contact, is provided above the gate region lying on the first cover layer and/or the second cover layer, and the metal region is connected neither to the drain contact nor to the source contact or to the gate contact. | 2011-06-09 |
| 20110133287 | METHOD FOR FORMING STRAINED CHANNEL PMOS DEVICES AND INTEGRATED CIRCUITS THEREFROM - An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦10 | 2011-06-09 |
| 20110133288 | TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a transistor of a semiconductor device comprises: forming a gate in a NMOS region and a PMOS region of a semiconductor substrate; forming a gate spacer on a sidewall of the gate; performing an ion implantation process on the NMOS region to form a junction region in the NMOS region; depositing an oxide film on the entire surface of the semiconductor substrate including the gate; removing hydrogen (H) existing in the oxide film and the gate spacer; and removing the oxide film in the PMOS region and performing a ion implantation process on the PMOS region to form a junction region in the PMOS region. | 2011-06-09 |
| 20110133289 | MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING - A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed. | 2011-06-09 |
| 20110133290 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME - A semiconductor device of high reliability and element-integrating performance, has a substrate (silicon substrate), a first trench made in the silicon substrate, a passive element layer buried in the first trench, and a first insulating film (silicon nitride film) arranged between the first trench and the passive element layer. The passive element layer projects upwardly relative to the substrate, and so too preferably the adjacent insulating film. An active element is formed such that its gate electrode, which is preferably fully silicided, has an upper end at a level higher than the upper surface of the passive element film. | 2011-06-09 |
| 20110133291 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - Disclosed is a fabrication method which includes: forming a first gate electrode and a second gate electrode which cross over an active region, the overall width of the second gate electrode being less than that of the first gate electrode; ion-implanting dopants into the active region at an oblique angle using the first and second gate electrodes as a mask for ion-implantation, thereby to form separated doped regions on opposite sides of the first gate electrode and to form a continuous doped region extending from one of opposite sides of the second gate electrode to the other. | 2011-06-09 |
| 20110133292 | FinFETs with Multiple Fin Heights - An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces. | 2011-06-09 |
| 20110133293 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film. | 2011-06-09 |
| 20110133294 | MICRO ELECTROMECHANICAL SYSTEMS (MEMS) HAVING A GAP STOP AND METHOD THEREFOR - A method of forming a micro-electromechanical system (MEMS) includes providing a cap substrate, providing a support substrate, depositing a conductive material over the support substrate, patterning the conductive material to form a gap stop and a contact, wherein the gap stop is separated form the contact by an opening, forming a bonding material over the contact and in the opening, wherein the gap stop and the contact prevent the bonding material from extending outside the opening, and attaching the cap substrate to the support substrate by the step of forming the bonding material. In addition, the structure is described. | 2011-06-09 |
