23rd week of 2017 patent applcation highlights part 65 |
Patent application number | Title | Published |
20170162673 | GATE-ALL-AROUND FIN DEVICE - A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type. | 2017-06-08 |
20170162674 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions. | 2017-06-08 |
20170162675 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer. | 2017-06-08 |
20170162676 | SEMICONDUCTOR DEVICE WITH ISOLATED BODY PORTION - Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body. | 2017-06-08 |
20170162677 | SONOS FLASH MEMORY DEVICE - A semiconductor device fabricated by forming a dummy layer on a semiconductor substrate, forming a groove in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer, eliminating the trap layer formed above the upper surface and at the sides of the dummy layer, and forming a top insulating film to cover a remaining trap layer and the exposed tunnel insulating film. | 2017-06-08 |
20170162678 | MULTILAYER PASSIVATION OR ETCH STOP TFT - The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition. | 2017-06-08 |
20170162679 | SEMICONDUCTOR DEVICE WITH TRENCH EDGE TERMINATION - A semiconductor device is provide that includes: a semiconductor body having a first surface, an inner region, and an edge region; a pn junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region; a recess extending from the first surface in the edge region into the semiconductor body, the recess comprising at least one sidewall; a dielectric filling the recess. In the dielectric, a dielectric number, in the lateral direction, decreases as a distance from the first sidewall increases. | 2017-06-08 |
20170162680 | SEMICONDUCTOR DEVICE - A semiconductor device may include a trench, a gate insulating film covering the trench, first conductive type career-injected regions intermittently appearing along a predetermined direction, a first conductive type drift region continuously present along the predetermined direction, a second conductive type body region filling a gap between the career-injected regions as seen along the predetermined direction, and a gate electrode disposed in the trench. A front end surface located on the front surface side of the gate electrode may include a first end surface at a portion of the gate electrode opposing the career-injected regions via the gate insulating film, and a second end surface at least a part of a portion of the gate electrode opposing the body region in the gap. The second end surface may be displaced to the rear surface side relative to the first end surface. | 2017-06-08 |
20170162681 | IGBT - An IGBT includes a rectangular trench including first to fourth trenches and a gate electrode arranged inside of the rectangular trench. An n-type emitter region includes a first emitter region being in contact with the first trench, and a second emitter region being in contact with the third trench. A body contact region includes a first body contact region being in contact with the second trench, and a second body contact region being in contact with the fourth trench. A surface body region is in contact with the trenches in ranges from connection portions to the emitter regions. | 2017-06-08 |
20170162682 | Semiconductor Device Having a Desaturation Channel Structure for Desaturating a Charge Carrier Concentration in an IGBT Cell - A semiconductor device includes a first IGBT cell having a second-type doped drift zone and a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell. The desaturation semiconductor structure includes a first-type doped region forming a pn-junction with the drift zone and two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction. The two trenches confine a mesa region including a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction. The desaturation channel region and the body region adjoin each other, and the desaturation channel region is a depletable region. | 2017-06-08 |
20170162683 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer. | 2017-06-08 |
20170162684 | ENHANCEMENT-MODE III-NITRIDE DEVICES - A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact. | 2017-06-08 |
20170162685 | STRESS RETENTION IN FINS OF FIN FIELD-EFFECT TRANSISTORS - Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin. | 2017-06-08 |
20170162686 | FIELD-EFFECT TRANSISTOR COMPRISING GERMANIUM AND MANUFACTURING METHOD THEREOF - The disclosed technology generally relates to semiconductor devices, and more particularly to transistors comprising germanium (Ge) in the channel, and to methods of manufacturing thereof. In one aspect, a field-effect transistor (FET) comprises an active region comprising germanium (Ge) and a gate stack formed on the active region. The gate stack comprises a Si-comprising passivation layer formed on the active region, an interfacial dielectric layer comprising SiO, (x>0) formed on the passivation layer, a dielectric capping layer comprising an interface dipole-forming material formed on the interfacial dielectric layer, a high-k dielectric layer formed on the dielectric capping layer and a gate electrode layer formed on the high-k dielectric layer. | 2017-06-08 |
20170162687 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: fainting a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor. | 2017-06-08 |
20170162688 | METAL GATE STRUCTURE AND METHOD OF FORMATION - Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures. | 2017-06-08 |
20170162689 | SGT MOSFET WITH ADJUSTABLE CRSS AND CISS - A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor substrate wherein a plurality of the trenched gates further include a shielded bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer. At least one of the shielded bottom electrode is connected a source metal and at least one of the top electrodes in the gate trench is connected to a source metal of the power device. | 2017-06-08 |
20170162690 | LDMOS DEVICE WITH BODY DIFFUSION SELF-ALIGNED TO GATE - A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode. | 2017-06-08 |
20170162691 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is provided. The semiconductor device includes a substrate including a first conductive type well region; a gate structure; a lightly-doped drain region and a lightly-doped source region disposed at two opposite sides of the gate structure; a second conductive type first doped region disposed in the lightly-doped drain region, wherein the doping concentration of the second conductive type first doped region is less than the doping concentration of the lightly-doped drain region; a heavily-doped source region disposed in the lightly-doped source region; and a heavily-doped drain region disposed in the second conductive type first doped region. The present disclosure also provides a method for manufacturing the semiconductor device. | 2017-06-08 |
20170162692 | Method and Apparatus for Use in Improving Linearity of MOSFETs Using an Accumulated Charge Sink-Harmonic Wrinkle Reduction - A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. | 2017-06-08 |
20170162693 | APPARATUS AND METHODS TO CREATE MICROELECTRONIC DEVICE ISOLATION BY CATALYTIC OXIDE FORMATION - Non-planar transistor devices which include oxide isolation structures formed in semiconductor bodies thereof through the formation of an oxidizing catalyst layer on the semiconductor bodies followed by an oxidation process. In one embodiment, the semiconductor bodies may be formed from silicon-containing materials and the oxidizing catalyst layer may comprise aluminum oxide, wherein oxidizing the semiconductor body to form an oxide isolation zone forms a semiconductor body first portion and a semiconductor body second portion with the isolation zone substantially electrically separating the semiconductor body first portion and the semiconductor body second portion. | 2017-06-08 |
20170162694 | TRANSISTOR AND METHOD OF FORMING SAME - A first aspect of the invention provides for a transistor. The transistor may include a gate stack on a substrate; a channel under the gate stack within the substrate; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer substantially separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion. | 2017-06-08 |
20170162695 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer. | 2017-06-08 |
20170162696 | SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURE WITH TWO CHANNEL LAYERS AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively. | 2017-06-08 |
20170162697 | SEMICONDUCTOR DEVICES HAVING HIGH-QUALITY EPITAXIAL LAYER AND METHODS OF MANUFACTURING THE SAME - A semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. The semiconductor device may include: a substrate; a fin-shaped first semiconductor layer spaced apart from the substrate; a second semiconductor layer at least partially surrounding a periphery of the first semiconductor layer; an isolation layer formed on the substrate, exposing at least a part of the second semiconductor layer, wherein the exposed part of the second semiconductor layer extends in a fin shape; and a gate stack formed on the isolation layer and intersecting the second semiconductor layer. | 2017-06-08 |
20170162698 | Enhancement-Mode Field Effect Transistor Having Metal Oxide Channel Layer - An enhancement-mode n-type field effect transistor is disclosed to have a metal oxide channel layer, a gate dielectric layer, a gate electrode, a source electrode, and a drain electrode. The metal oxide channel layer has a material selected from SnO | 2017-06-08 |
20170162699 | METAL OXIDE SEMICONDUCTOR LAYER FORMING COMPOSITION, AND METHOD FOR PRODUCING METAL OXIDE SEMICONDUCTOR LAYER USING SAME - The invention provides a metal oxide semiconductor layer forming composition containing a solvent represented by formula [1]: | 2017-06-08 |
20170162700 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased. | 2017-06-08 |
20170162701 | SEMICONDUCTOR DEVICE - Provided is a transistor which has favorable transistor characteristics and includes an oxide semiconductor, and a highly reliable semiconductor device which includes the transistor including the oxide semiconductor. In the semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode are stacked in this order, a sidewall insulating film is formed along side surfaces and a top surface of the gate electrode, and the oxide semiconductor film is subjected to etching treatment so as to have a cross shape having different lengths in the channel length direction or to have a larger length than a source electrode and a drain electrode in the channel width direction. Further, the source electrode and the drain electrode are formed in contact with the oxide semiconductor film. | 2017-06-08 |
20170162702 | 3D TRANSISTOR HAVING A GATE STACK INCLUDING A FERROELECTRIC FILM - A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (C | 2017-06-08 |
20170162703 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND ARRAY SUBSTRATE - The embodiments of present disclosure provide a thin film transistor, a method for manufacturing the same, and an array substrate. The thin film transistor comprises an active layer provided on a substrate, the active layer including a middle channel region, a first high resistance region and a second high resistance region provided respectively on external sides of the middle channel region, a source region provided on an external side of the first high resistance region and a drain region provided on an external side of the second high resistance region, wherein a base material of the active layer is diamond single crystal. According to the thin film transistor, the method for manufacturing the same, and the array substrate provided in the embodiments of present disclosure, by providing high resistance regions on external sides of the middle channel region of the active layer, the carrier mobility is reduced and the leakage current of the thin film transistor made of single crystalline diamond is effectively suppressed. | 2017-06-08 |
20170162704 | FIELD-EFFECT TRANSISTOR, DISPLAY ELEMENT, IMAGE DISPLAY DEVICE, AND SYSTEM - A field-effect transistor including: a gate electrode, which is configured to apply gate voltage; a source electrode and a drain electrode, which are configured to take electric current out; an active layer, which is disposed to be adjacent to the source electrode and the drain electrode and is formed of an oxide semiconductor; and a gate insulating layer, which is disposed between the gate electrode and the active layer, wherein the gate insulating layer contains a paraelectric amorphous oxide containing a Group A element which is an alkaline earth metal and a Group B element which is at least one selected from the group consisting of Ga, Sc, Y, and lanthanoid, and wherein the active layer has a carrier density of 4.0×10 | 2017-06-08 |
20170162705 | LOW NOISE AMPLIFIER TRANSISTORS WITH DECREASED NOISE FIGURE AND LEAKAGE IN SILICON-ON-INSULATOR TECHNOLOGY - A metal oxide semiconductor field effect transistor preferably fabricated with a silicon-on-insulator process has a first semiconductor region and a second semiconductor region in a spaced relationship thereto A body structure is defined by a channel segment between the first semiconductor region and the second semiconductor region, and a first extension segment structurally contiguous with the channel segment. A shallow trench isolation structure surrounds the first semiconductor region, the second semiconductor region, and the body structure, with a first extension interface being defined between the shallow trench isolation structure and the first extension segment of the body structure to reduce leakage current flowing from the second semiconductor region to the first semiconductor region through a parasitic path of the body structure. | 2017-06-08 |
20170162706 | LOW TEMPERATURE POLY SILICON (LTPS) THIN FILM TRANSISTOR (TFT) AND THE MANUFACTURING METHOD THEREOF - The present disclosure discloses a LTPS TFT and the manufacturing method thereof. The method includes: forming a semiconductor layer and a LTPS layer on the same surface on a base layer; forming an oxide layer is formed on one side of the semiconductor layer facing away the base layer, and forming the oxide layer on one side of the LTPS layer facing away the base layer; forming a first photoresist layer of a first predetermined thickness on the oxide layer; arranging a corresponding first cobalt layer on each of the photoresist layers, a vertical projection of the first cobalt layer overlaps with the vertical projection of the corresponding first photoresist layer; doping high-concentration doping ions into a first specific area of the semiconductor layer. With such configuration, the number of the masking process is decreased and the manufacturing time is reduced. | 2017-06-08 |
20170162707 | AMORPHOUS SILICON SEMICONDUCTOR TFT BACKBOARD STRUCTURE - The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer ( | 2017-06-08 |
20170162708 | TFT SUBSTRATES AND THE MANUFACTURING METHODS THEREOF - The TFT array substrate and the manufacturing method thereof are disclosed. The dual-layer structure having the bottom gate electrode, including the metal layer and the transparent metal oxide layer, and the common electrode, including the common electrode, may be formed by the same masking process. In this way, the number of masking processes may be decreased so as to enhance the manufacturing efficiency and the cost. | 2017-06-08 |
20170162709 | Method for Manufacturing Thin Film Transistor, Thin Film Transistor and Display Panel - The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer. | 2017-06-08 |
20170162710 | Method for Fabricating Enhancement-mode Field Effect Transistor Having Metal Oxide Channel Layer - A method for fabricating an enhancement-mode n-type field effect transistor is disclosed. The method involves forming a metal oxide channel layer, forming a gate dielectric layer, forming a gate electrode, and forming a source electrode and a drain electrode. The metal oxide channel layer has a material selected from SnO | 2017-06-08 |
20170162711 | STRUCTURE AND PROCESS FOR OVERTURNED THIN FILM DEVICE WITH SELF-ALIGNED GATE AND S/D CONTACTS - Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material. | 2017-06-08 |
20170162712 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, AND ARRAY SUBSTRATE - A TFT, a method for manufacturing the TFT, and an array substrate are disclosed. In the TFT according to the present disclosure, the nano conductive points that are independent from one another are formed in a channel area of the active layer, so that the channel area of the active layer can be divided into a plurality of sub channels that are independent from one another, and an equivalent electric field strength thereof can be increased. The larger the equivalent electric field strength is, the higher the carrier mobility ratio would be, and the larger the saturation current of the TFT would become. Therefore, the TFT with a higher definition and a higher aperture ratio can be manufactured. | 2017-06-08 |
20170162713 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND ORGANIC EL DISPLAY DEVICE - A thin film transistor includes: a gate electrode; a source electrode and a drain electrode; an oxide semiconductor layer used as a channel layer; and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, wherein metallic elements included in the oxide semiconductor layer include at least indium (In), and fluorine (F) is included in a region which is an internal region in the oxide semiconductor layer and is close to the gate insulating layer. | 2017-06-08 |
20170162714 | NANOMETER SEMICONDUCTOR DEVICES HAVING HIGH-QUALITY EPITAXIAL LAYER AND METHODS OF MANUFACTURING THE SAME - There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer. | 2017-06-08 |
20170162715 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a method of manufacturing a thin film transistor, includes forming an island-like first insulating layer containing oxygen above an insulating substrate, forming an oxide semiconductor layer above the insulating substrate and the first insulating layer and in contact with the first insulating layer, and performing heat treatment to supply oxygen from the first insulating layer to an overlapping area of the oxide semiconductor layer, which is overlaid on the first insulating layer. | 2017-06-08 |
20170162716 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE - A novel semiconductor device including an oxide semiconductor is provided. In particular, a planar semiconductor device including an oxide semiconductor is provided. A semiconductor device including an oxide semiconductor and having large on-state current is provided. The semiconductor device includes an oxide insulating film, an oxide semiconductor film over the oxide insulating film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a gate insulating film between the source electrode and the drain electrode, and a gate electrode overlapping the oxide semiconductor film with the gate insulating film. The oxide semiconductor film includes a first region overlapped with the gate electrode and a second region not overlapped with the gate electrode, the source electrode, and the drain electrode. The first region and the second region have different impurity element concentrations. The gate electrode, the source electrode, and the drain electrode contain the same metal element. | 2017-06-08 |
20170162717 | CO-PLANAR OXIDE SEMICONDUCTOR TFT SUBSTRATE STRUCTURE AND MANUFACTURE METHOD THEREOF - Provided is a co-planar oxide semiconductor TFT substrate structure, in which an active layer includes a main body and a plurality of short channels connected to the main body and are separated with a plurality of strip metal electrodes to make the active layer possess higher mobility and lower leak current. Also provided is a manufacture method of the co-planar oxide semiconductor TFT substrate structure, in which with the plurality of strip metal electrodes formed between the source and the drain, which are separately positioned, as deposing the oxide semiconductor layer, the plurality of short channels can be formed between the source and the drain. The method is simple and does not require additional mask or process to obtain the active layer structure different from prior art. The manufactured actively layer possesses higher mobility and lower leak current. Thus, the performance of the TFT element can be improved. | 2017-06-08 |
20170162718 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a transistor having a reduced number of oxygen vacancies in a channel formation region of an oxide semiconductor with stable electrical characteristics or high reliability is provided. A gate insulating film is formed over a gate electrode; an oxide semiconductor layer is formed over the gate insulating film; an oxide layer is formed over the oxide semiconductor layer by a sputtering method to form an stacked-layer oxide film including the oxide semiconductor layer and the oxide layer; the stacked-layer oxide film is processed into a predetermined shape; a conductive film containing Ti as a main component is formed over the stacked-layer oxide film; the conductive film is etched to form source and drain electrodes and a depression portion on a back channel side; and portions of the stacked-layer oxide film in contact with the source and drain electrodes are changed to an n-type by heat treatment. | 2017-06-08 |
20170162719 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H | 2017-06-08 |
20170162720 | Gate Structure - A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench. | 2017-06-08 |
20170162721 | DIODE STRUCTURE - A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region. | 2017-06-08 |
20170162722 | PHOTOVOLTAIC STRUCTURES WITH ELECTRODES HAVING VARIABLE WIDTH AND HEIGHT - A method of fabricating a solar cell is described. The solar cell can include a photovoltaic structure and a metallic grid on the photovoltaic structure. The metallic grid can include one or more electroplated metal layers, a busbar, and a plurality of finger lines connected to the busbar, where one or more finger lines have variable widths. | 2017-06-08 |
20170162723 | SPOT-WELDED AND ADHESIVE-BONDED INTERCONNECTS FOR SOLAR CELLS - Approaches for fabricating spot-welded and adhesive bonded interconnects for solar cells, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a back surface and an opposing light-receiving surface. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the back surface of the substrate. A conductive contact structure is disposed on the plurality of alternating N-type and P-type semiconductor regions. An interconnect structure is electrically connected to the conductive contact structure. The interconnect structure includes a plurality of protrusions in contact with the conductive contact structure. Each of the plurality of protrusions is spot-welded to the conductive contact structure and is surrounded by an adhesive material. | 2017-06-08 |
20170162724 | FAST PROCESS FLOW, ON-WAFER INTERCONNECTION AND SINGULATION FOR MEPV - A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern. | 2017-06-08 |
20170162725 | SOLAR CELL - A solar cell includes a front side for light incidence, an opposite back side, a crystalline semiconductor substrate of a first or second conductivity type, a front side passivating region with a passivating layer and a conductive layer of the first type, a back side passivating region with a passivating layer and a conductive layer of the second type, a front side contact with one front side conductive material and front side electrical contacts on the front side conductive material, a front side light coupling layer on the front side, a back side contact opposite the front side contact and formed by back side conductive material and a back side electrical contact thereon. The front side has lower light absorption and better antireflective property. The front side conductive material is thinner in regions between and/or besides front side electrical contacts than in regions below front side electrical contacts. | 2017-06-08 |
20170162726 | PHOTODIODE AND PHOTODIODE ARRAY | 2017-06-08 |
20170162727 | METHOD OF FORMING ELECTRODE, ELECTRODE MANUFACTURED THEREFROM AND SOLAR CELL - A method of forming an electrode, an electrode for a solar cell manufactured, and a solar cell, the method including forming a pattern of a finger electrode by: coating a composition for forming a first electrode that includes a conductive powder, an organic vehicle, and a first glass frit that is free of silver and phosphorus, and drying the coated composition for forming a first electrode; forming a pattern of a bus electrode by: coating a composition for forming a second electrode that includes a conductive powder, an organic vehicle, and a second glass frit that includes silver and phosphorus, and drying the coated composition for forming a second electrode; and firing the resultant patterns. | 2017-06-08 |
20170162728 | ETCHING OF SOLAR CELL MATERIALS - A solar cell is fabricated by etching one or more of its layers without substantially etching another layer of the solar cell. In one embodiment, a copper layer in the solar cell is etched without substantially etching a topmost metallic layer comprising tin. For example, an etchant comprising sulfuric acid and hydrogen peroxide may be employed to etch the copper layer selective to the tin layer. A particular example of the aforementioned etchant is a Co-Bra Etch® etchant modified to comprise about 1% by volume of sulfuric acid, about 4% by volume of phosphoric acid, and about 2% by volume of stabilized hydrogen peroxide. In one embodiment, an aluminum layer in the solar cell is etched without substantially etching the tin layer. For example, an etchant comprising potassium hydroxide may be employed to etch the aluminum layer without substantially etching the tin layer. | 2017-06-08 |
20170162729 | Solar Cell Emitter Region Fabrication Using Self-Aligned Implant and Cap - Methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells, are described. In an example, a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. The method also involves implanting, through a stencil mask, dopant impurity atoms in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. The method also involves forming, through the stencil mask, a capping layer on and substantially in alignment with the implanted regions of the silicon layer. The method also involves removing the non-implanted regions of the silicon layer, wherein the capping layer protects the implanted regions of the silicon layer during the removing. The method also involves annealing the implanted regions of the silicon layer to form doped polycrystalline silicon emitter regions. | 2017-06-08 |
20170162730 | SINGLE-STEP METAL BOND AND CONTACT FORMATION FOR SOLAR CELLS - A method for fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a first metal layer on the dielectric region. The method can also include forming a second metal layer on the first metal layer and locally heating a particular region of the second metal layer, where heating includes forming a metal bond between the first and second metal layer and forming a contact between the first metal layer and the solar cell structure. The method can include forming an adhesive layer on the first metal layer and forming a second metal layer on the adhesive layer, where the adhesive layer mechanically couples the second metal layer to the first metal layer and allows for an electrical connection between the second metal layer to the first metal layer. | 2017-06-08 |
20170162731 | PHOTOVOLTAIC MODULE - A PV module includes a transparent substrate, a first solar cell unit, a crystalline silicon solar cell, and a spacer. The first solar cell unit is between the transparent substrate and the crystalline silicon solar cell, and the first solar cell unit includes a first electrode, a second electrode, and a I-III-VI semiconductor layer between the first electrode and the second electrode. The I-III-VI semiconductor layer includes at least gallium (Ga) and sulfur (S), and the energy gap thereof is more than that of crystalline silicon. Moreover, the crystalline silicon solar cell and the first solar cell unit are separated by the spacer. | 2017-06-08 |
20170162732 | ARRANGEMENT FOR A THIN-FILM PHOTOVOLTAIC CELL STACK AND ASSOCIATED FABRICATION METHOD - An arrangement for a thin-film photovoltaic cell stack comprises a substrate layer for a photovoltaic cell and a molybdenum grid positioned on the substrate layer, an ultra-thin alloy layer made of copper, indium, gallium and selenium positioned on the molybdenum grid, and a buffer layer positioned on the ultra-thin alloy layer made of copper, indium, gallium and selenium and a window layer positioned on the buffer layer. | 2017-06-08 |
20170162733 | PROCESS FOR PREPARING QUANTUM DOT ARRAY AND QUANTUM DOT SUPERLATTICE - The present invention presents a process for preparing a quantum dot array comprising at least the steps of: (a) providing a crystalline semiconductor substrate surface; (b) depositing quantum dots on the said substrate surface by a process of successive ionic layer adsorption and reaction (SILAR). The steps can be repeated to build up a quantum dot superlattice structure. | 2017-06-08 |
20170162734 | POLYESTER FILM COMPRISING AMORPHOUS POLYESTER - A photovoltaic cell comprising a transparent front-plane, an opaque back-plane and an encapsulant resin wherein said back-plane comprises a polyester film comprising a base layer (B) comprising a crystallisable polyester and a heat-sealable layer (A) comprising an amorphous copolyester wherein: (i) said amorphous copolyester is derived from an aliphatic diol and a cycloaliphatic diol and at least one aromatic dicarboxylic acid (ii) said polyester film is disposed in the photovoltaic cell such that layer (A) is in contact with the encapsulant resin. | 2017-06-08 |
20170162735 | SOLAR CELL STRUCTURE FOR WIRELESS CHARGING - A solar cell structure for wireless charging includes a substrate and at least one thin film solar cell disposed on a surface of the substrate, wherein the thin film solar cell has a winding coil structure. Accordingly, in the thin film solar cell, the electrode which is the winding coil structure may be used as electromagnetic induction coil or millimeter-wave radio wave receiving radiator. | 2017-06-08 |
20170162736 | PHOTOVOLTAIC MODULE INTERCONNECT JOINTS - Photovoltaic (PV) cells that can be interconnected with improved interconnect joints to form PV cell strings and PV modules. The improved interconnect joints comprise at least two types of adhesive bonding regions to maximize both electrical conductivity and mechanical strength of interconnect joints coupling terminals of PV cells. The disclosed approaches to PV cell interconnection provide greater manufacturing rates and higher quality PV cell strings and PV modules. | 2017-06-08 |
20170162737 | BIFACIAL PHOTOVOLTAIC MODULE - A bifacial photovoltaic module with at least one bifacial solar cell is provided. The at least one bifacial solar cell includes a substrate with a front-side and a rear-side. The front-side is the light incident side and the rear-side has rear-side contact structure. The rear-side contact structure includes a plurality of electrically conductive contact fingers, which have a first metal, a plurality of solder pads electrically connected to the contact fingers. The solder pads have a top. The solder pads have a second metal, which is different from the first metal. The rear-side contact structure further includes several cell connectors electrically connected to the solder pads. The top of the solder pads is free from the contact fingers in an area along one direction. The cell connectors are disposed planar on or above this area. | 2017-06-08 |
20170162738 | METALLIC PHOTOVOLTAICS - According to some aspects, an apparatus for converting electromagnetic radiation into electric power is provided, comprising a first layer comprising a first semiconductor material, an absorber in contact with the first layer, a second layer comprising a second semiconductor material, the second layer being in contact with the absorber, and a reflector to reflect at least a portion of electromagnetic radiation passing through the second layer. According to some aspects, a method of forming an apparatus for converting electromagnetic radiation into electric power is provided, comprising forming a reflector on a substrate, forming a first layer in contact with the reflector, the first layer comprising a first semiconductor material, forming an absorber in contact with the first layer, and forming a second layer in contact with the absorber, the second layer comprising a second semiconductor material. | 2017-06-08 |
20170162739 | INVERTED METAMORPHIC MULTIJUNCTION SOLAR CELL WITH MULTIPLE METAMORPHIC LAYERS - The disclosure describes multi-junction solar cell structures that include two or more graded interlayers. | 2017-06-08 |
20170162740 | TANDEM NANOFILM PHOTOVOLTAIC CELLS JOINED BY WAFER BONDING - An energy conversion device comprises at least two thin film photovoltaic cells fabricated separately and joined by wafer bonding. The cells are arranged in a hierarchical stack of decreasing order of their energy bandgap from top to bottom. Each of the thin film cells has a thickness in the range from about 0.5 μm to about 10 μm. The photovoltaic cell stack is mounted upon a thick substrate composed of a material selected from silicon, glass, quartz, silica, alumina, ceramic, metal, graphite, and plastic. Each of the interfaces between the cells comprises a structure selected from a tunnel junction, a heterojunction, a transparent conducting oxide, and an alloying metal grid; and the top surface and/or the lower surface of the energy conversion device may contain light-trapping means. | 2017-06-08 |
20170162741 | METHODS FOR PRODUCING PHOTOVOLTAIC MATERIAL AND DEVICE ABLE TO EXPLOIT HIGH ENERGY PHOTONS - Methods for producing photovoltaic material and a device able to exploit high energy photons. The photovoltaic material is obtained from a conventional photovoltaic material having a top surface intended to be exposed to photonic radiation, having a built-in P-N junction delimiting an emitter part and a base part and including at least one area or region specifically designed, treated or adapted to absorb high energy or energetic photons, located adjacent or near at least one hetero-interface. This material is subjected to treatments resulting in the formation of at least one semiconductor based metamaterial field or region being created, as a transitional region of the or a hetero-interface, in an area located continuous or proximate to the or an absorption area or region for the energetic photons of the photonic radiation impacting the photovoltaic material. | 2017-06-08 |
20170162742 | PACKAGED SEMICONDUCTOR DEVICES AND RELATED METHODS - A packaged semiconductor device includes a substrate, a die, at least one electrical connector, a first mold compound formed of translucent material, and a second mold compound. A first face of the die is electrically and mechanically coupled to the substrate. The at least one electrical connector electrically couples at least one electrical contact on a second face of the die with at least one conductive path of the substrate. The first mold compound formed of a translucent material at least partially encapsulates the die and the at least one electrical connector. The second mold compound at least partially encapsulates the first mold compound and forms a window through which the first mold compound is exposed. In implementations the second mold compound is opaque and the first mold compound is transparent. In implementations the substrate includes a lead frame having a die flag and a plurality of lead frame fingers. | 2017-06-08 |
20170162743 | Germanium Photodetector with SOI Doping Source - Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe. | 2017-06-08 |
20170162744 | LOW-COST SOLAR CELL METALLIZATION OVER TCO AND METHODS OF THEIR FABRICATION - Methods for fabricating busbar and finger metallization over TCO are disclosed. Rather than using expensive and relatively resistive silver paste, a high conductivity and relatively low cost copper is used. Methods for enabling the use of copper as busbar and fingers over a TCO are disclosed, providing good adhesion while preventing migration of the copper into the TCO. Also, provisions are made for easy soldering contacts to the copper busbars. | 2017-06-08 |
20170162745 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - The purpose of the present invention is to provide a semiconductor light-emitting device having good life characteristics and higher light extraction efficiency than conventional devices. This semiconductor light-emitting device includes a substrate; semiconductor layers including a first semiconductor layer, an active layer, and a second semiconductor layer; a first electrode; and a second electrode. The opposite surface of the first semiconductor layer from the active layer comprises a smooth surface portion and a roughened surface portion, the smooth surface portion is provided in a region where the first electrode is formed, the roughened surface portion is provided at least in a part of a region where the first electrode is not formed, and the second semiconductor layer and the second electrode are in contact with each other at a position outside an outer edge of the first electrode. | 2017-06-08 |
20170162746 | LIGHT-EMITTING DEVICE AND DISPLAY DEVICE INCLUDING THE SAME - A light-emitting device includes a substrate including a top surface and a first side surface, wherein an area of the top surface is larger than an area of the first side surface, and a light-emitting structure on the first side surface of the substrate, the light-emitting structure having a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer, wherein the light-emitting structure emits a first light having a first peak wavelength, and wherein an emission area of a first light emitted through the top surface of the substrate is larger than an emission area of a first light emitted through the first side surface of the substrate. | 2017-06-08 |
20170162747 | LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING ELEMENT ASSEMBLY - The light-emitting element of the present disclosure has a constant light emission intensity over a specific range of emission angle of light emitted from the center of its main light-emitting surface. | 2017-06-08 |
20170162748 | POLYHEDRON OF WHICH UPPER WIDTH IS NARROWER THAN LOWER WIDTH, MANUFACTURING METHOD THEREFOR, AND PHOTOELECTRIC CONVERSION DEVICE COMPRISING SAME - Provided are a polyhedron of which the upper width is narrower than the lower width, a manufacturing method therefor, and a photoelectric conversion device comprising the same. The photoelectric conversion device comprises: a substrate; a polyhedron disposed on the substrate and of which the upper width is narrower than the lower width; and a semiconductor layer disposed on the polyhedron. The photoelectric conversion device to which the polyhedron, of which the upper width is narrower than the lower width, is applied can have improved photoelectric conversion efficiency due to structural characteristics of the polyhedron. | 2017-06-08 |
20170162749 | OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD OF PRODUCING SAME - An optoelectronic semiconductor chip which is a light emitting diode includes a semiconductor layer sequence having an n-conducting layer sequence, a p-conducting layer sequence, an active zone, at least one etching signal layer, and an etching structure, wherein the etching structure extends at least right into the etching signal layer, the etching signal layer has a signal constituent, the active zone generates radiation and is based on InAlGaP or on InAlGaAs, the etching signal layer is situated in the p-conducting layer sequence and is based on In | 2017-06-08 |
20170162750 | TRANSPARENT ELECTRON BLOCKING HOLE TRANSPORTING LAYER - A light emitting diode includes an active region configured to emit light, a composite electrical contact layer, and a transparent electron blocking hole transport layer (TEBHTL). The composite electrical contact layer includes tow materials. At least one of the two materials is a metal configured to reflect a portion of the emitted light. The TEBHTL is arranged between the composite electrical contact layer and the active region. The TEBHTL has a thickness that extends at least a majority of a distance between the active region and the composite electrical contact layer. The TEBHTL has a band-gap greater than a band-gap of light emitting portions of the active region. The band-gap of the TEBHTL decreases as a function of distance from the active region to the composite electrical contact layer over a majority of the thickness of the TEBHTL. | 2017-06-08 |
20170162751 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device includes a semiconductor stack, including a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer; a first metal layer formed on a top surface of the second semiconductor layer; a second metal layer formed on a top surface of the first semiconductor layer; an insulative layer formed on the top surface of the first semiconductor layer and the top surface of the second semiconductor layer; wherein a space between a sidewall of the first metal layer and a sidewall of the semiconductor stack is less than 3 μm. | 2017-06-08 |
20170162752 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device includes providing a light emitting element; and forming a protective film on a surface of the light emitting element, wherein the step of forming the protective film includes: (i) providing first quantity of oxygen at the surface of the light emitting element, (ii) combining a first quantity of a first metal with the first quantity of oxygen, (iii) combining a second quantity of oxygen with the first quantity of metal, (iv) combining a first quantity of a second metal, different from the first metal, with the second quantity of oxygen and first quantity of the first metal, and (v) combining a third quantity of oxygen with the first quantity of the second metal. | 2017-06-08 |
20170162753 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor light-emitting device is provided. The semiconductor light-emitting device may include a light-emitting structure, an electrode, an ohmic layer, an electrode layer, an adhesion layer, and a channel layer. The light-emitting structure include a compound semiconductor layer. The electrode may be disposed on the light-emitting structure. The ohmic layer may be disposed under the light-emitting structure. The electrode layer may include a reflective metal under the ohmic layer. The adhesion layer may be disposed under the electrode layer. The channel layer may be disposed along a bottom edge of the light-emitting structure. | 2017-06-08 |
20170162754 | CHIP SUBSTRATE - A chip substrate includes conductive layers, an insulation layer configured to electrically isolate the conductive layers, and a cavity composed of a groove formed at a predetermined depth in a region including the insulation layer. One side of the cavity includes a first surface and a second surface continuously extending from the first surface, the first surface is formed to vertically extend from a lower portion of the cavity and the second surface is formed so as to have the same slope as the other side of the cavity, whereby the distance between one side of the lower portion of the cavity and the insulation layer is increased. | 2017-06-08 |
20170162755 | PACKAGE SUBSTRATE AND LED FLIP CHIP PACKAGE STRUCTURE - A package substrate includes: an insulating substrate, a first and a second soldering pads spacedly disposed on a first surface of the insulating substrate, a first and a second electrodes spacedly disposed on an opposite second surface of the insulting substrate. The first and the second soldering pads are electrically connected to the first and the second electrodes respectively. Moreover, a first and a second grooves are defined on the first surface of the insulating substrate, the first and the second grooves are spaced from each other and disposed between the first and the second soldering pads. The invention further provides a LED flip chip package structure including the package substrate, a LED flip chip and fluorescent glue. The invention adds the grooves in the spacing between the soldering pads as a buffer space for melted solder flowing during reflow soldering process and therefore can relieve short-circuit phenomenon. | 2017-06-08 |
20170162756 | Quantum Dot Based Color Conversion Layer in Display Devices - Embodiments of a display device including barrier layer coated quantum dots and a method of making the barrier layer coated quantum dots are described. Each of the barrier layer coated quantum dots includes a core-shell structure and a hydrophobic barrier layer disposed on the core-shell structure. The hydrophobic barrier layer is configured to provide a distance between the core-shell structure of one of the quantum dots with the core-shell structures of other quantum dots that are in substantial contact with the one of the quantum dots. The method for making the barrier layer coated quantum dots includes forming reverse micro-micelles using surfactants and incorporating quantum dots into the reverse micro-micelles. The method further includes individually coating the incorporated quantum dots with a barrier layer and isolating the barrier layer coated quantum dots with the surfactants of the reverse micro-micelles disposed on the barrier layer. | 2017-06-08 |
20170162757 | METHOD FOR IMPROVING DEFECT-FREE RATE OF LED LIGHT SOURCE, PHOSPHOR POWDER, AND LED LIGHT SOURCE - A method for improving optical performance of an LED light source, a light conversion filter obtained by using the method, and the corresponding LED light source. In the method, an LED chip is packaged by using a light wavelength conversion component, and the light wavelength conversion component is at least provided with two types of light conversion filters with light excitation performance. With the excitation of light rays that are sent by the LED chip and have wavelengths in an ascending order, sent light rays show an opposite change tendency in light intensities of light rays after the light rays are converted by the two types of light conversion filters. The method can reduce the discrete degree of chroma distribution of light transmitted by the LED light source, and improve the defect-free rate of the LED light source. | 2017-06-08 |
20170162758 | LED BASED DEVICE WITH WIDE COLOR GAMUT - The invention provides a lighting unit comprising a source of blue light, a source of green light, a first source of red light comprising a first red luminescent material, configured to provide red light with a broad band spectral light distribution, and a second source of red light comprising a second red luminescent material, configured to provide red light with a spectral light distribution comprising one or more red emission lines. Especially, the first red luminescent material comprises (Mg,Ca,Sr)AlSiN | 2017-06-08 |
20170162759 | LIGHT EMITTING DEVICE, ILLUMINATION DEVICE AND LIQUID CRYSTAL TELEVISION - A light emitting device which emits a secondary light with high color purity and has a fast response speed is obtained. A KSF phosphor ( | 2017-06-08 |
20170162760 | LIGHT-EMITTING DEVICE HAVING SURFACE-MODIFIED LUMINOPHORES - A light-emitting device including a substrate, a first light-emitting diode disposed on the substrate, a molding member encapsulating the first light-emitting diode, and luminophores dispersed in the molding member and including a surface-modified luminophore, in which the surface-modified luminophore includes a fluorinated coating and a fluoride luminophore including a manganese activator. The fluoride luminophore is selected from the group consisting of K | 2017-06-08 |
20170162761 | LIGHT EMITTING DEVICE WITH NANOSTRUCTURED PHOSPHOR - Embodiments of the invention include a light emitting device, a first wavelength converting material, and a second wavelength converting material. The first wavelength converting material includes a nanostructured wavelength converting material. The nanostructured wavelength converting material includes particles having at least one dimension that is no more than 100 nm in length. The first wavelength converting material is spaced apart from the light emitting device. | 2017-06-08 |
20170162762 | ENCAPSULANT MODIFICATION IN HEAVILY PHOSPHOR LOADED LED PACKAGES FOR IMPROVED STABILITY - Heavily phosphor loaded LED packages having higher stability and a method for increasing the stability of heavily phosphor loaded LED packages. The silicone content of the packages is increased by decreasing the amount of one phosphor of the blend or by increasing the thickness of the silicone phosphor blend layer. | 2017-06-08 |
20170162763 | LIGHT-EMITTING DEVICE - A light-emitting device includes a light-emitting element, a cover layer, and an anti-adhesion layer. The light-emitting element has a top surface, a bottom surface and a first side surface. The cover layer covers the light-emitting element and includes a first transparent binder and a plurality of wavelength conversion particles dispersed within the first transparent binder. The anti-adhesion layer includes a fluoro-containing material, and is disposed on the cover layer and the top surface. | 2017-06-08 |
20170162764 | Quantum Dot Encapsulation Techniques - Quantum dots and methods of making quantum dots are described. A method begins with forming quantum dots having a core-shell structure with a plurality of ligands on the shell structure. The method includes exchanging the plurality of ligands with a plurality of second ligands. The plurality of second ligands have a weaker binding affinity to the shell structure than the plurality of first ligands. The plurality of second ligands are then exchanged with hydrolyzed alkoxysilane to form a monolayer of hydrolyzed alkoxysilane on a surface of the shell structure. The method includes forming a barrier layer around the shell structure by using the hydrolyzed alkoxysilane as a nucleation center. | 2017-06-08 |
20170162765 | LIGHT EMITTING DEVICE - A light emitting device includes a base substrate having a recessed portion at a flat upper surface thereof. The recessed portion has an inner wall. A sealing member is provided in the recessed portion. The sealing member contains surface-treated particles, or particles coexisting with a dispersing agent. The particles have a particle diameter of 1 nm or more and 100 μm or less. The particles are made of an organic material or an inorganic material. The organic material and the inorganic material are free of a phosphor. The at least a part of an edge portion of the sealing member is a region located in the vicinity of an edge of the recessed portion which is a boundary between a surface of the inner wall and the flat upper surface. The at least one of the particles and aggregates of particles are unevenly distributed in the region. | 2017-06-08 |
20170162766 | METHOD FOR PRODUCING LIGHT EMITTING DEVICE - A method for producing a light emitting device includes spraying a resin mixture onto a light emitting element using a pulse spraying method to deposit the resin mixture on the light emitting element. The resin mixture includes a thixotropy imparting agent. The resin mixture is cured to form a light transmissive member via which light emitted from the light emitting element is to transmit to an outside of the light emitting device. | 2017-06-08 |
20170162767 | PACKAGE STRUCTURE OF AN ULTRAVIOLET LIGHT EMITTING DIODE - A package structure of an ultraviolet light emitting diode is provided, which includes a substrate, a transparent body, at least one ultraviolet light emitting diode, a connecting element and an ultraviolet shielding layer. The transparent body is disposed on the substrate. The transparent body has a space inside thereof. The at least one ultraviolet light emitting diode is disposed on the substrate and inside the space. The connecting element is disposed between the substrate and the transparent body. The ultraviolet shielding layer is disposed between the transparent body and the connecting element. | 2017-06-08 |
20170162768 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting device includes a semiconductor light-emitting element having a first electrode and a second electrode, a transparent layer covering the semiconductor light-emitting element, a stretchable electrical connection structure and an electrical contact portion. The stretchable electrical connection structure is formed in the transparent layer and electrically connects the first electrode, and the electrical contact portion is formed on the transparent layer and electrically connects the second electrode. | 2017-06-08 |
20170162769 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR PRODUCING SAME, AND DISPLAY DEVICE - A semiconductor light-emitting device ( | 2017-06-08 |
20170162770 | PACKAGE, LIGHT EMITTING DEVICE, AND METHODS OF MANUFACTURING THE PACKAGE AND THE LIGHT EMITTING DEVICE - A package for mounting a light emitting element includes a recess; a pair of lead electrodes exposed at a bottom surface of the recess; a plating layer covering a surface of each of the pair of lead electrodes; and a resin molded body retaining the pair of lead electrodes, and forming an area between the pair of lead electrodes at the bottom surface of the recess and a lateral surface of the recess. At least one of the lead electrodes has a front surface protrusion that is linearly formed along the resin molded body at the bottom surface of the recess and along a periphery of the bottom surface of the recess, and a back surface protrusion that is formed at a position at a back surface opposite to a position of the front surface protrusion, and at least a tip of each of the front surface protrusion and the back surface protrusion is exposed outside the plating layer. | 2017-06-08 |
20170162771 | CARRIER, CARRIER LEADFRAME, AND LIGHT EMITTING DEVICE - A carrier leadframe, including a frame body and a carrier, is provided. The frame body includes at least one supporting portion, and the carrier includes a shell and at least one electrode portion and is mechanically engaged with the frame body via the supporting portion. A method for manufacturing the carrier leadframe as described above, as well as a light emitting device made from the carrier leadframe and a method for manufacturing the device, are also provided. The carrier leadframe has carriers that are separate in advance and mechanically engaged with the frame body, thereby facilitating the quick release of material after encapsulation. Besides, in the carrier leadframe as provided, each carrier is electrically isolated from another carrier, so the electric measurement can be performed before the release of material. Therefore, the speed and yield of production of the light emitting device made from the carrier leadframe is improved. | 2017-06-08 |
20170162772 | HEAT-DISSIPATION DEVICE OF LED - Disclosed is a heat-dissipation device of an LED. The device comprises one or a plurality of heat conducting material silks; a heat-dissipation housing of an LED chip is contacted with one end of the heat conducting material silks through heat conducting materials or in a direct manner, in order to transmit the heat to the heat conducting material silks and heat the surrounding air through the heat conducting material silks; the heat conducting material silks are arranged in an air flowing pipeline, and the heat is taken away by the flowing air; the pipeline is made of insulation materials. The weight and size of the heat-dissipation device of the LED can be reduced exponentially under the condition that a proper working temperature for the LED chip is ensured, and the ground insulation of the whole heat-dissipation device can be ensured. | 2017-06-08 |