23rd week of 2017 patent applcation highlights part 64 |
Patent application number | Title | Published |
20170162573 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, and a dielectric layer. The MOS transistor includes a gate structure formed over the substrate. The dielectric layer is formed aside the gate structure, and the dielectric layer is doped with a strain modulator. A lattice constant of the strain modulator is larger than a lattice constant of an atom of the dielectric layer. | 2017-06-08 |
20170162574 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type impurities. A stress may be applied onto a channel region of a transistor, so that the semiconductor device may have good electrical characteristics. | 2017-06-08 |
20170162575 | HIGH-K METAL GATE TRANSISTOR STRUCTURE AND FABRICATION METHOD THEREOF - The present disclosure provides HKMG transistor structures and fabrication methods thereof. An exemplary method includes providing a base substrate having a first region and a second region; forming a dielectric layer having a first opening in the first region and a second opening in the second region over; forming a gate dielectric layer on a side surface of the first opening and a portion of the base substrate in the first opening and on a side surface of the second opening and a portion of the base substrate in the second opening; filling a sacrificial layer in the first opening; forming a second work function layer in the second opening and a second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming a first work function layer in the first opening and a first gate electrode layer on the first work function layer. | 2017-06-08 |
20170162576 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain. | 2017-06-08 |
20170162577 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode. | 2017-06-08 |
20170162578 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The inventive concepts provide methods of manufacturing a semiconductor device. The method includes forming a thin layer structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming a through-hole penetrating the thin layer structure and exposing the substrate, forming a semiconductor layer covering an inner sidewall of the through-hole and partially filling the through-hole, oxidizing a first portion of the semiconductor layer to form a first insulating layer, and injecting oxygen atoms into a second portion of the semiconductor layer. An oxygen atomic concentration of the second portion is lower than that of the first insulating layer. Oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time. | 2017-06-08 |
20170162579 | MULTI BIT CAPACITORLESS DRAM AND MANUFACTURING METHOD THEREOF - A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap. | 2017-06-08 |
20170162580 | METHOD FOR MANUFACTURING STATIC RANDOM ACCESS MEMORY DEVICE - In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars. | 2017-06-08 |
20170162581 | METHOD FOR FABRICATING A LOCAL INTERCONNECT IN A SEMICONDUCTOR DEVICE - A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region. | 2017-06-08 |
20170162582 | METHOD AND STRUCTURE TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES - A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of exposed fin ends. A set of sidewall spacers are formed on the set of exposed fin ends, forming a set of spacer covered fin ends. The set of sidewall spacers prevent epitaxial growth at the set of spacer covered fin ends. A semiconductor device includes a set of fin structures having a set of fin ends. A set of inhibitory layers are disposed at the set of fin ends to inhibit excessive epitaxial growth at the fin ends. | 2017-06-08 |
20170162583 | STATIC RANDOM ACCESS MEMORY (SRAM) DEVICE FOR IMPROVING ELECTRICAL CHARACTERISTICS AND LOGIC DEVICE INCLUDING THE SAME - A static random access memory (SRAM) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer transistor is connected to the output node of the first inverter, and a second transfer transistor is connected to the output nodes of the second inverter. Each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having multi-bridge channels. At least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having a different number of multi-bridge channels from the other transistors. | 2017-06-08 |
20170162584 | METHOD TO PREVENT LATERAL EPITAXIAL GROWTH IN SEMICONDUCTOR DEVICES - The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure, the set of fins having respective cut faces of a set of cut faces located at respective fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends of the set of fins of the FinFET structure. The photoresist pattern over the set of fin ends differs from the photoresist pattern over other areas of the FinFET structure as the photoresist pattern over the set of fin ends protects the first dielectric material at the set of fin ends. A set of dielectric blocks is formed at the set of fin ends, wherein each of the dielectric blocks covers at least one cut face. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step. | 2017-06-08 |
20170162585 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device including: a first layer including a first monocrystalline layer, the first layer including first logic cells; a second layer including a monocrystalline semiconductor layer, the second layer overlying the first layer, the second layer including second transistors, where the logic cells include a Look-Up-Table logic cell, and where the second transistors are aligned to the first logic cells with less than 200 nm alignment error. | 2017-06-08 |
20170162586 | SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE - A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction it spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed. | 2017-06-08 |
20170162587 | Ferroelectric Capacitor, Ferroelectric Field Effect Transistor, And Method Used In Forming An Electronic Component Comprising Conductive Material And Ferroelectric Material - A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×10 | 2017-06-08 |
20170162588 | SEMICONDUCTOR NONVOLATILE MEMORY ELEMENT AND MANUFACTURING METHOD THEREOF - A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile memory element includes a control gate electrode, a floating gate electrode, source/drain terminals, a thin first gate insulating film, and a second gate insulating film that is thick enough not to be broken down even when a voltage higher than an operating voltage of the semiconductor integrated circuit device is applied thereto, the first and second gate insulating films being formed below the control gate electrode. Thus, provided is a normally on type semiconductor nonvolatile memory element in which a threshold voltage can be regulated through injection of a large amount of charge with respect to the operating voltage from a drain terminal into the floating gate electrode via the second gate insulating film, and injected carriers do not leak in an operating voltage range. | 2017-06-08 |
20170162589 | Transistors, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string. | 2017-06-08 |
20170162590 | Si RECESS METHOD IN HKMG REPLACEMENT GATE TECHNOLOGY - The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar. | 2017-06-08 |
20170162591 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first source seed layer, a second source seed layer disposed over the first source seed layer while being spaced apart from the first source seed layer, a stacked structure formed on the second source seed layer, channel layers extending inside the first source seed layer by penetrating the stacked structure, and an interlayer source layer extending into a space between the first source seed layer and the second source seed layer while contacting each of the channel layers, the first source seed layer, and the second source seed layer. | 2017-06-08 |
20170162592 | VERTICAL RESISTOR IN 3D MEMORY DEVICE WITH TWO-TIER STACK - A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack. | 2017-06-08 |
20170162593 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a substrate; a stacked body; a columnar portion; and a plate portion. The substrate has a major surface. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion includes a semiconductor body and a memory film. The memory film includes a charge storage portion. The plate portion is provided in the stacked body. The plate portion extends along the stacking direction of the stacked body and a major surface direction of the substrate. The plate portion includes a plate conductor and a sidewall insulating film. The sidewall insulating film provided between the plate conductor and the stacked body. The stacked body includes an air gap. The air gap is provided between the sidewall insulating film and the electrode layer. | 2017-06-08 |
20170162594 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit. | 2017-06-08 |
20170162595 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a stacked body, a memory cell array, and a columnar portion. The stacked body is provided on a major surface of a substrate. The stacked body includes a plurality of electrode layers stacked with an insulating body interposed. The memory cell array is provided inside the stacked body. The columnar portion is provided inside the memory cell array. The columnar portion extends along a stacking direction of the stacked body. The columnar portion includes a semiconductor body and a memory film. The memory film includes a charge storage portion. The substrate includes a first contact portion contacting the semiconductor body. A configuration of the first contact portion is convex along the stacking direction. | 2017-06-08 |
20170162596 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film. | 2017-06-08 |
20170162597 | DIFFERENTIAL ETCH OF METAL OXIDE BLOCKING DIELECTRIC LAYER FOR THREE-DIMENSIONAL MEMORY DEVICES - A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion. | 2017-06-08 |
20170162598 | DISPLAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE - A display substrate, a method for fabricating the same, and a display device are disclosed. The display substrate comprises a plurality of pixels; and a plurality of slit patterns, which are arranged between at least two of the plurality of pixels, and comprise a plurality of slits arranged in a rubbing direction. Slit patterns are provided, and each of slit patterns comprises slits in the rubbing direction. Thus, during a rubbing alignment process, the slit patterns can guide a rubbing cloth to move in the rubbing direction. Accordingly, the alignment of the rubbing cloth is prevented from changing in the rubbing process, a good alignment layer is formed, rubbing Mura is avoided, and the lifetime of the rubbing cloth is extended. | 2017-06-08 |
20170162599 | TRANSISTOR SUBSTRATE AND DISPLAY DEVICE - A transistor substrate includes a plurality of first transistors formed between a power supply wire and a first conductive wire, and a plurality of second transistors formed between the power supply wire and a second conductive wire. A length of a portion of the power supply wire between the plurality of second transistors and a drive signal generation circuit is longer than a length of a portion of the power supply wire between the plurality of first transistors and the drive signal generation circuit, and a total sum of channel widths of second channels included in the plurality of second transistors is wider than a total sum of channel widths of first channels included in the plurality of first transistors. | 2017-06-08 |
20170162600 | MANUFACTURING METHODS OF FLEXIBLE DISPLAY PANELS, FLEXIBLE GLASS SUBSTRATES, AND FLEXIBLE DISPLAY PANELS - A manufacturing method of flexible display panels, a flexible glass substrate, and a flexible display panel are disclosed. The manufacturing method of the flexible display panel includes: forming a TFT layer at one side of a flexible glass substrate; forming a polymer enhanced layer at the other side of the flexible glass substrate; curing the polymer enhanced layer; forming a display layer on the TFT layer; and forming an encapsulation layer on the side of the flexible glass substrate where the TFT layer is located. With such configuration, the compressive strength of the flexible glass substrate is enhanced so as to enhance the quality of products. | 2017-06-08 |
20170162601 | GAS BARRIER LAMINATE, SEMICONDUCTOR DEVICE, DISPLAY ELEMENT, DISPLAY DEVICE, AND SYSTEM - A gas barrier laminate includes a substrate and a barrier layer formed on at least one of faces of the substrate. The barrier layer includes composite oxide including silicon and alkaline-earth metal. | 2017-06-08 |
20170162602 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 2017-06-08 |
20170162603 | Semiconductor Device - A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween. | 2017-06-08 |
20170162604 | Thin Film Transistor and Manufacturing Method Thereof, Array Substrate and Display Device - A thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The method includes forming a gate electrode, a gate insulating layer, a metal oxide semiconductor (MOS) active layer, a source electrode and a drain electrode on a substrate. The MOS active layer includes forming a pattern layer of indium oxide series binary metal oxide including a first pattern directly contacting with the source electrode and the drain electrode. An insulating layer formed over the source electrode and the drain electrode acts as a protection layer, the pattern layer of indium oxide series binary metal oxide is implanted with metal doping ions by using an ion implanting process, and is annealed, so that the indium oxide series binary metal oxide of the third pattern is converted into the indium oxide series multiple metal oxide to form the MOS active layer. | 2017-06-08 |
20170162605 | DISPLAY DEVICE - To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension. | 2017-06-08 |
20170162606 | DISPLAY DEVICE - A display device is provided, which includes a substrate structure containing a substrate with a pixel region, and the pixel region includes an aperture region. A metal oxide semiconductor transistor is disposed over the substrate and includes a metal oxide semiconductor layer with a first channel region, a first gate electrode corresponding to the first channel region, and a silicon oxide insulating layer on the metal oxide semiconductor layer. The silicon oxide insulating layer includes an opening corresponding to the aperture region. A polysilicon transistor is disposed over the substrate. The display device also includes an opposite substrate structure, and a display medium between the substrate structure and the opposite substrate structure. | 2017-06-08 |
20170162607 | METHOD FOR MANUFACTURING ACTIVE-MATRIX DISPLAY PANEL, AND ACTIVE-MATRIX DISPLAY PANEL - Manufacturing method including forming, over substrate, TFT layer, planarization layer, and display element in this order. Forming of TFT layer involves forming passivation layer to cover TFT layer electrode, such as upper electrode, and to come in contact with planarizing layer. Forming of display element involves forming bottom electrode to come in contact with planarizing layer. TFT layer electrode and bottom electrode are connected by: first forming, in planarizing layer, first contact hole exposing passivation layer at bottom thereof; then forming second contact hole exposing TFT layer electrode at bottom thereof through dry-etching passivation layer exposed at bottom of first contact hole using fluorine-containing gas; then forming liquid repellent film containing fluorine on passivation layer inner surface facing second contact hole; and forming bottom electrode along planarizing layer inner surface and passivation layer inner surface respectively facing first contact hole and second contact hole. | 2017-06-08 |
20170162608 | LIQUID CRYSTAL DISPLAY DEVICE, EL DISPLAY DEVICE, AND MANUFACTURING METHOD THEREOF - A display device is manufactured with five photolithography steps: a step of forming a gate electrode, a step of forming a protective layer for reducing damage due to an etching step or the like, a step of forming a source electrode and a drain electrode, a step of forming a contact hole, and a step of forming a pixel electrode. The display device includes a groove portion which is formed in the step of forming the contact hole and separates the semiconductor layer. | 2017-06-08 |
20170162609 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A display panel includes a first substrate, a second substrate and a display medium layer disposed between the first and second substrates. The first substrate includes a plurality of first conducive lines, a plurality of second conducive lines, and a plurality of transistors to define pixel regions. At least one of the transistors includes a gate electrode, a first insulating layer on the gate electrode, an active layer on the first insulating layer, a first electrode and a second electrode on the active layer. The first electrode includes a first transparent conductive material layer and a second transparent conductive material layer formed on the first transparent conductive material layer. The second conducive line connected to the first electrode includes the first and second transparent conductive material layers and a metal layer disposed between the first and second transparent conductive material layers. | 2017-06-08 |
20170162610 | METHOD FOR MANUFACTURING LTPS TFT SUBSTRATE STRUCTURE AND STRUCTURE OF LTPS TFT SUBSTRATE - The present invention provides a method for manufacturing an LTPS TFT substrate structure and a structure of an LTPS TFT substrate. The method for manufacturing the LTPS TFT substrate structure according to the present invention provides patterns of a thermally conductive electrical-insulation layer that are of the same size and regularly distributed under a buffer layer of a driving TFT area to absorb heat in a subsequent excimer laser annealing process so as to speed up the cooling rate of amorphous silicon to form crystal nuclei that gradually grow up in the annealing process. Since the thermally conductive electrical-insulation layer is made up of regularly distributed and size-consistent patterns, crystal grains of a polycrystalline silicon layer located in the driving TFT area show improved consistency and homogeneity and the grain sizes are relatively large to ensure the consistency of electrical property of the driving TFT. The structure of the LTPS TFT substrate structure according to the present invention includes patterns of a thermally conductive electrical-insulation layer that are regularly distributed under a buffer layer of a driving TFT area and have the same size, so that crystal grains of a polycrystalline silicon layer located in the driving TFT area show improved consistency and homogeneity and the grain sizes are relatively large and thus, the electrical property of the driving TFT is consistent. | 2017-06-08 |
20170162611 | MANUFACTURE METHOD OF OXIDE SEMICONDUCTOR TFT SUBSTRATE AND STRUCTURE THEREOF - The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The method continuously forms the gate isolation layer ( | 2017-06-08 |
20170162612 | Preparation Method of Oxide Thin-Film Transistor - A preparation method of an oxide thin-film transistor is disclosed, and this method includes: forming a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode; forming of the active layer, the source electrode and the drain electrode includes: sequentially forming an oxide semiconductor thin film and a source-drain electrode metal thin film on a base substrate, an entire surface of the oxide semiconductor thin film being in direct contact with the source-drain electrode metal thin film; and patterning the oxide semiconductor thin film and the source-drain electrode metal thin film with a dual-tone mask so as to form the active layer, the source electrode and the drain electrode by a single patterning process. | 2017-06-08 |
20170162613 | PHOTODETECTOR-ARRAYS AND METHODS OF FABRICATION THEREOF - A photodetector-array and fabrication method thereof are disclosed. The photodetector-array includes a first and second semiconductor structures having respective active regions defining respective pluralities of active photodetectors and active readout integrated circuit pixels (RICPs) electronically connectable to one another respectively. The first and second semiconductor structures are made with different semiconductor materials/compositions having different first and second coefficients of thermal expansion (CTEs) respectively. The pitch distances of the active photodetectors and the pitch distances of the respective active RICPs are configured in accordance with the difference between the first and second CTEs, such that at high temperatures, at which electrical coupling between the first and second semiconductor structures is performed, the electric contacts of the active photodetectors and of their respective RICPs overlap. Accordingly, after the first and second semiconductor structures are bonded together, at least 99.5% of the active photodetector are electrically connected with their respective RICPs. | 2017-06-08 |
20170162614 | DETECTOR MODULE FOR AN IMAGING SYSTEM - A detector module for detecting photons includes a detector formed from a semiconductive material, the detector having a first surface, an opposing second surface, and a plurality of sidewalls extending between the first and second surfaces, and a guard band coupled to the sidewalls, the guard band having a length that extends about a circumference of the detector, the guard band having a width that is greater than a thickness of the detector such that an upper rim segment of the guard band projects beyond the first surface of the detector, the upper rim segment being folded over a peripheral region of the first surface along the circumference of the detector, the guard band configured to reduce recombinations proximate to the edges of the detector. | 2017-06-08 |
20170162615 | IMAGE PICKUP APPARATUS HAVING PHOTOELECTRIC CONVERSION FUNCTION - An image pickup apparatus that makes it possible to achieve both high picture quality and a wide dynamic range is provided. Each pixel unit included in the image pickup apparatus includes: four photodiodes; four transfer transistors; a charge storage portion (four floating diffusions) for storing electric charges generated at the photodiodes; an amplification transistor; a select transistor; and a reset transistor. The image pickup apparatus further includes multiple coupling transistors. Each coupling transistor couples together the charge storage portions of two pixel units of the pixel units. A scanning circuit switches on or off the coupling transistors according to read mode. | 2017-06-08 |
20170162616 | IMAGE PICKUP DEVICE AND IMAGE PICKUP SYSTEM - An image pickup device according to an embodiment includes a substrate on which a plurality of pixel circuits are disposed, a semiconductor layer disposed on the substrate, a first electrode disposed on the semiconductor layer, and a second electrode disposed between the semiconductor layer and the substrate. A continuous portion of the semiconductor layer includes a light receiving region disposed between the first electrode and the second electrode and a charge hold region different from the light receiving region. | 2017-06-08 |
20170162617 | IMAGING APPARATUS AND IMAGING SYSTEM - An imaging apparatus according to the present invention includes a substrate including a plurality of pixel circuits arranged thereon and a semiconductor layer disposed on the substrate. Each of the plurality of pixel circuits includes an amplification transistor configured to output a signal based on charge generated in the semiconductor layer. The charge generated in the semiconductor layer is transferred in a first direction parallel to a surface of the substrate. | 2017-06-08 |
20170162618 | IMAGING ELEMENT, ELECTRONIC DEVICE, AND INFORMATION PROCESSING DEVICE - The present disclosure relates to an imaging element, an electronic device, and an information processing device capable of more easily providing a wider variety of photoelectric conversion outputs. | 2017-06-08 |
20170162619 | IMAGING DEVICE - A device that includes an analog-to-digital converter circuit and a control circuit is disclosed. The analog-to-digital converter circuit converts at least one of analog pixel output signals from a pixel array, to at least one of digital signals. The analog-to-digital converter circuit includes a comparator which generates a comparator output signal for operatively enabling and disabling, in accordance with a reference signal and an analog pixel output signal from the pixel array, a counter generating a digital signal. The control circuit disables, in accordance with the comparator output signal, the comparator. | 2017-06-08 |
20170162620 | FINGERPRINT RECOGNITION CHIP PACKAGING STRUCTURE AND PACKAGING METHOD - A packaging structure and a packaging method for a fingerprint identification chip are provided. The packaging structure includes a substrate, a sensing chip, a wire and a plastic encapsulation layer. The substrate is provided with a first solder pad layer. The sensing chip has a first surface and a second surface opposite to the first surface, the first surface comprises a sensing area and a peripheral area surrounding the sensing area, and the surface of the sensing chip in the peripheral area is provided with a second solder pad layer. Two ends of the wire are electrically connected to the first solder pad layer and the second solder pad layer respectively. The plastic encapsulation layer is made of a polymer, the plastic encapsulation layer surrounds the wire and the sensing chip. | 2017-06-08 |
20170162621 | LIGHT CHANNELS WITH MULTI-STEP ETCH - An image sensor includes a plurality of photodiodes disposed in a semiconductor layer, a first isolation layer, and a dielectric filler. The dielectric filler is disposed in a trench in the first isolation layer, and the first isolation layer is disposed between the semiconductor layer and the dielectric filler. At least one additional isolation layer is disposed proximate to the first isolation layer, and a plurality of light channels in the at least one additional isolation layer extend through the at least one additional isolation layer to the dielectric filler. The plurality of light channels is disposed to direct light into the plurality of photodiodes. | 2017-06-08 |
20170162622 | Backside Structure and Methods for BSI Image Sensors - BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer. | 2017-06-08 |
20170162623 | PHOTOELECTRIC CONVERSION APPARATUS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a photoelectric conversion apparatus includes forming a first semiconductor region of a first conductivity type in a trench provided in a semiconductor substrate, forming an insulating member on the semiconductor substrate, and forming a second semiconductor region of a second conductivity type that forms a photoelectric conversion portion. The first semiconductor region is present between the second semiconductor region and the insulating member in a direction perpendicular to a depth direction of the semiconductor substrate. | 2017-06-08 |
20170162624 | SOLID-STATE IMAGE PICKUP DEVICE, MANUFACTURING METHOD, AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state image pickup device, a manufacturing method, and an electronic apparatus, which can obtain high charge transfer efficiency from a photoelectric conversion unit to a floating diffusion layer. The floating diffusion layer is arranged in a rectangular shape so as to surround a gate electrode of a vertical transistor whose groove portion is rectangular. A reset drain is formed so as to be adjacent to the floating diffusion layer through a reset gate. A potential of the floating diffusion layer is reset to the same potential as that of the reset drain by applying a predetermined voltage to the reset gate. It is possible to apply the present disclosure to, for example, a CMOS solid-state image pickup device used in an image pickup device such as a camera. | 2017-06-08 |
20170162625 | SOLID-STATE IMAGING DEVICE, METHOD FOR PRODUCING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - This solid-state imaging device | 2017-06-08 |
20170162626 | ENCAPSULATION OF MAGNETIC TUNNEL JUNCTION STRUCTURES IN ORGANIC PHOTOPATTERNABLE DIELECTRIC MATERIAL - Methods and devices are provided to construct magnetic devices, such as magnetic random access memory devices, having MTJ (magnetic tunnel junction) structures encapsulated in organic photopatternable dielectric material. For example, a method includes forming an MTJ structure on a semiconductor substrate, encapsulating the MTJ structure in a layer of organic photopatternable dielectric material, patterning the layer of organic photopatternable dielectric material to form a contact opening in the layer of organic photopatternable dielectric material to the MTJ structure, and filling the contact opening with metallic material. | 2017-06-08 |
20170162627 | METHOD FOR PRODUCING A RESISTIVE MEMORY CELL - A method for manufacturing a memory cell includes forming a stack of layers comprising a first electrode and a dielectric layer, and forming a second electrode. Forming the second electrode includes depositing the second electrode on the dielectric layer, and defining the contour of the second electrode in such a way that the second electrode forms a protruding element above the dielectric layer having inclined flanks, the angle between the flanks of the second electrode forming an acute angle with the plane wherein the dielectric layer mainly extends. | 2017-06-08 |
20170162628 | ULTRALOW POWER CARBON NANOTUBE LOGIC CIRCUITS AND METHOD OF MAKING SAME - A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage. | 2017-06-08 |
20170162629 | DISPLAY SUBSTRATE, MANUFACTURING METHOD AND DRIVING METHOD THEREOF, AND DISPLAY DEVICE - A display substrate, a manufacturing method and a driving method thereof, and a display device are provided. The display substrate includes a substrate, a gate layer disposed on the substrate, a gate insulating layer disposed on the gate layer, a pixel defining layer disposed on the gate insulating layer, the pixel defining layer includes a plurality of defining regions, a light emitting layer in the defining regions of the pixel defining layer disposed on the gate insulating layer, wherein the light emitting layer includes an electron excitation layer, a light excitation layer and a hole excitation layer, and a source/drain layer disposed on the light emitting layer. According to an embodiment of the present disclosure, light emission and control of light emission can be realized merely by a three-layer structure of a gate layer, a light emitting layer and a source/drain layer, and compared with the OLED light emitting structure of the prior art, the layer structure is simpler, the light emitted is less blocked, and luminous efficiency is higher. | 2017-06-08 |
20170162630 | Light-Emitting Device - There is provided a light emitting device which enables a color display with good color balance. A triplet compound is used for a light emitting layer of an EL element that emits red color, and a singlet compound is used for a light emitting layer of an EL element that emits green color and a light emitting layer of an EL element that emits blue color. Thus, an operation voltage of the EL element emitting red color may be made the same as the EL element emitting green color and the EL element emitting blue color. Accordingly, the color display with good color balance can be realized. | 2017-06-08 |
20170162631 | ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL, ELECTRONIC DEVICE AND MANUFACTURING METHOD - The present disclosure provides an OLED display panel, an electronic device, and a manufacturing method. The OLED display panel comprises a substrate, and a plurality of pixel regions formed on the substrate to emit light of different colors. A pixel region includes a first electrode, a light-emitting function layer, and a second electrode, configured facing away from the substrate. The second electrode is a light-emitting side electrode of the OLED display panel. Differences in transmittances at different wavelengths of the second electrode satisfy the following equations: |T(450 nm)−T(530 nm)|≦15%, |T(610 nm)−T(530 nm)|≦15%, and |T(400 nm)−T(700 nm)|≦50%, where T(Xnm) is a transmittance at a wavelength of Xnm of the second electrode. | 2017-06-08 |
20170162632 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode display device can include a display panel including a plurality of pixels, at least one pixel among the plurality of pixels including first to fourth sub-pixels defined at intersection regions between gate lines and data lines; and first to third color filter layers corresponding to the first sub-pixel, the third sub-pixel and the fourth sub-pixel, respectively; the second sub-pixel includes: an emission area, and first and second color filter patterns disposed in the second sub-pixel configured to absorb light incident from an outside of the organic light emitting diode display device, the first color filter pattern and a second color filter pattern are different colors; and the first color filter pattern or the second color filter pattern has a first gap between an edge of the first or second color filter pattern and an edge of the emission area. | 2017-06-08 |
20170162633 | ORGANIC LIGHT EMITTING DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - An exemplary embodiment discloses an organic light emitting display panel including a base substrate comprising first pixels configured to emit a light having a first wavelength and second pixels configured to emit a light having a second wavelength and a pixel definition layer disposed on the base substrate. The pixel definition layer includes first and second openings. The first opening corresponds to light emitting areas of n (n is a natural number equal to or greater than 2) first pixels among the first pixels. The second opening corresponds to light emitting areas of m (m is a natural number equal to or greater than 1 and smaller than n) second pixels among the second pixels. An area of the light emitting area of each of the first pixels is smaller than an area of the light emitting area of each of the second pixels. | 2017-06-08 |
20170162634 | OLED Display Device And Display Apparatus Including The Same - An OLED display device includes a substrate and an OLED display units formed on the substrate, in which n is an integer which is greater than 1. The OLED display unit comprises: a first electrode, a first functional layer, a second electrode, a second functional layer, and a first light-emitting layer and a second light-emitting layer disposed between the first functional layer and the second functional layer; the first functional layer is disposed above the first electrode and the second functional layer is disposed below the second electrode, or, the first functional layer is disposed below the first electrode and the second functional layer is disposed above the second electrode. Wherein, the first light-emitting layer and the second light-emitting layer are disposed side by side in a horizontal direction, and, each of the light-emitting layers corresponds to at least two sub-pixels in the OLED display unit. | 2017-06-08 |
20170162635 | ORGANIC LIGHT EMITTING DIODE SUBSTRATE AND ORGANIC LIGHT EMITTING DIODE DEVICE - Provided are an Organic Light Emitting Diode (OLED) substrate and an OLED device. The OLED substrate includes: a transparent substrate, and a light emitting unit and a photoelectric conversion unit provided on the transparent substrate. The transparent substrate has an upper surface, a lower surface opposite to the upper surface, and a lateral surface. The light emitting unit is provided on the upper surface of the transparent substrate. The photoelectric conversion unit is provided on the lateral surface of the transparent substrate for absorbing light transmitted through the lateral surface of the transparent substrate and converting the absorbed light into electric energy through photoelectric conversion. | 2017-06-08 |
20170162636 | TRANSPARENT DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - A transparent display device that may improve light transmittance in a transmissive mode, and a method for fabricating the same are discussed. The transparent display device according to an embodiment includes a first substrate, a second substrate facing a first surface of the first substrate, and a third substrate facing a second surface of the first substrate; a display unit arranged between the first and third substrates, and including a transmissive area and an emission area; and a light controller arranged between the first and second substrates, and transmitting or shielding incident light. The light controller includes a control thin film transistor provided on the first surface of the first substrate; a first electrode provided on the control thin film transistor; a second electrode provided on one surface of the second substrate facing the first substrate; and liquid crystal cells arranged between the first electrode and the second electrode. The control thin film transistor is arranged to correspond to the emission area. | 2017-06-08 |
20170162637 | DISPLAY DEVICE - A display device includes a substrate including a first surface, and a second surface opposite the first surface, and defining a through portion passing therethrough, a pixel array including a plurality of pixels surrounding the through portion at the first surface, a plurality of scan lines extending along a first direction for providing scan signals to the pixels, and a plurality of data lines extending along a second direction crossing the first direction for providing data signals to the pixels, the plurality of data lines including first and second data lines adjacent the through portion at different layers, and having at least a portion thereof curved along a perimeter of the through portion. | 2017-06-08 |
20170162638 | METHOD FOR MANUFACTURING ORGANIC EL DISPLAY PANEL - An organic EL display panel manufacturing method including: preparing a substrate; forming at least first electrodes on the substrate; forming, by performing photolithography on the substrate having the first electrodes, a bank layer made of a photoresist and having apertures corresponding one-to-one with the first electrodes; forming a functional layer in each of the apertures by applying an ink containing a functional material to the aperture and drying the applied ink; and forming at least a second electrode on the functional layer. The forming of the bank layer includes: applying the photoresist to the substrate having the first electrodes; forming apertures corresponding one-to-one with the first electrodes in the photoresist by performing exposure using a mask and then developing the photoresist; after forming the apertures, performing exposure of the photoresist having the apertures; after performing the exposure of the photoresist having the apertures, baking the photoresist. | 2017-06-08 |
20170162639 | AMOLED BACKPLANE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an AMOLED backplane includes manufacturing a TFT substrate and forming a corrugation structure on the TFT substrate, which includes raised sections and recessed sections alternating each other; coating organic photoresist on the TFT substrate that includes the corrugation structure formed thereon to form a planarization layer in such a way that an upper surface of a portion of the planarization layer corresponding to and located above the corrugation structure includes a curved configuration corresponding to the corrugation structure; forming a pixel electrode on the planarization layer in such a way that the pixel electrode shows a curved configuration; and forming, in sequence, a pixel definition layer that has an opening to expose the curved configuration and a photo spacer on the pixel electrode and the planarization layer. | 2017-06-08 |
20170162640 | THIN FILM TRANSISTOR ARRAY PANEL AND ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING THE SAME - An exemplary embodiment of the present invention provides a thin film transistor array panel and an organic light emitting diode display including the same including a substrate, a semiconductor disposed on the substrate, a first gate insulation layer disposed on the semiconductor, and a first diffusion barrier layer disposed on the first gate insulation layer. A second diffusion barrier layer is disposed on a lateral surface of the first diffusion barrier layer. A first gate electrode is disposed on the first diffusion barrier layer. A source electrode and a drain electrode are connected to the semiconductor. The first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal. | 2017-06-08 |
20170162641 | DISPLAY DEVICE, METHOD OF MANUFACTURING DISPLAY DEVICE, AND ELECTRONIC APPARATUS - A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer. | 2017-06-08 |
20170162642 | LIGHT EMITTING DEVICE - The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced. | 2017-06-08 |
20170162643 | OLED DISPLAY, DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting diode (OLED) display, a display device and a manufacturing method thereof are provided. The OLED display includes a base substrate; and OLED pixel units arranged on the base substrate in a matrix. Each OLED pixel unit includes at least one OLED structure, and the OLED structure includes a cathode layer, an anode layer and an organic light emitting layer located therebetween, and the OLED pixel unit further includes a pixel circuit that is connected correspondingly with the OLED structure and configured to drive it to illuminate light. The pixel circuit includes a switching unit and a capacitor located above or below the layer in which the switching unit is located. | 2017-06-08 |
20170162644 | Display Device - A display device having a high aperture ratio and including a capacitor that can increase capacitance is provided. A pair of electrodes of the capacitor is formed using a light-transmitting conductive film. One of the electrodes of the capacitor is formed using a metal oxide film, and the other of the electrodes of the capacitor is formed using a light-transmitting conductive film. With such a structure, light can be emitted to the capacitor side when an organic insulating film is provided over the capacitor and a pixel electrode of a light-emitting element is formed over the organic insulating film. Thus, the capacitor can transmit light and can overlap the light-emitting element. Consequently, the aperture ratio and capacitance can be increased. | 2017-06-08 |
20170162645 | DISPLAY DEVICE - A display device includes contact holes opened in an insulating film outside of a display area in which pixels are arranged, and having a conductive film exposed in bottom portions, a first metal film formed to cover the contact holes and come in contact with the conductive film of the bottom portions, and a transparent conductive film formed on the first metal film. | 2017-06-08 |
20170162646 | PILLAR RESISTOR STRUCTURES FOR INTEGRATED CIRCUITRY - Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts. | 2017-06-08 |
20170162647 | SUBSTRATE RESISTOR WITH OVERLYING GATE STRUCTURE - An illustrative method includes, among other things, forming a plurality of fins. A subset of the plurality of fins is selectively removed, leaving at least a first fin to define a first fin portion and at least a second fin to define a second fin portion. A first type of dopant is implanted into a substrate to define a resistor body and the first type of dopant is implanted into the first and second fins. The first fin portion is disposed above a first end of the resistor body and the second fin is disposed above a second end of the resistor body. An insulating layer is formed above the resistor body. At least one gate structure is formed above the insulating layer and above the resistor body. | 2017-06-08 |
20170162648 | Capacitor Formed On Heavily Doped Substrate - The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate. | 2017-06-08 |
20170162649 | TRENCH-GATE TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - There is provided a trench-gate type semiconductor device that can prevent breakdown of a gate insulating film caused by a displacement current flowing into a protective diffusion layer at a portion of a trench underlying a gate electrode at a turn-off time and simultaneously improves a current density by narrowing a cell pitch. The semiconductor device has a gate electrode | 2017-06-08 |
20170162650 | FINFET WITH REDUCED PARASITIC CAPACITANCE - A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer. | 2017-06-08 |
20170162651 | SEMICONDUCTOR DEVICE HAVING A GATE ALL AROUND STRUCTURE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device includes a wire pattern spaced apart from a substrate and extended in a first direction, a gate electrode disposed around a circumference of the wire pattern and extended in a second direction that is different from the first direction, a source disposed on a first side of the gate electrode, a drain disposed on a second side of the gate electrode, the source and the drain connected to the wire pattern and a gate spacer disposed on first and second sidewalls of the gate electrode, on the source and on the drain. | 2017-06-08 |
20170162652 | NANOWIRE DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a nanowire device is disclosed. The method includes providing a substrate, wherein the substrate comprises a pair of support pads, a recess disposed between the support pads, a second insulating layer disposed on the support pads, a third insulating layer disposed on a bottom of the recess, and at least one nanowire suspended between the support pads at a top portion of the recess; forming a first insulating layer on the nanowire; depositing a dummy gate material over the substrate on the first insulating layer, and patterning the dummy gate material to form a dummy gate structure surrounding a channel region; forming a first oxide layer on laterally opposite sidewalls of the dummy gate; and extending the nanowire on laterally opposite ends of the channel region to the respective support pads, so as to form a source region and a drain region. | 2017-06-08 |
20170162653 | SEMICONDUCTOR DEVICE HAVING GERMANIUM ACTIVE LAYER WITH UNDERLYING DIFFUSION BARRIER LAYER - Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack. | 2017-06-08 |
20170162654 | FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A field effect transistor and a semiconductor device including the same are provided. The semiconductor device may include a channel layer, which is provided on a substrate and includes a two-dimensional atomic layer made of a first material, and a source/drain layer, which is provided on the substrate and includes a second material. The first material may be one of phosphorus allotropes, the second material may be one of carbon allotropes, and the channel layer and the source/drain layer may be connected to each other by covalent bonds between the first and second materials. | 2017-06-08 |
20170162655 | SCHOTTKY BARRIER DIODE - A semiconductor device includes a semiconductor layer including a Ga | 2017-06-08 |
20170162656 | INTEGRATED CMOS WAFERS - The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type. | 2017-06-08 |
20170162657 | POST GROWTH DEFECT REDUCTION FOR HETEROEPITAXIAL MATERIALS - A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor. | 2017-06-08 |
20170162658 | LDMOS with Adaptively Biased Gate-Shield - An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off. | 2017-06-08 |
20170162659 | SEMICONDUCTOR DEVICE - A stable high-frequency amplification characteristic with a high power is obtained by providing a source field plate electrode in an area of a drain electrode side of a gate electrode and connecting the source field plate electrode to a source electrode with a fine wiring layer. In addition, a stress-absorbing layer is stacked on an upper surface of an insulator film just above the gate electrode, and a source field plate electrode is formed above the gate electrode to interpose the stress-absorbing layer, so that a stress is absorbed by a source field plate electrode side, and a mechanical damage to the gate electrode and peripheral portions thereof is suppressed. | 2017-06-08 |
20170162660 | Semiconductor Device Comprising a Field Effect Transistor and Method of Manufacturing the Semiconductor Device - A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region. | 2017-06-08 |
20170162661 | SEMICONDUCTOR DEVICE CONTACTS - Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices. | 2017-06-08 |
20170162662 | SEMICONDUCTOR DEVICE - Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode. | 2017-06-08 |
20170162663 | GATE SPACER AND METHODS OF FORMING - Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment. | 2017-06-08 |
20170162664 | LATERAL BIPOLAR TRANSISTOR - A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size. | 2017-06-08 |
20170162665 | SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME - A Schottky barrier diode includes: an n+ type of silicon carbide substrate; an n− type of epitaxial layer formed on a first surface of the n+ type of silicon carbide substrate; a plurality of p+ regions formed inside the n− type of epitaxial layer; a Schottky electrode formed in an upper portion of the n− type of epitaxial layer of an electrode region; and an ohmic electrode formed on a second surface of the n+ type of silicon carbide substrate, wherein the plurality of p+ regions are formed to be spaced apart from each other at a predetermined interval within the n− type of epitaxial layer. | 2017-06-08 |
20170162666 | METAL-SEMICONDUCTOR-METAL (MSM) HETEROJUNCTION DIODE - In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer. | 2017-06-08 |
20170162667 | SEMICONDUCTOR MIXED GATE STRUCTURE - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a fin structure, a metal gate and a first polysilicon strip. The fin structure is on the substrate. The metal gate is over the fin structure and is substantially perpendicular to the fin structure. The first polysilicon strip is at a first edge of the fin structure and is substantially parallel to the metal gate. | 2017-06-08 |
20170162668 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a fin extending in a first direction. A dummy layer is formed including a plurality of semiconductor layers disposed on the fin. Each of the plurality of semiconductor layers have different impurity concentrations from each other. The dummy layer is etched to form a dummy gate electrode. | 2017-06-08 |
20170162669 | METHOD OF FORMING THE GATE ELECTRODE OF FIELD EFFECT TRANSISTOR - This description relates to a method of forming the gate electrode of a semiconductor device, the method including providing a substrate comprising a dummy gate electrode (DGE), a source/drain (S/D) region, a spacer on a dummy gate sidewall, and an isolation feature, depositing a contact etch stop layer (CESL) over the DGE, the S/D region and the spacer, depositing an interlayer dielectric (ILD) layer over the CESL, performing a first chemical mechanical polishing (CMP) to expose the CESL over the DGE, performing a second CMP to expose the DGE, removing an upper portion of the CESL and the spacer, and performing a third CMP to expose the CESL over the S/D region to produce a structure in which an entire top surface of the CESL over the S/D region and isolation feature is substantially co-planar with a top surface of the DGE. | 2017-06-08 |
20170162670 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING FIN-SHAPED PATTERNS - A method for fabricating a semiconductor device is provided. The method includes forming a first fin-shaped pattern including an upper part and a lower part on a substrate, forming a second fin-shaped pattern by removing a part of the upper part of the first fin-shaped pattern, forming a dummy gate electrode intersecting with the second fin-shaped pattern on the second fin-shaped pattern, and forming a third fin-shaped pattern by removing a part of an upper part of the second fin-shaped pattern after forming the dummy gate electrode, wherein a width of the upper part of the second fin-shaped pattern is smaller than a width of the upper part of the first fin-shaped pattern and is greater than a width of an upper portion of the third fin-shaped pattern. | 2017-06-08 |
20170162671 | FIN FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD TO FORM DEFECT FREE MERGED SOURCE AND DRAIN EPITAXY FOR LOW EXTERNAL RESISTANCE - A method of forming a semiconductor device that includes providing a plurality of fin structures, wherein a surface of the fin structures has a first orientation for a diamond shaped epitaxial growth deposition surface. A first epitaxial semiconductor material having a diamond geometry is grown on the diamond shaped epitaxial growth surface. A blocking material is formed protecting a lower portion of the first epitaxial semiconductor material. An upper portion of the first epitaxial semiconductor material is removed to expose a second orientation surface of the first epitaxial semiconductor material for merged epitaxial semiconductor growth. A second epitaxial semiconductor material is epitaxially formed on the first epitaxial semiconductor material. The second epitaxial semiconductor material has a substantially planar upper surface and extends into direct contact with at least two adjacent fin structures. | 2017-06-08 |
20170162672 | SBFET TRANSISTOR AND CORRESPONDING FABRICATION PROCESS - A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer. | 2017-06-08 |