| 23rd week of 2012 patent applcation highlights part 68 |
| Patent application number | Title | Published |
|---|
| 20120144111 | METHOD AND DEVICE FOR UTILIZING APPLICATION-LEVEL PRIOR KNOWLEDGE FOR SELECTIVELY STORING DATA IN HIGHER PERFORMANCE MEDIA - A method for selectively storing data identified by a software application in higher performance media may include executing control programming for an operating system and a software application hosted by the operating system. The software application assigns a first importance level to a first portion of data and a second importance level to a second portion of data. A first portion of data having the first importance level assigned by the software application is stored in a first storage medium at the instruction of the operating system. A second portion of data having the second importance level assigned by the software application is stored in a second storage medium at the instruction of the operating system. The second storage medium has at least one performance, reliability, or security characteristic different from the first storage medium. | 2012-06-07 |
| 20120144112 | MANAGEMENT COMPUTER AND VOLUME CONFIGURATION MANAGEMENT METHOD - The configuration of volumes provided by a plurality of storage apparatuses with an external connection function is optimized. | 2012-06-07 |
| 20120144113 | METHOD OF PROCESSING DATA AND SYSTEM USING THE SAME - A host generates an address array including a header and each start address to perform a data processing operation, which may for example be 4 Kbytes of a random read operation or a random write operation, and transmits a generated address array to a data storage device through a data bus. The data storage device, in the case of a random read operation, outputs each data corresponding to the each start address to the host successively by using the address array. In the case of a random write operation, the data storage device receives each data corresponding to each start address from the host and stores it in a memory core. | 2012-06-07 |
| 20120144114 | REDUNDANCY ARRAY OF INEXPENSIVE DISKS CONFIGURATION USING SIMPLE NETWORK MANAGEMENT PROTOCOL - A method of configuring a storage device is disclosed. The method generally includes the steps of (A) receiving a single data unit over a communication network, the data unit (i) being transferred via the communication network using a standard communication protocol, (ii) defining both (a) a plurality of new configuration items that define a new configuration of the storage device and (b) a command to be performed by the storage device and (iii) having a standard markup language format, (B) calculating at least one configuration change from a plurality of current configuration items to the new configuration items, the current configuration items defining a current configuration of the storage device, (C) adjusting the storage device into the new configuration based on the at least one configuration change and (D) performing a requested operation with the storage device in the new configuration in response to the command. | 2012-06-07 |
| 20120144115 | STORAGE MEDIUM ADAPTER, INFORMATION WRITING DEVICE AND INFORMATION WRITING SYSTEM - A storage medium adapter | 2012-06-07 |
| 20120144116 | STORAGE APPARATUS AND STORAGE AREA ALLOCATION METHOD - A storage system, method and program product, the system comprising: storage devices; and a controller configured to: provide virtual volumes to a host computer; manage logical units on the storage device and storage pools; allocate, in response to receiving a write request to a virtual volume, a storage region of the storage pools; and store data related to the write request in the storage region allocated, wherein the controller is further configured to: allocate first storage region in first storage pool to first virtual volume based on first size of the first storage region or the first virtual volume; allocate a second storage region in a second storage pool to a second virtual volume of the plurality of virtual volumes based on a second size of the second storage region or the second virtual volume. | 2012-06-07 |
| 20120144117 | RECOMMENDATION BASED CACHING OF CONTENT ITEMS - Content item recommendations are generated for users based on metadata associated with the content items and a history of content item usage associated with the users. Each content item recommendation identifies a user and a content item and includes a score that indicates how likely the user is to view the content item. Based on the content item recommendations, and constraints of one or more caches, the content items are selected for storage in one or more caches. The constraints may include users that are associated with each cache, the geographical location of each cache, the size of each cache, and/or costs associated with each cache such as bandwidth costs. The content items stored in a cache are recommended to users associated with the cache. | 2012-06-07 |
| 20120144118 | METHOD AND APPARATUS FOR SELECTIVELY PERFORMING EXPLICIT AND IMPLICIT DATA LINE READS ON AN INDIVIDUAL SUB-CACHE BASIS - A method and apparatus are described for selectively performing explicit and implicit data line reads. A controller, located in a cache, individually monitors the data resource availability for each of a plurality of sub-caches also located in the cache. The controller receives a data line request, generates an individual implicit tag request for each of the sub-caches that currently have sufficient data resources to perform an implicit data line read, and generates an individual explicit tag request for each of the sub-caches that do not currently have sufficient data resources to perform an implicit data line read. Each tag request includes an address of the requested data line and an indicator, (represented by at least one bit), of whether the tag request is an explicit or implicit tag request. | 2012-06-07 |
| 20120144119 | PROGRAMMABLE ATOMIC MEMORY USING STORED ATOMIC PROCEDURES - A processing core in a multi-processing core system is configured to execute a sequence of instructions as a single atomic memory transaction. The processing core validates that the sequence meets a set of one or more atomicity criteria, including that no instruction in the sequence instructs the processing core to access shared memory. After validating the sequence, the processing core executes the sequence as a single atomic memory transaction, such as by locking a source cache line that stores shared memory data, executing the validated sequence of instructions, storing a result of the sequence into the source cache line, and unlocking the source cache line. | 2012-06-07 |
| 20120144120 | PROGRAMMABLE ATOMIC MEMORY USING HARDWARE VALIDATION AGENT - A processing core in a multi-processing core system is configured to execute a sequence of instructions as an atomic memory transaction. Executing each instruction in the sequence comprises validating that the instruction meets a set of one or more atomicity criteria, including that executing the instruction does not require accessing shared memory. Executing the atomic memory transaction may comprise storing memory data from a source cache line into a target register, reading or modifying the memory data stored in the target register as part of executing the sequence, and storing a value from the target register to the source cache line. | 2012-06-07 |
| 20120144121 | Demand Based Partitioning of Microprocessor Caches - Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein the shared cache memory is effectively shared on a line-by-line basis among the plurality of logical processing partitions of the multi-core processor. | 2012-06-07 |
| 20120144122 | METHOD AND APPARATUS FOR ACCELERATED SHARED DATA MIGRATION - A method and apparatus for accelerated shared data migration between cores is disclosed. | 2012-06-07 |
| 20120144123 | READ-AHEAD PROCESSING IN NETWORKED CLIENT-SERVER ARCHITECTURE - Various embodiments for read-ahead processing in a networked client-server architecture by a processor device are provided. Read messages are grouped by a plurality of unique sequence identifications (IDs), where each of the sequence IDs corresponds to a specific read sequence, consisting of all read and read-ahead requests related to a specific storage segment that is being read sequentially by a thread of execution in a client application. The storage system uses the sequence id value in order to identify and filter read-ahead messages that are obsolete when received by the storage system, as the client application has already moved to read a different storage segment. Basically, a message is discarded when its sequence id value is less recent than the most recent value already seen by the storage system. The sequence IDs are used by the storage system to determine corresponding read-ahead data to be loaded into a read-ahead cache. | 2012-06-07 |
| 20120144124 | METHOD AND APPARATUS FOR MEMORY ACCESS UNITS INTERACTION AND OPTIMIZED MEMORY SCHEDULING - A method and an apparatus for modulating the prefetch training of a memory-side prefetch unit (MS-PFU) are described. An MS-PFU trains on memory access requests it receives from processors and their processor-side prefetch units (PS-PFUs). In the method and apparatus, an MS-PFU modulates its training based on one or more of a PS-PFU memory access request, a PS-PFU memory access request type, memory utilization, or the accuracy of MS-PFU prefetch requests. | 2012-06-07 |
| 20120144125 | Instruction for Pre-Fetching Data and Releasing Cache Lines - A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction. | 2012-06-07 |
| 20120144126 | APPARATUS, METHOD, AND SYSTEM FOR INSTANTANEOUS CACHE STATE RECOVERY FROM SPECULATIVE ABORT/COMMIT - An apparatus and method is described herein for providing instantaneous, efficient cache state recover upon an end of speculative execution. Speculatively accessed entries of a cache memory are marked as speculative, which may be on a thread specific basis. Upon an end of speculation, the speculatively marked entries are transitioned in parallel by a speculative port to their appropriate, thread specific, non-speculative coherency state; these parallel transitions allow for instantaneous commit or recovery of speculative memory state. | 2012-06-07 |
| 20120144127 | DATA TRANSMISSION - A method of transmitting data from a first module to addressable storage devices in a second module. The method comprises: transmitting from the first module to a second module in a first transmission cycle an address identifying a storage device in the second module for a data item; at the second module, determining the status of a storage location in the device identified by the address for holding a data item and dispatching in a second transmission cycle a pre-emptive acknowledgement signal, the state of which depends on the status of that storage location; transmitting in the second transmission cycle the data item from the first module to the second module; transmitting the address in a later transmission cycle from the first module to the second module; and selectively transmitting one of the data item and a next data item depending on the state of the pre-emptive acknowledgement signal. | 2012-06-07 |
| 20120144128 | CUSTOM ATOMICS USING AN OFF-CHIP SPECIAL PURPOSE PROCESSOR - An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache line. The apparatus further comprises an atomic program execution unit that is configured to execute the atomic program as a single atomic memory transaction with a guarantee of forward progress. | 2012-06-07 |
| 20120144129 | High Performance Real-Time Read-Copy Update - A technique for reducing reader overhead when referencing a shared data element while facilitating realtime-safe detection of a grace period for deferring destruction of the shared data element. The grace period is determined by a condition in which all readers that are capable of referencing the shared data element have reached a quiescent state subsequent to a request for a quiescent state. Common case local quiescent state tracking may be performed using only local per-reader state information for all readers that have not blocked while in a read-side critical section in which the data element is referenced. Uncommon case non-local quiescent state tracking may be performed using non-local multi-reader state information for all readers that have blocked while in their read-side critical section. The common case local quiescent state tracking requires less processing overhead than the uncommon case non-local quiescent state tracking. | 2012-06-07 |
| 20120144130 | Optimizing Output Vector Data Generation Using A Formatted Matrix Data Structure - A computer system retrieves a packet that includes non-zero elements that correspond to sparse-matrix rows. Within the packet, the non-zero elements are stored in predefined fields that each correspond to one of the sparse-matrix rows. The computer system computes output values to correspond with each of the sparse-matrix rows using the non-zero elements and corresponding input values. In turn, the computer system stores the computed output values in consecutive locations within an output buffer and processes the output values accordingly. | 2012-06-07 |
| 20120144131 | SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE - An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it. | 2012-06-07 |
| 20120144132 | MANAGEMENT OF PERSISTENT MEMORY IN A MULTI-NODE COMPUTER SYSTEM - A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications. | 2012-06-07 |
| 20120144133 | METHOD AND SYSTEM FOR STORAGE AND EVALUATION OF DATA, ESPECIALLY VITAL DATA - A method for evaluation and aggregating storage of data, especially multivariate time series, such as sensor and vital data, the data being acquired via at least one sensor ( | 2012-06-07 |
| 20120144134 | NONVOLATILE SEMICONDUCTOR MEMORY AND STORAGE DEVICE - According to one embodiment, a nonvolatile semiconductor memory includes two memory planes in a chip, a I/O circuit in the chip, the I/O circuit shared by the two memory planes, and a control circuit in the chip, the control circuit controlling a write operation, a verify operation and a read operation to the two memory planes independently. Each of the two memory planes comprises a memory cell array and a data register stored write data temporarily. The control circuit configured to transfer the write data to the data registers in the two memory planes in parallel to execute the write and verify operations to every memory plane one by one in a mirroring write mode, and transfer the write data to the data register in one of the two memory planes to execute the write and verify operations in a normal write mode. | 2012-06-07 |
| 20120144135 | REDUCTION OF COMMUNICATION AND EFFICIENT FAILOVER PROCESSING IN DISTRIBUTED SHARED MEMORY-BASED APPLICATION - Various embodiments for reducing communication between cluster nodes and optimizing failover processing in a distributed shared memory (DSM)-based application by at least one processor device are provided. In one embodiment, for a data structure operable on a DSM, a read-mostly portion is maintained in a single copy sharable between the cluster nodes while an updatable portion is maintained in multiple copies, each of the multiple copies dedicated to a single cluster node. | 2012-06-07 |
| 20120144136 | RESTORATION OF DATA FROM A BACKUP STORAGE VOLUME - A method is provided for restoring data from a backup storage volume onto a source storage volume. A content of a memory unit of the backup storage volume and a content of the corresponding memory unit of the source storage volume are loaded into a computer memory, and are compared in the computer memory for identity. The content of the memory unit of the backup storage volume is written to the corresponding memory unit of the source storage volume if the comparison indicates that the content of the compared memory units is not identical. The invention further relates to a system for restoring data from a backup storage volume onto a source storage volume comprising a restore software running on a data processing device, which is connected to the backup storage volume and the source storage volume, whereby the restore software performs the above method. | 2012-06-07 |
| 20120144137 | STORAGE SYSTEM AND REMOTE COPY RECOVERY METHOD - The storage system includes a first storage device, configured to be installed in a first site and providing a primary logical volume in which data received from a host computer is written; a second storage device, configured to be installed in a second site and providing a virtual logical volume, which has no structure for storing data received from the first storage system; and a third storage device, configured to be installed in a third site and providing a secondary logical volume in which data received from the second storage system is written. Data written in the primary logical volume of the first storage device are remote-copied to the secondary logical volume of the third storage device via the virtual logical volume of the second storage device. | 2012-06-07 |
| 20120144138 | Locking Access To Data Storage Shared By A Plurality Of Compute Nodes - Methods, apparatuses, and computer program products are provided for locking access to data storage shared by a plurality of compute nodes. Embodiments include maintaining, by a compute node, a queue of requests from requesting compute nodes of the plurality of compute nodes for access to the data storage, wherein possession of the queue represents possession of a mutual-exclusion lock on the data storage, the mutual-exclusion lock indicating exclusive permission for access to the data storage; and conveying, based on the order of requests in the queue, possession of the queue from the compute node to a next requesting compute node when the compute node no longer requires exclusive access to the data storage. | 2012-06-07 |
| 20120144139 | CONTENT MODIFICATION CONTROL USING READ-ONLY TYPE DEFINITIONS - Disclosed are methods, systems and products, including a method that includes establishing in a computing environment, implemented using at least one processor-based device, a non-immutable object as being a read-only object, the computing environment not allowing performance of operations that cause modification of the read-only non-immutable object. The method also includes preventing by the at least one processor-based device performance of an operation on the read-only non-immutable object that would cause the read-only non-immutable object to be modified. | 2012-06-07 |
| 20120144140 | Memory Protection Unit and a Method for Controlling an Access to a Memory Device - A memory protection unit includes at least a first access control unit and a second access control unit programmed for controlling an access to a memory device. Further a method to operate a processing system comprising multiple processing devices and multiple memory protection units associated to the multiple processing devices, The access to the memory by a processing device is approved if first access control unit and second access control unit of the memory protection associated to the processing device approves the access and access is rejected if first access control unit or second access control unit rejects the access. The first access control unit is programmable by the associated processing device alone and the programming of the second access control unit is readable by an additional processing device which is to be used in a system with multiple programming devices, not the associate processing device. | 2012-06-07 |
| 20120144141 | Storage Device and Method for Storage Device State Recovery - A storage device and method for storage device state recovery are provided. In one embodiment, a storage device commences an authentication process to authenticate a host device. The authentication process comprises a plurality of phases, and the storage device stores the state of the authentication process, wherein the state indicates the phase(s) of the authentication process that have been successfully completed. After a power loss, the storage device retrieves the state of the authentication process and resumes an operation with the host device without re-performing the phase(s) of the authentication process that have been completed. | 2012-06-07 |
| 20120144142 | SERIAL ADVANCED TECHNOLOGY ATTACHMENT WRITE PROTECTION: MASS STORAGE DATA PROTECTION DEVICE - A mass storage device protection system may have a mass storage device, a processor configured to generate at least one serial write command signal to the mass storage device via a serial communication link, and a storage protector configured for communication with the processor and mass storage device, the storage protector configured to do the following: intercept the at least one serial write command signal, and determine whether the at least one serial write command signal comprises an authorized command signal or an unauthorized command signal. | 2012-06-07 |
| 20120144143 | MOVING PICTURE CODING APPARATUS AND MOVING PICTURE DECODING APPARATUS - A video encoder ( | 2012-06-07 |
| 20120144144 | DYNAMIC MEMORY ALLOCATION AND RELOCATION TO CREATE LOW POWER REGIONS - Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects. | 2012-06-07 |
| 20120144145 | APPARATUS AND METHOD FOR MEASURING LIFESPAN OF MEMORY DEVICE - A method for measuring a lifespan of a memory device includes measuring an operation time of the memory device and generating lifespan information by comparing the measured operation time with a reference operation time. | 2012-06-07 |
| 20120144146 | MEMORY MANAGEMENT USING BOTH FULL HARDWARE COMPRESSION AND HARDWARE-ASSISTED SOFTWARE COMPRESSION - Systems and methods to manage memory are provided. A particular method may include selecting one of a plurality of compression modes to perform memory compression operations at a server computer. The plurality of compression modes may include a first memory compression mode configured to perform a first memory compression operation using a compression engine, and a second compression mode configured to perform a second memory compression operation using the compression engine. At least one of the first compression operation and the second compression operation may be performed according to the selected compression mode. | 2012-06-07 |
| 20120144147 | STORAGE APPARATUS TO WHICH THIN PROVISIONING IS APPLIED - A storage control apparatus includes a first logical volume in which data has been stored in a pool that includes at least one of one or a plurality of logical volumes based on a plurality of physical storage devices as a pool volume, and divides the first logical volume into at least two real areas. The storage control apparatus allocates the first logical volume to a second logical volume that is a virtual logical volume that has been divided into at least two virtual areas. The storage control apparatus executes a first data movement processing for moving all data of the first logical volume to at least one pool volume other than the first logical volume, and allocates a real area of a movement destination of the data to a virtual area of an allocated destination of a real area of a movement source of the data as substitute for the real area in the first data movement processing. | 2012-06-07 |
| 20120144148 | METHOD AND DEVICE OF JUDGING COMPRESSED DATA AND DATA STORAGE DEVICE INCLUDING THE SAME - A write method of a data storage device including a storage media includes receiving data to be stored in the storage media; judging whether the received data is compressed data, without externally provided additional information; and selectively compressing the received data according to the judgment result, wherein the judging whether the received data is compressed data is made based on a distribution of actual symbols included in at least part of the received data. | 2012-06-07 |
| 20120144149 | CAPACITY MANAGEMENT IN DEDUPLICATION STORAGE SYSTEMS - Various embodiments for capacity management in a deduplication computing storage environment by a processor device are provided. A deduplication storage capacity is estimated as a function of an expected deduplication ratio, the expected deduplication ratio being a combined average of a current deduplication ratio and a configured deduplication ratio, the current deduplication ratio depending on the data currently stored in the deduplication storage, and the configured deduplication ratio being an estimate made at a configuration stage of the deduplication computing storage environment. | 2012-06-07 |
| 20120144150 | DATA PROCESSING APPARATUS - A data processing apparatus may include a data acquisition unit, a plurality of buffer units including a storage capacity and an additional storage capacity, a valid data amount calculation unit that calculates an amount of valid data and outputs valid data information indicating whether or not the data is valid, and a data write control unit that controls writing of the data to one of the plurality of buffer units. The valid data amount calculation unit may determine the number of the units based on the calculated amount of valid data and the additional storage capacity. The data acquisition unit may acquire data included in the units, the number of which is determined by the valid data amount calculation unit. The data write control unit may control whether or not to write the data to one of the plurality of buffer units based on the valid data information. | 2012-06-07 |
| 20120144151 | METHODS AND SYSTEM FOR ENSURING MEMORY DEVICE INTEGRITY - A method for protecting memory segments of a memory device is provided. The method includes receiving, by a processor coupled to the memory device, a request to allocate memory from an application, being executed by the processor, wherein the request includes a requested memory size and allocating, by the processor, a portion of memory having a size greater than the requested memory size. The method also includes creating, by the processor, a permitted read counter associated with the allocated portion of memory, wherein the permitted read counter is initialized to an initial value, and determining, by the processor, whether access to the memory segment is permitted using the permitted read counter. A system for protecting memory segments of a memory device is also disclosed. | 2012-06-07 |
| 20120144152 | TRANSACTION LOG RECOVERY - The present disclosure includes methods for transaction log recovery in memory. One such method includes examining a number of entries saved in a transaction log to determine a write pattern, reading the memory based on the write pattern, updating the transaction log with information associated with data read from the memory based on the write pattern, and updating a logical address (LA) table using the transaction log. | 2012-06-07 |
| 20120144153 | Dynamic Address Translation With Change Record Override - A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation. | 2012-06-07 |
| 20120144154 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER - Storing translation lookaside buffer (TLB) entries are in a TLB | 2012-06-07 |
| 20120144155 | System Of Rotating Data In A Plurality Of Processing Elements - A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to the processing element's positions. | 2012-06-07 |
| 20120144156 | METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING APPARATUS - A method for controlling an information processing apparatus including a processor which operates an operating system and a kernel which is operated independently of the operating system, and a network interface through which the information processing apparatus is connectable to an other information processing apparatus, the method includes notifying, by the operating system, the kernel of system down information about the operating system, determining, by the kernel, a kind of an Internet protocol included in a packet received from the other information processing apparatus connected through the network interface, creating, by the kernel, a packet for notifying of the system down in accordance with the determined kind of the Internet protocol, and transmitting, by the kernel, the created packet to the other information processing apparatus via the network interface. | 2012-06-07 |
| 20120144157 | Allocation of Mainframe Computing Resources Using Distributed Computing - There is disclosed a system and method for allocation of mainframe computing resources using distributed computing. In particular, the present application is directed to a system whereby a mainframe process intended for execution on a metered processor may be identified as executable on a non-metered processor. Thereafter, the mainframe computer may initiate execution of the remote process on the remote non-metered processor. If necessary, high-speed access to data available to the metered processor is provided to the non-metered processor. The process operates directly on data available to the metered processor. Once completed, the process signals the mainframe computer that the process is complete. Both metered and non-metered processor configuration and management may be accomplished using the administrative interface. | 2012-06-07 |
| 20120144158 | SYSTEMS AND METHODS FOR COMPILING AN APPLICATION FOR A PARALLEL-PROCESSING COMPUTER SYSTEM - A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications. | 2012-06-07 |
| 20120144159 | QUANTUM PROCESSOR - One embodiment of the invention includes a quantum processor system. The quantum processor system includes a first resonator having a first characteristic frequency and a second resonator having a second characteristic frequency greater than the first characteristic frequency. A qubit cell is coupled to each of the first resonator and the second resonator. The qubit cell has a frequency tunable over a range of frequencies including the first characteristic frequency and the second characteristic frequency. A classical control mechanism is configured to tune the frequency of the qubit cell as to transfer quantum information between the first resonator and the second resonator. | 2012-06-07 |
| 20120144160 | MULTIPLE-CYCLE PROGRAMMABLE PROCESSOR - The multi-cycle programmable processor emulates the features of a conventional microprocessor. Processor hardware functional units include a program counter (instruction pointer), an arithmetic and logic unit, an accumulator, an instruction register, a 2×1 multiplexer, 2×4 decoder, 1×2 decoder, an AND gate and an OR gate. Additionally, a controller modeled by a finite state machine (FSM) is operably connected to the microprocessor functional units and has a plurality of states that defines the operation of the microprocessor functional units. Each control state of the FSM implements the transfer of information between the registers of the datapath. The execution sequences through three states: an instruction fetch; an instruction decode; and instruction execute. The controller issues the required signals to the various hardware components to execute the instruction needed in three clock cycles. | 2012-06-07 |
| 20120144161 | CARRYLESS MULTIPLICATION PREFORMATTING APPARATUS AND METHOD - An apparatus is provided for performing carryless multiplication. The apparatus has an opcode dectector and a carryless preformat unit. The opcode dectector is configured to receive a carryless multiplication instruction, and is configured to assert a carryless signal responsive to receipt of the carryless multiplication instruction. The carryless preformat unit is configured to partition the first operand into parts responsive to assertion of the carryless signal, where the parts are configured such that a Booth encoder selects first partial products corresponding to a second operand and is precluded from selection of second partial products corresponding to the second operand, and where the second partial products are results of implicit carry operations. The first partial products are exclusive-ORed together to yield a carryless multiplication result. | 2012-06-07 |
| 20120144162 | SYSTEMS AND METHODS FOR DETERMINING COMPUTE KERNELS FOR AN APPLICATION IN A PARALLEL-PROCESSING COMPUTER SYSTEM - A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications. | 2012-06-07 |
| 20120144163 | DATA PROCESSING METHOD AND SYSTEM BASED ON PIPELINE - A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage. | 2012-06-07 |
| 20120144164 | PROCESSOR REGISTER RECOVERY AFTER FLUSH OPERATION - An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction result information. The general purpose register may temporarily store instruction opcode and register bits information for use during dispatch, execution and other operations. The processor includes a recovery buffer unit for use during flush recovery operations. The processor may use recovery valid and recovery pending bits that correspond with each instruction during the register recovery from flush operation. | 2012-06-07 |
| 20120144165 | SIDEBAND PAYLOADS IN PSEUDO NO-OPERATION INSTRUCTIONS - A pseudo no-op instruction in an instruction stream is detected, and the pseudo no-op instruction is decoded as being an opcode, wherein a parameter of the pseudo no-op instruction uniquely identifies the opcode. The method makes use of a pseudo no-op instruction and provides the pseudo no-op instruction with additional semantics outside of the instruction stream execution. New or enhanced functionality can be implemented in application software in a fashion that fully preserves backward compatibility to software and processors that do not support the new or enhanced functionality. If these functionalities are not supported, then the legacy software or processor will merely see and execute the pseudo no-op instruction, which will effectively do nothing at all. | 2012-06-07 |
| 20120144166 | CONTROL SIGNAL MEMOIZATION IN A MULTIPLE INSTRUCTION ISSUE MICROPROCESSOR - A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit. | 2012-06-07 |
| 20120144167 | APPARATUS FOR EXECUTING PROGRAMS FOR A FIRST COMPUTER ARCHITECTURE ON A COMPUTER OF A SECOND ARCHITECTURE - A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor. | 2012-06-07 |
| 20120144168 | ODD AND EVEN START BIT VECTORS - A method and apparatus is presented for identifying instructions in a stream of information by preprocessing the stream of information, creating a vector of instructions and breaking the vector of instructions into two or more vectors for picking the identified instructions at a high frequency. | 2012-06-07 |
| 20120144169 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER READABLE MEDIUM - An information processing apparatus includes the following elements. A generator generates, on the basis of instruction information which describes processing to be executed for obtaining output data from raw data, processing definition information that defines details of the processing, upon inputting the instruction information. A determination unit determines whether output data associated with the currently generated processing definition information and data to be used as raw data is stored in a first memory, the first memory storing therein output data which has been obtained in accordance with previously generated processing definition information in association with data used as the raw data and the processing definition information. An output unit outputs, if the determination unit determines that the output data is stored in the first memory, the output data stored in the first memory without causing a processor to execute the processing. | 2012-06-07 |
| 20120144170 | DYNAMICALLY SCALABLE PER-CPU COUNTERS - Embodiments include a reference counting system and method for a multiprocessor system including distributed per-CPU counters having a dynamically variable batch size. A global counter is dynamically updated as each per-CPU counter reaches its associated batch size. An initial batch size provides a desired scalability. The batch size is automatically reduced as the global count approaches a predefined target, to increase the accuracy of the global count. Counting can be performed atomically using architecturally supported atomic operations. Using synchronized counters, counting can be done with a lock held by each processor to provide the necessary mutual exclusion for performing the atomic operations. | 2012-06-07 |
| 20120144171 | Mechanism for Detection and Measurement of Hardware-Based Processor Latency - A mechanism for detection and measurement of hardware-based processor latency is disclosed. A method of the invention includes issuing an instruction to stop all running instructions on one or more processors of a multi-core computing device, starting a latency measurement code loop on each of the one or more processors, wherein for each of the one or more processors the latency measurement code loop operates to sample a time stamp counter (TSC) for a first time reading and sample the TSC for a second time reading after a predetermined period of time, and determine whether a difference between the first and the second time readings represents a discontinuous time interval where an operating system (OS) of the computing device does not control the one or more processors. | 2012-06-07 |
| 20120144172 | Interrupt Distribution Scheme - In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor. | 2012-06-07 |
| 20120144173 | UNIFIED SCHEDULER FOR A PROCESSOR MULTI-PIPELINE EXECUTION UNIT AND METHODS - A unified scheduler for a processor execution unit and methods are disclosed for providing faster throughput of micro-instruction/operation execution with respect to a multi-pipeline processor execution unit. In one example, an execution unit has a plurality of pipelines that operate at a predetermined clock rate, each pipeline configured to process a selected subset of microinstructions. The execution unit has a scheduler that includes a unified queue configured to queue microinstructions for all of the pipelines and a picker configured to direct a queued microinstruction to an appropriate pipeline for processing based on an indication of readiness for picking. Preferably, when all of the pipelines are ready to receive a microinstruction for processing and there is at least one microinstruction queued that is ready for picking for each pipeline, the picker picks and directs a queued microinstructions to each of the pipelines in a single clock cycle. | 2012-06-07 |
| 20120144174 | MULTIFLOW METHOD AND APPARATUS FOR OPERATION FUSION - A method and apparatus for utilizing scheduling resources in a processor are disclosed. A complex operation is assigned for execution as two micro-operations; a first micro-operation and a second micro-operation. The first micro-operation, which may be an address-generation operation, is executed using at least one of a first processing unit or a load and store unit and the second micro-operation, which may be an execution operation, is executed using a second processing unit, where at least one operand of the second micro-operation is an outcome of the first micro-operation. | 2012-06-07 |
| 20120144175 | METHOD AND APPARATUS FOR AN ENHANCED SPEED UNIFIED SCHEDULER UTILIZING OPTYPES FOR COMPACT LOGIC - An integrated circuit is disclosed wherein microinstructions are selectively queued for execution in an execution unit having multiple pipelines where each pipeline is configured to execute a selected subset of a set of supported microinstructions. The execution unit receives microinstruction data including an operation code OpCode and an operation type OpType. The OpType data being at least one bit less that a minimum binary size of an OpCode required to uniquely identify the microinstruction. The OpType data selected to indicate a category of microinstructions having common execution requirement characteristics. The microinstructions are selectively queued for pipeline processing by the execution unit pipelines based on the OpType without decoding the OpCode of the microinstruction. | 2012-06-07 |
| 20120144176 | Method for Setting a Boot List to Disks with Multiple Boot Logical Volumes - A method dynamically determines the contents of a Boot Logical Volume from within a System Management Service menu. Responsive to receiving the scan request, a system dynamically scans a root volume group to identify special files associated with the various base operating systems stored on the boot logical volumes of the root volume group. The system then maps the files to a specific operating systems version, and presents a list of the available operating systems on the various boot logical volumes to a user. | 2012-06-07 |
| 20120144177 | FAST COMPUTER STARTUP - Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information. | 2012-06-07 |
| 20120144178 | FAST COMPUTER STARTUP - Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information. | 2012-06-07 |
| 20120144179 | FAST COMPUTER STARTUP - Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information. | 2012-06-07 |
| 20120144180 | BASEBOARD MANAGEMENT CONTROLLER AND METHOD FOR SHARING SERIAL PORT - A baseboard management controller (BMC) connects with a COM serial port. The BMC includes an input queue and an output queue. If a basic input output system (BIOS) of the BMC has been initialized, the COM serial port is used by the BIOS. When a processor of the BMC sends a control command to a sharing system of the BMC, the input queue and the output queue are converted to time division multiplex (TDM) queues. The COM serial port may be used by the BIOS or by the BMC according to an ID flag of each element of the TDM queues. | 2012-06-07 |
| 20120144181 | MOTHERBOARD AND METHOD FOR DISPLAYING HOST SYSTEM PARAMETER - A motherboard and a method for displaying a host system parameter are provided. The motherboard includes a bridge circuit receiving the host system parameter, a microcontroller connected to the bridge circuit, and a transmitter connected to the microcontroller. The microcontroller is capable of directly capturing the host system parameter from the bridge circuit and then transmitting the system parameter to the transmitter when the motherboard is powered on. | 2012-06-07 |
| 20120144182 | APPARATUS AND METHOD FOR FAST BOOTING BASED ON VIRTUALIZATION TECHNIQUE - An apparatus for fast booting based on a virtualization technique includes: a hardware comprising a processor, a memory and a storage where a status information corresponding to an operating system (OS) is stored; and a virtual machine monitor (VMM) for interfacing between the OS and the hardware, wherein the VMM is operated by the processor and loads the status information on the memory. Herein, the status information may be pre-generated to include data in the memory in a state where the OS is completely booted. | 2012-06-07 |
| 20120144183 | APPARATUS AND METHOD FOR CONTROLLING A COMPUTER SYSTEM WITH AT LEAST TWO POWER SUPPLY UNITS - A computer system includes at least two power supply units providing an output-side operating voltage from at least one input-side supply voltage, at least one power-consuming component operated in at least one normal operating mode with a first power consumption and operated in a restricted operating mode with at least one second power consumption lower than the first power consumption, the power-consuming component electrically coupled to the at least two power supply units; a controller coupled to the at least two power supply units and the power-consuming component; and at least one management component coupled to the controller. | 2012-06-07 |
| 20120144184 | DATA PROCESSING DEVICE - A statue management section of a control section is provided with a corresponding real number storage section that stores a real number converted from a logical number by a configuration number converting section. When the corresponding real number storage section has stored configuration information with a real number of the next transition state, the state management section directly supplies the real number to the configuration information storage section in the next or later processing cycle. | 2012-06-07 |
| 20120144185 | COUNTING DELEGATION USING HIDDEN VECTOR ENCRYPTION - Counting values can be encrypted as a set of counting value cyphertexts according to a hidden vector encryption scheme using sample values of a set of samples, where each of the samples can include multiple sample values. Additionally, tokens can be generated. The tokens can be configured according to the hidden vector encryption scheme, such that each of the tokens can enable decryption of matching cyphertexts. Processing of the counting value cyphertexts and the tokens can be delegated to a map-reduce computer cluster. The cluster can run a map-reduce program to produce and return count representations. Each count representation can represent a count of a set of the counting value cyphertext(s) whose decryption was enabled by one or more of the token(s). For example, the counts may be counts that can be used in constructing a data structure such as a decision tree. | 2012-06-07 |
| 20120144186 | METHOD FOR VERIFICATION OF DECRYPTION PROCESSES - The present invention describes a verification method which allows to ensure that the decryption process has been done honestly by the entity in charge of that. | 2012-06-07 |
| 20120144187 | Application Layer Security Proxy for Automation and Control System Networks - Embodiments provide an application layer security proxy that protects substation automation systems. The application layer security proxy inspects a received, inbound data packet at the application layer, and either drops the data packet, forwards the data packet, or processes the data packet rather than dropping it in order to maintain the communications network connection, the later two according to a predefined role-based access control policy. The application layer security proxy calculates a round trip time for each reply to a received, inbound data packet and observes the bandwidth usage from the amount of bytes transmitted. Round trip time and bandwidth usage are used to detect abnormal communication traffic. | 2012-06-07 |
| 20120144188 | METHOD FOR CONNECTING A FIRST COMPUTER NETWORK TO AT LEAST A SECOND EXTENDED COMPUTER NETWORK - Method for connecting a first computer network and at least a second extended computer network wherein the at least second extended computer network is not connected to the Internet and does not have a routing path to the first computer network, the method comprising: installing a concentration router within an intermediate network and associating the concentration router to a public IP address; interconnecting the intermediate network to the at least second extended computer network through a CPE router, and interconnecting the intermediate network to the first computer network via the Internet passing through the concentration router; implementing an IP tunnel between the at least second extended computer network and the first computer network across the direct intermediate network and the Internet, wherein the IP tunnel is implemented as a first external and encrypted IP tunnel, across the Internet, and a second internal non-encrypted IP tunnel across the intermediate network. | 2012-06-07 |
| 20120144189 | WLAN AUTHENTICATION METHOD, WLAN AUTHENTICATION SERVER, AND TERMINAL - An authentication method, a server, and a terminal for a wireless local area network (WLAN) are provided. The method includes: redirecting a Hypertext Transfer Protocol (HTTP) request message sent by a WLAN terminal to an address of a login webpage of a WLAN network and returning the redirected HTTP request message to the WLAN terminal; sending authentication request information carrying an International Mobile Subscriber Identity (IMSI) identifier of a Subscriber Identity Module (SIM) card sent by the WLAN terminal to an Authentication/Authorization/Accounting (AAA) server corresponding to the address of the login webpage of the WLAN network, such that the AAA server performs authentication based on the IMSI identifier. | 2012-06-07 |
| 20120144190 | DEVICES AND METHODS FOR ESTABLISHING AND VALIDATING A DIGITAL CERTIFICATE - A digital certificate is configured to confirm the association of a public key assigned to a device as the owner of the public key to the device. The digital certificate further has an additional digital certificate, the additional digital certificate being a certificate of an additional device configured to digitally sign the digital certificate of the device. The certification process can be improved, wherein particularly the verification of digital certificates is improved. The various embodiments are particularly useful for applications where a secure communication of information or data is desired and/or should be made possible. | 2012-06-07 |
| 20120144191 | SECURE TRANSPORT OF MULTICAST TRAFFIC - A request to receive multicast data, associated with a multicast group, may be transmitted. The request may be transmitted via a tunnel. Group keys may be received in response to the request. The group keys may be based on the multicast group. An encapsulated packet may be received via another tunnel. The encapsulated packet may be processed, using the group keys, to obtain a multicast packet associated with the multicast data. The multicast packet may be forwarded to at least one multicast recipient. | 2012-06-07 |
| 20120144192 | METHOD, DEVICE, AND SYSTEM FOR MANAGING PERMISSION INFORMATION - A method, a device, and a system for managing permission information are provided. The method includes: receiving a permission modification instruction, where the permission modification instruction is used to instruct modification of permission information of a file; modifying the permission information according to the permission modification instruction of the file; and sending an Identifier (ID) of the file and the modified permission information to a server. The device includes: a modification module, a processing module, and a first sending module. The system includes: a client and a server. The server and the file jointly store the permission information, thereby effectively improving the flexibility of file encryption, reducing the burden of the server, and improving the performance of the server. | 2012-06-07 |
| 20120144193 | Open protocol for authentication and key establishment with privacy - A suite of efficient authentication and key establishment protocols for securing contact or contactless interfaces between communicating systems. The protocols may be used in secure physical access, logical access and/or transportation applications, among other implementations. The system authenticates a mobile device such as a smart card and/or mobile phone equipped with a secure element presented to one or more host terminals and establishes shared secure messaging keys to protect communications between the device and terminal. Secure messaging provides an end-to-end protected path of digital documents or transactions through the interface. The protocols provide that the device does not reveal identification information to entities different from a trusted host. The terminal may be a contactless reader at a door for controlling physical access, a desktop, laptop or kiosk for controlling logical access, and/or an access point for obtaining an encrypted digital ticket from an authenticated mobile device used for transit applications. | 2012-06-07 |
| 20120144194 | Service providing client, wireless terminal and method for implementing binding - The disclosure discloses a service providing client, a wireless terminal and a method for implementing binding. The service providing client comprises a transmission module, which is configured to transmit authentication information to the wireless terminal ( | 2012-06-07 |
| 20120144195 | METHOD AND SYSTEM FOR UNIFIED MOBILE CONTENT PROTECTION - Media content is delivered to a variety of mobile devices in a protected manner based on client-server architecture with a symmetric (private-key) encryption scheme. A media preparation server (MPS) encrypts media content and publishes and stores it on a content delivery server (CDS), such as a server in a content distribution network (CDN). Client devices can freely obtain the media content from the CDS and can also freely distribute the media content further. They cannot, however, play the content without first obtaining a decryption key and license. Access to decryption keys is via a centralized rights manager, providing a desired level of DRM control. | 2012-06-07 |
| 20120144196 | System and Method for Secure Control of Resources of Wireless Mobile Communication Devices - Systems and methods for secure control of a wireless mobile communication device are disclosed. Each of a plurality of domains includes at least one wireless mobile communication device asset. When a request to perform an operation affecting at least one of the assets is received, it is determined whether the request is permitted by the domain that includes the at least one affected asset, by determining whether the entity with which the request originated has a trust relationship with the domain, for example. The operation is completed where it is permitted by the domain. Wireless mobile communication device assets include software applications, persistent data, communication pipes, and configuration data, properties or user or subscriber profiles. | 2012-06-07 |
| 20120144197 | POINT-TO-POINT COMMUNICATION METHOD IN A WIRELESS SENSOR NETWORK AND METHODS OF DRIVING COORDINATORS AND COMMUNICATION DEVICES IN THE WIRELESS SENSOR NETWORK - The present invention relates to a point-to-point communication method that performs mutual authentication and creates link keys without using a master key. The point-to-point communication method can include authentication by exchanging authentication information between a first node and a second node from among the plural nodes; and having each of the first node and the second node create a link key, after the authentication is completed. During the authentication, the authentication information uses a secret key of a corresponding coordinator (node). | 2012-06-07 |
| 20120144198 | USER AUTHENTICATION IN A MOBILE ENVIRONMENT - A data channel transmission can be used to authenticate a voice channel transmission. A third party trusted authentication server can be used to authenticate the identity of one or more parties to a call where at least one of the parties to the call is using a mobile device. A PKI authentication methodology or other symmetric or asymmetric encryption/decryption methodology can be used in a mobile network environment to identify and authenticate a first user to a second user. The authentication request sent to the third party trusted server can be encrypted, signed and transmitted over a data channel (such as an internet connection or SMS or MMS connection), concurrent with the voice channel transmission. In response to validation by the third party trusted server, the third party trusted server can send an authentication indication to the second user's device, which can display identification information and other (optional) data associated with the first user. | 2012-06-07 |
| 20120144199 | COMMUNICATION APPARATUS, CONTROL METHOD FOR COMMUNICATION APPARATUS, AND PROGRAM - A communication apparatus of the present invention is a communication apparatus that communicates with a plurality of other communication apparatuses, and starts processing for setting an address for the communication apparatus using encrypted communication when encrypted communication with the plurality of communication apparatuses becomes possible by sharing encryption keys for encrypting communication with the other communication apparatuses. | 2012-06-07 |
| 20120144200 | CONTENT SECURITY TRANSMISSION PROTECTION DEVICE AND SYSTEM THEREOF, AND CONTENT SECURITY TRANSMISSION METHOD - The invention relates to information security technologies, provides a content security transmission device and a content security transmission system which separate data transmission function of a digital interface from data management and processing function thereof, and provides a content security transmission method based on the device and the system. The content security transmission protection device comprises digital interfaces and a management/processing unit, the management/processing unit is configured in a specific chip in the device, used for updating a revocation list stored therein and collecting information from downstream devices. A transmitting device and a forwarding device in the content security transmission protection system comprise digital interfaces and management/processing units. The invention employs software in the specific chip CPU to implement data management and processing function without increasing cost, thus being capable of increasing any functions, improving flexibility and expansibility of the system, and greatly reducing size and cost of digital interface chips, namely reducing the development difficulty. The digital interfaces only implement simple data transmission function at fast processing speed. | 2012-06-07 |
| 20120144201 | SECURE ELEMENT AUTHENTICATION - Secure element authentication techniques are described. In implementations, a confirmation is received that an identity of a user has been physically verified using one or more physical documents. One or more credentials that are usable to authenticate the user are caused to be stored in a secure element of a mobile communication device of the user, the secure element implemented using tamper-resistant hardware. | 2012-06-07 |
| 20120144202 | SECURE AUTHENTICATION FOR CLIENT APPLICATION ACCESS TO PROTECTED RESOURCES - An authorization server receives a request for an access token, for accessing a protected resource, from a client application executing on a device, wherein the request includes a client identifier that uniquely identifies the client application and a device identifier that uniquely identifies the device. The authorization server performs authentication of the client identifier and the device identifier. The authorization server returns a valid access token to the client application, based on the authentication of the client identifier and the device identifier, to enable the client application access to the protected resource. | 2012-06-07 |
| 20120144203 | Authenticating a User with Hash-Based PIN Generation - Systems and methods for authenticating a user of a service are disclosed. A Personal Identification Number (PIN) is generated using a plurality of variables, and a user is authenticated by comparing the PIN generated at the user's mobile device with a PIN generated on an authentication server. The authentication enables the user to access a service or resource hosted on a host server. When requesting access to the resource, the user generates a device PIN and transmits the device PIN along with their unique key into the host server. The host server forwards the device PIN and the key to the authentication server. The authentication server generates a server PIN and compares the server PIN to the device PIN. If the two PINs match, the authentication server transmits a successful authentication response to the host server. The PIN generation process is a standard hash process, such as MD5 or SHA1, and uses at least the key provided by the user, a device identifier, and a current date/time. The device identifier is one of a unique identifier of the hardware on the mobile device or a unique identifier of a communication channel. This combination of the device identifier and the key ensures that only an authorized user is allowed access to the service. | 2012-06-07 |
| 20120144204 | UPDATES OF BIOMETRIC ACCESS SYSTEMS - Methods are disclosed for performing an update to a biometric access system. An instruction is received at a handheld device defining the update. An encoded signal is generated from the instruction to be transmitted to a biometric terminal from the handheld device. An acknowledgment is received from the biometric terminal at the handheld device that the encoded signal has been received and acted upon. Update information is transmitted from the handheld device over a network to a server to record the update. | 2012-06-07 |
| 20120144205 | Cryptographic Architecture with Instruction Masking and other Techniques for Thwarting Differential Power Analysis - An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption. | 2012-06-07 |
| 20120144206 | INFORMATION PROCESSING APPARATUS, REMOVABLE STORAGE DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM - An information processing apparatus includes an encrypted authentication unit that obtains, as encrypted information, the estimated total capacity of a storage medium included in a removable storage device, which is the target of encrypted authentication, a storage use unit that obtains the total capacity of a storage medium to which data is written, and a determination unit that restricts the use by the storage use unit of the storage medium to which the data is written depending on whether the difference between the estimated total capacity and the total capacity is equal to or more than a predetermined threshold. | 2012-06-07 |
| 20120144207 | SYSTEMS AND METHODS FOR TRANSFORMATION OF LOGICAL DATA OBJECTS FOR STORAGE - Systems and methods for encrypting a plaintext logical data object for storage in a storage device operable with at least one storage protocol, creating, reading, writing, optimization and restoring thereof. Encrypting the plaintext logical data object comprises creating in the storage device an encrypted logical data object comprising a header and one or more allocated encrypted sections with predefined size; encrypting one or more sequentially obtained chunks of plaintext data corresponding to the plaintext logical data object thus giving rise to the encrypted data chunks; and sequentially accommodating the processed data chunks into said encrypted sections in accordance with an order said chunks received, wherein said encrypted sections serve as atomic elements of encryption/decryption operations during input/output transactions on the logical data object. | 2012-06-07 |
| 20120144208 | INDEXED TABLE BASED CODE ENCRYPTING/DECRYPTING DEVICE AND METHOD THEREOF - An indexed table based code encrypting device adapted to encrypt an executable file of a computer program includes: an index creator configured to classify codes of the executable file into code blocks using a call code and store the number of calls and start addresses of the code blocks; and a block encrypter configured to encrypt the code blocks with encryption keys. An encryption key of a code block (hereinafter, first type code block) called once is created by using a code block calling the first type code block and an encryption key of a code block (hereinafter, second type code block) called twice or more is created by using a random number. The encryption keys of the first and second type code blocks are stored in the executable file. | 2012-06-07 |
| 20120144209 | METHODS FOR PROCESS KEY ROLLOVER/RE-ENCRYPTION AND SYSTEMS THEREOF - A method according to one embodiment includes defining a new encryption band with a length that is consistent with a redundant array of inexpensive disks (RAID) parity strip; freeing a working extent in a working stride on the RAID. In an iterative process until each stride in a source band is depleted of data: marking a source extent in a source stride from which to gather data to be re-encrypted; marking parity inconsistent in the working stride in the new encryption band; performing a second iterative process; and freeing the working extent. The second iterative process is performed until each extent in a source stride is depleted of data. Additional systems, methods and computer program products are also presented. | 2012-06-07 |
| 20120144210 | ATTRIBUTE-BASED ACCESS-CONTROLLED DATA-STORAGE SYSTEM - The current application is directed to computationally efficient attribute-based access control that can be used to secure access to stored information in a variety of different types of computational systems. Many of the currently disclosed computationally efficient implementations of attribute-based access control employ hybrid encryption methodologies in which both an attribute-based encryption or a similar, newly-disclosed policy-encryption method as well as a hierarchical-key-derivation method are used to encrypt payload keys that are employed, in turn, to encrypt data that is stored into, and retrieved from, various different types of computational data-storage systems. | 2012-06-07 |
