| 23rd week of 2012 patent applcation highlights part 32 |
| Patent application number | Title | Published |
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| 20120140502 | BEAM PATTERN CHANGING STRUCTURE FOR HEAD LAMP - A beam pattern changing structure for a head lamp is provided, which includes a light source provided in the head lamp to emit light, a reflector provided in the head lamp to reflect the light irradiated through the light source, a shield provided in front of the reflector, and an actuator mounted on the shield to make the shield rotatable. Accordingly, since low beams, high beams, and diverse beam pattern regions in the beam pattern changing stages are all implemented through one light source, the driver's visibility can be maximally secured and the glare of the opposite vehicle can be prevented. Further, the designs of the head lamps for the high beams and the low beams are the same, and thus the merchantability is increased. | 2012-06-07 |
| 20120140503 | Head Lamp for Vehicle - A head lamp for the vehicle includes an upper light source for illuminating a high beam, a lower light source for illuminating a low beam, a reflector for reflecting light emitted from the upper light source and the lower light source, and a projection lens, provided at a front portion of the reflector, for illuminating the reflected light outwardly. Since the low-beam module and the high-beam/low-beam module are employed in a unitary body by using the plurality of light sources, various light distribution patterns can be formed to maximize a merchantable quality. | 2012-06-07 |
| 20120140504 | LIGHT EMITTING DEVICE, VEHICLE HEADLAMP, ILLUMINATION DEVICE, AND VEHICLE - A headlamp | 2012-06-07 |
| 20120140505 | VEHICULAR HEADLAMP - Disclosed is a vehicular headlamp which includes a lamp unit placed in a lamp unit outer case constituted by an outer cover and a lamp housing. The lamp unit includes a light emitting diode provided as a light source; a circuit substrate mounted with the light emitting diode and having a connection terminal for supplying power to the light emitting diode; a projection lens configured to project light emitted from the light emitting diode and irradiate the projected light forwardly; and a cover member placed to surround the light emitting diode and include a colored part of which an inner peripheral surface is formed as an incident surface, on which a part of the light emitted from the light emitting diode is incident, and in which a predetermined color other than a yellow color is given to a surface other than the incident surface. | 2012-06-07 |
| 20120140506 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD - A semiconductor light-emitting device and a method for manufacturing the same can include a wavelength converting layer in order to emit various colored lights including white light. The semiconductor light-emitting device can include a base board, a frame located on the base board, at least one light-emitting chip mounted on the base board, the wavelength converting layer located between an optical plate and each outside surface of the chips so as to extend toward the optical plate using a meniscus control structure, and a reflective material layer disposed at least between the frame and both side surfaces of the wavelength converting layer and the optical plate. The semiconductor light-emitting device can be configured to improve light-emitting efficiency and color variability between the light-emitting chips by using the reflective material layer as each reflector, and therefore can emit a wavelength-converted light having a high light-emitting efficiency from various small light-emitting surfaces. | 2012-06-07 |
| 20120140507 | LIGHTING UNIT - A lighting unit can form a plurality of light distribution patterns without use of a shield and without an act of shielding light from a light source. The lighting unit can include a laser diode, a fluorescent member with a fluorescent portion configured to receive blue light from the laser diode and emit white light, and a projector type lens configured to project the white light. The fluorescent member can be rotated around a rotation shaft perpendicular to the optical axis of the projector type lens and shaped such that when the fluorescent member is rotated by a predetermined angle by the driving member and viewed from the projector type lens, a plurality of contours of the fluorescent portion can be changed according to the predetermined angle. | 2012-06-07 |
| 20120140508 | VEHICLE LIGHTING DEVICE - A vehicle lighting device can include a plurality of semiconductor light-emitting devices and a projector lens configured to illuminate a front of a vehicle with light emitted from the semiconductor light-emitting devices. The projector lens can include a plurality of incidence surfaces which perform main control of light distribution, and respectively correspond to the semiconductor light-emitting devices. A single exit surface of the projector lens can include a plurality of exit regions which emits light entering through the incidence surfaces into the projector lens, wherein the exit regions provided next to each other overlap with each other. | 2012-06-07 |
| 20120140509 | Illuminated Winter Sports Board - The present invention includes an illuminated winter sports board having a deck equipped with a plurality of light emitting devices, such as LEDs, which are mounted to the deck in a distinct ornamental pattern. The LEDs are in electrical connection with an energy source, such as a rechargeable battery in a removable battery pack. In a preferred embodiment, the rechargeable battery is mounted into the deck in a removable pack which can be charged without removing it from the deck. A microcontroller may be incorporated which provides for the selective illumination of the light emitting devices, and which may pulse, flicker, or create other aesthetically pleasing illumination patterns. | 2012-06-07 |
| 20120140510 | Illuminated Sports Board - The present invention includes a skate board having a deck, a pair of trucks mounted beneath the deck and equipped with wheels. The deck is equipped with a plurality of light emitting devices, such as LEDs, which are mounted to the deck in a distinct pattern. The LEDs are in electrical connection with an energy source, such as a rechargeable battery. In a preferred embodiment, the rechargeable battery is mounted into the deck in a removable pack which can be charged without removing it from the deck. A microcontroller may be incorporated which provides for the selective illumination of the light emitting devices, and which may pulse, flicker, or create other aesthetically pleasing illumination patterns. | 2012-06-07 |
| 20120140511 | Method and system for correcting an optical beam - Embodiments of the present invention provide a system and method for shaping an annular focal spot pattern to allow for more efficient optical coupling to a small gauge optical fiber. An embodiment of the present invention can include an illumination source operable to transmit an optical beam along an optical path, an optical fiber, and a correcting element positioned in the optical path between the illumination source and the optical fiber, the correcting element configured to reshape the optical beam to increase an amount of light received by the optical fiber. | 2012-06-07 |
| 20120140512 | Backlight Module and a Wire Positioning Device Thereof - A backlight module and a wire positioning/holding device for the frame structure thereof are disclosed. The backlight module mainly includes a frame and a light source module. The light source module is disposed on the lateral side or on the bottom of the frame. The wire holding device mainly includes a main body and a winding pillar. A first guide slot is disposed on the main body, and the first guide slot has an inlet end and an outlet end. The winding pillar extends from the main body and is situated at one side of the first guide slot. The winding pillar and the main body together form a wire holding portion. The wire holding portion is disposed corresponding to the outlet end of the first guide slot to receive the wires of the light source module coming out of the outlet end. | 2012-06-07 |
| 20120140513 | LIGHT GUIDE PLATE, LIGHT GUIDE UNIT, LIGHTING DEVICE, AND DISPLAY DEVICE - An illumination device ( | 2012-06-07 |
| 20120140514 | BACK LIGHT ASSEMBLY AND DISPLAY DEVICE HAVING THE SAME - A backlight assembly and a display device having the same, the backlight assembly including a light guide panel that guides fight, a light source to generate light, being mounted to at least one end of the light guide panel, and a bottom chassis made of a reflective resin capable of reflecting light and mounted to cover a rear side of the light guide panel. | 2012-06-07 |
| 20120140515 | Methods, Systems, and Products for Illuminating Displays - Methods, systems, and products illuminate display devices. Light is injected into a waveguide and directed onto an array of picture elements. The light reflects from the array of picture elements through the waveguide, thus illuminating the array of picture elements. | 2012-06-07 |
| 20120140516 | LIGHT GUIDE DEVICE AND BACKLIGHT MODULE - The backlight module comprises a light guide device, pluralities of light sources and at least one optical film. The light guide device further contains body, first microstructures, second microstructures, flat portions and diffusive beads. The first microstructures are disposed on reflective surface. A first point and a second point are disposed at two ends of the first microstructure with a first width (P | 2012-06-07 |
| 20120140517 | ILLUMINATION DEVICE - This invention has an object to provide an illumination device capable of selecting freely the contour of the light emitting portions and the light distribution feature according to the shape of the institution installed with this device and to user's desires, suppressing light brightness differences as well as light intensity profile differences due to viewing angle upon improving the light outputting efficiency, and being manufactured with lower costs. The invented illumination device includes plural light guide plates formed with reflection dots reflecting a shape of processing dots by pressing the matrix shaped processing dots provided at an ultrasound processing horn, an LED light source for rendering LED light enter into the light guide plates, and a holding member for holding the LED light source, wherein the plural light guide plates are arranged to have a major surface having the reflection dots to be angled differently. | 2012-06-07 |
| 20120140518 | LIGHTGUIDE - Flexible unitary lightguide and a method of making the same are disclosed. The lightguide includes a structured input side that includes a first pattern having smaller features superimposed on a second pattern having larger features. The lightguide further includes a structured top surface that includes a first region and a different second region. The first region includes a plurality of discrete light extractors for extracting light that propagates within the flexible unitary lightguide by total internal reflection. The second region includes a taper portion for directing light from the structured input side to the first region. The light extractors form a periodic array that has a first period along the length of the flexible unitary lightguide. The first period is such that substantially no visible moir fringes occur when the flexible unitary lightguide is used as a backlight in a pixelated display. | 2012-06-07 |
| 20120140519 | SURFACE LIGHT SOURCE APPARATUS AND DISPLAY APPARATUS USING SAME - A surface light source apparatus capable of keeping a high in-plane brightness uniformity and a high light utilization efficiency without increasing the size of a frame, and also to provide a display apparatus including the surface light source apparatus. The surface light source apparatus includes a point light source, and a light guide plate having a hole formed near first side surface that is one side surface thereof, the hole being formed at a position where the point light source is to be arranged. The first side surface of the light guide plate has, in a portion thereof near the hole, a prism having a saw-toothed shape in a cross-section thereof parallel to a front surface of the light guide plate. | 2012-06-07 |
| 20120140520 | LIGHT EMITTING DEVICE MODULE AND BACKLIGHT UNIT INCLUDING THE SAME - Disclosed is a light emitting device module, which includes a circuit board having at least two cavities, a reflective layer formed on a surface of each cavity, and a light emitting device package disposed in each cavity. The light emitting device package includes a package body and a light emitting device disposed on the package body, the light emitting device being electrically connected to a first lead frame and a second lead frame. | 2012-06-07 |
| 20120140521 | FLAT PANEL DISPLAY - In a flat panel display, a reflector and a light guide plate are enlarged and a support section is formed on the light guide plate. A support component made of Methylsilanol Mannuronate with high stiffness is configured onto the support section and utilized for supporting a cell. After optical films are configured on the light guide plate, and between the support component, the cell is then placed on the support component. Finally, a top frame and two covers are assembled to complete the assembly of the flat panel display. | 2012-06-07 |
| 20120140522 | Reflecting structure, light-scattering member, light-guiding plate and lighting device - A reflecting structure is provided with a first surface having two side-end portions opposing each other and a plurality of light scatterers, each scattering light, formed on the first surface. In a section perpendicular to an axis located on the first surface between the two side-end portions, the height of each of the light scatterers from the first surface gets smaller from the axis toward the side-end portion. | 2012-06-07 |
| 20120140523 | DC-DC CONVERTER AND MANUFACTURING METHOD THEREOF - A DC-DC converter is driven by single high input voltage, and includes a voltage converter circuit and a control circuit. The increase of the occupied area of the DC-DC converter is suppressed. The DC-DC converter includes an input terminal to which input voltage is applied; a voltage converter circuit connected to the input terminal, and including a first transistor; a control circuit configured to control the voltage converter circuit, and including a second transistor including a silicon material in a channel formation region; and a third transistor provided between the input terminal and the control circuit, and configured to convert the input voltage into power supply voltage that is lower than the input voltage. The first transistor and the third transistor include an oxide semiconductor material in channel formation regions. The first transistor and the third transistor are stacked over the second transistor with an insulating film provided therebetween. | 2012-06-07 |
| 20120140524 | POWER SUPPLY AND ARC PROCESSING POWER SUPPLY - A power supply that performs output PWM control and PSM control. The PWM control is performed when the required output is such that a control signal is set with a larger ON pulse width than a predetermined narrow pulse width allowing for sufficient activation of switching elements in an inverter circuit and an auxiliary switching circuit. The PSM control is performed when the required output is such that the control signal for each switching element is set with a smaller ON pulse width than the predetermined narrow pulse width. The PSM control adjusts the phase of a control pulse signal so that the ON pulse is fixed to the predetermined narrow pulse width. | 2012-06-07 |
| 20120140525 | ENERGY TRANSFER ASSEMBLY WITH TUNED LEAKAGE INDUCTANCE AND COMMON MODE NOISE COMPENSATION - An energy transfer assembly with tuned leakage inductance and common mode noise compensation is disclosed. An example energy transfer assembly for use in a resonant power converter includes a first winding wound around a bobbin mounted on a magnetic core. The first winding has a first number of layers proximate to a first end along a length of the bobbin and a second number of layers proximate to a second end along the length of the bobbin. The energy transfer assembly also includes a second winding wound around the bobbin. The second winding has a third number of layers proximate to the first end along the length of the bobbin and a fourth number of layers proximate to the second end along the length of the bobbin. The first and second windings are wound around the bobbin such that at least a portion of one of the first and second windings overlaps at least a portion of an other one of the first and second windings around the bobbin. A degree of overlap between the first and second windings is non-uniform between the first and second ends along the length of the bobbin such that a ratio of the first number to the third number does not equal a ratio of the second number to the fourth number. | 2012-06-07 |
| 20120140526 | SYNCHRONOUS RECTIFIER BI-DIRECTIONAL CONVERTER - A system and method for bi-directional voltage conversion are disclosed. A charge current is received at a first voltage on a first force commutated synchronous rectifier, and the charge current is controlled by the first force commutated synchronous rectifier. An inductor is charged by the charge current, and a discharge current from the inductor is controlled by the second force commutated synchronous rectifier. | 2012-06-07 |
| 20120140527 | CONVERTING LEAKAGE CURRENT TO DC OUTPUT - A power source capable of supplying power to operate electronics of a system is disclosed. In one example, the power source takes advantage of an electrical potential difference between primary and secondary grounds. The power source can reduce system cost and power consumption. | 2012-06-07 |
| 20120140528 | FORWARD CONVERTER TRANSFORMER SATURATION PREVENTION - A power converter in one aspect limits the magnetic flux in a transformer. A control circuit included in the power converter includes a pulse width modulator, a logic circuit and a saturation prevention circuit. The saturation prevention circuit asserts a first signal when a first integral value of the input voltage reaches a first threshold value and asserts a second signal after a delay time that begins when a difference between the first integral value and a second integral value of a reset voltage of the transformer falls to a second threshold value. The logic circuit turns off the switch when the first signal is asserted, and allows the switch to turn on and off in accordance with the pulse width modulator when the second signal is asserted. | 2012-06-07 |
| 20120140529 | Energy Recirculation and Active Clamping to Improve Efficiency of Flyback or Push Pull DC to DC Converters - The present invention is a new circuit topology to improve the efficiency of a flyback or push-pull converter or any other DC/DC converter that incorporates a transformer and whose switching device's active node (drain for MOSFETs and collector for IGBTs) has no direct energy releasing path to the power supply. The present invention uses an auxiliary DC/DC converter separate from the main DC/DC converter to reroute the parasitic energy stored in the transformer's or inductor's leakage inductance, allowing for the output of the main DC/DC converter to be augmented with the energy that would otherwise be lost. The energy stored in the leakage inductance is converted and redirected to either the load side or the power supply side of the main DC/DC converter in a series or a parallel configuration. The present invention significantly increases the overall efficiency of the system by eliminating the power loss. | 2012-06-07 |
| 20120140530 | SWITCHING POWER SUPPLY APPARATUS AND IMAGE FORMING APPARATUS - A switching power supply apparatus includes a voltage holding unit which holds voltage generated in an auxiliary winding of a transformer, and a voltage detecting unit which detects voltage applied to the first switching unit. When the first switching unit operates such that voltage generated in a secondary winding of the transformer may be low, voltage is supplied from the voltage holding unit to the first switching unit in accordance with the voltage detected by the voltage detecting unit to thus turn on the first switching unit. | 2012-06-07 |
| 20120140531 | FLYBACK PRIMARY SIDE OUTPUT VOLTAGE SENSING SYSTEM AND METHOD - A method and apparatus of primary side output voltage sensing for a flyback power converter preserves secondary-side tranformer isolation without the use of opto-isolators and does not require multiple high-speed sample and hold circuits. A timing circuit measures the duration of the diode conduction interval during a first PWM control cycle and applies this measurement to set the voltage sampling time of the feedback loop during the next PWM cycle. The voltage sampling time for the next PWM cycle is configurable and may be set to occur near the middle of the diode conduction interval or near the end of the diode conduction interval. The cycle-to-cycle PWM duty cycle adjustment step size may be limited to ensure that the diode conduction interval does not vary substantially from cycle to cycle. | 2012-06-07 |
| 20120140532 | PULSE WIDTH MODULATION CONTROL METHOD AND SYSTEM FOR MITIGATING REFLECTED WAVE EFFECTS IN OVER-MODULATION REGION - Power conversion systems and methods are provided for operating a multi-phase inverter to drive a load while mitigating reflected waves, in which one or more PWM modulating signals are selectively adjusted if at least one of the phase signals or values is transitioning into or out of an over-modulation range outside a pulse width modulation carrier waveform range. | 2012-06-07 |
| 20120140533 | SOLAR PHOTOVOLTAIC SYSTEM WITH CAPACITANCE-CONVERTIBNG FUNCTION - A solar photovoltaic system with a capacitance-converting function provides a DC power source through a solar cell, and the DC power source is converted into an AC power source, thus performing a grid-connected operation with a utility power. The solar photovoltaic system further includes a capacitance conversion apparatus, a DC-to-DC converter, a DC-to-AC converter, and a filter circuit. In addition, the capacitance conversion apparatus has an inductor, a first power switch component, a second power switch component, and a capacitor, which are electrically connected to each other. Instead of the conventional electrolytic capacitor, the capacitor conversion apparatus is used to provide energy-storing, energy-releasing, and filtering functions, thus increasing the operation life of the solar | 2012-06-07 |
| 20120140534 | POWER CONVERSION SYSTEM AND COMMUNICATION ADDRESS SETTING METHOD - There is provided a power conversion system, and a photovoltaic inverter includes a communication unit that broadcast-transmits a setting request signal of a predetermined communication address. The photovoltaic inverter includes a display unit that displays the predetermined communication address indicated by the setting request signal, and an address setting unit that generates a setting completion signal indicating that the predetermined communication address has been set as the communication address of the photovoltaic inverter if an input accepting unit accepts an input such that the predetermined communication address is set. An address management unit of the photovoltaic inverter generates a setting request signal indicating a communication address other than the predetermined communication address if the setting completion signal for the predetermined communication address is received. | 2012-06-07 |
| 20120140535 | METHOD FOR OPERATING A CONVERTER CIRCUIT - A method for operating a converter circuit is provided. The converter circuit includes a converter unit and a transformer. The transformer includes at least one winding set with a primary winding and a secondary winding. The converter unit is connected, on the AC voltage side, to the primary winding of the respective winding set. In order to compensate for undesirable saturation of the transformer, the converter unit is used to deliberately apply a DC voltage to the primary winding of the respective winding set of the transformer. | 2012-06-07 |
| 20120140536 | METHOD FOR FUNCTIONALLY CHECKING A VACUUM SWITCH OF A TRACTION CONVERTER - A method for functionally checking a vacuum switch of a traction inverter having a grid-side four-quadrant chopper and a load-side pulse inverter electrically connected in parallel on the DC side by a DC intermediate circuit. The AC side of the chopper is connected to a secondary winding of a traction transformer, with the primary winding of the traction transformer connectable to an AC grid voltage by a vacuum switch. When the vacuum switch is open, the chopper is actuated precisely when the AC grid voltage is temporally located relative to the chopper input voltage, such that the amplitude of a voltage difference between the AC grid voltage and the chopper input voltage corresponds to a predetermined test voltage. It is then checked whether current flows from the AC supply grid to the chopper. The functionality of the vacuum switch can thus be checked at any time without a test device. | 2012-06-07 |
| 20120140537 | ACTIVE RECTIFICATION CONTROL - An active rectification system includes an active rectifier, a pulse width modulation (PWM) control, and a closed loop vector control. The PWM control portion is configured to control switching of the active rectifier and the closed loop vector control is configured to generate the required duty cycles for the PWM signals that regulate the DC voltage output and force a three-phase current input of the active rectifier to align with a three-phase pole voltage input of the active rectifier. | 2012-06-07 |
| 20120140538 | SYNCHRONOUS RECTIFIER BI-DIRECTIONAL CURRENT SENSOR - A method and apparatus for bi-directional current sensing for a synchronous rectifier bi-directional converter system is disclosed. A first current is measured through a first synchronous rectifier via a first transformer to provide a first signal. A second current is measured through a second force synchronous rectifier via a second transformer to provide a second signal. The first signal and the second signal are DC restored to provide a first DC restored signal and a second DC restored signal respectively. A first correction current is added to the first DC restored signal to produce a first corrected signal, and a second correction current is added to the second DC restored signal to produce a second corrected signal. The first corrected signal and the second corrected signal are added to produce a combined signal. | 2012-06-07 |
| 20120140539 | GAS COOLED TRACTION DRIVE INVERTER - The present invention provides a modular circuit card configuration for distributing heat among a plurality of circuit cards. Each circuit card includes a housing adapted to dissipate heat in response to gas flow over the housing. In one aspect, a gas-cooled inverter includes a plurality of inverter circuit cards, and a plurality of circuit card housings, each of which encloses one of the plurality of inverter cards. | 2012-06-07 |
| 20120140540 | CHARGE SHARING IN A TCAM ARRAY - A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor. | 2012-06-07 |
| 20120140541 | MEMORY BUILT-IN SELF TEST SCHEME FOR CONTENT ADDRESSABLE MEMORY ARRAY - A method and apparatus for testing a content addressable memory (CAM) array includes writing known data to the CAM array and providing comparison data to the CAM array. A determination is made whether the CAM array is operating correctly responsive to a comparison of the known data and the comparison data. | 2012-06-07 |
| 20120140542 | Arrays of Nonvolatile Memory Cells - Disclosed is an array of nonvolatile memory cells includes five memory cells per unit cell. Also disclosed is an array of vertically stacked tiers of nonvolatile memory cells that includes five memory cells occupying a continuous horizontal area of 4F | 2012-06-07 |
| 20120140543 | One Time Programming Memory and Method of Storage and Manufacture of the Same - The present invention relates to a one time programming memory and method of storage and manufacture of the same. It belongs to microelectronic memory technology and manufacture field. The one time programming memory comprises a diode ( | 2012-06-07 |
| 20120140544 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF DRIVING THE SAME - A semiconductor memory apparatus includes a resistive memory cell configured to be applied with a command voltage pulse with a different voltage level, depending upon an input command, and a feedback unit coupled between one end and the other end of the resistive memory cell, and configured to detect whether an amount of current which passes through the resistive memory cell reaches a target level and selectively form a pull-down current path for limiting an amount of current which the resistive memory cell passes, wherein the feedback unit controls the target level according to the command voltage pulse. | 2012-06-07 |
| 20120140545 | SEMICONDUCTOR DEVICE AND METHOD OF SENSING DATA OF THE SEMICONDUCTOR DEVICE - In one example embodiment, the semiconductor device includes a memory cell array having at least one memory cell disposed in a region at which at least one bit line and at least one word line cross. A sensing unit senses data stored in the at least one memory cell. The sensing unit includes a connection control unit configured to control a connection between the at least one bit line and a sensing line based on a control signal, the control signal having a voltage level that varies based on a value of data being sensed by the sensing unit. | 2012-06-07 |
| 20120140546 | Multi-Bit Resistance-Switching Memory Cell - A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell. | 2012-06-07 |
| 20120140547 | Multi-Bit Resistance-Switching Memory Cell - A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell. | 2012-06-07 |
| 20120140548 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, semiconductor memory device includes: semiconductor substrate; parallel first lines stacked on substrate; parallel second lines intersecting first lines; memory cell array including memory cells at intersections of first and second lines and each including variable resistance element and selecting element series-connected together; first control circuit provided in second region of substrate adjoining first region immediately under array; second control circuit provided in first region of substrate; and dummy lines formed in same layer as second lines, such that they intersect first lines in region above first control circuit. First control circuit applies first voltage to selected first line. Second control circuit applies second voltage lower than first voltage to selected second line, and to dummy lines, third voltage by which potential difference applied to memory cells at intersections of selected first line and dummy lines becomes lower than on-voltage of selecting element. | 2012-06-07 |
| 20120140549 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element. | 2012-06-07 |
| 20120140550 | INTEGRATED CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR DEVICE - An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop. | 2012-06-07 |
| 20120140551 | STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAGE SUPPRESSION AND LEVEL CONTROL - A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided at higher supply voltages. | 2012-06-07 |
| 20120140552 | WRITE ASSIST STATIC RANDOM ACCESS MEMORY CELL - Static random access memory (SRAM) cells are disclosed. In one example embodiment the SRAM cell includes a latch having a first node and a second node for storing bit information at the first node and a complement of the bit at the second node. The SRAM cell further includes a first switch controlled by a write operation signal, connected between a supply voltage and a first pull-up transistor of the latch and a third switch controlled the write operation signal, connected between the second node and a ground. The SRAM cell further includes a second switch controlled by the write operation signal, connected between the supply voltage and a second pull-up transistor and a fourth switch controlled by the write operation signal, connected between the second node and the ground. The write operation signals are generated by a first complex gate and a second complex gate. | 2012-06-07 |
| 20120140553 | REVERSIBLE LOW-ENERGY DATA STORAGE IN PHASE CHANGE MEMORY - A phase change memory (PCM) device utilizes low energy pulses to write data to PCM storage elements (cells). Methods, devices and systems are described that use low energy reset pulses to reset cells that have been previously set using a method that keeps a portion of the PCM cells in an amorphous phase. The reset is reversible by utilizing a low energy set pulse. | 2012-06-07 |
| 20120140554 | COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT - A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states. | 2012-06-07 |
| 20120140555 | MULTILEVEL PHASE CHANGE MEMORY OPERATION - Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed. | 2012-06-07 |
| 20120140556 | METHOD OF OPERATING FLASH MEMORY - A method of operating a flash memory is described. When a first storage site has 2 | 2012-06-07 |
| 20120140557 | PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE - Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse. | 2012-06-07 |
| 20120140558 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A control circuit applies a write pulse voltage to a selected word line to perform a write operation to 1-page memory cells along the selected word line. The circuit then performs a verify read operation to confirm whether the data write to the 1-page memory cells is completed. According to the result of the verify read operation, a step-up operation is performed out to raise the write pulse voltage by a step-up voltage. The control circuit changes the amount of the step-up voltage according to a distribution width of a first threshold voltage distribution generated in process of the write operation to the memory cells. | 2012-06-07 |
| 20120140559 | SELECTIVE MEMORY CELL PROGRAM AND ERASE - Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed. | 2012-06-07 |
| 20120140560 | METHOD AND MEMORY CONTROLLER FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY - An exemplary method for reading data stored in a flash memory includes: controlling the flash memory to perform a plurality of read operations upon each of a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from each of the memory cells as one of the bit sequences by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences. | 2012-06-07 |
| 20120140561 | MEMORY DEVICE CAPABLE OF IMPROVING WRITE PROCESSING SPEED AND MEMORY CONTROL METHOD - According to one embodiment, a memory device includes a memory unit, a first storage unit, a second storage unit, a third storage unit, a data move unit, and a controller. The first storage unit stores a logical address and an intermediate address. The second storage unit stores the intermediate address and the physical address corresponding to the intermediate address. The third storage unit stores a flag corresponding to the logical address and the intermediate address. The flag represents whether read of latest data by a read operation has succeeded. When the flag stored in the third storage unit represents a success of the read of the latest data, the controller determines whether write has been done for the same logical address of the memory unit during the data move processing, and if the write has been done, invalidates the data move processing. | 2012-06-07 |
| 20120140562 | NONVOLATILE MEMORY DEVICE AND METHOD OF MAKING THE SAME - A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors. | 2012-06-07 |
| 20120140563 | PUMP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A pump circuit includes a plurality of clock control circuits configured to transfer a clock to respective output terminals in response to respective pump-off signals or block the clock from being transferred to the respective output terminals, a plurality of charge pumps configured to generate respective high voltages by performing respective pumping operations in response to respective clock signals of the output terminals, and a plurality of switching circuits configured to transfer the respective high voltages to a final output terminal in response to respective control signals. | 2012-06-07 |
| 20120140564 | NON-VOLATILE ONE-TIME-PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY CONFIGURATION CIRCUIT - A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications. | 2012-06-07 |
| 20120140565 | Scalable Electrically Eraseable And Programmable Memory - A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor connected to a first bit line, a second non-volatile memory transistor connected to a second bit line, and a source access transistor coupled to common source line. The source access transistor includes: a first diffusion region continuous with a source region of the first non-volatile memory transistor and a second diffusion region continuous with a source region of the second non-volatile memory transistor. | 2012-06-07 |
| 20120140566 | PROGRAMMING METHOD OF NON-VOLATILE MEMORY DEVICE - A programming method includes setting the voltages of bit lines, performing a program operation, performing a program verify operation by supplying a program verify voltage and determining whether all of the memory cells of the selected page have been programmed with a target threshold voltage or higher, counting the number of passed memory cells corresponding to a number of pass bits, if, a result of the program verify operation, the program operation failed to program all of the memory cells of the selected page to the target threshold voltage or higher, and making a determination that determines whether the number of pass bits is greater than the first number of pass permission bits, and raising a voltage of a bit line coupled to a failed memory cell, if, as a result of the determination, the number of pass bits is greater than the first number of pass permission bits. | 2012-06-07 |
| 20120140567 | NAND STEP UP VOLTAGE SWITCHING METHOD - Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired. | 2012-06-07 |
| 20120140568 | Programming Memory With Reduced Pass Voltage Disturb And Floating Gate-To-Control Gate Leakage - Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states. | 2012-06-07 |
| 20120140569 | MEMORY CELL OPERATION - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses. | 2012-06-07 |
| 20120140570 | EEPROM with Increased Reading Speed - In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage V | 2012-06-07 |
| 20120140571 | ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE - An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array. | 2012-06-07 |
| 20120140572 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a switching element coupled between a power supply line and an output terminal of a power supply circuit for supplying a power supply voltage, wherein the switching element is configured to be turned on in response to a standby signal, a page buffer including a plurality of latch circuits, wherein a voltage input terminal of at least one of the latch circuits is coupled to the output terminal of the power supply circuit and a voltage input terminal of at least another one of the latch circuits is coupled to the power supply line, and a control logic circuit configured to generate the standby signal according to an operation mode of the semiconductor memory device. | 2012-06-07 |
| 20120140573 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a page buffer configured to store data received from selected memory cells in response to a read command, a first register configured to store first data received from the page buffer in response to a first control signal, a second register configured to store second data received from the page buffer in response to a second control signal, a data I/O circuit configured to, while the first or second data is outputted from the first register or the second register, respectively, input third data received from the page buffer to the other one of the first and second registers, and a control logic configured to sequentially supply the first control signal and the second control signal in outputting the first and second data. | 2012-06-07 |
| 20120140574 | NON-VOLATILE MEMORY DEVICE AND SENSING METHOD THEREOF - A non-volatile memory device is disclosed, which performs a sensing operation using a current. The non-volatile memory device includes a cell array including one or more unit cells, configured to read or write data, a current-voltage converter configured to convert a sensing current corresponding to data stored in the unit cell into a sensing voltage, and perform a precharge operation of the sensing voltage upon receiving the sensing current in response to a current driving signal at an activation time point of a word line of the cell array, and a sense-amp configured to compare the sensing voltage with a predetermined reference voltage, and amplify the compared result. | 2012-06-07 |
| 20120140575 | PROCESS TOLERANT LARGE-SWING SENSE AMPLFIER WITH LATCHING CAPABILITY - A process-tolerant large-swing sense amplifier with latching capability includes top-array and bottom-array access. The sense amplifier provides improved tolerance to process variation, reduces design complexity, reduces power consumption, and reduces the physical footprint of the circuit. In addition, the sense amplifier provides write-through functionality through the read data bus. | 2012-06-07 |
| 20120140576 | MEMORY DEVICE, TEST OPERATION METHOD THEREOF, AND SYSTEM INCLUDING THE SAME - A test operation method of a memory device is provided. The test operation method includes a reference current generator generating a reference current and providing a reference voltage generated based on the reference current to one of input terminals of a sense amplifier; providing a read voltage generated based on a read current of a memory cell to another one of the input terminals of the sense amplifier; and the sense amplifier comparing the reference voltage with the read voltage. | 2012-06-07 |
| 20120140577 | MULTI-CHIP PACKAGE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array including first memory cells for storing data and second memory cells for storing chip identification (ID) information, a data comparison circuit configured to compare input data and the stored data of the first memory cells and to output comparison data, and output circuits configured to output the comparison data received in parallel from the data comparison circuit. The comparison data is outputted through a selected one of the output circuits according to an enable signal generated based on the chip ID information. | 2012-06-07 |
| 20120140578 | SEMICONDUCTOR DEVICE HAVING PLURAL INTERNAL VOLTAGE GENERATING CIRCUITS AND METHOD OF CONTROLLING THE SAME - Such a device is disclosed that includes a terminal, a first voltage generator generating, when activated, a voltage at the terminal and stopping, when deactivated, generating the voltage, and a second voltage generator generating, when activated, the voltage at the terminal and stopping, when deactivated, generating the voltage. The first voltage generator being configured to be activated in response to a first control signal taking an active level and deactivated in response to the first control signal taking an inactive level, and the second voltage generator being configured to be activated in response to each of the first control signal and a second control signal taking an active level and deactivated in response to at least one of the first and second control signal taking an inactive level. | 2012-06-07 |
| 20120140579 | MULTI-CHIP PACKAGE AND OPERATING METHOD THEREOF - A multi-chip package includes a voltage generating circuit configured to generate a power source voltage and a plurality of memory chips coupled to the voltage generating circuit to each receive the power source voltage, wherein the memory chips are each configured to postpone an operation if the power source voltage is lower than a target voltage and perform the operation when the power source voltage reaches the target voltage. | 2012-06-07 |
| 20120140580 | INTEGRATED CIRCUIT HAVING VOLTAGE GENERATION CIRCUITRY FOR MEMORY CELL ARRAY, AND METHOD OF OPERATING AND/OR CONTROLLING SAME - A method of generating a voltage on an integrated circuit device comprising a memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit device further comprises voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, (ii) apply a second voltage to a second group of associated bit lines, (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry. | 2012-06-07 |
| 20120140581 | Multiple Cycle Memory Write Completion - A memory system that reduces the memory cycle time of a memory cell by performing an incomplete write operation. The voltage on a storage node of the memory cell does not reach a full supply voltage during the incomplete write operation. The incomplete write operation is subsequently completed by one or more additional accesses, wherein the voltage on the storage node is pulled to a full supply voltage. The incomplete write operation may be completed by: subsequently writing the same data to the memory cell during an idle cycle; subsequently writing data to other memory cells in the same row as the memory cell; subsequently reading data from the row that includes the memory cell; or refreshing the row that includes the memory cell during an idle cycle. One or more idle cycles may be forced to cause the incomplete write operation to be completed in a timely manner. | 2012-06-07 |
| 20120140582 | WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURES - A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry. | 2012-06-07 |
| 20120140583 | MULTI-CHIP MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME - A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands. | 2012-06-07 |
| 20120140584 | SEMICONDUCTOR SYSTEM, SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR INPUT/OUTPUT OF DATA USING THE SAME - A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller. | 2012-06-07 |
| 20120140585 | Retention voltage generation - An integrated circuit and method are provided, the integrated circuit comprising retention voltage generation circuitry which receives a supply voltage from a supply voltage node and provides a retention voltage at a retention voltage node. Functional circuitry is connected between the retention voltage node and a reference voltage node, the functional circuitry being held in a data retention state when at least a minimum voltage is provided between the retention voltage node and the reference voltage node. Each of the functional circuitry and the retention voltage generation circuitry comprise at least one p-type threshold device and at least one n-type threshold device, the p-type threshold devices and the n-type threshold devices respectively having a characteristic threshold voltage and the at least one p-type threshold device and the at least one n-type threshold device in the retention voltage generation circuitry being connected in parallel between the supply voltage node and the retention voltage node. A variation in the characteristic threshold voltage of either the at least one p-type threshold device or the at least one n-type threshold device in the functional circuitry is accompanied by a corresponding variation in the characteristic threshold voltage of either the at least one p-type threshold device or the at least one n-type threshold device respectively in the retention voltage generation circuitry, thus maintaining at least the minimum voltage between the retention voltage node and the reference voltage node and thus keeping the functional circuitry in the data retention state. | 2012-06-07 |
| 20120140586 | NONVOLATILE MEMORY DEVICE HAVING STACKED TRANSISTOR CONFIGURATION - A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, an address decoder that selects one of the memory blocks in response to an input address and generates a first control signal and a second control signal, a plurality of metal lines connected with the memory blocks and extending along a first direction, a plurality of pass transistors that connect the address decoder with a first subset of the metal lines connected with the selected memory block in response to the first control signal, and a plurality of ground transistors that supply a low voltage to a second subset of the metal lines connected with unselected memory blocks in response to the second control signal. The ground transistors have channels that extend along a second direction perpendicular to the first direction. | 2012-06-07 |
| 20120140587 | METHOD FOR TREATING A MONOMER, PRE-POLYMER, POLYMER OR A CORRESPONDING MIXTURE - The invention relates to a method for treating a monomer, pre-polymer, polymer or a corresponding mixture, in particular for producing a dope for producing a polymer fibre, in particular a p-aramide fibre, in which the monomer, pre-polymer, polymer, additives or a corresponding mixture is admixed with a solvent, blended, fused, homogenised and/or degassed and then discharged, which takes place at least partially in a reactor ( | 2012-06-07 |
| 20120140588 | Fluidized Mixing And Blending of Nanopowders With Secondary Gas Flow - Methods and systems for enhancing fluidization of nanoparticle and/or nanoagglomerates and for mixing and blending nanoparticle/nanoagglomerate systems at the nanoscale are provided. A fluidization chamber is provided with a fluidizing medium (e.g., a fluidizing gas) directed in a first fluidizing direction, e.g., upward into and through a bed containing a volume of nanoparticles and/or nanopowders. A second source of air/gas flow is provided with respect to the fluidization chamber, the secondary air/gas flow generally being oppositely (or substantially oppositely) directed relative to the fluidizing medium. Turbulence created by the secondary gas flow, e.g., a jet from a micro jet nozzle, is advantageously effective to aerate the agglomerates and the shear generated by the jet is advantageously effective to break apart nanoagglomerates and/or reduce the tendency for nanoagglomerates to form or reform. A downwardly directed source of secondary gas flow located near the main gas distributor leads to full fluidization of the entire amount of powder in the column. In addition, the oppositely directed fluid flow facilitates powder circulation within the fluidization chamber, thereby enhancing fluidization and mixing/blending results. | 2012-06-07 |
| 20120140589 | MIXING DEVICE HAVING A BEARING FOR A RECEIVING DEVICE - Disclosed is a mixing device for mixing, in particular, contents of laboratory vessels. The mixing device has a receiving device for receiving mixtures, a drive for setting the receiving device in a mixing movement relative to a chassis in which the receiving device moves on a closed path, and a bearing for guiding the receiving device in the mixing movement. The bearing has at least two supports, each with two bearing areas spaced apart from each other and having at least substantially no translatory and at least two rotational degrees of freedom. One bearing area bears the support at the chassis, and the other bearing area bears the receiving device at the support. The bearing has a guidance device, which guides the rotation of the receiving device relative to the chassis during the mixing movement. | 2012-06-07 |
| 20120140590 | Gravity Fed Beverage Dispenser - The present application provides a dispensing system for mixing a first fluid and a second fluid. The dispensing system may include a first fluid source with the first fluid therein, a volumetric dosing chamber in communication with the first fluid source, a vent tube extending from within the volumetric dosing chamber to about the first fluid source such that a dose of the first fluid from the first fluid source flows into the volumetric dosing chamber under the force of gravity until the first fluid reaches the vent tube, a first fluid dispensing line in communication with the volumetric dosing chamber, a second fluid source with the second fluid therein, and a second fluid dispensing line in communication with the second fluid source. The dose of the first fluid may flow through the first fluid dispensing line and the second fluid may flow through the second fluid dispensing line. | 2012-06-07 |
| 20120140591 | HOMOGENIZING MIXER - Provided is a homogenizing mixer including: a container having an internal space so that materials whose properties differ are contained therein; a fixed frame that is disposed so as to be fixed at the bottom of the container, and communicates from the inside of the container; an agitating unit that is disposed in the fixed frame, so as to be lifted up and down by medium of an lifting unit, and that agitates the materials contained in the container; a driving unit that is disposed on the bottom of the agitating unit for transferring a rotational driving force for the agitating unit; and a discharging unit that is stirred by the agitating unit and discharging a homogenized material to the outside of the mixer. | 2012-06-07 |
| 20120140592 | 3D DEGHOSTING OF MULTICOMPONENT OR OVER/UNDER STREAMER RECORDINGS USING CROSS-LINE WAVENUMBER SPECTRA OF HYDROPHONE DATA - A technique includes obtaining pressure data that was acquired by seismic sensors towed as part of a three-dimensional spread of streamers and obtaining particle motion data, which are indicative of particle motion at locations of the sensors. The technique includes estimating cross-line spectra of the pressure data based at least in part on the pressure data, and the technique includes deghosting the particle motion data based at least in part on the estimated cross-line spectra. | 2012-06-07 |
| 20120140593 | TIME-LAPSE SEISMIC COMPARISONS USING PRE-STACK IMAGING AND COMPLEX WAVE FIELD COMPARISONS TO IMPROVE ACCURACY AND DETAIL - A method, computer program product and system for improving the accuracy and detail in determining changes in properties associated with sub-surface geological structures. A first and a second time-lapse seismic data taken for a first and a second seismic survey, respectively, are received. If no calibration for the first and second time-lapse seismic data are needed, then an absolute time-lapse comparison is made. In the absolute time-lapse comparison, the time-lapse seismic data taken at a depth level below a reference level is compared with time-lapse seismic data taken at the reference level. If however, calibration is needed, then a residual time-lapse comparison is made. In the residual time-lapse comparison, the derived residual phase and amplitude differences at a depth level below the reference level are compared with the derived residual phase and amplitude differences at the reference level. | 2012-06-07 |
| 20120140594 | SEISMIC DATA APPARATUS AND METHODS - Methods and apparatus are provided related to seismic sensor data. Seismic sensor signaling is digitally sampled in accordance with a local clock and without synchronization to standardized time. Timestamp data is used to synthesize data correspondent to an artificial stimulus waveform. Cross-correlation of the synthesized data with the seismic sensor data yields a correlation result. The correlation result can be scaled to an original starting time for the seismic data sampling. The scaled correlation result can be stored in computer-accessible media and subject to further processing or interpretation. | 2012-06-07 |
| 20120140595 | ULTRASOUND PROBE AND ULTRASOUND DIAGNOSTIC APPARATUS - An ultrasound probe connected to an ultrasound diagnostic apparatus configured to transmit an ultrasound beam to a target object is provided. The ultrasound probe includes a switching unit including N/2 channels, each channel configured to switch between a first pole and a second pole, wherein N is a natural number, N/2 first transducer elements connected to the first pole and placed in two-dimensions, wherein a placement is defined in an x-axis direction and a y-axis direction, and N/2 second transducer elements connected to the second pole and placed in two-dimensions, wherein the placement is defined in the x-axis and y-axis directions, wherein a placement of a channel number of the first transducer elements and a placement of a channel number of the second transducer elements differ in the x-axis and y-axis directions. | 2012-06-07 |
| 20120140596 | METHOD AND DEVICE FOR DETECTING TARGET OBJECT - This disclosure provides a target object detection device for outwardly transmitting a detection pulse and detecting a target object based on a returned reception signal. The device includes a first peak holding module for extracting, at every predetermined cycle, a maximum value of the reception signals obtained in the predetermined cycle, a second peak holding module for extracting, at the same predetermined cycle, a minimum value of the reception signals obtained in the predetermined cycle, and a target object determiner for determining a level rising and a level falling of the reception signal indicating the target object by using a gradient between the minimum and maximum values extracted at different peak holding positions. | 2012-06-07 |
| 20120140597 | SECURITY MONITORING SYSTEM USING BEAMFORMING ACOUSTIC IMAGING AND METHOD USING THE SAME - Disclosed is a security monitoring method determining whether a trespasser is detected and a position of the trespasser in a set security space and monitoring sound generated at the position of the trespasser by using an acoustic image generated from acoustic signals generated by an acoustic generating device and an acoustic measuring device in an array type. An exemplary embodiment of the present disclosure provides a security monitoring system including: an acoustic generating device that generates acoustic signals; a plurality of acoustic measuring devices that receive the acoustic signals; and an acoustic image processing device that generates an acoustic image using a beamforming algorithm from the acoustic signals received in the plurality of acoustic measuring devices and determines a position of a trespasser by comparing the acoustic image after the trespasser is detected with the acoustic image before the trespasser is detected. | 2012-06-07 |
| 20120140598 | SIGNAL PROCESSING METHOD - A computing part computes a correlation coefficient representing a level of correlation among acoustic signals for a plurality of channels. A filtering part smoothes a time variation of the correlation coefficient computed. A center component reducer reduces a correlation component that is common in the acoustic signals by using the correlation coefficient. Then, the correlation component extracted by the reducer is reduced from each of the acoustic signals. | 2012-06-07 |
| 20120140599 | ALARM CLOCK AND METHOD FOR OPERATING SAME - An alarm clock includes a main body having a clock dial, an alarm module, a camera module, a storage member and a processor. The alarm module is attached to the main body and for sending out an alarm signal at a preset time. The camera module is rotatably mounted on the main body and for capturing a first image of a predetermined area within a viewing range thereof prior to sending out the alarm signal, and a second image after the alarm signal is sent out. The storage member is configured for storing the first image and the second image. The processor is configured for comparing the second image with the first image to determine if a person is located in the viewing range, and controlling the alarm module and the camera module to operate based on the determined result. An operating method of the alarm clock is also provided. | 2012-06-07 |
| 20120140600 | TABLE LAMP WITH ALARM CLOCK - A table lamp includes a lamp base, a clock, and a controlling module. The lamp base receives an LED module therein. The controlling module includes a timer electrically connected to the clock and a controller electrically connected to the LED module and a speaker. The timer is configured for setting an alarm time for the clock. When the clock goes to the alarm time set by the timer, the controller turns on LEDs of the LED module one by one within a desired time and turns on the speaker to generate arousal sound. | 2012-06-07 |
| 20120140601 | ELECTRONIC DEVICE PROVIDED WITH WIRELESS COMMUNICATION FUNCTION - An electronic device includes: a communication section to wirelessly communicate with an external device; a first section to make the communication section establish a wireless connection with the external device; a detective section to detect whether the electronic device is in a used condition or an unused condition; a second section to shift to a power-saving mode when the unused condition is detected for a while; and a third section to cancel the power-saving mode when the used condition is detected during the power-saving mode, wherein the second section cuts off the connection if the connection is still alive when shifting to the power-saving mode; and the third section changes a connection processing for making the first section establish the connection after the power-saving mode was canceled, based on a connecting condition from a time of detecting the last used condition to a time of shifting to the power-saving mode. | 2012-06-07 |
