| 23rd week of 2013 patent applcation highlights part 59 |
| Patent application number | Title | Published |
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| 20130145097 | Selective Access of a Store Buffer Based on Cache State - An apparatus includes a cache memory that includes a state array configured to store state information. The state information includes a state that indicates updated corresponding to a particular address of the cache memory is not stored in the cache memory but is available from at least one of multiple sources external to the cache memory, where at least one of the multiple sources is a store buffer. | 2013-06-06 |
| 20130145098 | MEMORY PREFETCH SYSTEMS AND METHODS - Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline associated with the selected memory vault is empty. | 2013-06-06 |
| 20130145099 | Method, System and Server of Removing a Distributed Caching Object - The present disclosure discloses a method, a system and a server of removing a distributed caching object. In one embodiment, the method receives a removal request, where the removal request includes an identifier of an object. The method may further apply consistent Hashing to the identifier of the object to obtain a Hash result value of the identifier, locates a corresponding cache server based on the Hash result value and renders the corresponding cache server to be a present cache server. In some embodiments, the method determines whether the present cache server is in an active status and has an active period greater than an expiration period associated with the object. Additionally, in response to determining that the present cache server is in an active status and has an active period greater than the expiration period associated with the object, the method removes the object from the present cache server. By comparing an active period of a located cache server with an expiration period associated with an object, the exemplary embodiments precisely locate a cache server that includes the object to be removed and perform a removal operation, thus saving the other cache servers from wasting resources to perform removal operations and hence improving the overall performance of the distributed cache system. | 2013-06-06 |
| 20130145100 | MANAGING METADATA FOR DATA IN A COPY RELATIONSHIP - Provided is a method for managing metadata for data in a copy relationship copied from a source storage to a target storage. Information is maintained on a copy relationship of source data in the source storage and target data in the target storage. The source data is copied from the source storage to the cache to copy to target data in the target storage indicated in the copy relationship. Target metadata is generated for the target data comprising the source data copied to the cache. An access request to requested target data comprising the target data in the cache is processed and access is provided to the requested target data in the cache. The target metadata for the requested target data in the target storage is discarded in response to determining that the requested target data in the cache has not been destaged to the target storage. | 2013-06-06 |
| 20130145101 | Method and Apparatus for Controlling an Operating Parameter of a Cache Based on Usage - A method and apparatus are provided for controlling power consumed by a cache. The method comprises monitoring usage of a cache and providing a cache usage signal responsive thereto. The cache usage signal may be used to vary an operating parameter of the cache. The apparatus comprises a cache usage monitor and a controller. The cache usage monitor is adapted to monitor a cache and provide a cache usage signal responsive thereto. The controller is adapted to vary the operating parameter of the cache in response to the cache usage signal. | 2013-06-06 |
| 20130145102 | MULTI-LEVEL INSTRUCTION CACHE PREFETCHING - One embodiment of the present invention sets forth an improved way to prefetch instructions in a multi-level cache. Fetch unit initiates a prefetch operation to transfer one of a set of multiple cache lines, based on a function of a pseudorandom number generator and the sector corresponding to the current instruction L1 cache line. The fetch unit selects a prefetch target from the set of multiple cache lines according to some probability function. If the current instruction L1 cache | 2013-06-06 |
| 20130145103 | REDUCING SEQUENCE CACHE LATCH CONTENTION IN A DATABASE SYSTEM - In a database system having a plurality of concurrently executing session processes, the method commences by establishing a master list of sequences, the master list comprising a plurality of sequence objects which in turn define a sequence of values used for numbering and other identification within the database system. To reduce sequence cache latch access contention, multiple tiers of latches are provided. Methods of the system provide a first tier having a first tier “global” latch to serialize access to the master list such that at any point in time, only one of the concurrently executing session processes is granted access to the master list, from which master list are allocated sequences on demand. A second tier of latches is provided, the second tier having multiple second tier latches to serialize access to corresponding allocated sequences of values such that at any point in time, only one of the concurrently executing session processes is granted access to the allocated sequence. The multiple tiers serve to reduce the likelihood of contention to the first tier latch. | 2013-06-06 |
| 20130145104 | METHOD AND APPARATUS FOR CONTROLLING CACHE REFILLS - A method and apparatus are provided for controlling a cache. The cache includes a plurality of storage locations, each having a priority associated therewith, and wherein the cache evicts data from one or more of the storage locations based on the priority associated therewith. The method comprises: storing historical information regarding data being evicted from the cache; retrieving data from a secondary memory in response to a miss in the cache; assigning a priority to the retrieved data based on the historical information; and storing the retrieved data in the cache with an indication of the assigned priority. | 2013-06-06 |
| 20130145105 | Data Storage Systems and Methods - Example data storage systems and methods are described. In one implementation, a method identifies data to be written to a shared storage system that includes multiple storage nodes. The method communicates a write operation vote request to each of the multiple storage nodes. The write operation vote request is associated with a data write operation to write the identified data to the shared storage system. A positive response is received from at least a portion of the multiple storage nodes. The data write operation is initiated in response to receiving positive responses from a quorum of the storage nodes. | 2013-06-06 |
| 20130145106 | COMMAND PORTAL FOR SECURELY COMMUNICATING AND EXECUTING NON-STANDARD STORAGE SUBSYSTEM COMMANDS - A command portal enables a host system to send non-standard or “vendor-specific” storage subsystem commands to a storage subsystem using an operating system (OS) device driver that does not support or recognize such non-standard commands. The architecture thereby reduces or eliminates the need to develop custom device drivers that support the storage subsystem's non-standard commands. To execute non-standard commands using the command portal, the host system embeds the non-standard commands in blocks of write data, and writes these data blocks to the storage subsystem using standard write commands supported by standard OS device drivers. The storage subsystem extracts and executes the non-standard commands. The non-standard commands may alternatively be implied by the particular target addresses used. The host system may retrieve execution results of the non-standard commands using standard read commands. The host-side functionality of the command portal may be embodied in an API that is made available to application developers. | 2013-06-06 |
| 20130145107 | IDLE POWER CONTROL IN MULTI-DISPLAY SYSTEMS - A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for the multiple display devices utilizes multiple channels for higher bandwidth. A systems controller within the graphics processor determines a retraining condition, such as an idle power state, is satisfied for one or more channels of the multiple memory channels. The graphics processor divides each respective screen for the multiple display devices into multiple horizontal bars. For each one of the multiple horizontal bars, the corresponding data may be rearranged from being distributed across the multiple channels to being stored in a single one of the multiple channels. The systems controller determines a given channel is an upcoming free channel. This free channel is retrained while it is free. Retraining may include at least reducing its memory clock (MCLK) frequency. | 2013-06-06 |
| 20130145108 | ADVANCING AND REWINDING A REPLAYED PROGRAM EXECUTION - In an embodiment, a data processing system comprises a storage system coupled to a unit under test comprising a heap memory, a static memory and a stack; second logic operable to perform: detecting one or more changes in a first state of the heap memory and the static memory; storing, in the storage system, as a state point of the unit under test, the one or more changes in the first state of the heap memory and the static memory; third logic operable to perform: receiving a request to change the memory under test to a particular state point; in response to the request, loading the particular state point from the storage system and applying the particular state point to the heap memory and the static memory to result in changing the heap memory and the static memory to a second state that is substantially equivalent to the first state. | 2013-06-06 |
| 20130145109 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND STORAGE MEDIUM - The invention relates to an information processing apparatus which performs mirroring for synchronizing storage contents of a first storage unit and a second storage unit. If mirroring is valid when the information processing apparatus is started, the information processing apparatus detects a storage unit attached to itself. If a detection result indicates that no storage unit has been detected or one storage unit has been detected, the information processing apparatus displays, on a display unit, a connection acknowledgement screen for the storage unit which has not been detected. If the detection result indicates that two storage units have been detected, activation processing is executed for the information processing apparatus. | 2013-06-06 |
| 20130145110 | STORAGE CONTROLLER AND DATA MANAGEMENT METHOD - This storage controller providing a volume for storing data transmitted from a host system includes a management unit for managing the data written in the volume with a first block area, or a second block area in the first block area which is smaller than the first block area; a snapshot acquisition unit for acquiring a snapshot of the volume at a prescribed timing; and a transfer unit for transferring the data of the volume acquired with the snapshot of the snapshot acquisition unit to an external device with the first block area or the second block area. | 2013-06-06 |
| 20130145111 | MEMORY CONTROL DEVICE, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD FOR MEMORY CONTROL DEVICE - When the number of memories in memory clusters ( | 2013-06-06 |
| 20130145112 | TIME MANAGED READ AND WRITE ACCESS TO A DATA STORAGE DEVICE - Time managed read and write access to a data storage device. As a part of time managed read and write access to a data storage device, a request for read and/or write access to the data storage device is accessed and it is determined whether the request for read and/or write access to the data storage device is to be granted. Based on the determination, read and/or write access to the data storage device is either allowed or blocked. If read and/or write access is allowed, read and/or write access is terminated after passage of a predetermined period of time. | 2013-06-06 |
| 20130145113 | MEMORY PINNING THROUGH BUFFER ENCAPSULATION - The present invention extends to methods, systems, and computer program products for memory pinning through buffer encapsulation. Within a managed execution environment, a wrapper object encapsulates a memory buffer that is to be shared with a native routine executing in a native execution environment. The wrapper object manages operation of a memory manager on a memory heap corresponding to the memory buffer. The wrapper object includes a first function which sets a pin on the memory buffer and returns a pointer identifying the memory buffer. Setting the pin causes the memory manager to cease moving the memory buffer within the memory heap. The wrapper object also includes a second function which releases the pin on the memory buffer. | 2013-06-06 |
| 20130145114 | CONTROL OF PAGE ACCESS IN MEMORY - The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters. | 2013-06-06 |
| 20130145115 | SPATIAL EXTENT MIGRATION FOR TIERED STORAGE ARCHITECTURE - Provided are techniques for migrating a first extent, determining a spatial distance between the first extent and a second extent, determining a ratio of a profiling score of the second extent to the spatial distance, and, in response to determining that the ratio exceeds a threshold, migrating the second extent. | 2013-06-06 |
| 20130145116 | COMPACTING DISPERSED STORAGE SPACE - A method begins by a processing module identifying a first storage space zone that includes a plurality of deleted encoded data slices and a plurality of active encoded data slices. The method continues with the processing module determining to compact the first storage space zone based on a function of the plurality of deleted encoded data slices and the plurality of active encoded data slices. The method continues with the processing module retrieving the plurality of active encoded data slices from the first storage space zone, identifying a second storage space zone, storing the plurality of active encoded data slices in the second storage space zone, and erasing the plurality of deleted encoded data slices and the plurality of active encoded data slices from the first storage space zone when the first storage space zone is to be compacted. | 2013-06-06 |
| 20130145117 | COORDINATING WRITE SEQUENCES IN A DATA STORAGE SYSTEM - According to one aspect of the present disclosure, a system and technique for coordinating write sequences in a data storage system includes a processor configured to receive from a primary device, responsive to the primary device receiving a request to write to primary storage, a request for a sequence number. The system also includes a sequence generator configured to: generate a current sequence number for the write; generate a first identifier indicating an identity of secondary devices writing to secondary storage based on the current sequence number; generate a second identifier indicating an identity of secondary devices writing to secondary storage based on the current sequence number and a previous sequence number; transmit the current sequence number and the second identifier to the primary device; and transmit the current sequence number and the first identifier to the secondary devices writing to secondary storage based on the previous sequence number. | 2013-06-06 |
| 20130145118 | Virtual Storage Mirror Configuration in Virtual Host - A method for configuring mirrors of virtual storage devices in a virtual host includes obtaining a topology connection relationship between the virtual storage devices to be configured with mirrors and the virtual host, where the topology connection relationship is a hierarchical relationship in a tree shape with the virtual host as a root node and the virtual storage devices to be configured with mirrors as leaf nodes, and configuring the mirrors of the virtual storage devices to be configured with mirrors in the virtual host according to the obtained topology connection relationship. The method and the system for configuring mirrors of virtual storage devices in a virtual host can increase reliability. | 2013-06-06 |
| 20130145119 | Determining A Desirable Number Of Segments For A Multi-Segment Single Error Correcting Coding Scheme - A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement. | 2013-06-06 |
| 20130145120 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 2013-06-06 |
| 20130145121 | DYNAMICALLY CONFIGURABLE PLACEMENT ENGINE - A stream application may allocate processing elements to one or more compute nodes (or hosts) to achieve a desired optimization goal. Each optimization mode may define processing element selection criteria and/or host selection criteria. When allocating a processing element to a host, a scheduler may place each processing element individually. Accordingly, the scheduler may use the processing element selection criteria for selecting which processing element in the stream application to allocate next. The scheduler may then determine, based on one or more constraints, which host the processing element can be placed on. If the scheduler determines that multiple hosts are suitable candidates for the processing element, it may use the host selection criteria to pick one of the candidate hosts that further optimize the stream application to meet the desired goal. Examples of different optimization goals that may be achieved using processing element and host selection criteria include optimizing performance, decreasing maintenance and operating costs, increasing solvability, sharing limited computer resources with other applications, and the like. | 2013-06-06 |
| 20130145122 | INSTRUCTION PROCESSING METHOD OF NETWORK PROCESSOR AND NETWORK PROCESSOR - The present invention provides an instruction processing method of a network processor and a network processor. The method includes: when executes a pre-added combined function call instruction, adding an address of its next instruction to a stack top of a first stack; judging, according to the combined function call instruction, whether an enable flag of each additional feature is enabled, and if enabled, adding a function entry address corresponding to an additional feature to the stack top of the first stack; and after finishing judging all enable flags, popping a function entry address in the first stack, and executing a function corresponding to a popped function entry address until the address of the next instruction is popped. In the present invention, only one judgment jump instruction needs to be added to a main line procedure to implement function call of enabled additional features, which saves an instruction execution cycle. | 2013-06-06 |
| 20130145123 | Computing Core Application Access Utilizing Dispersed Storage - A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to fetch an instruction from the processing module and determines whether the instruction is currently stored in the main memory. When the instruction is not currently stored in the main memory, the memory controller determines whether the instruction is stored in a distributed storage network (DSN) memory as one or more sets of encoded instruction slices; and, when it is, the memory controller addresses the DSN memory to retrieve the one or more sets of encoded instruction slices. When at least a threshold number of encoded instruction slices are retrieved for each of the one or more sets of encoded instruction slices, the one or more sets of encoded instruction slices are decoded using a dispersed storage error coding function to reconstruct the instruction, which is provided to the processing module. | 2013-06-06 |
| 20130145124 | SYSTEM AND METHOD FOR PERFORMING SHAPED MEMORY ACCESS OPERATIONS - One embodiment of the present invention sets forth a technique that provides an efficient way to retrieve operands from a register file. Specifically, the instruction dispatch unit receives one or more instructions, each of which includes one or more operands. Collectively, the operands are organized into one or more operand groups from which a shaped access may be formed. The operands are retrieved from the register file and stored in a collector. Once all operands are read and collected in the collector, the instruction dispatch unit transmits the instructions and corresponding operands to functional units within the streaming multiprocessor for execution. One advantage of the present invention is that multiple operands are retrieved from the register file in a single register access operation without resource conflict. Performance in retrieving operands from the register file is improved by forming shaped accesses that efficiently retrieve operands exhibiting recognized memory access patterns. | 2013-06-06 |
| 20130145125 | Bitstream Buffer Manipulation With A SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 2013-06-06 |
| 20130145126 | REGISTER MAPPING WITH MULTIPLE INSTRUCTION SETS - A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file | 2013-06-06 |
| 20130145127 | ZERO VALUE PREFIXES FOR OPERANDS OF DIFFERING BIT-WIDTHS - A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilised for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption. | 2013-06-06 |
| 20130145128 | PROCESSING CORE WITH PROGRAMMABLE MICROCODE UNIT - A method and circuit arrangement utilize a programmable microcode unit that is capable of being programmed via software to modify the instruction sequences output by the microcode unit in response to microcode instructions issued to the microcode unit. Among other benefits, a programmable microcode unit consistent with the invention enables customization of a processor design to handle specific applications or tasks, as well as to support specific hardware configurations such as specific execution units. In addition, a programmable microcode unit may be updatable, e.g., to correct bugs or faults found in previous instruction sequences supported by the unit. | 2013-06-06 |
| 20130145129 | REGISTER RENAMING DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING REGISTER RENAMING - A data processing apparatus and method are provided. A processor performs data processing operations in response to data processing instructions which reference logical registers. A set of physical registers stores data values which are subjected to the data processing operations. A tag storage stores for each physical register a tag value indicative of one of the logical registers. The processor references the tag storage to perform the data processing operations. A tag value exchanger performs a tag switch exchanging two tag values in the tag storage when the processor executes a predetermined instruction which references two logical registers and for which a choice of which two physical registers are mapped to which of the two logical registers will have no effect on an outcome of the data processing operations. The tag value exchanger performs the tag switch with respect to the tag values indicative of the two logical registers. | 2013-06-06 |
| 20130145130 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING REGISTER RENAMING WITHOUT ADDITIONAL REGISTERS - The data processing apparatus (and method) has processing circuitry for performing data processing operations in response to data processing instructions, the data processing instructions referencing logical registers. A set of physical registers are provided for storing data values for access by the processing circuitry when performing the data processing operations. Register renaming storage stores a one-to-one mapping between the logical registers and the physical registers, with the register renaming storage being accessed by the processing circuitry when performing the data processing operations in order to map the referenced logical registers to corresponding physical registers. Update circuitry is arranged to identify the physical registers corresponding to those multiple logical registers in the register renaming storage. Altered one-to-one mapping between multiple logical registers and identified physical registers is employed when performing the current data processing operation. | 2013-06-06 |
| 20130145131 | Flexible Microprocessor Register File - Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control. | 2013-06-06 |
| 20130145132 | STATICALLY SPECULATIVE COMPILATION AND EXECUTION - A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the speculative static information in an instruction set architecture of a processor, and executing a compiled computer program using the speculative static information, wherein executing supports static speculation driven mechanisms and controls. | 2013-06-06 |
| 20130145133 | PROCESSOR, APPARATUS AND METHOD FOR GENERATING INSTRUCTIONS - A processor, apparatus and method to use a multiple store instruction based on physical addresses of registers are provided. The processor is configured to execute an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating apparatus is configured to generate an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating method includes detecting a code area that instructs to store data of a plurality of registers in a memory, from a program code. The instruction generating method further includes generating an instruction corresponding to the code area by mapping physical addresses of the registers to a first area of the instruction. | 2013-06-06 |
| 20130145134 | SYSTEM AND METHOD FOR PERFORMING A BRANCH OBJECT CONVERSION TO PROGRAM CONFIGURABLE LOGIC CIRCUITRY - A method and system are provided for deriving a resultant software code from an originating ordered list of instructions that does not include overlapping branch logic. The method may include deriving a plurality of unordered software constructs from a sequence of processor instructions; associating software constructs in accordance with an original logic of the sequence of processor instructions; determining and resolving memory precedence conflicts within the associated plurality of software constructs; resolving forward branch logic structures into conditional logic constructs; resolving back branch logic structures into loop logic constructs; and/or applying the plurality of unordered software constructs in a programming operation by a parallel execution logic circuitry. The resultant plurality of unordered software constructs may be converted into programming reconfigurable logic, computers or processors, and also by means of a computer network or an electronics communications network. | 2013-06-06 |
| 20130145135 | PERFORMANCE OF PROCESSORS IS IMPROVED BY LIMITING NUMBER OF BRANCH PREDICTION LEVELS - A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread). for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribe threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold. | 2013-06-06 |
| 20130145136 | HANDLING EXCEPTIONS IN A DATA PARALLEL SYSTEM - A method of handling exceptions in a data parallel system includes forwarding exceptions thrown by concurrent worker tasks to a coordination task. The thrown exceptions are aggregated into an aggregation exception structure. It is determined whether the aggregation exception structure will be handled by an exception handler. The concurrent worker tasks are unwound when it is determined that the aggregation exception structure will be handled. | 2013-06-06 |
| 20130145137 | Methods and Apparatus for Saving Conditions Prior to a Reset for Post Reset Evaluation - A processor reset control circuit is configured to automatically capture a pre-reset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs. | 2013-06-06 |
| 20130145138 | METHODS AND DEVICES FOR CONFIGURING A DEVICE BASED ON PERSONAL IDENTIFICATION INFORMATION - Methods and electronic devices for configuring an electronic device based on personal identification information are described. In one example aspect, the method may include: obtaining personal identification information in a first application; and based on the personal identification information and one or more predetermined rules, determining if a second application should be loaded onto the electronic device. | 2013-06-06 |
| 20130145139 | REGULATING ACCESS USING INFORMATION REGARDING A HOST MACHINE OF A PORTABLE STORAGE DRIVE - Described herein are techniques for regulating access to a portable storage drive, that stores an operating system securely, using information regarding a host machine. In accordance with some of the techniques described herein, when a portable storage drive that stores an operating system securely is to be accessed by a host machine, information regarding the host machine, such as information regarding the hardware of the host machine, may be retrieved and evaluated to determine whether to grant access to the host machine. When the host machine is granted access, the host machine may access secured data stored on the portable storage drive in any suitable manner. In some cases, accessing the secured data may include decrypting the secured data and transferring decrypted data to another storage of the host machine. The decrypted information may include an operating system that is booted by the host machine. | 2013-06-06 |
| 20130145140 | SYSTEM AND METHOD FOR TEMPORARY SECURE BOOT OF AN ELECTRONIC DEVICE - The invention discloses system and method of temporary secure boot process of an electronic device. The method comprises: generating a first token according to an identification data of the electronic device; sending a request along with the first token to a service provider, the request corresponding to a boot package; receiving a second token and a boot package from the service provider; verifying the second token and the boot package; and executing the boot package according to verification result. | 2013-06-06 |
| 20130145141 | INFORMATION PROCESSING APPARATUS AND UPDATE PROCESS SUPPORT SYSTEM - An information processing apparatus includes a storage unit that stores reboot necessity information for respective versions of programs that are install targets of an electronic device, the reboot necessity information indicating whether the electronic device needs to be rebooted when a first program of a first version installed in the electronic device is updated to a second program of a second version; an extracting unit that extracts difference information indicating a difference between the first program and the second program in response to a request to acquire the second program, the request specifying the first version of the first program; a determining unit that determines whether the electronic device needs to be rebooted when the second program is installed, based on the difference between the first version and the second version indicated in the difference information and the reboot necessity information; and a responding unit that returns a determination result. | 2013-06-06 |
| 20130145142 | COMPUTER DEVICE SEPARABLE INTO MULTIPLE SUB-COMPUTERS - A method for separating a dividable computer device into multiple sub-computers may include receiving, by the dividable computer device, a command to separate a sub-computer from the dividable computer device. The method may also include detecting by the dividable computer device separation of the sub-computer and reconfiguring the dividable computer device for operation without the separated sub-computer in response to each sub-computer being separated. | 2013-06-06 |
| 20130145143 | COMPUTER DEVICE SEPARABLE INTO MULTIPLE SUB-COMPUTERS - A method for separating a dividable computer device into multiple sub-computers may include receiving, by the dividable computer device, a command to separate a sub-computer from the dividable computer device. The method may also include detecting by the dividable computer device separation of the sub-computer and reconfiguring the dividable computer device for operation without the separated sub-computer in response to each sub-computer being separated. | 2013-06-06 |
| 20130145144 | SWITCHING BETWEEN MOBILE USER INTERFACES FOR PERSONAL AND WORK ENVIRONMENTS - One or more embodiments of the invention facilitate switching between a host environment of a mobile device and a guest environment of the mobile device. One method comprises configuring the host environment to launch a user interface (UI) proxy application upon receiving an indication by a user on a user interface (UI) of the mobile device of a desire to switch from the host environment to the guest environment. Upon a launch of the UI proxy application as a result of receiving the indication, the UI proxy application initiates a request to wake-up the guest environment and facilitates access by a hardware framebuffer of the mobile device to contents of a memory buffer that is updated with display data for the guest environment as a result of a waking-up of the guest environment. | 2013-06-06 |
| 20130145145 | SYSTEM AND METHOD OF SECURING DATA USING A SERVER-RESIDENT KEY - A system and method for increasing security of data is presented. This system uses a remote server to increase the security of locally stored data, even in the presence of physical and software security threats. This method is significantly bolstered when at least a small portion of memory on the local machine used to temporarily store the encryption key is safe from physical and software attacks and can be further bolstered if user-interaction is required upon authentication. | 2013-06-06 |
| 20130145146 | SYSTEMS AND METHODS FOR BULK ENCRYPTION AND DECRYPTION OF TRANSMITTED DATA - A method for using a network appliance to efficiently buffer and encrypt data for transmission includes: receiving, by an appliance via a connection, two or more SSL records comprising encrypted messages; decrypting the two or more messages; buffering, by the appliance, the two or more decrypted messages; determining, by the appliance, that a transmittal condition has been satisfied; encrypting, by the appliance in response to the determination, the first decrypted message and a portion of the second decrypted message to produce a third SSL record; and transmitting, by the appliance via a second connection, the third record. Corresponding systems are also described. | 2013-06-06 |
| 20130145147 | Content Protection Method - A method for protecting content to be distributed to a pool of receiving terminals connected to a content distribution network and each having a specific security level depending on the technical securing means used, the method comprising the following steps:
| 2013-06-06 |
| 20130145148 | PASSCODE RESTORATION - A system method that includes providing a passcode to a user based on presentation of both a recovery key and an active token is described herein. | 2013-06-06 |
| 20130145149 | AUTHENTICATION DEVICE, AUTHENTICATION METHOD AND COMPUTER READABLE MEDIUM - There is provided an authentication device in which a network access authenticating unit executes a first network access authentication process with a communication device; master key generator generates a first master key shared with the communication device in accordance with a result of the first network access authentication process; an application-oriented encryption key generator generates a first encryption key for an application, which is shared with the communication device, on the basis of the first master key; a master key identifier determiner determines an identifier of the first master key; and an application-oriented encryption key identifier determiner determines an identifier of the first encryption key for the application in accordance with the identifier of the first master key. | 2013-06-06 |
| 20130145150 | CODE SIGNING SYSTEM AND METHOD - A novel code signing system, computer readable media, and method are provided. The code signing method includes receiving a code signing request from a requestor in order to gain access to one or more specific application programming interfaces (APIs). A digital signature is provided to the requestor. The digital signature indicates authorization by a code signing authority for code of the requestor to access the one or more specific APIs. In one example, the digital signature is provided by the code signing authority or a delegate thereof. In another example, the code signing request may include one or more of the following: code, an application, a hash of an application, an abridged version of the application, a transformed version of an application, a command, a command argument, and a library. | 2013-06-06 |
| 20130145151 | Derived Certificate based on Changing Identity - A first device with a changing identity establishes a secure connection with a second device in a network by acting as its own certificate authority. The first device issues itself a self-signed root certificate that binds an identity of the first device to a long-term public key of the first device. The root certificate is digitally signed using a long-term private key, where the long-term public key and the long-term private key form a public/private key pair. The first device provides its root certificate to the second device in any trusted manner. The first device can then create a certificate for one or more short-term identities acquired by the first device and sign the newly-created certificate using the long-term private key. The first device can authenticate itself to the second device by sending the newly-created certificate to the second device. | 2013-06-06 |
| 20130145152 | SECURE PREFIX AUTHORIZATION WITH UNTRUSTED MAPPING SERVICES - In one embodiment, a first router associated with a first network node sends a first map lookup that includes a particular device identifier associated with a second network node to a mapping service that maintains a plurality of mappings that associate device identifiers with device locations. The first router receives, from a second router associated with the second network node, a map response that includes a particular device location that corresponds to the particular device identifier for the second network node. The first router establishes a secure session with the second router, and determines, based on the secure session, whether the second router is authorized to reply for the particular device identifier associated with the second network node. | 2013-06-06 |
| 20130145153 | METHOD AND DEVICE FOR SECURE NOTIFICATION OF IDENTITY - A system, methods and devices for the secure notification of an identity in a communications network. The methods include sending or receiving a communication including a hash of a certificate of a device to notify or detect the presence of the device in a network. Each certificate is associated with an identity which is excluded from the communication of the hash of the certificate. The received hash is compared to hashes of certificates stored in an electronic device to determine an identity. The identity may represent an electronic device or a user of the electronic device. | 2013-06-06 |
| 20130145154 | GAMING MACHINE CERTIFICATE CREATION AND MANAGEMENT - Methods and systems for creating and managing certificates for gaming machines in a gaming network using a portable memory device. A gaming machine creates a certificate signing request which is stored on a portable memory device at the machine. Then, the memory device is coupled with an appropriate CA server. A certificate batch utility program on the server downloads and processes the CSRs. A certificate services program on the server issues gaming machine certificates according to the CSRs. In one embodiment, the certificates are uploaded onto the memory device, along with copies of certificate authority server certificates, including a root CA certificate. Then, the memory device is coupled with the gaming machine and software on the machine identifies and downloads its certificate based on the certificate file name. | 2013-06-06 |
| 20130145155 | PROVISIONING MULTIPLE DIGITAL CERTIFICATES - A method of provisioning a first digital certificate and a second digital certificate based on an existing digital certificate includes receiving information related to the existing digital certificate. The existing digital certificate includes a first name listed in a Subject field and a second name listed in a SubjectAltName extension. The method also includes receiving an indication from a user to split the existing digital certificate and extracting the first name from the Subject field and the second name from the SubjectAltName extension of the existing digital certificate. The method further includes extracting the public key from the existing digital certificate, provisioning the first digital certificate with the first name listed in a Subject field of the first digital certificate and the public key, and provisioning the second digital certificate with the second name listed in a Subject field of the second digital certificate and the public key. | 2013-06-06 |
| 20130145156 | SYSTEMS AND METHODS FOR CREDENTIALING - A method includes issuing non-unique credentials to an operations management agent (“the agent”). The method further includes establishing a first encrypted communication channel between an operations management server (“the server”) and the agent based on the non-unique credentials. The method further includes issuing, automatically based on the establishing, unique credentials to the agent. The method further includes replacing, automatically based on the issuing of the unique credentials, the first encrypted communication channel with a second encrypted communication channel that is based on the unique credentials. | 2013-06-06 |
| 20130145157 | SYSTEM AND METHOD FOR ADJUSTING THE FREQUENCY OF UPDATING CERTIFICATE REVOCATION LIST - A method for adjusting the frequency of updating certificate revocation list is provided. The method is used in a certificate authority. The method includes: receiving a first information indicating security levels from neighbor certificate authorities in a neighborhood or a central certificate authority; detecting whether the certificate authority has received a signal indicating that a user is using a revoked certificate and generating a second information of a security level; calculating an index value or a set of index values by the first information indicating the security levels of neighborhoods and the second information indicating its own security level; and adjusting the update frequency of updating the certificate revocation list according to the calculated index values or the set of index values. | 2013-06-06 |
| 20130145158 | System and Web Security Agent Method for Certificate Authority Reputation Enforcement - Network security administrators are enabled to revoke certificates with their customizable certificate authority reputation policy store which is informed by an independent certificate authority reputation server when a CA is deprecated or has fraudulent certificate generation. The custom policy store overrides trusted root certificate stores accessible to an operating system web networking layer or to a third party browser. Importing revocation lists or updating browsers or operating system is made redundant. The apparatus protects an endpoint from a man-in-the-middle attack when a certificate authority has lost control over certificates used in TLS. | 2013-06-06 |
| 20130145159 | TERMINAL APPARATUS FOR TRANSMITTING OR RECEIVING A SIGNAL CONTAINING PREDETERMINED INFORMATION - A modem unit and the like receive packets sent from a base station apparatus and receives packets sent from other terminal apparatuses. A processing unit processes the received packets. For the packets received by the modem unit and the like from the base station apparatus, a private key complying with a public key cryptosystem is used for a digital signature, whereas a symmetric key complying with a symmetric key cryptosystem is used for data. For the packets received from the other terminal apparatuses, a symmetric key complying with the symmetric key cryptosystem is used for the digital signature. | 2013-06-06 |
| 20130145160 | SYSTEM AND METHOD FOR MOUNTING ENCRYPTED DATA BASED ON AVAILABILITY OF A KEY ON A NETWORK - A system and a method are provided for retrieving decryption keys from a secure location that is separate from the encrypted data. In particular, for each decryption key, there is an associated key ID, public and private authentication key pair and a storage key. The decryption key is encrypted and can be decrypted with the storage key. A key-server securely stores the encrypted decryption key, key ID and public authentication key. A separate key-host stores the storage key, key ID and private authentication key. For the key-host to retrieve the encrypted decryption key, the key-server first authenticates the key-host using the authentication keys. Upon receipt of the encrypted decryption key, the key-host decrypts the encrypted key using the storage key. The decryption key is then used for decrypting the encrypted data. | 2013-06-06 |
| 20130145161 | DIGITAL RIGHTS MANAGEMENT OF STREAMING CONTENTS AND SERVICES - Managing digital rights of contents and services streamed to a client device, including: receiving and validating a certificate from the client device; enabling the client device to log into and communicate with a server using a secure protocol to establish a private relationship between the client device and the server; and transmitting a resource identifier to the client device using the secure protocol when the private relationship is established. | 2013-06-06 |
| 20130145162 | DEVICE AND AUTHENTICATION METHOD THEREFOR - According to one embodiment, a device includes first and second data generator, a one-way function processor, and a data output interface. The first data generator generates a second key by encrypting a host constant with a first key in AES operation. The second data generator generates a session key by encrypting a random number with a second key in AES operation. The one-way function processor generates authentication information by processing secret identification information with the session key in one-way function operation. The data output interface outputs the encrypted secret identification information, a family key block, and the authentication information to outside of the device. | 2013-06-06 |
| 20130145163 | NEAR FIELD REGISTRATION OF HOME SYSTEM AUDIO-VIDEO DEVICE - A near field communication (NFC) sticker which stores a key is attached to a new client device. A remote commander in a home network reads the key using a NFC interface and IR-transmits it to a home network server. Once the client is connected to the network, it encrypts its own device information with the key and sends the encrypted information to the server, which decrypts the data with the key sent from the remote commander. In this way, client device registration is executed easily and securely. | 2013-06-06 |
| 20130145164 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a device includes a first memory area to store a first key. A second memory area stores encrypted secret identification (ID) information generated from secret ID information with a family key. A third memory area stores a family key block including data generated from the family key with an ID key. An authentication module performs authentication. A second key is generated from a first number with the first key, a session key is generated from a random number with the second key, and authentication information is generated from the secret ID information with the session key. The encrypted secret ID information, family key block and the authentication information is output. | 2013-06-06 |
| 20130145165 | METHOD OF SENDING A SELF-SIGNED CERTIFICATE FROM A COMMUNICATION DEVICE - A method of sending a self-signed certificate from a communication device, the self-signed certificate being signed by the communication device. The method includes: receiving a communication in relation to establishing a session from a second communication device in proximity to said communication device, outputting on an output device of said communication device a certificate hash of the self-signed certificate or an address of where to obtain the certificate hash, and sending the self-signed certificate to said second communication device. The method may also include sending a broadcast message to announce a presence of the communication device. | 2013-06-06 |
| 20130145166 | SYSTEM AND METHOD FOR DATA AUTHENTICATION AMONG PROCESSORS - The invention discloses system and method for data authentication among processors. The method comprises: generating a first key, by a first processor, according to a first identification data and a first algorithm; generating a first digest, by the first processor, according to data to be transmitted, the first identification data and a second algorithm; generating a digital signature, by the first processor, according to the first key, the first digest and a third algorithm; and transmitting the data and the digital signature from the first processor to a second processor. | 2013-06-06 |
| 20130145167 | Optimized Integrity Verification Procedures - Some embodiments of the invention provide a method of verifying the integrity of digital content. At a source of the digital content, the method generates a signature for the digital content by applying a hashing function to a particular portion of the digital content, where the particular portion is less than the entire digital content. The method supplies the signature and the digital content to a device. At the device, the method applies the hashing function to the particular portion of the digital content in order to verify the supplied signature, and thereby verifies the integrity of the supplied digital content. | 2013-06-06 |
| 20130145168 | MASKED DIGITAL SIGNATURES - A method for creating and authenticating a digital signature is provided, including selecting a first session parameter k and generating a first short term public key derived from the session parameter k, computing a first signature component r derived from a first mathematical function using the short term public key, selecting a second session parameter t and computing a second signature component s derived from a second mathematical function using the second session parameter t and without using an inverse operation, computing a third signature component using the first and second session parameters and sending the signature components (s, r, c) as a masked digital signature to a receiver computer system. In the receiver computer system, a recovered second signature component s′ is computed by combining a third signature component with the second signature component to derive signature components (s′, r) as an unmasked digital signature. | 2013-06-06 |
| 20130145169 | EFFICIENT AUTHENTICATION FOR MOBILE AND PERVASIVE COMPUTING - A method and system for authenticating messages is provided. A message authentication system generates an encrypted message by encrypting with a key a combination of a message and a nonce. The message authentication system generates a message authentication code based on a combination of the message and the nonce modulo a divisor. To decrypt and authenticate the message, the message authentication system generates a decrypted message by decrypting with the key the encrypted message and extracts the message and the nonce. The message authentication system then regenerates a message authentication code based on a combination of the extracted message and the extracted nonce modulo the divisor. The message authentication system then determines whether the regenerated message authentication code matches the original message authentication code. If the codes match, then the integrity and authenticity of the message are verified. | 2013-06-06 |
| 20130145170 | CROSS SYSTEM SECURE LOGON - A cross system secure logon in a target system by using a first authentication system and a second authentication system. A correct password may be valid on the first authentication system and the second authentication system. An aspect includes receiving an input password, generating a first hash key by using the first authentication system, and/or generating a second hash key by using the second authentication system, wherein each authentication system uses a system unique non-collision free hash algorithm. Further, in one aspect, comparing the first hash key with a first predefined hash key of the correct password stored in the first authentication system, and/or comparing the second hash key with a second predefined hash key of the correct password stored in the second authentication system. Furthermore, granting access to the target system based on at least one of the comparisons. | 2013-06-06 |
| 20130145171 | METHOD AND SYSTEM FOR SECURE DATA ACCESS AMONG TWO DEVICES - An embodiment of the present invention provides a method for secure data access among two devices. The method comprises: retrieving unique information corresponding to a first electronic device and a storage device; generating an encryption key according to the unique information; generating a password string for secure a data file; encrypting the password string with the encryption key; and locking and storing the data file together with the encrypted password string in the storage device. | 2013-06-06 |
| 20130145172 | TOKEN ACTIVATION - Systems and methods for activating a token to enable a user to enter a transaction based on information received from a recovery key and a passcode are described herein. | 2013-06-06 |
| 20130145173 | TOKEN MANAGEMENT - Systems and methods for generating replacement tokens are described herein. | 2013-06-06 |
| 20130145174 | INFRASTRUCTURE INDEPENDENT RECOVERY KEY RELEASE - Aspects of the subject matter described herein relate to recovering locked data. In aspects, stakeholders of locked volume(s) are identified. Security data of the volume(s) that can be used to unlock the volume(s) is collected from one or more computing devices hosting the volume(s). The security data and stakeholder data is stored on a recovery store. If a stakeholder needs to unlock a volume, the stakeholder may communicate with a recovery manager, provide certain data, and receive data that may be used to unlock the volume. Auditing may be performed for attempts to obtain the unlocking data from the recovery store. | 2013-06-06 |
| 20130145175 | METHOD AND APPARATUS FOR ENCIPHERING/DECIPHERING DIGITAL RIGHTS MANAGEMENT OBJECT - A method and an apparatus for enciphering/deciphering digital rights management object are provided. The DRM enciphering method includes the following steps: A plurality of content objects which are divided from a digital content are received. A plurality of DRM vectors are generated according to tacit information between the DRM enciphering apparatus and the DRM deciphering apparatus. The content objects are respectively enciphered according to the DRM vectors to generate a plurality of DRM objects. | 2013-06-06 |
| 20130145176 | CIRCUIT PERSONALIZATION - A method distributes personalized circuits to one or more parties. The method distributes a generic circuit to each party, encrypts a unique personalization value using a secret encryption key, and transmits each encrypted personalization value to the corresponding party. Each party then stores the encrypted personalization value in their circuit. The stored encrypted personalization value allows a piece of software to be properly executed by the circuit. A semiconductor integrated circuit is arranged to execute a piece of software that inputs a personalization value as an input parameter. The circuit comprises a personalization memory arranged to store an encrypted personalization value; a key memory for storing a decryption key; a control unit comprising a cryptographic circuit arranged to decrypt the encrypted personalization value using the decryption key; and a processor arranged to receive the decrypted personalization value and execute the software using the decrypted personalization value. | 2013-06-06 |
| 20130145177 | MEMORY LOCATION SPECIFIC DATA ENCRYPTION KEY - Contents of a memory are encrypted using an encryption key that is generated based on a random number and a memory location at which the contents are stored. Each of a plurality of locations of a memory can be associated with a respective unique pointer value, and an encryption key may be generated based on the unique pointer value and the random number. In some examples, the random number is unique to a power-up cycle of a system comprising the memory or is generated based on a time at which the data to be stored by the memory at the selected memory location is written to the memory. | 2013-06-06 |
| 20130145178 | PORTABLE SECURE DATA FILES - A portable secure data file includes an encrypted data portion and a metadata portion. When a request associated with a current user of a device to access a portable secure data file is received, one or more records in the metadata portion are accessed to determine whether the current user is permitted to access the file data in the encrypted data portion. If a record indicates the user is permitted to access the file data, a content encryption key in that record is used to decrypt the encrypted data portion. | 2013-06-06 |
| 20130145179 | Corralling Virtual Machines With Encryption Keys - A virtual machine comprises a unique identifier that is associated with one or more encryption keys. A management server encrypts the virtual machine's virtual hard disk(s) using the one or more associated encryption keys. The management server further provides the one or more encryption keys to a limited number of one or more servers in a system. Only those one or more servers that have been provided the one or more encryption keys can be used to load, access, and/or operate the virtual machine. The management server can thus differentiate which virtual machines can be operated on which servers by differentiating which servers can receive which encryption keys. In one implementation, a management server encrypts all virtual machines in the system, but encrypts virtual machines with sensitive data with a limited set of encryption keys, and further provides those encryption keys to a limited set of trusted servers. | 2013-06-06 |
| 20130145180 | METHOD OF POWER CALCULATION FOR PERFORMANCE OPTIMIZATION - A system and method for efficient management of operating modes within an IC for optimal power and performance targets. On a same die, an SOC includes one or more processing units and a input/output (I/O) controller (IOC). The multiple interfaces within the IOC manage packets and messages according multiple different protocols. The IOC maintains an activity level for each one of the multiple interfaces. This activity level may be based at least on a respective number of transactions executed by a corresponding one of the multiple interfaces. The IOC determines a power estimate for itself based on at least the activity levels. In response to detecting a difference between the power estimate and an assigned I/O power limit for the IOC, a power manager adjusts at least respective power limits for the one or more processing units based on at least the difference. | 2013-06-06 |
| 20130145181 | System and Method for Long Range Power Over Ethernet Using Integrated Boost Repeaters - A system and method for long range power over Ethernet (PoE) using integrated boost repeaters. The integrated boost repeater includes a boost converter module that boosts a voltage level received by a powered device on a first port of the integrated boost repeater to a second voltage level that is applied by a power source equipment to a second port of the integrated boost repeater. In one embodiment, the boost converter module boosts the voltage to a level that is greater than a voltage level output by an originating power source equipment. | 2013-06-06 |
| 20130145182 | POWER SUPPLY DEVICE FOR SERVER SYSTEMS - A power supply device for a server system includes a main power supply, a control microchip, a first switch, a trigger, a second switch, and an auxiliary power supply. When a voltage of the main power supply is within a predetermined range, the control microchip keeps the first switch turned off and the trigger keeps the second switch turned on, so that a voltage of the auxiliary power supply is transmitted to the server system via the second switch. When the main power supply is outside the predetermined range, the control microchip turns on the first switch and the trigger turns off the second switch, so that the voltage of the auxiliary power supply is transmitted to ground. | 2013-06-06 |
| 20130145183 | MANAGEMENT SYSTEM, MANAGEMENT APPARATUS, MANAGEMENT METHOD, AND COMPUTER-READABLE MEDIUM - A management system which includes an image forming apparatus having a plurality of functions, and a management apparatus which manages the image forming apparatus, the management apparatus comprises: a power consumption acquisition unit which acquires information of power consumptions for the respective functions of the image forming apparatus; a supply power acquisition unit which acquires information of a supply power to be supplied to the image forming apparatus; a determination unit which determines a power consumption value to be consumed by the image forming apparatus based on the information of the power consumptions for the acquired respective functions and the information of the acquired supply power; and a setting unit which sets a power consumption of the image forming apparatus to be operated at the determined power consumption value. | 2013-06-06 |
| 20130145184 | ELECTRONIC APPARATUS AND IMAGE FORMING APPARATUS - An electronic apparatus comprising: a main body including a reception unit and a processing unit; and a power supply device switches between an operation state for supplying power from an external power source to the main body and a standby state for supplying power from a secondary battery to the reception unit without supplying power from the power source to the main body. Charging of the battery with power from the power source is performed during the operation state and is terminated when a value indicating power level of the battery reaches a threshold value Vt satisfying (discharge lower limit VL+Vs)≦Vt| 2013-06-06 | |
| 20130145185 | DEMAND BASED POWER ALLOCATION - A demand based power re-allocation system includes one or more subsystems to assign a power allocation level to a plurality of servers, wherein the power allocation level is assigned by priority of the server. The system may throttle power for one or more of the plurality of servers approaching the power allocation level, wherein throttling includes limiting performance of a processor, track server power throttling for the plurality of servers. The method compares power throttling for a first server with power throttling for remaining servers in the plurality of servers and adjusts throttling of the plurality of servers, wherein throttled servers receive excess power from unthrottled servers. | 2013-06-06 |
| 20130145186 | UNIVERSAL SERIAL BUS DEVICE CAPABLE OF REMOTE WAKE-UP THROUGH A SPECIAL MASK CIRCUIT - The present invention discloses a Universal Serial Bus (“USB”) device capable of remote wake-up through a special mask circuit. The USB device includes an Ethernet port to transmit a first signal in response to a predetermined network packet, a wake-up pin to transmit a second signal in response to a remote wake-up trigger signal, a remote wake-up circuit to generate a wake-up signal in response to either the first signal or the second signal, and a mask circuit to receive the wake-up signal and delay transmission of the wake-up signal to a remote USB host for a predetermined delay time. | 2013-06-06 |
| 20130145187 | MULTI-DEVICE POWERSAVING - A control system reduces energy consumption in a multi-device system comprising a plurality of devices. The control system includes at least one processor. The processor is programmed to receive a job to be executed, as well as a selection of one of the plurality of devices for executing the job and a transfer cost for transferring the job from the selected device to each of the plurality of devices. A device to execute the job is determined through optimization of a first cost function. The first cost function is based on the device selection and the transfer costs. The job is assigned to the determined device and a time-out for each device in the multi-device system is determined through optimization of a second cost function. The second cost function is based on an expected energy consumption by the multi-device system. The devices are provided with the determined time-outs. | 2013-06-06 |
| 20130145188 | Advanced Pstate Structure with Frequency Computation - A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity. | 2013-06-06 |
| 20130145189 | SERVER SYSTEM CAPABLE OF DECREASING POWER CONSUMPTION AND METHOD THEREOF - A server system and a control method applied therein are illustrated. The server system includes a server cabinet, servers accommodated in the server cabinet, a cooling fan module for cooling the servers, a thermal sensor detecting an ambient temperature in the server cabinet, and a controller. The controller includes a speed control module controlling a rotation speed of the fan module according to the ambient temperature and any overloading of servers, an obtaining module receives power consumed values of the servers, a determining module determining if a ratio of the highest power consumed value to the lowest power consumed value is greater than a predetermined value, and an executing module reducing the clocking speed of the server having the highest power consumed value if the determining module determines that the ratio of the highest power consumed value to the lowest power consumed value is greater than the predetermined value. | 2013-06-06 |
| 20130145190 | DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM - A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode. | 2013-06-06 |
| 20130145191 | UNIVERSAL SERIAL BUS DEVICE AND METHOD FOR POWER MANAGEMENT - The present invention discloses a Universal Serial Bus (“USB”) device with a power saving mechanism. The USB device includes an Ethernet physical layer, a USB physical layer, a wakeup packet detection circuit configured to receive a wakeup packet from the Ethernet physical layer, and a standby power saving control circuit. The standby power saving control circuits selects a connection speed from the group including EEE, 10 Mbps, 100 Mbps, 1 Gbps and 10 Gbps, wherein the standby power saving control circuit is able to connect to a wakeup device at the selected connection speed, so that the USB system can enter an optimal power saving status while in a standby mode. The connection speeds are defined in the specification of IEEE 802.3az as 10BASE-T, 100BASE-TX, 1000BASE-T, 10GBASE-T, 1000BASE-KX, 10GBASE-KX4, 10GBASE-KR. | 2013-06-06 |
| 20130145192 | COMPUTER AND CONTROL METHOD THEREOF - A computer includes a CPU and a system unit, and further includes a power source which generates source power, a system driving power generator which converts the source power to system power and which provides power to the system unit, a CPU driving power generator which outputs driving power to drive the CPU, and a controller which selectively supplies the source power or the system power to an input terminal of the CPU driving power generator according to an operation mode of the CPU. Thus, a computer adjusts a level of power supplied to a CPU driving power generator according to a CPU mode and improves power efficiency, and includes a control method thereof. | 2013-06-06 |
| 20130145193 | DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM - A data processing device includes: a first power-on reset circuit; a second power-on reset circuit with higher power consumption and higher reset voltage accuracy than the first power-on reset circuit; a storage unit storing information for determining whether to keep the second power-on reset circuit in an active state or an inactive state; and a central processing unit initialized in response to respective outputs of the first and second power-on reset circuits and setting the information in the storage unit. | 2013-06-06 |
| 20130145194 | METHODS FOR OPERATING AN APPARATUS HAVING MULTIPLE STAND-BY MODES - A method for operating an apparatus, such as a video signal receiver, having first and second stand-by modes when the apparatus is in an off state, wherein the first stand-by mode provides a different start-up time and consumes a different amount of power than the second stand-by mode, is capable of saving power without requiring a user to wait a long time for a start-up sequence. According to an exemplary embodiment, the method includes enabling display of a user interface allowing user selections for a plurality of different time periods of a day; and enabling a user to select, via the user interface, one of at least three different options for each one of the different time periods, wherein a first one of the options includes setting the apparatus to the first stand-by mode for the time period, a second one of the options includes setting the apparatus to the second stand-by mode for the time period, and a third one of the options includes setting the apparatus to a statistical mode for the time period, wherein the statistical mode includes setting the apparatus to one of the first and second stand-by modes for the time period based on a user's past viewing habits during the time period. | 2013-06-06 |
| 20130145195 | SYSTEM AND METHOD OF MANAGING POWER AT A PORTABLE COMPUTING DEVICE AND A PORTABLE COMPUTING DEVICE DOCKING STATION - A method of managing power distribution between a portable computing device (PCD) and a PCD docking station is disclosed and may include determining that the PCD is docked with the PCD docking station, switching a power supply to the PCD from a PCD battery to a PCD docking station battery, and powering the PCD and the PCD docking station from the PCD docking station battery. Further, the method may include determining whether a PCD battery power equals a charge condition and charging the PCD battery when the PCD battery power equals the charge condition. The method may also include monitoring a PCD docking station battery power, determining whether the PCD docking station battery power equals a warning condition, and transmitting a first warning when the PCD docking station battery power equals the warning condition. | 2013-06-06 |
| 20130145196 | INFORMATION PROCESSING APPARATUS AND METHOD - An information processing apparatus includes: a plurality of electric power generating elements; detection means for determining whether each of the plurality of electric power generating elements has an electromotive force equal to or higher than a predetermined value; determination means determining an input operation performed by a user by identifying an electric power generating element having an electromotive force below the predetermined value when at least one of the plurality of electric power generating elements is determined as having an electromotive force below the predetermined value according to the detection means; processing means carrying out a process associate with the input operation determined by the determination means; and bypass means which is provided in parallel with the electric power generating elements and through which a current flows when the electric power generating elements have an electromotive force below the predetermined value. | 2013-06-06 |
