| 23rd week of 2014 patent applcation highlights part 32 |
| Patent application number | Title | Published |
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| 20140153255 | Luminaire - A luminaire according to an embodiment includes a main body attached to an attachment surface such as the ceiling or the wall of a building. The luminaire includes a light-emitting surface substantially parallel to the attachment surface. A semiconductor light-emitting element is arranged on the light-emitting surface. A cover body having translucency is attached to the main body to cover the light-emitting surface. The inner surface of the cover body includes a refracting surface forming an acute angle with respect to an optical axis of light emitted from the semiconductor light-emitting element and located in a position further on the inner side than a peripheral edge section of the main body. The outer surface of the cover body includes an outer peripheral surface projecting further to the outer side than a peripheral edge section of the main body. | 2014-06-05 |
| 20140153256 | LIGHT DUCT TEE EXTRACTOR - The disclosure generally relates to highly efficient light duct light extractors that are capable of extracting a portion of the light propagating within a light duct with nearly 100 percent efficiency. In particular, the described light extractors are configured in a “Tee” shape with a reflective diverter element. | 2014-06-05 |
| 20140153257 | LIGHTING FIXTURE ASSEMBLY - Implementations of the present invention comprise lighting fixture assemblies that minimize the visibility of hardware and shadows. In particular, the lighting fixture assemblies may include no supporting hardware extending through an internal space defined, in whole or in part, by the lighting fixture assembly. In addition, the lighting fixture assemblies may include a gap between a bottom/top panel and a side panel of the lighting fixture assembly. Accordingly, lighting fixture assemblies of one or more implementations of the present invention can reduce or eliminate the visibility of internal supporting hardware and shadows on the exterior surfaces of the lighting fixture assemblies. | 2014-06-05 |
| 20140153258 | COLOR CUSTOMIZABLE TABLE LAMP AND METHOD OF MAKING THE SAME - A lamp having a hollow clear body supported between a base and a cap, a hollow pipe carrying an electrical cord and a light socket dispensed internally of said hollow clear body between said base and said cap and removable through the open upper end of said body to allow the body to become free standing so that a color bearing material can be applied to the internal surface of the clear body. | 2014-06-05 |
| 20140153259 | LED LAMP - A LED lamp includes a lamp base unit including an insulative base, a mating connection device configured like the base of a conventional incandescent bulb and located at the bottom side of the insulative base, an insulative hollow column located at the top side of the insulative, a heat sink including a plurality of radiation fins radially arranged around the insulative hollow column, a light-emitting module including a heat transfer plate fastened to the heat sink at the top, a circuit board supported on the heat transfer plate and light-emitting devices installed in the circuit board, and a light transmissive lampshade fastened to the heat sink and covered over the light-emitting module. | 2014-06-05 |
| 20140153260 | Systems, Methods, and Devices Providing a Quick-Release Mechanism for a Modular LED Light Engine - A light emitting diode module is removably coupled to a heat sink with screws and includes slots configured to receive at least a portion of the screw therethrough, the width of the slot being greater than the thread-width of the screw but less than the width of the screw head. Some slots also include a keyhole having a diameter greater than the width of the screw head. For embodiments without keyholes, the module is coupled to a heat sink by loosening the screws, sliding them into the slots, and tightening the screws to hold the LED module in place. For embodiments with one or more keyholes, the keyhole is vertically aligned with the screw, the module is moved down over the screw, and the screw is moved into the narrower portion of the slot. Then, the screws are tightened to hold the module in place against the heat sink. | 2014-06-05 |
| 20140153261 | ILLUMINATION DEVICE WITH CARRIER AND ENVELOPE - An illumination device comprising a light source ( | 2014-06-05 |
| 20140153262 | GLASS CERAMIC BODY, SUBSTRATE FOR MOUNTING LIGHT EMITTING ELEMENT, AND LIGHT EMITTING DEVICE - To provide a glass ceramic body, whereby light which transmits through the substrate and leaks (i.e. emits) out of the incident direction is reduced, and the number of voids at the surface of the substrate and in the inside of the substrate is low, | 2014-06-05 |
| 20140153263 | TWO PART FLEXIBLE LIGHT EMITTING SEMICONDUCTOR DEVICE - Provided is a light emitting semiconductor device comprising a flexible dielectric layer, a conductive layer on at least one side of the dielectric layer, at least one cavity or via in the dielectric substrate, and a light emitting semiconductor supported by the cavity or via. Also provided is a support article comprising a flexible dielectric layer, a conductive layer on at least one side and at least one cavity or via in the dielectric substrate. Further provided is a flexible light emitting semiconductor device system comprising the above-described light emitting semiconductor device attached to the above-described support article. | 2014-06-05 |
| 20140153264 | AQUARIUM LAMP BRACKET ASSEMBLY - An aquarium lamp bracket assembly includes a bracket including a base frame, a coupling tube located at the front side of the base frame defining an axial coupling hole and a longitudinal opening and a clamping member extended from the back side of the base frame and defining with the elongated base member a clamping mouth for fastening to a glass panel of an aquarium housing, and an adjustable lamp tube holder including a pivot shaft angularly adjustably mounted in the coupling hole in the coupling tube, a lamp tube holder shell holding a lamp tube and and a neck connected between the pivot shaft and the lamp tube holder shell and inserted through the longitudinal opening of the bracket. | 2014-06-05 |
| 20140153265 | MODULAR LIGHTING SYSTEM AND METHOD EMPLOYING LOOSELY CONSTRAINED MAGNETIC STRUCTURES - A lighting system including modules containing LEDs or other electroluminescent devices and loosely constrained magnetic structures at least partially contained within cavities in the module substrate that are connected to fixtures under magnetic force. The loosely constrained magnetic structures accommodate mechanical variations in the system and provide a method to connect modules mechanically, electrically and thermally to different fixtures or positions in fixtures without tools. The relatively short distance separating magnetic structures provides high connection forces with the use of relatively small magnets. Magnets and electrical contacts are not located directly between the LED subassembly and the fixture, which provides higher thermal conductivity pathways to remove heat from the LEDs. Biasing members may be used to increase thermal contact. Magnetic structures may, but are not required, to conduct electricity. Fixtures that attach to modules include rails, sockets, heat sinks and two-dimensional structures with recessed electrodes for improved electrical safety. | 2014-06-05 |
| 20140153266 | DISPLAY DEVICE - A display device includes a flexible display panel for displaying an image, and a printed circuit board electrically connected with the flexible display panel through a circuit film. The printed circuit board may include a plurality of boards in a stack, the boards being respectively provided with integrated circuits, driving chips, and circuit wires, and a conducting portion connecting circuit wires of at least two boards among the plurality of boards. | 2014-06-05 |
| 20140153267 | MOUNTING APPARATUS FOR ADJUSTABLY POSITIONING A LIGHTING DEVICE - A mounting apparatus for adjustably positioning a lighting device. The mounting apparatus includes a mounting bracket having an ear and a first indicator associated with the ear. The mounting apparatus also includes a second indicator adapted to be coupled to the lighting device for conjoint rotational movement about a rotational axis with respect to the mounting bracket. The second indicator and the lighting device may be selectively rotated about the rotational axis such that the second indicator is located in a desired position with respect to the first indicator whereby the lighting device is located in a desired measured orientation with respect to the mounting bracket. | 2014-06-05 |
| 20140153268 | GEAR SCREW ADJUSTER - A headlamp assembly includes a simplified adjusting mechanism for adjusting the aim of a headlamp. The mechanism includes a gear screw that is snap-fit into the headlamp housing, a grommet that is positioned around the gear screw and snap-fit into the headlamp reflector, and an O-ring to ensure a good seal. | 2014-06-05 |
| 20140153269 | Vehicle Auxiliary Lighting System - A vehicle auxiliary lighting system (VALS) that is designed to have installed on the lower inner edge of a vehicle's rear-facing, upward-opening door a set of rear facing lights. When the rear door is lifted, the lights are manually or automatically activated and produce a light beam that can easily be viewed by oncoming vehicular traffic. The illuminated light provides an extra margin of safety to personnel attending to a disabled vehicle that has been parked adjacent a road. | 2014-06-05 |
| 20140153270 | Light assembly for bicycle seat post - A light assembly mounted in recess of a seat post of a bicycle is provided with a push button moveably mounted on a mouth of the recess and including a bossed hole on a rear surface; a resilient conductor fastened in the bossed hole; a controller circuit fastened in the recess and including two spaced contacts spaced from the conductor in a non-depressed position, the contacts being electrically connected to the controller circuit; LEDs disposed on a front surface of the controller circuit facing the rear surface of the push button; and a battery mounted to a rear surface of the controller circuit and electrically connected to the contacts. A pressing of the push button electrically connects the conductor to the contacts so that an electric energy is supplied from the battery to the LEDs for illumination via the contacts, the conductor, and the controller circuit. | 2014-06-05 |
| 20140153271 | LIGHTED VEHICLE CARGO AREA ARRANGEMENT - A lighted vehicle cargo area arrangement includes a cargo area wall structure and a lighting system. The cargo area wall structure includes a first wall surface facing a vehicle cargo area. The lighting system includes a rail, a mounting bracket and a lamp. The rail is fixedly coupled to the cargo area wall structure and defines a lamp receiving space located laterally between an outboard surface of the rail and the first wall surface. The mounting bracket includes a rail attachment section rigidly attached to the rail and a lamp attachment section. The lamp is attached to the lamp attachment section. The lamp is aimed to shine light beneath the mounting bracket and the rail toward the vehicle cargo area. | 2014-06-05 |
| 20140153272 | LIGHTING AND/OR SIGNALING DEVICE, NOTABLY FOR A MOTOR VEHICLE - A lighting and/or signaling device, notably for a motor vehicle, comprising at least one light source and one light guide, the source comprising a support and a plurality of light emitting components arranged on the support so as to emit a beam of light, the device being configured to direct the beam toward the guide, in which device the support is a printed circuit and/or the light emitting components are light emitting diodes, in which device the light emitting components are arranged in such a way as to define an emission surface for the beam of light on a face of the support, in which device the light source is configured so that the emission surface has a longitudinally extending axis, in which device the light guide comprises at least one emitting portion configured to emit light out of the guide, and at least one guide portion, situated between the source and the emitting portion, configured to transmit the beam of light from the source to the emitting portion. | 2014-06-05 |
| 20140153273 | VEHICULAR LAMP - A vehicular lamp includes a transparent planar light emitting body including a first light emitting surface and a second light emitting surface which face each other, a first reflector and a second reflector. The transparent planar light emitting body emits light from the first light emitting surface and the second light emitting surface. The first reflector reflects light from the first light emitting surface to the front. The second reflector reflects light from the second light emitting surface to the front. | 2014-06-05 |
| 20140153274 | VEHICLE LIGHTING APPARATUS - At least a part of light emitted from a light source fixed to a heat sink | 2014-06-05 |
| 20140153275 | VEHICLE LIGHTING SYSTEM - A vehicle lighting system includes first and second lighting devices. The first lighting device has a first opening, and the second lighting device has a second opening. The first opening provides access to a first installation space on the first lighting device, and the second opening provides access to a second installation space on the second lighting device. The first and second installation spaces are essentially mirror images of one another. A first fan unit is located at the first opening and a second fan unit is located at the second opening. The first and second fan units are essentially mirror images of one another. | 2014-06-05 |
| 20140153276 | LIGHT EMITTING DEVICE AND VEHICLE LAMP - A light emitting device can include a base portion including a surface, a back surface, and a first through hole penetrating the surface and the back surface. A light-transmitting member can be fixed to the surface so as to cover the first through hole. A semiconductor light emitting element can emit light to pass through the first through hole and for irradiating the light-transmitting member. An optical system can be provided for condensing the light from the semiconductor light emitting element and locally irradiating the light-transmitting member with the light. A foil body can be provided and can include a second through hole for light emitted from the light-transmitting member to pass through and has elasticity. The light-transmitting member can be sandwiched between the foil body around the second through hole and the base portion with part of the light-transmitting member exposed from the second through hole. | 2014-06-05 |
| 20140153277 | ASSEMBLING STRUCTURE FOR LED LAMP MODULE - An assembling structure of an LED lamp module includes an LED lamp base ( | 2014-06-05 |
| 20140153278 | BODY CAVITY ILLUMINATION SYSTEM - A cavity illumination system according to the present disclosure may include one or more illumination elements composed of a transparent or semi-transparent, biocompatible sterilizable polymer and one or more illumination sources. The sterilizable polymer operates as a waveguide. An illumination element may incorporate micro structured optical components such as for example gratings, prisms and or diffusers to operate as precision optics for customized delivery of the light energy. The micro structured optical components may also be used to polarize and/or filter the light energy entering or exiting the illumination element. | 2014-06-05 |
| 20140153279 | Shelf Illumination Device - A shelf illumination device ( | 2014-06-05 |
| 20140153280 | OPTICAL MEMBER, DISPLAY DEVICE HAVING THE SAME AND METHOD FOR FABRICATING THE SAME - Disclosed are an optical member, a display device including the same, and a method of fabricating the same. The optical member includes a barrier film; an adhesive layer bonded onto the barrier film and including a plurality of wavelength conversion particles and an adhesive; and a detachable film detachably attached onto the adhesive layer. | 2014-06-05 |
| 20140153281 | BACKLIGHT UNIT AND DISPLAY DEVICE - The present invention provides a backlight unit including a light source and a light guide plate, wherein the backlight unit further includes a set of reflectors, the set of reflectors includes a first reflector and a second reflector, the first reflector is arranged at a side of the light guide plate, the second reflector is arranged at the back of the light guide plate, the light source is arranged below the first reflector, the first reflector is used for reflecting light emitted from the light source into the light guide plate, and light exits from the front of the light guide plate after being scattered by the light guide plate and being reflected by the second reflector. Correspondingly, a display device including the backlight unit is provided. The backlight unit has advantages of small thickness, increased effective illumination area, and various shapes. | 2014-06-05 |
| 20140153282 | LIGHTING ASSEMBLY WITH A LIGHT GUIDE HAVING LIGHT-REDIRECTING EDGE FEATURES - A lighting assembly includes a light source to emit on-axis light rays at smaller angles relative to an optical axis of the light source, and off-axis light rays at larger angles relative to the optical axis and spectrally different from the on-axis light rays. The lighting assembly additionally includes a light guide having a light input edge adjacent the light source and opposed major surfaces between which light from the light source propagates by total internal reflection. The light input edge has an edge feature aligned with the light source to receive light therefrom. The edge feature specularly redirects the on-axis light rays and the off-axis light rays differently to increase overlap between the on-axis light rays and the off-axis light rays within the light guide. The increased overlap reduces spatial color variation of light extracted from the light guide between locations at different angles from the optical axis. | 2014-06-05 |
| 20140153283 | BACKLIGHT MODULES AND LIQUID DISPLAY DEVICES WITH THE SAME - A backlight module includes a light guiding plate and a light source is disclosed. | 2014-06-05 |
| 20140153284 | LIGHT SOURCE DEVICE OF BACKLIGHT UNIT FOR DISPLAY - A light source device of a backlight unit in which a circuit board on which light-emitting diodes (LEDs) are mounted is disposed inside a rear cover and a heat dissipating means for dissipating heat generated from the LEDs to an outside is disposed between the rear cover and the circuit board. The circuit board is implemented as a patterned substrate which includes a thin sheet and a conductive pattern formed on the thin sheet, the conductive pattern connecting the LEDs to a power source, thereby reducing a thickness through which the heat generated by the LEDs is to be conducted to the heat dissipating means. The heat generated from the LEDs can be more rapidly and efficiently dissipated. Due to the more simplified structure, the light source device can be decreased in weight and be rapidly assembled. | 2014-06-05 |
| 20140153285 | Lighting Assembly with Defined Angular Output - A lighting assembly includes a light guide and solid-state light emitters to edge-light the light guide, the light emitters arrayed along a transverse direction. The light guide includes two or more sets of optical elements of well-defined shape. Light output from the lighting assembly by the first and second set of optical elements have a first and a second light ray angle distribution, respectively. The optical elements are configured such that when measured in a plane perpendicular to the light guide and the transverse direction: 1) the first and second light ray angle distributions are significantly narrower than an omnidirectional output distribution; and 2) the peak of the second light ray angle distribution is displaced from the peak of the first light ray angle distribution. | 2014-06-05 |
| 20140153286 | LIGHT GUIDE PLATE, BACKLIGHT MODULE AND DISPLAY DEVICE - The present invention is directed to a light guide plate, a backlight module and a display device with the light guide plate comprising a bottom surface containing space for holding light sources, a light emitting surface opposite the bottom surface and a quantum dot layer is arranged in the containing space in the direction of the light emitting surface. Since the bottom surface of the light guide plate is provided with the containing space for holding the light sources, and the light sources are limited within the containing space, light diffusion due to the fact that the light sources are positioned outside the light guide plate is reduced, loss of light is reduced, and quantity of the light sources in the backlight module is reduced. Since the quantum dot layer is arranged in the containing space toward a direction of the light emitting surface, white mixed light is formed according to fluorescent effect of quantum dot materials. Further, as the quantum dots have the characteristics of high color gamut and high transmittance, display effect can be improved. | 2014-06-05 |
| 20140153287 | SYSTEM AND METHOD FOR IMPROVING POWER CONVERSION EFFICIENCY - A power conversion system includes at least one switching unit. The switching unit includes a switching device including a channel and a body diode integrated with the channel. The switching device includes a first terminal, a second terminal, and a third terminal. The channel provides a positive direction current flow path to allow a positive direction current to flow through in response to a first turn-on switching control signal supplied to the first terminal. The body diode provides a first negative direction current flow path to allow a negative direction current to flow through in response to a first turn-off switching control signal. The channel provides a second negative direction current flow path to allow the negative direction current to flow through in response to a second turn-on switching control signal. | 2014-06-05 |
| 20140153288 | DC-DC CONVERTER WITH LC RESONANCE CIRCUIT - A DC-DC converter includes a capacitor configured to be charged for a predetermined period by an external voltage, an inductor configured to constitute an LC resonance circuit together with the capacitor, a closed-loop current path configured to release energy accumulated in the capacitor after the predetermined period to cause a current flowing in the LC resonance circuit to oscillate, a transformer configured to receive a current flowing in the closed-loop current path, and a rectifying circuit situated on an output side of the transformer. | 2014-06-05 |
| 20140153289 | Secondary Side Serial Resonant Full-Bridge DC/DC Converter - The present invention relates to a secondary side serial resonant full-bridge DC/DC converter, comprising: a transistor full-bridge unit, a transformer unit, a resonant unit, a rectifying unit, and an output unit. Particularly, in the present invention, a resonant inductor and a resonant capacitor of the resonant unit and a load resistor of the output unit constitute a serial resonant circuit having a serial resonant frequency; therefore, when the circuit frequency is operated on the serial resonant frequency, the resonant inductor impedance would be offset by the resonant capacitor impedance, such that the circuit is operated in the zero current switch (ZCS) region, and the output voltage variation can be controlled in ±0.2%. Moreover, through the serial resonant circuit, the issue about the resonant components hard to be designed due to their small characteristic impedance can simultaneously be improved. | 2014-06-05 |
| 20140153290 | DC/DC CONVERTER WITH VARIABLE OUTPUT VOLTAGE - A DC/DC converter includes a transformer having a primary winding electrically connected to a resonant network and a secondary winding having a plurality of taps including a common tap, a first tap, and a second tap. The DC/DC converter further includes a plurality of rectifier circuits including a first rectifier circuit electrically connected to the common tap, a second rectifier circuit electrically connected to the first tap, and a third rectifier circuit electrically connectable to the second tap. The DC/DC converter also includes a switch electrically connected between the second tap and the third rectifier circuit. The switch is operable to electrically connect and disconnect the third rectifier circuit from the second tap. | 2014-06-05 |
| 20140153291 | DUAL-MODE, AC/DC POWER CONVERTER WITH POWER FACTOR CORRECTION - A dual-mode circuit for the control of an AC/DC power converter is disclosed. An example dual-mode controller circuit generates a waveform that drives a switch on or off and controls the power converter. The controller circuit in addition to power factor correction (PFC) circuitry includes a critical conducting mode (CrM) module as well as a discontinuous conducting mode (DCM) module configured to generate waveforms adapted for CrM and DCM operation of a power converter. The circuit includes a node for receiving a feedback signal of a voltage or a current. Based on the received signal, one of the modules is selected at a time to supply the waveform at the output of the dual-mode controller. An example of the output waveform is a series of pulses that are configured to drive the switch that controls the transfer of power between input and output of the power converter. | 2014-06-05 |
| 20140153292 | PRIMARY SIDE SENSE OUTPUT CURRENT REGULATION - The embodiments disclosed herein describe a method of a controller to maintain a substantially constant average output current at the output of a switching power converter. In one embodiment, the controller uses a regulation voltage that corresponds to the primary peak current regulation level to regulate the average output current. | 2014-06-05 |
| 20140153293 | Double-Output Half-Bridge LLC Serial Resonant Converter - The present invention relates to a double-output half-bridge LLC serial resonant converter, comprising: a half-bridge rectifying unit, a first resonant unit, a first transformer unit, a first rectifying unit, a first output unit, a second resonant unit, a second transformer unit, a second rectifying unit, a second output unit, a voltage dividing unit, a voltage regulating unit, a light-coupling isolation unit, and a control unit. In the present invention, the double-output half-bridge LLC serial resonant converter has an inventive circuit framework, which can not only solve the unbalance load current and the output voltage cross regulation occurred in the conventional double-output convertor, but also normally modulate the no-load or light-load output voltage; therefore the output voltage deviation can be effectively controlled. | 2014-06-05 |
| 20140153294 | AC/DC Power Converter Arrangement - A converter arrangement, includes a DC/DC stage comprising a plurality of DC/DC converters. Each of the plurality of DC/DC converters is operable to receive one of a plurality of direct input voltages. The DC/DC stage is configured to generate an output voltage from the plurality of direct input voltages. | 2014-06-05 |
| 20140153295 | Buck-Flyback Converter - A two-transistor flyback converter includes a transformer having a primary side and a secondary side, a first transistor connected between an input voltage source and a first terminal of the primary side, a second transistor connected between ground and a second terminal of the primary side, and a diode directly connected between the first terminal of the primary side and ground. The first and second transistors are operable to switch on and off simultaneously and with no current return from the primary side to the input voltage source when the input voltage source is less than a reflected voltage from the secondary side. | 2014-06-05 |
| 20140153296 | ISOLATED POWER CONVERSION APPARATUS AND METHOD OF CONVERTING POWER - An isolated power conversion apparatus includes an isolation transformer and an auto charge pump circuit. The isolation transformer has a primary side and a second side, wherein the primary side is electrically connected to a pulsed power supply, and the secondary side has a first end and a second end; the auto charge pump circuit electrically connects the isolation transformer to a loading to improve power conversion efficiency and suppress output voltage ripples. | 2014-06-05 |
| 20140153297 | POWER SUPPLY CONTROLLER WITH INPUT VOLTAGE COMPENSATION FOR EFFICIENCY AND MAXIMUM POWER OUTPUT - An apparatus includes an ON/OFF controller for regulating an output of a switched mode power supply by selectively enabling current conduction by a power switch within enabled switching cycles and disabling current conduction by the power switch within disabled switching cycles. The controller includes a logic block and a time-to-frequency converter. The logic block generates a drive signal that enables the current conduction by the power switch within respective enabled switching cycles and disables the current conduction by the power switch within respective disabled switching cycles. The time-to-frequency converter generates a variable-frequency clock signal that defines durations of the switching cycles, where the time-to-frequency converter increases a duration of a switching cycle in response to a decrease in duration of current conduction by the power switch in a previously enabled switching cycle. | 2014-06-05 |
| 20140153298 | INVERTER WITH COUPLED INDUCTANCES - An inverter for converting a direct current flowing between two input lines into an alternating current flowing between two output lines includes first and second series circuits each including two switches configured to switch at a high frequency and of an inductance connected between the switches, wherein the two inductances are magnetically coupled. The inverter further includes diodes which lead from opposite sides of the inductances to a first intermediate point and diodes leading from a second intermediate point to the opposite sides of the inductances, and an unfolding circuit which forwards a direct current flowing between the intermediate points and consisting of sine-shaped half-waves to the output lines with a polarity changing half-wave by half-wave. | 2014-06-05 |
| 20140153299 | POWER FACTOR CORRECTION DEVICE - There is provided a power factor correction device including: a main switching unit including a first main switch and a second main switch performing a switching operation with predetermined phase differences; an auxiliary switching unit including a first auxiliary switch and a second auxiliary switch forming a transmission path for surplus power existing before the first main switch and the second main switch are turned on, respectively; an inductor unit positioned between a power input unit to which AC power is applied and the main switching unit and accumulating or discharging energy according to a switching operation of the main switching unit; and an auxiliary inductor unit regulating an amount of current flowing in the auxiliary switching unit in the event of a switching operation of the auxiliary switching unit. | 2014-06-05 |
| 20140153300 | POWER CONVERSION APPARATUS - Disclosed is a power conversion apparatus with further reduced inductance of conductors coupling condensers. The power conversion apparatus includes a smoothing circuit having first and second electrolytic condensers connected to each other in series and third and fourth electrolytic condensers connected to each other in series. The distance between a positive terminal of the first electrolytic condenser and a negative terminal of the third electrolytic condenser is shorter than the distance between the positive terminal of the first electrolytic condenser and a positive terminal of the fourth electrolytic condenser. The distance between the positive terminal of the fourth electrolytic condenser and a negative terminal of the second electrolytic condenser is shorter than the distance between the positive terminal of the fourth electrolytic condenser and the positive terminal of the first electrolytic condenser. | 2014-06-05 |
| 20140153301 | AC SIGNAL DETECTOR AND THE METHOD THEREOF - An AC signal detector having: a rectify circuit having a first input terminal and a second input terminal configured to receive an AC signal, and an output terminal configured to provide a rectified signal based on the AC signal; a detecting circuit having an input terminal coupled to the output terminal of the rectify circuit to receive the rectified signal, and an output terminal configured to provide a square signal based on the rectified signal; and an unplug indicate circuit having an input terminal coupled to the detecting circuit to receive the square signal, and an output terminal configured to provide an unplug indicate signal based on the square signal. | 2014-06-05 |
| 20140153302 | AUTOMATIC AC BUS VOLTAGE REGULATION FOR POWER DISTRIBUTION GRIDS - A system for automatically regulating voltage on a distribution-level AC bus having an actual voltage and a nominal voltage includes an electronic power converter connected to the distribution-level AC bus. The system generates a feedback signal representative of the actual voltage of the distribution-level AC bus and produces an input control signal in response to the feedback signal. The input control signal is representative of a commanded level of reactive power. The electronic power converter is responsive to the input control signal to deliver a commanded reactive power output to the distribution-level AC bus, and the commanded reactive power output pushes the actual voltage towards the nominal voltage. | 2014-06-05 |
| 20140153303 | SOLAR MODULE HAVING A BACK PLANE INTEGRATED INVERTER - A solar module device with a back plane integrated inverter device includes a substrate member having a front side and a back side. The device has a plurality of solar cells, which includes a first group of solar cells connected in a first serial configuration and a second group of solar cells connected in a second serial configuration, and a tab wire configuration formed overlying the front side of the substrate member. The tab wire includes a first interconnection coupled to the first set of solar cells in the first serial configuration and a second interconnection coupled to the second set of solar cells in the second serial configuration. The device has an inverter device coupled to a back side of the substrate member. The inverter device includes a first set of connections coupled to the first interconnection and a second set of connections coupled to the second interconnection. | 2014-06-05 |
| 20140153304 | AC-DC CONVERTER FOR WIDE RANGE OUTPUT VOLTAGE AND HIGH SWITCHING FREQUENCY - An electrical circuit includes an input for an AC input voltage coupled to a first inductive element with first and second outputs coupled to respective first and second nodes, and a four-quadrant (4-Q) switch coupled between the first and second nodes. A capacitor is coupled between the first node and a third node, a second inductive element is coupled between the third node and the second node, and a first bidirectional device and a first diode are coupled in series between a positive output node and a negative output node. A first output of the second inductive element is coupled between the first bidirectional device and the first diode. A second bidirectional device and a second diode are coupled in series between the positive output node and the negative output node. A second output of the second inductive element is coupled between the second bidirectional device and the second diode. | 2014-06-05 |
| 20140153305 | AC/DC CONVERTER WITH PASSIVE POWER FACTOR CORRECTION CIRCUIT AND METHOD OF CORRECTING POWER FACTOR - An AC/DC converter includes a rectifier circuit and a power factor correction circuit. An input port of the rectifier circuit receives an alternate current. The power factor correction circuit includes a first inductor, a second inductor, a first capacitor, a second capacitor, a first diode and a second diode. An end of the first inductor electrically connects to a positive pole of an output port of the rectifier circuit, and the other end electrically connects to a ground terminal of the output port through two parallel series routes which are bridged by the first diode. Wherein a series route contains the first capacitor and the second diode, and the other series route contains the second inductor and the second capacitor. The second capacitor is provided for parallel connecting with a loading. In this way, the input current could be controlled to increase the power factor effectively. | 2014-06-05 |
| 20140153306 | AC/DC CONVERTER AND METHOD OF CORRECTING POWER FACTOR - An AC/DC converter includes a rectifier circuit and an active power factor correction circuit. The rectifier circuit is electrically connected to a power supply, and is used to convert an alternate current into a direct current, wherein the rectifier circuit has a positive output and a negative output for sending out the direct current. The active power factor correction circuit electrically connects the rectifier circuit and a loading, wherein the active power factor correction circuit is used to suppress voltage ripples provided to the loading. | 2014-06-05 |
| 20140153307 | DRIVER DEVICE FOR POWER FACTOR CORRECTION CIRCUIT - There is provided a driver device for a power factor correction circuit including first and second main switches that are switched on and off with a phase difference therebetween, and first and second auxiliary switches that provide conduction paths of surplus voltage in the first and second main switches before the first and second main switches are switched on, the driver device including: an input unit receiving a plurality of input signals; and an output unit outputting a first control signal for the first main switch, a second control signal for the second main switch, a third control signal for the first auxiliary switch, and a fourth control signal for the second auxiliary switch based on a plurality of input signals. | 2014-06-05 |
| 20140153308 | RECTIFIER CHARGE RATE CONTROLLER - A rectifier circuit comprising an AC input, at least one thyristor coupled to the AC input, a DC bus driven by the at least one thyristor, a controller arranged to: derive a first current in the DC bus, derive a maximum current demand on the DC bus, and provide a trigger signal to the at least one thyristor based on the derived maximum current and the derived first current. | 2014-06-05 |
| 20140153309 | FREQUENCY CONVERTER AND SWITCHING METHOD THEREOF - A frequency converter includes a comparator, an error computation unit and a calibration unit. The comparator receives a reference voltage signal and a triangle wave signal, and outputs a switching signal. The switching signal is fed back to the error computation unit to calculate an error signal by computing the reference signal and the switching signal. The calibration unit calibrates the triangle wave signal or the reference voltage signal according to the error signal. | 2014-06-05 |
| 20140153310 | CONTENT ADDRESSABLE MEMORY - A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F | 2014-06-05 |
| 20140153311 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each including a storage element and a switching element which are connected in series between adjacently paired ones of the bit lines. Gates of the switching elements of the memory cells connected between one of the adjacently paired ones of the bit lines are respectively connected to different ones of the word lines. A plurality of the storage elements and a plurality of the switching elements of the adjacent memory cells are alternately connected in series. | 2014-06-05 |
| 20140153312 | MEMORY CELLS HAVING FERROELECTRIC MATERIALS - Memory cells having ferroelectric materials and methods of operating and forming the same are described herein. As an example, a memory cell can include a first electrode and a second electrode, and an ion source and a ferroelectric material formed between the first electrode and the second electrode, where the ferroelectric material serves to stabilize storage of ions transitioned from the ion source. | 2014-06-05 |
| 20140153313 | System and Methods Using a Multiplexed Reference for Sense Amplifiers - A sense amplifier system includes a first path, a second path, a memory cell, a first reference cell, a second reference cell, and a switch component. The switch component is configured to switch connections between the first and second reference cells and the first and second paths according to a sampling phase and an amplification phase. | 2014-06-05 |
| 20140153314 | SYSTEM AND A METHOD FOR DESIGNING A HYBRID MEMORY CELLWITH MEMRISTOR AND COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR - The embodiments herein relates to a hybrid non-volatile memory cell system and architecture for designing integrated circuits. The system comprises CMOS access transistor connected to a memristor which stores a data based on a resistance. The system has a word line for accessing the hybrid memory and two bit lines carrying data of mutually opposite values for transferring a data from the memory. The two terminals of the transistor are connected respectively to a first terminal of the memristor and to a first bit line. The gate terminals of the transistors are coupled together to form a word line. The access transistors control the two bit lines during a read and write operation. A control logic performs a read and write operation with the hybrid memory cells. The memory architecture prevents a power leakage during data storage and controls a drift in a state during a read process. | 2014-06-05 |
| 20140153315 | SEMICONDUCTOR MEMORY APPARATUS, REFRESH METHOD AND SYSTEM - Disclosed are a semiconductor memory apparatus, and refresh method and system. The semiconductor memory apparatus includes: a memory cell array including a plurality of resistive memory cells; and a control block configured to control at least one of a mode and a schedule of a refresh operation for the plurality of memory cells to be variable based on digital code values reflecting resistance states of the plurality of resistive memory cells. Therefore, the refresh of the resistive memory is efficiently performed, and as a result, performance deterioration may be minimized, and a lifespan of the device may be extended. | 2014-06-05 |
| 20140153316 | Methods of Reading and Using Memory Cells - Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is applied for a sufficient duration of time; and the reading is conducted with a pulse that is of too short of a time duration to be sufficient for the write operation. In some embodiments, the pulse utilized for the reading may have an absolute value of voltage that is greater than or equal to the voltage utilized for the write operation. In some embodiments, the memory cells may comprise non-ohmic devices; such as memristors and diodes. | 2014-06-05 |
| 20140153317 | SILICON-BASED NANOSCALE RESISTIVE DEVICE WITH ADJUSTABLE RESISTANCE - A non-volatile solid state resistive device that includes a first electrode, a p-type poly-silicon second electrode, and a non-crystalline silicon nanostructure electrically connected between the electrodes. The nanostructure has a resistance that is adjustable in response to a voltage being applied to the nanostructure via the electrodes. The nanostructure can be formed as a nanopillar embedded in an insulating layer located between the electrodes. The first electrode can be a silver or other electrically conductive metal electrode. A third (metal) electrode can be connected to the p-type poly-silicon second electrode at a location adjacent the nanostructure to permit connection of the two metal electrodes to other circuitry. The resistive device can be used as a unit memory cell of a digital non-volatile memory device to store one or more bits of digital data by varying its resistance between two or more values. | 2014-06-05 |
| 20140153318 | CIRCUIT AND METHOD FOR READING A RESISTIVE SWITCHING DEVICE IN AN ARRAY - A read circuit for sensing a resistance state of a resistive switching device in a crosspoint array utilizes an equipotential preamplifier connected to a selected column line of the resistive switching device in the array. The equipotential preamplifier delivers a sense current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. The read circuit has a reference current source for generating a sense reference current, and a current comparator connected to evaluate the sense current delivered by the equipotential preamplifier against the sense reference current and generating an output signal indicative of the resistance state of the resistive switching device. | 2014-06-05 |
| 20140153319 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor. | 2014-06-05 |
| 20140153320 | SEMICONDUCTOR STORAGE DEVICE - A memory cell power supply circuit for each column includes a first PMOS transistor and a second PMOS transistor connected together in series between a first power supply and a second power supply. A connection point between the first and second PMOS transistors is output as a memory cell power supply. A control signal which is based on a column select signal and a write control signal is input to a gate terminal of the first PMOS transistor. A signal which is an inverted version of the signal input to the gate terminal of the first PMOS transistor is input to a gate terminal of the second PMOS transistor. | 2014-06-05 |
| 20140153321 | Methods and Apparatus for FinFET SRAM Arrays in Integrated Circuits - Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit are provided. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y | 2014-06-05 |
| 20140153322 | SRAM Cell Comprising FinFETs - A Static Random Access Memory (SRAM) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction. The first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries. A CVss line carrying a VSS power supply voltage crosses the first long boundary and the second long boundary. The CVss line is parallel to the second direction. A bit-line and a bit-line bar are on opposite sides of the CVss line. The bit-line and the bit-line bar are configured to carry complementary bit-line signals. | 2014-06-05 |
| 20140153323 | Methods for Operating SRAM Cells - A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other. | 2014-06-05 |
| 20140153324 | Magnetic Tunnel Junction Memory Device - A magnetic-assist, spin-torque transfer magnetic tunnel junction device and a method for performing a magnetic-assist, spin-torque-transfer write to the device are disclosed. In an exemplary embodiment, the magnetic tunnel junction device includes a first electrode, a pinned layer disposed on the first electrode, a free layer disposed on the pinned layer, and a barrier layer disposed between the pinned layer and the free layer. The device further includes a second electrode electrically coupled to the free layer, the second electrode containing a magnetic assist region. In some embodiments, the magnetic assist region is configured to produce a net magnetic field when supplied with a write current. The net magnetic field is aligned to assist a spin-torque transfer of the write current on the free layer. | 2014-06-05 |
| 20140153325 | BODY VOLTAGE SENSING BASED SHORT PULSE READING CIRCUIT - As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1V supply voltage, which is greater than reference designs achieve at 5 ns performance. | 2014-06-05 |
| 20140153326 | CELL SENSING CIRCUIT FOR PHASE CHANGE MEMORY AND METHODS THEREOF - A cell sensing circuit for a phase changing memory and methods thereof are provided. A specific one of the proposed methods includes: providing a sensing circuit having a sense amplifier, and two identical stable currents respectively received by a reference cell and a target cell; establishing a cell voltage on a cell side and a reference voltage on a reference side respectively via the two identical stable currents; and using the sense amplifier to determine a logic state of the target cell based on a voltage difference between the reference voltage and the cell voltage. | 2014-06-05 |
| 20140153327 | VOLTAGE CONTROLLED SPIN TRANSPORT CHANNEL - A spin transport channel includes a dielectric layer contacting a conductive layer. The dielectric layer includes at least one of a tantalum oxide, hafnium oxide, titanium oxide, and nickel oxide. An intermediate spin layer contacts the dielectric layer. The intermediate spin layer includes at least one of copper and silver. The conductive layer is more electrochemically inert than the intermediate spin layer. A polarizer layer contacts the intermediate spin layer. The polarizer layer includes one of a nickel-iron based material, iron, and cobalt based material. The conductive layer and intermediate layer are disposed on opposite sides of the dielectric layer. The dielectric layer and the polarizer layer are disposed on opposite sides of the intermediate spin layer. The intermediate spin layer is arranged to form a conducting path through the dielectric layer configured to transport a plurality of electrons. Each of the plurality of electrons maintains a polarized electron spin. | 2014-06-05 |
| 20140153328 | COMPLEMENTARY SOI LATERAL BIPOLAR FOR SRAM IN A CMOS PLATFORM - An example embodiment is a memory array. The memory array includes a SOI substrate and lateral bipolar junction transistors (BJTs) fabricated on the SOI substrate. The BJTs form first and second inverters cross coupled to form a memory cell. A read circuit outputs the binary state of the memory cell. A power supply is configured to supply a Vdd voltage to the read circuit and to supply a Vcc and a Vee voltage to the first set of lateral bipolar transistors and the second set of lateral bipolar transistors, wherein the Vee voltage is at least zero volts and the Vcc voltage is greater than the Vee voltage and is equal to or less than the Vdd voltage. | 2014-06-05 |
| 20140153329 | NONVOLATILE MEMORY DEVICE COMPRISING PAGE BUFFER AND OPERATION METHOD THEREOF - A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set. | 2014-06-05 |
| 20140153330 | METHOD FOR OPERATING NON-VOLATILE MEMORY DEVICE AND MEMORY CONTROLLER - An operating method for a non-volatile memory device includes applying first and second read voltages to a first word line to perform a read operation; counting first memory cells each having a threshold voltage belonging to a first voltage range between the first read voltage and the second read voltage; applying a third read voltage to the first word line sequentially after applying the second read voltage to count second memory cells each having a second threshold voltage belonging to a voltage range between the second read voltage and the third read voltage; comparing the number of first memory cells counted and the number of second memory cells counted; determining a fourth read voltage based on a result of the comparing; and applying the fourth read voltage to the first word line sequentially after applying the third read voltage. | 2014-06-05 |
| 20140153331 | MULTI-LEVEL CELL MEMORY DEVICE AND OPERATING METHOD THEREOF - According to an example embodiment of inventive concepts, an operating method of a non-volatile memory device includes: performing a first hard decision read operation that includes applying a first voltage if a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch. | 2014-06-05 |
| 20140153332 | DETERMINING SOFT DATA FROM A HARD READ - Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state. | 2014-06-05 |
| 20140153333 | Systems and Methods to Avoid False Verify and False Read - In a nonvolatile NAND memory array, a NAND block may be falsely determined to be in an erased condition because of the effect of unwritten cells prior to the erase operation. Such cells may be programmed with dummy data prior to erase, or parameters used for a verify operation may be modified to compensate for such cells. Read operations may be similarly modified to compensate for unwritten cells. | 2014-06-05 |
| 20140153334 | TERMINATION FOR COMPLEMENTARY SIGNALS - Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described. | 2014-06-05 |
| 20140153335 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 2014-06-05 |
| 20140153336 | SEMICONDUCTOR MEMORY DEVICE HAVING A PLURALITY OF CHIPS AND CAPABILITY OF OUTPUTTING A BUSY SIGNAL - One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips. | 2014-06-05 |
| 20140153337 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The memory cells are stacked above a semiconductor substrate, and each includes a charge accumulation layer and control gate. The word lines are coupled to the control gates. The driver circuit repeats a programming operation to write data in a memory cell coupled to a selected word line. In the programming operation, a first voltage is applied to the selected word line, a second voltage to a first unselected word line, and a third voltage to a second unselected word line. The control circuit steps up the first voltage and steps down the second voltage in repeating the programming. | 2014-06-05 |
| 20140153338 | MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM USING SOFT READ VOLTAGES - A method is provided for operating a memory system. The method includes reading nonvolatile memory cells using a first soft read voltage, a voltage level difference between the first soft read voltage and a first hard read voltage being indicated by a first voltage value; and reading the nonvolatile memory cells using a second soft read voltage paired with the first soft read voltage, a voltage level difference between the second soft read voltage and the first hard read voltage being indicated by a second voltage value. The second voltage value is different than the first voltage value. Also, a difference between the first voltage value and the second voltage value corresponds to the degree of asymmetry of adjacent threshold voltage distributions among multiple threshold voltage distributions set for the nonvolatile memory cells of the memory system. | 2014-06-05 |
| 20140153339 | NONVOLATILE MEMORY DEVICE HAVING SELECTABLE SENSING MODES, MEMORY SYSTEM HAVING THE SAME AND PROGRAMMING METHOD THEREOF - A non-volatile memory device which includes a sensing mode selector configured to select a sensing mode according to environment information. A page buffer senses a data state of a memory cell in one of a plurality of sensing methods, depending upon the selected sensing mode. | 2014-06-05 |
| 20140153340 | METHOD FOR ERASING CHARGE TRAP DEVICES - A method of erasing charge trap devices includes applying a first erase voltage to the charge trap devices; applying an erase verify voltage to the charge trap devices; performing a current first fail bit check operation including comparing a first number of charge trap devices, which are determined to be an erase fail based on the erase verify voltage, to a first reference value and determining a pass or fail based on the comparison result; when the current first fail bit check operation is determined to be a fail, determining whether a previous first fail bit check operation performed during a previous erase loop was passed or not; and when the previous first fail bit check operation performed during the previous erase loop was passed, setting a third erase voltage to a same level as a second erase voltage used during the previous erase loop. | 2014-06-05 |
| 20140153341 | SEQUENTIAL ACCESS MEMORY WITH MASTER-SLAVE LATCH PAIRS AND METHOD OF OPERATING - A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array. | 2014-06-05 |
| 20140153342 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MONITORING REFERENCE VOLTAGE THEREOF - A semiconductor integrated circuit includes a write path coupled to a pad, a read path coupled to the pad, and a reference voltage output control block configured to apply a reference voltage to the pad through the write path in response to a reference voltage monitoring signal. The read path is electrically isolated from the pad in response to the reference voltage monitoring signal. | 2014-06-05 |
| 20140153343 | LOW VOLTAGE SENSING SCHEME HAVING REDUCED ACTIVE POWER DOWN STANDBY CURRENT - A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 2014-06-05 |
| 20140153344 | SEMICONDUCTOR MEMORY DEVICE, SYSTEM HAVING THE SAME AND METHOD FOR GENERATING REFERENCE VOLTAGE FOR OPERATING THE SAME - A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage. | 2014-06-05 |
| 20140153345 | METHOD OF OPERATING WRITE ASSIST CIRCUITRY - A method includes causing, by a first circuit, a first signal transition at a first node based on a clock signal. A first edge, from a first level to a second level, of a word line signal is generated responsive to the first signal transition. A second signal transition at a second node is caused by a second circuit based on the clock signal. The second circuit and the first circuit are configured to cause the second signal transition to occur later than the first signal transition by a delay time. A first edge, from a third logic level to a fourth level, of a tracking word line signal is generated responsive to the second signal transition. | 2014-06-05 |
| 20140153346 | Read Assist Scheme for Reducing Read Access Time in a Memory - A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory. | 2014-06-05 |
| 20140153347 | INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY - An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier. | 2014-06-05 |
| 20140153348 | Operation Scheme for Non-Volatile Memory - A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted. | 2014-06-05 |
| 20140153349 | Simultaneous Two/Dual Port Access on 6T SRAM - A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal. | 2014-06-05 |
| 20140153350 | METHODS AND APPARATUSES FOR REFRESHING MEMORY - Apparatuses and methods for memory refreshing memory cells is described. An example method includes receiving a self refresh command at a memory. The method further includes refreshing the memory at a first refresh rate after receiving the self refresh command. The method further includes refreshing the memory at a second refresh rate in response to a determination that each memory cell of the memory has been refreshed at the first refresh rate. The first refresh rate is greater than a second refresh rate. | 2014-06-05 |
| 20140153351 | MEMORY DEVICE POWER CONTROL - The apparatus described herein may comprise a first set of transistors, including a first transistor and a second transistor, and a second set of transistors, including a third transistor and a fourth transistor. Gates of the first and second transistors may be coupled to a first signal and a second signal, respectively, each indicating whether a corresponding one of a first supply voltage and a second supply voltage reaches a first threshold voltage or a second threshold voltage to power on a first circuit or a second circuit of a memory device. Gates of the third and fourth transistors may be coupled to a first inverted version of the first signal and a second inverted version of the second signal, respectively. An outcome signal of the second set of transistors may indicate a power-on state of the memory device responsive to power states of the first and second signals. | 2014-06-05 |
| 20140153352 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - A method for accessing a plurality of DRAM devices each having a plurality of banks, includes determining an operating mode for the plurality of DRAM devices, providing a chip selection address and a bank address with an active command to activate a first bank in a first one of the plurality of DRAM devices and, while the first bank in the first one of the plurality of DRAM devices is activated, one or more first banks in remaining DRAM devices of the plurality of DRAM devices are: not activated if the operating mode is determined to be a logical rank address mode, and possibly activated if the operating mode is determined to be a physical rank address mode, and subsequently providing at least a bank address with a column command to access the first bank in the first one of the plurality of DRAM devices. | 2014-06-05 |
| 20140153353 | METHOD AND AN APPARATUS FOR ADDING AN ADDITIVE TO A CEMENT-LIKE COMPOSITION - Disclosed is a method for adding an additive to a cement-like composition, preferably a concrete mixture. The method includes forming a liquid flow, preferably a water flow; feeding an additive to the system; dosing said additive to said liquid flow by feeding it transversely and/or counter-currently to the liquid flow in such a way that mixture is formed which includes said additive and nanocellulose; and adding the formed mixture as an additive to a cement-like composition. Furthermore, disclosed is a cement-like composition and to an apparatus for adding an additive to a cement-like composition. | 2014-06-05 |
| 20140153354 | ARRANGEMENT AND METHOD FOR HANDLING CEMENT MORTAR - Mixing device for handling of a cement product, comprising a carryable mixing unit for mixing of powder and water, a feeder unit for feeding in powder to the mixing unit and a flexible tube packet connecting the mixing unit to the feeder unit, wherein the mixing unit comprises a receiver part for powder, dosing equipment for powder, dosing equipment for water, a mixer for mixing of powder and water and an outlet pump for feeding out the finished mixed cement product. An advantage of the invention is that the mixing unit can be carried by one person, which simplifies the handling of the mixing unit. A further advantage is that dosing and mixing of a cement product takes place automatically. The mixing of the cement product thus may take place continually. | 2014-06-05 |
