| 23rd week of 2014 patent applcation highlights part 17 |
| Patent application number | Title | Published |
|---|
| 20140151755 | BACKSIDE CMOS COMPATIBLE BIOFET WITH NO PLASMA INDUCED DAMAGE - The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer. | 2014-06-05 |
| 20140151756 | FIN FIELD EFFECT TRANSISTORS INCLUDING COMPLIMENTARILY STRESSED CHANNELS - A stressed single crystalline epitaxial semiconductor layer having a first type stress is formed on a single crystalline substrate layer. First and second semiconductor fins are formed by patterning the stressed single crystalline epitaxial semiconductor layer. A center portion of each first semiconductor fin is undercut to form a recessed region, while the bottom surface of each second semiconductor fin maintains epitaxial registry with the single crystalline substrate layer. The center portion of each first semiconductor fin is under a second type of stress, which is the opposite of the first type of stress. A first field effect transistor formed on the first semiconductor fins can include first channels under the second type of stress along direction of current flow, and a second field effect transistor formed on the second semiconductor fins can include second channels under the first type of stress along the direction of current flow. | 2014-06-05 |
| 20140151757 | SUBSTRATE-TEMPLATED EPITAXIAL SOURCE/DRAIN CONTACT STRUCTURES - Single crystalline semiconductor fins are formed on a single crystalline buried insulator layer. After formation of a gate electrode straddling the single crystalline semiconductor fins, selective epitaxy can be performed with a semiconductor material that grows on the single crystalline buried insulator layer to form a contiguous semiconductor material portion. The thickness of the deposited semiconductor material in the contiguous semiconductor material portion can be selected such that sidewalls of the deposited semiconductor material portions do not merge, but are conductively connected to one another via horizontal portions of the deposited semiconductor material that grow directly on a horizontal surface of the single crystalline buried insulator layer. Simultaneous reduction in the contact resistance and parasitic capacitance for a fin field effect transistor can be provided through the contiguous semiconductor material portion and cylindrical contact via structures. | 2014-06-05 |
| 20140151758 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a ridge extending along the first direction and the drift zone including a superjunction layer stack. | 2014-06-05 |
| 20140151759 | FACET-FREE STRAINED SILICON TRANSISTOR - The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended. | 2014-06-05 |
| 20140151760 | DOPED FLOWABLE PRE-METAL DIELECTRIC - A method of filling gaps between gates with doped flowable pre-metal dielectric (PMD) and the resulting device are disclosed. Embodiments include forming at least two dummy gates on a substrate, each dummy gate being surrounded by spacers; filling a gap between adjacent spacers of the at least two dummy gates with a flowable PMD; implanting a dopant in the flowable PMD; and annealing the flowable PMD. Doping the flowable PMD prevents erosion of the PMD, thereby providing a voidless gap-fill. | 2014-06-05 |
| 20140151761 | Fin-Like Field Effect Transistor (FinFET) Channel Profile Engineering Method And Associated Device - A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin. | 2014-06-05 |
| 20140151762 | Semiconductor Device and Method of Forming the Same - A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film. | 2014-06-05 |
| 20140151763 | SEMICONDUCTOR STRUCTURE HAVING CONTACT PLUG AND METHOD OF MAKING THE SAME - The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same. | 2014-06-05 |
| 20140151764 | SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF - A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a base, an epitaxy layer, a first well, a second well, a third well, a first heavily doping region, a second heavily doping region, a implanting region and a conductive layer. The epitaxy layer is disposed on the base. The first well, the second well and the third well are disposed in the epitaxy layer. The third well is located between the first well and the second well. A surface channel is formed between the first heavily doping region and the second heavily doping region. The implanting region is fully disposed between the surface channel and the base and disposed at a projection region of the first well, the second well and the third well. | 2014-06-05 |
| 20140151765 | GATE-ALL-AROUND CARBON NANOTUBE TRANSISTOR WITH SELECTIVELY DOPED SPACERS - A method of fabricating a semiconducting device is disclosed. A carbon nanotube is formed on a substrate. A portion of the substrate is removed to form a recess below a section of the carbon nanotube. A doped material is applied in the recess to fabricate the semiconducting device. The recess may be between one or more contacts formed on the substrate separated by a gap. | 2014-06-05 |
| 20140151766 | FinFET DEVICE WITH DUAL-STRAINED CHANNELS AND METHOD FOR MANUFACTURING THEREOF - A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed. | 2014-06-05 |
| 20140151767 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact. | 2014-06-05 |
| 20140151768 | TERAHERTZ IMAGER WITH DETECTION CIRCUIT - A pixel circuit including: a differential detection circuit having first and second transistors coupled in series between differential output nodes of an antenna, the antenna being configured to be sensitive to terahertz radiation, and wherein: a first main conducting node of the first transistor is coupled to a first of the differential output nodes of the antenna; and a first main conducting node of the second transistor is coupled to a second of said differential output nodes of the antenna, wherein second main conducting nodes of the first and second transistors are formed by a common semiconductor region. | 2014-06-05 |
| 20140151769 | DETECTION APPARATUS AND RADIATION DETECTION SYSTEM - A detection apparatus includes a conversion layer configured to convert incident light or radiation into a charge, electrodes configured to collect a charge produced as a result of the conversion by the conversion layer, and impurity semiconductor layers arranged between the electrodes and the conversion layer. The conversion layer is arranged over the electrodes so as to cover the electrodes. A part of the conversion layer which covers a region between an adjacent pair of the electrodes includes a portion smaller in film thickness than a part of the conversion layer which covers edges of the electrodes. | 2014-06-05 |
| 20140151770 | THIN FILM DEPOSITION AND LOGIC DEVICE - A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer. | 2014-06-05 |
| 20140151771 | THIN FILM DEPOSITION AND LOGIC DEVICE - A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer. | 2014-06-05 |
| 20140151772 | UNIFORM FINFET GATE HEIGHT - A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen. | 2014-06-05 |
| 20140151773 | FINFET eDRAM STRAP CONNECTION STRUCTURE - A method of forming a strap connection structure for connecting an embedded dynamic random access memory (eDRAM) to a transistor comprises forming a buried oxide layer in a substrate, the buried oxide layer defining an SOI layer on a surface of the substrate; forming a deep trench through the SOI layer and the buried oxide layer in the substrate; forming a storage capacitor in a lower portion of the deep trench; conformally doping a sidewall of an upper portion of the deep trench; depositing a metal strap on the conformally doped sidewall and on the storage capacitor; forming at least one fin in the SOI layer, the fin being in communication with the metal strap; forming a spacer over the metal strap and over a juncture of the fin and the metal strap; and depositing a passive word line on the spacer. | 2014-06-05 |
| 20140151774 | NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME - Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars. | 2014-06-05 |
| 20140151775 | CONTROL GATE - A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation. | 2014-06-05 |
| 20140151776 | VERTICAL MEMORY CELL - Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension. | 2014-06-05 |
| 20140151777 | Semiconductor Memory Devices and Methods of Fabricating the Same - Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench. | 2014-06-05 |
| 20140151778 | Select Gate Formation for Nanodot Flat Cell - Methods of fabricating a memory device include forming a tunnel oxide layer over a memory cell area of a semiconductor substrate, forming a floating gate layer over the tunnel oxide layer in the memory cell area, the floating gate layer comprising a plurality of nanodots embedded in a dielectric material, forming a blocking dielectric layer over the floating gate layer in the memory cell area, removing portions of the blocking dielectric layer, the floating gate layer, the tunnel oxide layer, and the semiconductor substrate in the memory cell area to form a first plurality of isolation trenches, and forming isolation material within the first plurality of isolation trenches. | 2014-06-05 |
| 20140151779 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer. | 2014-06-05 |
| 20140151780 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes a floating gate formed over a substrate, a select gate formed adjacent to the floating gate with a gap defined therebetween, spacers formed on sidewalls of the floating gate and the select gate and filling the gap, a first junction region formed in the substrate adjacent to the floating gate, and a second junction region formed in the substrate adjacent to the select gate. | 2014-06-05 |
| 20140151781 | PROCESS FOR FABRICATING A TRANSISTOR COMPRISING NANOCRYSTALS - A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side. | 2014-06-05 |
| 20140151782 | Methods and Apparatus for Non-Volatile Memory Cells with Increased Programming Efficiency - Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided. | 2014-06-05 |
| 20140151783 | NONVOLATILE MEMORY INCLUDING MEMORY CELL ARRAY HAVING THREE-DIMENSIONAL STRUCTURE - A nonvolatile memory is provided which includes a plurality of channel layers and a plurality of insulation layers alternately stacked on a substrate in a direction perpendicular to the substrate, each of the plurality of channel layers including a plurality of channel films extending along a first direction on a plane parallel with the substrate; a plurality of conductive materials extending from a top of the channel layers and the insulation layers up to a portion adjacent to the substrate in a direction perpendicular to the substrate through areas among channel films of each channel layer; a plurality of information storage films provided between the channel films of the channel layers and the conductive materials; and a plurality of bit lines connected to the channel layers, respectively, wherein the conductive materials, the information storage films, and the channel films of the channel layers form a three-dimensional memory cell array, wherein the conductive materials form a plurality of groups, and wherein a distance between the groups is longer than a distance between conductive materials in each other. | 2014-06-05 |
| 20140151784 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween. A seed pattern is formed on a surface of the trench and a metal layer is formed on the seed pattern in the trench. | 2014-06-05 |
| 20140151785 | SEMICONDUCTOR DEVICE - The element electrodes of a semiconductor element are disposed in a cell region, while an outermost peripheral electrode electrically connected to a semiconductor substrate is disposed in a peripheral region. In the peripheral region, a second-conductivity-type layer is disposed above a super-junction structure. A potential division region is disposed above the second-conductivity-type layer to electrically connect the element electrodes and the outermost peripheral electrode and also divide the voltage between the element electrodes and the outermost peripheral electrode into a plurality of stages. A part of the potential division region overlaps the peripheral region when viewed from the thickness direction of the semiconductor substrate. | 2014-06-05 |
| 20140151786 | NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH - Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit. | 2014-06-05 |
| 20140151787 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence. | 2014-06-05 |
| 20140151788 | TRENCH POWER FIELD EFFECT TRANSISTOR DEVICE AND METHOD - In one embodiment, a structure for a trench power field effect transistor device with controlled, shallow, abrupt, body contact regions. | 2014-06-05 |
| 20140151789 | Semiconductor Device Including Trenches and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench. | 2014-06-05 |
| 20140151790 | APPROACH TO INTEGRATE SCHOTTKY IN MOSFET - An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions. | 2014-06-05 |
| 20140151791 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a memory cell region having a first transistor and a peripheral circuit region having a second transistor. The first transistor has a first source electrode and a first drain electrode, a first buried gate insulating film which is formed along an inner wall of a trench and whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and a buried gate electrode. The second transistor has a second source electrode and a second drain electrode, a first on-substrate gate insulating film whose relative dielectric constant is higher than a relative dielectric constant of silicon oxide, and an on-substrate gate electrode. A first Hf content percentage, which is a content percentage of hafnium in the first buried gate insulating film, is different from a second Hf content percentage, which is a content percentage of hafnium in the first on-substrate gate insulating film. | 2014-06-05 |
| 20140151792 | HIGH VOLTAGE HIGH SIDE DMOS AND THE METHOD FOR FORMING THEREOF - A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base region, a deep P-type region, an N-type lightly doped well region, a first N-type highly doped region, a second N-type highly doped region and a P-type highly doped region. | 2014-06-05 |
| 20140151793 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end portion thereof extending over the isolation layer. | 2014-06-05 |
| 20140151794 | SEMICONDUCTOR DEVICE INCLUDING A REDISTRIBUTION LAYER AND METALLIC PILLARS COUPLED THERETO - A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer. | 2014-06-05 |
| 20140151795 | SEMICONDUCTOR DEVICE INCLUDING GATE DRIVERS AROUND A PERIPHERY THEREOF - A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer. | 2014-06-05 |
| 20140151796 | HYBRID HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively. | 2014-06-05 |
| 20140151797 | SEMICONDUCTOR DEVICE INCLUDING ALTERNATING SOURCE AND DRAIN REGIONS, AND RESPECTIVE SOURCE AND DRAIN METALLIC STRIPS - A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips formed in a first metallic layer above the substrate and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions. | 2014-06-05 |
| 20140151798 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone. | 2014-06-05 |
| 20140151799 | Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively. | 2014-06-05 |
| 20140151800 | LATERAL DOUBLE-DIFFUSED MOSFET - A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain. | 2014-06-05 |
| 20140151801 | UNIFORM FINFET GATE HEIGHT - A method including providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer, removing a portion of the plurality of fins to form an opening, and forming a dielectric spacer on a sidewall of the opening. The method may also include filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen. | 2014-06-05 |
| 20140151802 | Semiconductor Device Having SSOI Substrate - A method comprises: forming a tensile SSOI layer on a buried oxide layer on a bulk substrate; forming a plurality of fins in the SSOI layer; removing a portion of the fins; annealing remaining portions of the fins to relax a tensile strain of the fins; and merging the remaining portions of the fins. | 2014-06-05 |
| 20140151803 | Inducing Channel Stress in Semiconductor-on-Insulator Devices by Base Substrate Oxidation - Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region. | 2014-06-05 |
| 20140151804 | Semiconductor Device Including a Fin and a Drain Extension Region and Manufacturing Method - One embodiment of a semiconductor device includes a fin on a first side of a semiconductor body. The semiconductor device further includes a body region of a second conductivity type in at least a part of the fin. The semiconductor device further includes a drain extension region of a first conductivity type, a source and a drain region of the first conductivity type, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region. | 2014-06-05 |
| 20140151805 | METHOD FOR FABRICATING A CONNECTION REGION IN A SEMICONDUCTOR DEVICE - Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a buried-type wordline in an active region defined on a SOI substrate, forming a silicon connection region for connecting an upper silicon layer to a lower silicon layer between neighboring buried type wordlines, and recovering the upper silicon layer on the silicon connection region. | 2014-06-05 |
| 20140151806 | Semiconductor Device Having SSOI Substrate - A method comprises: forming a tensile SSOI layer on a buried oxide layer on a bulk substrate; forming a plurality of fins in the SSOI layer; removing a portion of the fins; annealing remaining portions of the fins to relax a tensile strain of the fins; and merging the remaining portions of the fins. | 2014-06-05 |
| 20140151807 | COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE - A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer. | 2014-06-05 |
| 20140151808 | BULK FINFET ESD DEVICE - Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region. | 2014-06-05 |
| 20140151809 | APPARATUS FOR ESD PROTECTION - A structure comprises an N+ region formed over a substrate, a P+ region formed over the substrate, wherein the P+ region and the N+ region form a diode and a first epitaxial growth block region formed between the N+ region and the P+ region. | 2014-06-05 |
| 20140151810 | SEMICONDUCTOR DEVICES INCLUDING PROTRUDING INSULATION PORTIONS BETWEEN ACTIVE FINS - A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins. | 2014-06-05 |
| 20140151811 | SRAM Cell Comprising FinFETs - A Static Random Access Memory (SRAM) cell includes a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET, and a first pull-down FinFET and a second pull-down FinFET forming cross-latched inverters with the first pull-up FinFET and the second pull-up FinFET. A first pass-gate FinFET is connected to drains of the first pull-up FinFET and the first pull-down FinFET. A second pass-gate FinFET is connected to drains of the second pull-up FinFET and the second pull-down FinFET, wherein the first and the second pass-gate FinFETs are p-type FinFETs. A p-well region is in a center region of the SRAM cell and underlying the first and the second pull-down FinFETs. A first and a second n-well region are on opposite sides of the p-well region. | 2014-06-05 |
| 20140151812 | Contact Plugs in SRAM Cells and the Method of Forming the Same - A method includes forming a dielectric layer over a portion of an SRAM cell. The SRAM cell includes a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor, and a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively. A first mask layer is formed over the dielectric layer and patterned. A second mask layer is formed over the dielectric layer and patterned. The dielectric layer is etched using the first mask layer and the second mask layer in combination as an etching mask, wherein a contact opening is formed in the dielectric layer. A contact plug is formed in the contact opening. | 2014-06-05 |
| 20140151813 | COMPUTER CHIP ARCHITECTURE - A computer chip utilizing a hybrid metal gate wherein metal inserted poly silicon (MIPS) is used for nMOS and replacement metal gate (RMG) is used for pMOS, and wherein poly silicon doping over metal gates has been performed. The chip may be bombarded with boron isotopes or may have impurities added to dampen ringing noises. The chip may comprise a constituent material having characteristics of venting wells and distributed connections between layers. A highly reflective, stable metalloid agent may be bound to deposited metal layers. The constituent material may comprise a crystal having natural vacant states. The computer chip may comprise vertically stacked transistors. Vertical surface cavities located at metal junction points may serve as exhaust pipes. | 2014-06-05 |
| 20140151814 | METHODS FOR FORMING FINS FOR METAL OXIDE SEMICONDUCTOR DEVICE STRUCTURES - Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins. | 2014-06-05 |
| 20140151815 | READ-ONLY MEMORY AND ITS MANUFACTURING METHOD - A read-only memory includes a plurality of storage units arranged in an array. The read-only memory includes two kinds of storage units with different structures, the two kinds of storage units with different structures are a first MOS transistor and a second MOS transistor. A source and a drain of the first MOS transistor have the same type, a source and a drain of the second MOS transistor have inverse type. These two kinds of MOS transistors can be used to store binary 0 and 1 respectively. In the manufacturing method of the read-only memory, the same type of drain and source can be manufactured simultaneously, no extra mask plate is needed, so the extra mask plate of a conventional read-only memory can be saved. | 2014-06-05 |
| 20140151816 | NOVEL CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHODS OF MAKING SAME - One device includes first and second spaced-apart active regions formed in a semiconducting substrate, a layer of gate insulation material positioned on the first active region, and a conductive line feature that has a first portion positioned above the gate insulation material and a second portion that conductively contacts the second active region. One method includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, performing an etching process to remove a portion of the gate insulation material formed on the second active region to expose a portion of the second active region, and forming a conductive line feature that comprises a first portion positioned above the layer of gate insulation material formed on the first active region and a second portion that conductively contacts the exposed portion of the second active region. | 2014-06-05 |
| 20140151817 | SELF-ALIGNED CONTACTS - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 2014-06-05 |
| 20140151818 | SEMICONDUCTOR DEVICE WITH A SILICON DIOXIDE GATE INSULATION LAYER IMPLANTED WITH A RARE EARTH ELEMENT AND METHODS OF MAKING SUCH A DEVICE - One illustrative method disclosed herein includes forming a gate insulation layer on a semiconducting substrate, performing an ion implantation process to implant a rare earth element into the gate insulation layer, and forming a silicon-containing gate electrode above the gate insulation layer comprising the implanted rare earth element. One illustrative device disclosed herein includes a gate insulation layer positioned on a semiconducting substrate, wherein the gate insulation layer is comprised of silicon dioxide and a rare earth element, and a silicon-containing gate electrode positioned on the gate insulation layer. | 2014-06-05 |
| 20140151819 | Semiconductor Device Having SiGe Substrate, Interfacial Layer and High K Dielectric Layer - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an interfacial layer. An exemplary structure for a semiconductor device comprises a Si | 2014-06-05 |
| 20140151820 | GAS-DIFFUSION BARRIERS FOR MEMS ENCAPSULATION - A technique for forming an encapsulated microelectromechanical system (MEMS) device includes forming an integrated circuit using a substrate, forming a barrier using the substrate, and forming a MEMS device using the substrate. The method includes encapsulating the MEMS device in a cavity. The barrier is disposed between the integrated circuit and the cavity and inhibits the integrated circuit from outgassing into the cavity. The barrier may be substantially impermeable to gas migration from the integrated circuit. | 2014-06-05 |
| 20140151821 | MEMS STRUCTURE WITH ADAPTABLE INTER-SUBSTRATE BOND - A MEMS structure incorporating multiple joined substrates and a method for forming the MEMS structure are disclosed. An exemplary MEMS structure includes a first substrate having a bottom surface and a second substrate having a top surface substantially parallel to the bottom surface of the first substrate. The bottom surface of the first substrate is connected to the top surface of the second substrate by an anchor, such that the anchor does not extend through either the bottom surface of the first substrate or the top surface of the second substrate. The MEMS structure may include a bonding layer in contact with the bottom surface of the first substrate, and shaped to at least partially envelop the anchor. | 2014-06-05 |
| 20140151822 | Structured Gap for a MEMS Pressure Sensor - A method of fabricating a pressure sensor includes performing a chemical vapor deposition (CVD) process to deposit a first sacrificial layer having a first thickness onto a substrate. A portion of the first sacrificial layer is then removed down to the substrate to form a central region of bare silicon. One of a thermal oxidation process and an atomic layer deposition process is then performed to form a second sacrificial layer on the substrate having a second thickness in the central region that is less than the first thickness. A cap layer is then deposited over the first and second sacrificial layers. The second sacrificial layer is removed from the central region, and the first and second sacrificial layers are removed from a perimeter region that at least partially surrounds the central region on the substrate to form a contiguous, structured gap between the cap layer and the substrate, the structured gap having a first width in the central region and a second width in the perimeter region with the second width being greater than the first width. | 2014-06-05 |
| 20140151823 | MEMS DEVICES AND METHODS OF FORMING SAME - The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack. | 2014-06-05 |
| 20140151824 | SELF-ALIGNED WIRE FOR SPINTRONIC DEVICE - A method for fabricating a spintronic cell includes forming a cavity in a substrate, forming a wire in the cavity, depositing a spacer layer over exposed portions of the substrate and the conductive field line, depositing a layer of conductive material on a portion of the spacer layer, removing portions of the layer of conductive material to define a conductive strap portion, wherein the conductive strap portion has a first distal region a second distal region and a medial region arranged therebetween, wherein the medial region has a cross sectional area that is less than a cross sectional area of the first distal region and a cross sectional area of the second distal region, and forming an spintronic device stack on the conductive strap portion above the conductive field line. | 2014-06-05 |
| 20140151825 | GIANT MAGNETO-RESISTIVE SENSOR AND MANUFACTURING METHOD THEREOF - Disclosed herein are a giant magneto-resistive sensor including a free layer stacked on a substrate and having a rotatable magnetic moment; a ferromagnetic fixed layer having a magnetic moment; a pin layer disposed neighboring the fixed layer; and a spacer layer disposed between the free layer and the fixed layer and having a roughness in an interface contacting the fixed layer, and a method of manufacturing the giant magneto-resistive sensor. | 2014-06-05 |
| 20140151826 | GRAPHENE MAGNETIC TUNNEL JUNCTION SPIN FILTERS AND METHODS OF MAKING - A Tunnel Magnetic Junction of high magnetoresistance is prepared at temperatures and pressure consistent with Si CMOS fabrication and operation. A first metal layer of cobalt or nickel is grown on an interconnect or conductive array line of e.g., copper. The metal layer is formed by electron beam irradiation. Annealing at UHV at temperatures below 700K yields a carbon segregation that forms a few layer thick (average density 3.5 ML) graphene film on the metal layer. Formation of a second layer of metal on top of the graphene barrier layer yields a high performance MTJ. | 2014-06-05 |
| 20140151827 | MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER - The present invention is directed to an STT-MRAM device including a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; and a magnetic fixed layer separated from the magnetic reference layer structure by an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a first non-magnetic perpendicular enhancement layer, the first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer plane thereof, the magnetic fixed layer has a second invariable magnetization direction that is substantially perpendicular to layer plane thereof and is opposite to the first invariable magnetization direction. | 2014-06-05 |
| 20140151828 | SPIN-TORQUE MAGNETORESISTIVE STRUCTURES - Magnetoresistive structures, devices, memories, and methods for forming the same are presented. For example, a magnetoresistive structure includes a first ferromagnetic layer, a first nonmagnetic spacer layer proximate to the first ferromagnetic layer, a second ferromagnetic layer proximate to the first nonmagnetic spacer layer, and a first antiferromagnetic layer proximate to the second ferromagnetic layer. For example, the first ferromagnetic layer may comprise a first pinned ferromagnetic layer, the second ferromagnetic layer may comprise a free ferromagnetic layer, and the first antiferromagnetic layer may comprise a free antiferromagnetic layer. | 2014-06-05 |
| 20140151829 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC TUNNELING JUNCTION ELEMENTS HAVING IMPROVED PERFORMANCE THROUGH CAPPING LAYER INDUCED PERPENDICULAR ANISOTROPY AND MEMORIES USING SUCH MAGNETIC ELEMENTS - A magnetic element and a magnetic memory utilizing the magnetic element are described. A contact is electrically coupled to the magnetic element. The magnetic element includes pinned, nonmagnetic spacer, and free layers and a perpendicular capping layer adjoining the free layer and the contact. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy. The free layer is switchable between magnetic states when a write current is passed through the magnetic element. The free layer includes ferromagnetic layers interleaved with capping layer(s) such that a ferromagnetic layer resides at an edge of the free layer. The capping layer(s) are configured such that the ferromagnetic layers are ferromagnetically coupled. | 2014-06-05 |
| 20140151830 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS HAVING A GRADED MAGNETIC FREE LAYER - A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has a gradient in a critical switching current density (J | 2014-06-05 |
| 20140151831 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS HAVING A THERMALLY STABLE AND EASY TO SWITCH MAGNETIC FREE LAYER - A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer includes a plurality of subregions. Each of the subregions has a magnetic thermal stability constant. The subregions are ferromagnetically coupled such that the free layer has a total magnetic thermal stability constant. The magnetic thermal stability constant is such that the each of the subregions is magnetically thermally unstable at an operating temperature. The total magnetic thermal stability constant is such that the free layer is magnetically thermally stable at the operating temperature. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 2014-06-05 |
| 20140151832 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a light receiving element region, a peripheral region, a boundary region, a plurality of signal lines, and a conductive layer. In light receiving element region, light receiving elements for performing photoelectric conversion are formed. Peripheral region is formed outside light receiving element region for performing input/output of an electric signal from/to the outside of the semiconductor substrate. Boundary region is formed between light receiving element region and peripheral region. The plurality of signal lines are arranged in boundary region for performing input/output of electric signals between light receiving element region and peripheral region. Conductive layer is arranged in a layer different from each of the plurality of signal lines. A relative position of conductive layer as seen from each of the plurality of signal lines is all identical, and conductive layer is all arranged in an identical layer. | 2014-06-05 |
| 20140151833 | PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device according to an exemplary embodiment includes a first substrate, a photoelectric conversion layer disposed above the first substrate, a second substrate which is different from the first substrate and disposed on the photoelectric conversion layer, and a nano pillar layer disposed above the second substrate in which the nano pillar layer includes a plurality of nano pillars which is spaced apart from each other, so as to easily absorb the light. | 2014-06-05 |
| 20140151834 | MEMS Infrared Sensor Including a Plasmonic Lens - A method of fabricating a semiconductor device includes forming an absorber on a substrate, and supporting a cap layer over the substrate to define a cavity between the substrate and the cap layer in which the absorber is located. The method further includes forming a lens layer on the cap layer. The lens layer is spaced apart from the cavity and defines a plurality of grooves and an opening located over the absorber. | 2014-06-05 |
| 20140151835 | BACKSIDE ILLUMINATED IMAGE SENSORS AND METHOD OF MAKING THE SAME - A backside illuminated image sensor includes a substrate with a substrate depth, where the substrate includes a pixel region and a peripheral region. The substrate further includes a front surface and a back surface. The backside illuminated image sensor includes a first isolation structure formed in the pixel region of the substrate, where a bottom of the first isolation structure is exposed at the back surface of the substrate. The backside illuminated image sensor includes a second isolation structure formed in the peripheral region of the substrate, where the second isolation structure has a depth less than a depth of the first isolation structure. The backside illuminated image sensor includes an implant region adjacent to at least a portion of sidewalls of each isolation structure in the pixel region. | 2014-06-05 |
| 20140151836 | OPTICAL SEMICONDUCTOR APPARATUS - The optical semiconductor apparatus includes, on an n-GaAs substrate, a surface-emitting semiconductor laser device and a photodiode integrated on the periphery of the laser device with an isolation region interposed there between. The laser device is composed of an n-DBR mirror, an active region, and a p-DBR mirror and includes a columnar layered structure with its sidewall covered with an insulating film. The photodiode is formed on the substrate and has a circular layered structure wherein an i-GaAs layer and a p-GaAs layer surrounds the laser device with an isolating region interposed between the i-GaAs and p-GaAs layers and the laser device. The diameter of the photodiode is smaller than the diameter of the optical fiber core optically coupled with the optical semiconductor apparatus. Since the laser device and the photodiode are monolithically integrated, the devices do not require optical alignment, and thus, facilitate optical coupling with an optical fiber. | 2014-06-05 |
| 20140151837 | IMAGE SENSOR - An image sensor includes an objective lens arranged on an optical axis; a substrate including a plurality of photoelectric conversion devices; and a micro lens layer including a plurality of micro lenses corresponding to each of the plurality of photoelectric conversion devices, respectively, wherein the plurality of micro lenses includes a central micro lens corresponding to a central portion of the objective lens, and an edge micro lens corresponding to an edge portion of the objective lens, and the plurality of micro lenses are configured such that focal lengths of the micro lenses increase from the central micro lens toward the edge micro lens. | 2014-06-05 |
| 20140151838 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - There are provided a highly reliable semiconductor device capable of suppressing occurrence of cracks as well as securing flatness and a manufacturing method therefor. The semiconductor device includes: a semiconductor substrate; an element region; and a non-element region. The non-element region includes: a top-layer metal wiring in a top layer of metal wirings formed in the non-element region; a flattening film covering an upper surface of the top-layer metal wiring; and a protecting film formed over the flattening film. A removed part where the protecting film is removed is formed in at least part of the non-element region. | 2014-06-05 |
| 20140151839 | AVALANCHE PHOTODIODE WITH LOW BREAKDOWN VOLTAGE - An Si/Ge SACM avalanche photo-diodes (APD) having low breakdown voltage characteristics includes an absorption region and a multiplication region having various layers of particular thicknesses and doping concentrations. An optical waveguide can guide infrared and/or optical signals or energy into the absorption region. The resulting photo-generated carriers are swept into the i-Si layer and/or multiplication region for avalanche multiplication. The APD has a breakdown bias voltage of well less than 12 V and an operating bandwidth of greater than 10 GHz, and is therefore suitable for use in consumer electronic devices, high speed communication networks, and the like. | 2014-06-05 |
| 20140151840 | Method and Apparatus for CMOS Sensor Packaging - Methods and apparatus for forming a bond pad of a semiconductor device such as a backside illuminated (BSI) image sensor device are disclosed. The substrate of a device may have an opening at the backside, through the substrate reaching the first metal layer at the front side of the device. A buffer layer may be formed above the backside of the substrate and covering sidewalls of the substrate opening. A pad metal layer may be formed above the buffer layer and in contact with the first metal layer at the bottom of the substrate opening. A bond pad may be formed in contact with the pad metal layer. The bond pad is connected to the pad metal layer vertically above the substrate, and further connected to the first metal layer of the device at the opening of the substrate. | 2014-06-05 |
| 20140151841 | SEMICONDUCTOR DEVICES HAVING A POSITIVE-BEVEL TERMINATION OR A NEGATIVE-BEVEL TERMINATION AND THEIR MANUFACTURE - Disclosed herein are techniques of manufacturing semiconductor devices having a positive-bevel termination and/or a negative-bevel termination. In a particular example, techniques are disclosed for manufacture of a chip-size SiC device having an orthogonal positive-bevel termination used for the reverse blocking junction. The edge termination may be formed, for example, by cutting across a SiC wafer with a V-shaped dicing tool or blade. The cut may be performed by any suitable dicing tool. The cut may be across a p-n junction for forming positive-bevel termination. Subsequently, a surface of the termination may be etched for removing damage caused by the cutting process. | 2014-06-05 |
| 20140151842 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a semiconductor chip formed with cut fuses over one surface thereof; and migration preventing modules preventing occurrence of a phenomenon in which metal ions of the fuses migrate to cut zones of the fuses; each migration preventing module including: a ground electrode formed in the semiconductor chip to face the fuse with a first insulation member interposed therebetween; a floating electrode formed over the fuse with a second insulation member interposed therebetween to face the ground electrode with the fuse interposed therebetween; and a power supply electrode formed over the floating electrode with a third insulation member interposed therebetween. | 2014-06-05 |
| 20140151843 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING METAL OXIDE STRUCTURES, AND RELATED METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES - Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described. | 2014-06-05 |
| 20140151844 | INTEGRATED CIRCUITS SEPARATED BY THROUGH-WAFER TRENCH ISOLATION - An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material. | 2014-06-05 |
| 20140151845 | SEMICONDUCTOR DEVICE HAVING FUSE PATTERN - A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width. | 2014-06-05 |
| 20140151846 | SHIELDING SILICON FROM EXTERNAL RF INTERFERENCE - Consistent with an example embodiment, there is an integrated circuit device (IC) built on a substrate of a thickness. The IC comprises an active device region of a shape, the active device region having a topside and an underside. Through silicon vias (TSVs) surround the active device region, the TSVs having a depth defined by the substrate thickness. On the underside of and having the shape of the active device region, is an insulating layer. A thin-film conductive shield is on the insulating layer, the conductive shield is in electrical contact with the TSVs. | 2014-06-05 |
| 20140151847 | AREA-EFFICIENT CAPACITOR USING CARBON NANOTUBES - An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating. | 2014-06-05 |
| 20140151848 | MIMCAP STRUCTURE IN A SEMICONDUCTOR DEVICE PACKAGE - The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP is formed between a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures. | 2014-06-05 |
| 20140151849 | ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - An electronic module includes a substrate including at least one structure that reduces stress flow through the substrate, wherein the structure includes at least one trench in a surface of the substrate, and a plurality of capacitor legs disposed on an upper surface of the substrate. | 2014-06-05 |
| 20140151850 | PLATED STRUCTURES - A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate. | 2014-06-05 |
| 20140151851 | TAPERED VIA AND MIM CAPACITOR - A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit. | 2014-06-05 |
| 20140151852 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates. | 2014-06-05 |
| 20140151853 | Ion Implantation Apparatus, Ion Implantation Method, and Semiconductor Device - In the plasma-based ion implantation for accelerating positive ions of a plasma and implanting the positive ions into a substrate to be processed on a holding stage in a processing chamber where the plasma has been excited, ion implantation is achieved in the following manner: an RF power having a frequency of 4 MHz or greater is applied to the holding stage to cause a self-bias voltage to generate on the surface of the substrate. The RF power is applied a plurality of times in the form of pulses. | 2014-06-05 |
| 20140151854 | Method for Separating a Layer and a Chip Formed on a Layer - A method for separating a layer from a substrate. The method includes providing a plurality of trenches extending from a first main surface of the substrate into the substrate. A heat treatment of the substrate is performed such that edges of the trenches grow together at the first main surface to form a closed layer at the first main surface, wherein lower portions of the trenches form one or more cavities within the substrate. After that the closed layer is separated from the substrate along the one or more cavities. | 2014-06-05 |
