23rd week of 2009 patent applcation highlights part 26 |
Patent application number | Title | Published |
20090141505 | WHITE HEAT-HARDENING RESIN COMPOSITION, HARDENED MATERIAL, PRINTED-WIRING BOARD AND REFLECTION BOARD FOR LIGHT EMITTING DEVICE - A white heat-hardening resin composition includes rutile-type titanium oxide and a heat-hardening resin. | 2009-06-04 |
20090141506 | Illumination Device for Kitchen Hood - An illumination device for a kitchen hood includes a light case made by high heat conductive material and a circuit board is connected to an inside of the light case. A terminal is connected to the circuit board and located outside of the light case. A light unit is connected to the circuit board and located in the light case. The light unit directly contacts the inside of the light case so as to conduct the heat from the light unit to the light case. The light case includes an open bottom with which a cover is engaged and a bulb shade is located between the light unit and the cover so as to focus or guide the light beam from the light unit. | 2009-06-04 |
20090141507 | LIGHTING FIXTURE CHANNEL WITH DIFFUSER - Embodiments of this invention may include a lighting fixture having a channel provided with an integrally-formed structure for retaining a diffuser. According to one embodiment of the present invention, the end caps of a channel may include integrally formed retaining arms intended to abut and retain a diffuser located within the channel of the light fixture. Other embodiments of the invention provide interlocking structure for retaining the channel end caps in the desired position relative to the channel. According to one embodiment of the present invention, the end caps are secured to the channel body through a tab-slot connection. The slot and tab combination secure the end caps in a desired angle relative to the channel body. | 2009-06-04 |
20090141508 | LAMP WITH HEAT CONDUCTING STRUCTURE AND LAMP COVER THEREOF - A lamp with heat conducting structure includes a lamp cover made of heat dissipating material. The lamp cover has a hollow configuration therein. An interlayer is horizontally arranged in the lamp cover. The lamp cover is divided into a first space and a second space therein by the interlayer. A LED lamp assembly is disposed in the first space of the lamp cover. A power plug is disposed in the second space of the lamp cover. The power plug has a control circuit board in the second space. The control circuit board has an electronic element disposed thereon. A heat conducting tab protrudes from the interlayer of the lamp cover towards the second space. The heat conducting tab has a heat conducting surface corresponding to the electronic element to thermally contact with the electronic element. | 2009-06-04 |
20090141509 | LIGHTING APPARATUS FOR MOTORCYCLE - A lighting apparatus has a housing and is disposed at a lower end of a front fork of a motorcycle. The housing includes a front opening disposed on a side of a radiation direction of a lighting body and a side opening disposed on a center side in a width direction of a motorcycle. The side opening in the housing, covered by a lid, is wide enough for the lighting body to pass through. The housing includes a wire guide for withdrawing an electric wire and a drain hole formed in a bottom portion of the housing. The lighting body is fixed on a board. The housing includes rails disposed on an upper wall portion and a lower wall portion thereof, into which an upper end and a lower end of the board are to be fitted so as to position the lighting body in a longitudinal direction. | 2009-06-04 |
20090141510 | MOTORCYCLE - A lighting apparatus is mounted to a lower end of a front fork that supports a front wheel via a bearing portion. The lighting apparatus has a housing, an upper surface of which includes a bottom case receiving surface formed thereon. The bottom case receiving surface is shaped so that an outer periphery of a bottom case can fit therein. A rubber sheet is placed between the bottom case and the bottom case receiving surface to offer vibration isolation property. A bolt is screwed into a threaded hole in the bottom case so as to penetrate through a mounting portion having the bottom case receiving surface, so that the lighting apparatus is secured to the bottom case. | 2009-06-04 |
20090141511 | LIGHT BAR AND METHOD FOR MAKING - A light bar is described that is of a modular construction based on one or more large circuit boards that are populated with light beam assemblies and then fastened to an interior space of the light bar housing. Keys that automatically align the light beam assemblies on each of the boards precisely control placement of the assemblies on the board. In turn, each of the boards is keyed to the interior of the light bar housing so that when the board is fastened to the housing the light beam assemblies are automatically registered into alignment with the lenses in the housing so that the beams from the assemblies are properly oriented. The light bar is inexpensive to fabricate and can be assembled quickly and reliably, yet it provides for a high degree of customization, which is a requirement in the emergency vehicle lighting industry. | 2009-06-04 |
20090141512 | LICENSE PLATE ASSEMBLY - The present invention provides a license plate assembly comprising: (i) a housing comprising a back plate and upstanding side walls defining a cavity; (ii) a light guide having first and second major sides that are opposite to each other and one or more side faces defining a thickness of side light guide, said light guide being disposed in said housing and being arranged on said back plate of said housing; (iii) a light source mounted along one or more side faces of said light guide; (iv) a transparent and retroreflective license plate mounted on said first major side of said light guide; and wherein a cushioning layer is provided between said back plate of said housing and said light guide. | 2009-06-04 |
20090141513 | ADAPTIVE FRONT LIGHT SYSTEM USING LED HEADLAMP - Provided is an adaptive front light system (AFLS) for a vehicle. The AFLS comprising one or more light-emitting diode (LED) lamp units and a housing which accommodates the LED lamp units, wherein each of the LED lamp units comprises one or more LEDs as its light source and a reflector which reflects light emitted by the light source so that the reflected light can be directed forward, and said adaptive front light system is operable to form different beam patterns by selectively turning on or off the lamp units, and wherein one or more reflectors of the lamp units comprise a multi-face reflector including a plurality of cells having different curvature radiuses or focal points. | 2009-06-04 |
20090141514 | Brake caliper illumination system - Illumination of indicia positioned in or on a brake caliper via a removable and interchangeable back plate, face plate, housing, and illumination source mounted to or within or on a pocket in the housing of the caliper face is disclosed. | 2009-06-04 |
20090141515 | FLICKERLESS BACKLIGHT FOR A DISPLAY PANEL - A backlight assembly for a display panel comprising a diffuser, at least one lightpipe with a patterned surface inside the diffuser, a single sided LED light source attached to each end of the diffuser is disclosed. When a plurality of lightpipes is utilized a dual sided LED light source connects the lightpipes together. The patterned surface of the lightpipes diffuse or reflect light emitted by the LED light sources to provide a light with uniform brightness and intensity. The lightpipes are coated with a thin layer of visible-light transparent material which is doped with organic dye molecules. The organic dye has strong ultraviolet light absorption characteristics. By changing the doping concentration of the dye molecules the coating can become totally opaque or semi-transparent to certain wavelengths and selective wavelength conversion is obtained. In this way light color, brightness, and intensity can be varied or controlled. | 2009-06-04 |
20090141516 | OPTOELECTRONIC SEMICONDUCTOR COMOPNENT CAPABLE OF CENTRALIZING EMITTED LIGHT - An optoelectronic semiconductor component includes a light-emitting chip for emitting light, and a reflective substrate. A plurality of linear indent structures is formed on the reflective substrate. The light-emitting chip is installed on the reflective substrate and located on a side of the plurality of linear indent structures. The plurality of linear indent structures is capable of reflecting the light emitted from the light-emitting chip. | 2009-06-04 |
20090141517 | LIGHT REDIRECTING FILMS AND FILM SYSTEMS - Optical assembly includes a reflector layer, a generally planar first surface located on a first major plane, and a generally planar second surface located on a second major plane approximately parallel to the first major plane and superimposed thereon. The first and second surfaces have first and second patterns of well defined optical elements that are quite small in relation to the length and width of the optical assembly. At least some of the optical elements of the first pattern include a first sloped surface for reflecting at least some light (that is emitted from at least one light source that is quite small relative to the length and width of the optical assembly) towards at least some of the optical elements of the second pattern and for transmitting or refracting at least some light towards the reflector. At least some of the optical elements of the second pattern include a second sloped surface for transmitting or refracting at least some light and for reflecting at least some light towards at least some of the optical elements of the first pattern, wherein more light (that is emitted from the at least one light source) is transmitted or refracted by the second surface than by the first surface. | 2009-06-04 |
20090141518 | CIRCUIT AND METHOD FOR RECTIFYING AND REGULATING VOLTAGES - A circuit having a first input and a second input configured to apply an alternating voltage, a first output and a second output configured to supply a rectified and regulated voltage, a rectifier bridge circuit having a current return circuit, a third transistor and a fourth transistor, and a controller configured to regulate the voltage between the first and the second output to a constant value. The current return circuit is connected to the first input, the second input and to the second output. The third transistor is configured as a series voltage regulator and is connected to the first input and the first output. The fourth transistor is configured as a series voltage regulator and is connected to the second input and the first output. The controller is coupled to a control input of the third transistor and to a control input of the fourth transistor. Further, a method for rectifying and regulating voltages of a circuit is provided. The circuit and the method can be used in a contactless chip card. | 2009-06-04 |
20090141519 | DC/DC CONVERTER - Provided is a DC/DC converter including a power supply unit that includes a transformer having one primary side and a plurality of secondary sides and outputs a plurality of driving voltages for driving a load; and a constant current converting unit that is connected to one secondary side and a low-voltage stage of another secondary side adjacent to the one secondary side among the plurality of secondary sides of the transformer and boosts a driving voltage output from the one secondary side. | 2009-06-04 |
20090141520 | ISOLATED VOLTAGE CONVERTER WITH FEEDBACK ON THE PRIMARY WINDING, AND CORRESPONDING METHOD FOR CONTROLLING THE OUTPUT VOLTAGE - An embodiment of a voltage converter, designed to convert an input voltage into a regulated output voltage, having: a voltage transformer having a primary winding receiving the input voltage, a secondary winding supplying the output voltage (V | 2009-06-04 |
20090141521 | Method and apparatus of providing synchronous regulation for offline power converter - A synchronous regulation circuit is provided to improve the efficiency for an offline power converter. A secondary-side switching circuit is coupled to the output of the power converter to generate a synchronous signal and a pulse signal in response to an oscillation signal and a feedback signal. An isolation device transfers the synchronous signal from the secondary side to the primary side of the power converter. A primary-side switching circuit further receives the synchronous signal to generate a switching signal for soft switching a transformer. The pulse signal is utilized to control a synchronous switch for rectifying and regulating the power converter. The synchronous switch includes a power switch and a control circuit. The control circuit receives the pulse signal for turning on/off the power switch. The power switch is connected in between the transformer and the output of the power converter. In addition, a flyback switch is operated as a synchronous rectifier to freewheel the inductor current of the power converter. The flyback switch is turned on in response to the off of the power switch. The on time of flyback switch is correlated to the on time of the power switch. | 2009-06-04 |
20090141522 | SYSTEM AND METHOD FOR PROTECTION DURING INVERTER SHUTDOWN IN DISTRIBUTED POWER INSTALLATIONS - A protection method in a distributed power system including of DC power sources and multiple power modules which include inputs coupled to the DC power sources. The power modules include outputs coupled in series with one or more other power modules to form a serial string. An inverter is coupled to the serial string. The inverter converts power input from the string and produces output power. When the inverter stops production of the output power, each of the power modules is shut down and thereby the power input to the inverter is ceased. | 2009-06-04 |
20090141523 | Switching control circuit and AC/DC converter using the same - A switching control circuit for an AC/DC converter stops the switching of a switching device in a low-phase angle range of an AC power supply to prevent an improper recovery operation after a brownout is detected. | 2009-06-04 |
20090141524 | CONTROL DEVICE FOR POWER FACTOR CORRECTION DEVICE IN FORCED SWITCHING POWER SUPPLIES - Herein described is a control device of a device for the correction of the power factor in forced switching power supplies; said device for the correction of the power factor comprises a converter and said control device is coupled to the converter to obtain from an alternating input line voltage a regulated output voltage. The control device comprises generating means associated to a capacitor for generating a signal representative of the root-mean-square value of the alternating line voltage; the generating means are associated to means for discharging said capacitor. The control device comprises further means for discharging the capacitor suitable for discharging said capacitor when the signal representative of the root-mean-square value of the alternating line voltage goes below a given value. | 2009-06-04 |
20090141525 | POWER SOURCE DEVICE - A power source device includes an input terminal, a first switching element connected to the input terminal, a second switching element connected to the first switching element, a transformer having a primary coil connected to a connecting node between the first and second switching elements, a low-pass filter including a series body of a coil and a capacitor connected to a secondary coil of the transformer, an output terminal connected to a connecting node between the coil and the capacitor, a comparator having a first input terminal connected to the output terminal, and an alternating signal generator connected to a second terminal of the comparator. An output terminal of the comparator is connected to each control terminal of the first switching element and the second switching element via the temporary amplitude generation permissible section. | 2009-06-04 |
20090141526 | HARMONICS RELATED SYNCHRONIZATION FOR SWITCHING REGULATORS - Disclosed is a system and method for synchronizing switching regulators in an electronic system so that switching interference from the regulators may be kept from a given spectral region of interest. The system does this by selecting a master clock frequency such that each of the switching frequencies corresponding to each of the switching regulators is a harmonic of a fundamental frequency. Further, the master clock frequency is selected so that none of the switching regulators, each of which are driven by an harmonic of the fundamental frequency, generates switching interference in the spectral region of interest. Each of the switching regulators has a synchronization clock, which multiplies or divides the master clock frequency by an allocated harmonic factor. Each harmonic factor is selected to that the switching frequency is within the operating range of the particular switching regulator. | 2009-06-04 |
20090141527 | APPARATUS AND METHOD FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES - A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation. | 2009-06-04 |
20090141528 | APPARATUS AND METHOD FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY - A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array. | 2009-06-04 |
20090141529 | DESIGN STRUCTURE FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES - A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation. | 2009-06-04 |
20090141530 | STRUCTURE FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY - A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array. | 2009-06-04 |
20090141531 | ASSOCIATIVE MEMORY AND SEARCHING SYSTEM USING THE SAME - Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times. | 2009-06-04 |
20090141532 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other. | 2009-06-04 |
20090141533 | METAL GATE COMPATIBLE ELECTRICAL ANTIFUSE - A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions. | 2009-06-04 |
20090141534 | DETECTION APPARATUS AND METHOD FOR SEQUENTIALLY PROGRAMMING MEMORY - A detection apparatus for sequentially programming a memory is provided. The detection apparatus comprises a current sensor and a programming controller. The current sensor is coupled to a programming source and a memory cell. The current sensor detects change of a programming current between the programming source and the memory cell and generates a control signal according to the detection result. The programming controller is coupled to the current sensor. The programming controller receives the control signal and generates a programming state signal. | 2009-06-04 |
20090141535 | METHODS INVOLVING MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE - Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective. | 2009-06-04 |
20090141536 | Structure for a Configurable SRAM System and Method - A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently. | 2009-06-04 |
20090141537 | APPARATUS AND METHOD FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATIONAL CAPABILITY - A computational memory device includes an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows. | 2009-06-04 |
20090141538 | Voltage Controlled Static Random Access Memory - A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL | 2009-06-04 |
20090141539 | RADIATION TOLERANT SRAM BIT - In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters. | 2009-06-04 |
20090141541 | MAGNETORESISTIVE MEMORY ELEMENTS WITH SEPARATE READ AND WRITE CURRENT PATHS - A magnetoresistive memory element has a free layer, and a write current path aligned with a free layer plane. The memory element has a pinned layer with a magnetization direction aligned with that of the free layer. A barrier layer is disposed between the free layer and the pinned layer. The free, barrier and pinned layers together form a layer stack that has a read current path that extends through the layer stack and that is not aligned with the write current path in the free layer. | 2009-06-04 |
20090141542 | MRAM DESIGN WITH LOCAL WRITE CONDUCTORS OF REDUCED CROSS-SECTIONAL AREA - Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells. | 2009-06-04 |
20090141543 | MAGNETIC RANDOM ACCESS MEMORY, MANUFACTURING METHOD AND PROGRAMMING METHOD THEREOF - A magnetic random access memory (MRAM) and a manufacturing method and a programming method thereof are provided. The magnetic random access memory comprises a first magnetic tunnel junction structure and a second magnetic tunnel junction structure The second magnetic tunnel junction structure is electrically connected with the first magnetic tunnel junction structure, and the volume of the second magnetic tunnel junction structure is smaller than that of the first magnetic tunnel junction structure. | 2009-06-04 |
20090141544 | Mram and Operation Method of the Same - An operation method of an MRAM of the present invention is an operation method of the MRAM in which a data write operation is carried out in a toggle write. The operation method of the present invention includes: (A) reading a data from a data cell by using a reference signal which is generated by using a reference cell; (B) performing an error detection on the read data; (C) correcting the data stored in the data cell, when an error is detected in the read data; (D) reading the data from the data cell as a first re-read data after the (C), when the error is detected in the read data, (E) performing the error detection on the first re-read data; (F) correcting the data stored in the reference cell, when an error is detected in the first re-read data; (G) reading the data from the data cell as a second re-read data after the (F), when the error is detected in the first re-read data; (H) performing the error detection on the second re-read data; and (I) correcting the data stored in the data cell again, when the error is detected in the second re-read data. | 2009-06-04 |
20090141545 | Planar third dimensional memory with multi-port access - Embodiments of the invention relate generally to a planar third dimensional memory with multi-port access, the planar third dimensional memory including memory planes composed of a plurality of memory layers. The memory layers can include non-volatile memory elements. The planar third dimensional memory can also include insulation layers, each being formed to separate a memory layer from another memory layer, and a logic plane configured to control access to the plurality of memory planes. In some cases, the memory planes can be formed vertically above the logic plane. The logic plane can be formed in a substrate, such as a semiconductor wafer, for example. The planar third dimensional memory can include a multi-port interface that can be configured to provide access between a plurality of ports and the plurality of memory planes. | 2009-06-04 |
20090141546 | Method of operating a phase-change memory device - A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied. | 2009-06-04 |
20090141547 | Non-volatile memory devices and methods of fabricating and using the same - Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change. | 2009-06-04 |
20090141548 | MEMORY AND METHOD FOR DISSIPATION CAUSED BY CURRENT LEAKAGE - Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed. | 2009-06-04 |
20090141549 | Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith - At least one embodiment includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write unit configured to write data into the non-volatile memory cell array. The write unit is configured to perform writing of data such that each data will have reached a stable storage state in the non-volatile memory prior to being over-written in the write buffer. | 2009-06-04 |
20090141550 | Memory Array Having a Programmable Word Length, and Method of Operating Same - A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed. | 2009-06-04 |
20090141551 | METHOD FOR PERFORMING ERASING OPERATION IN NONVOLATILE MEMORY DEVICE - A method for performing erasing operation in a nonvolatile memory device includes the steps of applying an erasing voltage to P-wells of a selected memory cell block which is composed of a plurality of strings in each of which a plurality of memory cells and side memory cells are connected in series; performing soft programming operation by applying a soft programming voltage to word lines of the selected memory cell block; and programming the side memory cells by applying a programming voltage to the side memory cells. | 2009-06-04 |
20090141552 | MEMORY SYSTEM - A memory system includes a nonvolatile memory including a plurality of memory cells, each memory cell being configured to store n levels (n is a natural number of not less than 3) in accordance with a threshold voltage, and a converter which encodes input data in the form of a bit string, records the encoded data in the nonvolatile memory, and limits a difference between levels which adjacent memory cells can take to not more than a predetermined level lower than the n levels. | 2009-06-04 |
20090141553 | SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line. | 2009-06-04 |
20090141554 | MEMORY DEVICE HAVING SMALL ARRAY AREA - Memory arrays can be implemented including word lines connected to memory transistors and corresponding select transistors. Each memory transistor is also connected to an array select transistor. Each select transistor is also connected to a bit line. The memory transistors are arranged such that they define bytes of data. A well line is connected to each portion of the semiconductor substrate that defines an array of bytes. | 2009-06-04 |
20090141555 | METHOD OF PROGRAMMING AND ERASING A P-CHANNEL BE-SONOS NAND FLASH MEMORY - A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state. | 2009-06-04 |
20090141556 | METHOD OF VERIFYING PROGRAMMING OF A NONVOLATILE MEMORY DEVICE - A first verify voltage is applied to a word line of a selected memory cell, after a bit line is precharged, to program-verify the memory cell in a nonvolatile memory device. A first read evaluation operation for changing a voltage of the bit line is performed. Results of the first read evaluation operation are sensed using a first sensing voltage. A second read evaluation operation for changing the voltage of the bit line is performed again. Results of the second read verify operation are then sensed using the first sensing voltage. | 2009-06-04 |
20090141557 | SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND METHOD OF WRITING DATA TO SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold. | 2009-06-04 |
20090141558 | Sensing memory cells - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 2009-06-04 |
20090141559 | VERIFYING AN ERASE THRESHOLD IN A MEMORY DEVICE - In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s). | 2009-06-04 |
20090141560 | FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data line and configured to receive verification data through a page buffer during a verify operation. The flash memory device also includes a fail bit counter unit for counting the verification data, comparing counted fail bits and the number of ECC allowed bits, and outputting a pass or fail signal of a program operation according to the comparison result. | 2009-06-04 |
20090141561 | METHOD OF OPERATING A NON-VOLATILE MEMORY DEVICE - In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved. | 2009-06-04 |
20090141562 | NON-VOLATILE MEMORY DEVICE, METHODS OF FABRICATING AND OPERATING THE SAME - A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data. | 2009-06-04 |
20090141563 | Method for Operating a Non-Volatile Charge-Trapping Memory Device and Method for Determining Programming/Erase Conditions - A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation profile, upon going from erased to programmed state. | 2009-06-04 |
20090141564 | MEMORY REGISTER DEFINITION SYSTEMS AND METHODS - Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to be coupled to a first address in a memory device may be exchanged with an encoded bit to be coupled to a second address in the memory device. Apparatus, systems, and methods are disclosed that operate to invert encoded bits in logic circuits in the memory device if original bits were inverted. Additional apparatus, systems, and methods are disclosed. | 2009-06-04 |
20090141565 | SEMICONDUCTOR STORAGE DEVICE - A bit line potential monitor circuit is provided in a bit line, and a step-down circuit of the bit line is controlled base on information from the monitor circuit. As a result, the bit line is easily stepped down to an optimal potential level in accordance with a potential and a load capacity thereof without being affected by variability in devices or operation conditions. | 2009-06-04 |
20090141566 | STRUCTURE FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATION CAPABILITY - A design structure embodied in a machine readable medium used in a design process includes computational memory device having an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows. | 2009-06-04 |
20090141567 | Semiconductor device having memory array, method of writing, and systems associated therewith - In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received. | 2009-06-04 |
20090141568 | No-Disturb Bit Line Write for Improving Speed of eDRAM - A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines. | 2009-06-04 |
20090141569 | SEMICONDUCTOR MEMORY DEVICE - Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented. | 2009-06-04 |
20090141570 | Controlling Global Bit Line Pre-Charge Time for High Speed eDRAM - A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval. | 2009-06-04 |
20090141571 | Method and Apparatus for Initialization of Read Latency Tracking Circuit in High-Speed DRAM - A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing. | 2009-06-04 |
20090141572 | VOLTAGE CONTROL APPARATUS AND METHOD OF CONTROLLING VOLTAGE USING THE SAME - A voltage control apparatus and a method of controlling a voltage using the same. A voltage control apparatus includes a signal generator configured to output a burn-in control signal and a burn-in precharge signal in response to an all bank precharge command, and a voltage controller configured to supply either a first voltage or a second voltage lower than the first voltage to a word line in response to the burn-in control signal and the burn-in precharge signal. | 2009-06-04 |
20090141573 | System and Method for Better Testability of OTP Memory - A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory. | 2009-06-04 |
20090141574 | Memory accessing circuit and method - The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2 | 2009-06-04 |
20090141575 | Method and Apparatus for Idle Cycle Refresh Request in Dram - Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocating an idle cycle sequence to refresh at least a portion of the dynamic random access memory only if the determining step determines that a refresh of the dynamic random access memory is required. A refresh flag can optionally be set if a refresh is required. The idle cycle sequence comprises one or more idle cycles. The idle cycle sequence can optionally be allocated within a predefined duration of the refresh flag being set. The step of determining step whether a refresh of the dynamic random access memory is required can be based on real-time or expected conditions. | 2009-06-04 |
20090141576 | METHOD OF REFRESHING DATA IN A STORAGE LOCATION - An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate. | 2009-06-04 |
20090141577 | ANTI-FUSE REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING DRAM HAVING THE SAME - In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled. | 2009-06-04 |
20090141578 | FUSE BOX AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A fuse box of a semiconductor memory device which comprises a plurality of fuse units commonly connected to a power line, each of the fuse units comprising a first fuse connected with the power line; and a plurality of second fuses connected with the first fuse in parallel. If the second fuses are determined to be cut off, the first fuse is cut off instead of the second fuses. | 2009-06-04 |
20090141579 | Power Up/Down Sequence Scheme for Memory Devices - A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been pulled down to the low logic state; and disconnecting a current path from an external ground voltage to an internal ground voltage after a current path from an external power supply to an internal power supply has been completely disconnected. | 2009-06-04 |
20090141580 | Reduced Leakage Driver Circuit and Memory Device Employing Same - A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit. | 2009-06-04 |
20090141581 | Semiconductor Memory Arrangement and System - A semiconductor memory arrangement includes a control device with a first port and a second port, the first and second port being adapted to receive command and address signals, a first buffer device being coupled to the first port, a second buffer device being coupled to the second port and a plurality of memory units at least including a first group of memory units and a second group of memory units. | 2009-06-04 |
20090141582 | METHOD FOR RECORDING DATA USING NON-VOLATILE MEMORY AND ELECTRONIC APPARATUS THEREOF - A method for recording data using a non-volatile memory and an electronic apparatus thereof are provided. In the present method, a set of input data is provided. Then, a data structure of the input data is transformed into a bitmapping data structure. Afterwards, the input data is written sequentially into the non-volatile memory using at least one bit as a basic unit of modification. A total number of bits being modified is then calculated, so as to obtain information needed by the system. Therefore, a minimal memory space is used to record most information, so as to reduce the times for erasing the non-volatile memory and increase the life time of the non-volatile memory. | 2009-06-04 |
20090141583 | Reclaim Function for Semiconductor Processing Systems - In one embodiment, a method of controlling fluids in a semiconductor processing system includes mixing two or more chemical compounds in a blender to produce a solution and supplying the solution to a reclaim tank, where the solution is dispense to a process station. The solution can be monitored at a location between the tank and the process station to determine whether at least one of the chemical compounds is at a predetermined concentration. Upon determining that the at least one chemical compound in the solution is at the predetermined concentration the solution is flowed to the process station. The method further includes removing at least a portion of the solution from the process station and returning the removed portion of the solution to the reclaim tank. The removed portion of the solution is monitored at a location between the process station and the reclaim tank to determine whether at least one of the chemical compounds in the removed portion of the solution is at a predetermined concentration. Upon determining that the at least one chemical compound in the removed portion of the solution is at the predetermined concentration, the removed portion of solution is flowed to the process station. | 2009-06-04 |
20090141584 | Homogenisation valve - The invention relates to an improved homogenization valve, and more particularly, but not exclusively, to a homogenization valve for use in homogenizing emulsion explosives. The homogenization device comprises a body having a flow passage therethrough, opposing first and second homogenization members located in the flow passage; the homogenization members having opposing homogenization surfaces that form a flow restriction of the flow passage therebetween. At least one of the homogenization surfaces has a flow resistance being suitable to cause at least part of the flow passing through the flow restriction to be diverged in a non-linear path across the homogenization surface. | 2009-06-04 |
20090141585 | Turbulent device to prevent phase separation - A mixer for use in a transmission pipeline and a wellbore fluids pipeline having a mixing device. The pipeline extends from a well head to a processing facility. The mixer perturbs the flow into a non-laminar state. Mixer embodiments include a body having a cone shaped leading edge and a hemi-spherical end. Other embodiments include a double cone having a series of helical fins on the trailing end of the double cone and fins extending perpendicular to the pipeline axis having a triangular cross section. The fins may be staggered with a mix of vertically and horizontally orientations. | 2009-06-04 |
20090141586 | Mixing apparatus - The mixing rod having attached blades, the blades being of the propeller type or the impeller type, including propellers or impellers that are elongated flat-plate, curved, or contoured. The blades have arched projections extending upward or downward, or both. The arched projections are formed so that material to be blended or mixed can flow through the arch, that is, under the arch, when the blades are rotated. The blades optionally have apertures or holes therethrough, which apertures or holes, when present, are under or otherwise adjacent to the arched projections. | 2009-06-04 |
20090141587 | MARINE SEISMIC SURVEY METHOD AND SYSTEM - An inventive method provides for control of a seismic survey spread while conducting a seismic survey, the spread having a vessel, a plurality of spread control elements, a plurality of navigation nodes, and a plurality of sources and receivers. The method includes the step of collecting input data, including navigation data for the navigation nodes, operating states from sensors associated with the spread control elements, environmental data for the survey, and survey design data. The positions of the sources and receivers are estimated using the navigation data, the operating states, and the environmental data. Optimum tracks for the sources and receivers are determined using the position estimates and a portion of the input data that includes at least the survey design data. Drive commands are calculated for at least two of the spread control elements using the determined optimum tracks. The inventive method is complemented by an inventive system. | 2009-06-04 |
20090141588 | Flasher sonar device with light guide - A sonar device includes a light source, a rotatable element, a motor for rotating the rotatable element, and a display. A light guide mounted on the rotatable element has an inlet end aligned with the light source and an outlet end aligned with the display. Light emitted from the light source enters the inlet end of the light guide, is directed from the inlet end to the outlet end in a beam, and is emitted out the outlet end of the light guide. | 2009-06-04 |
20090141589 | Flashes sonar device with LCD annotations - A flasher sonar device includes a motor driven flasher that produces light output pulses at angular positions along a flasher ring lens based upon sonar returns. A liquid crystal display (LCD) positioned concentrically with the flasher ring lens displays a dynamic annotated range scale associated with the flasher ring lens. A controller coordinates operation of the motor driven flasher and the LCD. | 2009-06-04 |
20090141590 | Flasher sonar device with interleaved zoom - A flasher sonar device includes a flasher that produces light output pulses along a flasher ring display based upon sonar returns. A user interface selects between a normal mode and a zoom mode. When the normal mode is selected, a controller drives the flasher to display a normal range. When the zoom mode is selected, the controller divides the normal range into a first range and a second range, compresses the first range into a compressed range, enlarges the second range into an enlarged range, and drives the flasher to display the enlarged range interleaved with the compressed range. | 2009-06-04 |
20090141591 | System and Method for Extending GPS to Divers and Underwater Vehicles - A navigation system extends satellite navigation to divers, underwater vehicles, and surface vessels. The navigation system comprises a location reference unit and a plurality of sub-surface beacon units. The location reference unit includes a receiver to receive navigation signals from earth-orbiting satellites and/or an inertial navigation system. The location reference unit further includes control circuits to communicate with to sub-surface beacon units and to transmit location information to said sub-surface beacon units, and a transceiver to transmit location information to the sub-surface beacon units. The beacon units include control circuits to determine the location of the beacon unit based on location information received from the location reference unit, and a transceiver to receive location information from the location reference unit and to transmit location information to a guided unit to provide navigation assistance to the guided unit. | 2009-06-04 |
20090141592 | Telemetric Sensing Using Micromachined Ultrasonic Transducer - Implementations of a cMUT have a telemetric antenna operative to telemetrically transmit an output signal generated by the cMUT in reception mode (RX). The cMUT generates the output signal by converting a received energy applied on the cMUT. The received energy may be an acoustic wave or a low-frequency pressure signal. The acoustic wave may be generated by a separate acoustic energy source. The cMUT may form a modulated signal using a carrier signal modulated with the output signal, and telemetrically transmit the modulated signal carrying the output signal to increase efficiency. The antenna may also receive an input signal from outside to telemetrically power on the cMUT. | 2009-06-04 |
20090141593 | METHOD AND SYSTEM FOR ENHANCED DISPLAY OF TEMPORAL DATA ON PORTABLE DEVICES - A method for displaying temporal data on a portable device is presented. The method includes converting the temporal data to clock coordinates to generate a clock data set. In addition, the method includes presenting a clock plot representative of the clock data set on a dial of a clock. Systems and computer-readable medium that afford functionality of the type defined by this method are also contemplated in conjunction with the present technique. | 2009-06-04 |
20090141594 | Alarm process and device - An alarm process and device capable of waking a user more comfortably by means of a rousing instrument. For example, an alarm device may rouse a user a predetermined time before a desired waking time, resetting the user's sleep cycle before waking. A user may then be woken more comfortably at a desired waking time and during a preferable stage of the sleep cycle. | 2009-06-04 |
20090141595 | TIME-TO-DIGITAL CONVERTER APPARATUS - A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter. | 2009-06-04 |
20090141596 | TIMESHIFTING FOR A MULTIPLE-TUNER VEHICLE RADIO SYSTEM - Methods and apparatus are provided for timeshifting audio content in a multiple tuner audio system comprising a first tuner and a second tuner. One operating method involves maintaining a first data storage element for the first tuner, maintaining a second data storage element for the second tuner, receiving first audio content in realtime by the first tuner, and storing data representing the first audio content in the first data storage element, resulting in first stored content. The method also receives second audio content in realtime by the second tuner, and stores data representing the second audio content in the second data storage element, resulting in second stored content. The method thereafter generates a timeshifted audio signal corresponding to the first stored content or the second stored content. | 2009-06-04 |
20090141597 | NEAR FIELD OPTICAL RECORDING DEVICE AND A METHOD OF OPERATING A NEAR FIELD OPTICAL RECORDING DEVICE - A near field optical recording device and method of operating a near field optical recording device, the device being arranged to cooperate with an optical record carrier. The device comprising means to adjust tilt of a refractive optical element with respect to the optical record carrier according to a distance between the refractive optical element and the data layer of the optical record carrier to be accessed. | 2009-06-04 |
20090141598 | Apparatus for Adjusting Focus Offset and Method Thereof - The present invention provides an apparatus of an optical disc drive for adjusting a focus error signal. The apparatus includes a focus offset determining unit and an adjusting module. The focus offset determining unit is utilized for determining a target focus offset corresponding to a target condition, and the adjusting module is coupled to the focus offset determining unit and utilized for receiving the focus error signal and adjusting the focus error signal with the target focus offset to generate an adjusted focus error signal. | 2009-06-04 |
20090141599 | Recording medium, and method and apparatus of recording and reproducing data on the same - An apparatus of recording data on a recording medium includes a pickup unit and a microcomputer. The pickup unit records data in a plurality of data frames included in a cluster. The microcomputer controls the pickup unit to record status information within the cluster, which indicates a status of the data being recorded in each data frame. In addition, the microcomputer further controls the pickup unit to record previous location information within the cluster when the cluster is determined to be a replacement cluster. The previous location information indicates a previous location of an original cluster associated with the replacement cluster. | 2009-06-04 |
20090141600 | DATA ERROR MEASURE BASED RECORDING SPEED CONTROL - The present invention relates to determining a data writing speed for writing data on a medium ( | 2009-06-04 |
20090141601 | RECORDING METHOD AND OPTICAL DISC APPARATUS - A recording power adjustment process to adjust a recording power is carried out in each recording layer of a multilayered optical disc, and a shift test writing process to adjust the pulse condition of a recording pulse is carried out only with regard to some of the respective recording layers. Then, based on the processing result of the recording power adjustment process and the processing result of the shift test writing process, a processing result of the shift test writing process in each of the recording layers, to which the shift test writing process has not been performed, is predicted. Then, information is recorded on a corresponding recording layer of the multilayered optical disc while adjusting the pulse condition of the recording pulse based on the processing result of the shift test writing process or the prediction result. | 2009-06-04 |
20090141602 | RECORDING MEDIUM STRUCTURE CAPABLE OF DISPLAYING DEFECT RATE - A recording medium structure capable of displaying a defect rate is provided. The recording medium has at least one use area with endurance blocks, and each endurance block has an endurance value. The recording medium structure has a housing, a first and a second off-line display units arranged on the housing for respectively displaying a real defect rate and a potential defect rate of the recording medium. The real defect rate is calculated based on an error correction coed, and the potential defect rate is calculated based on an endurance values recorded in the endurabce table. | 2009-06-04 |
20090141603 | Information recording apparatus, information recording system, and information recording method - Disclosed is an information recording apparatus including: a storage portion configured to store information that is copy-protected; a recording portion configured to record, on a recording medium, the information stored in the storage portion; a first information extraction portion configured to extract, from the information stored in the storage portion, first information that indicates a feature of the information; a second information extraction portion configured to extract, from the information recorded on the recording medium, second information that indicates a feature of the information; a judgment portion configured to perform a comparison as to whether the first and second information match, and judge whether the information recorded on the recording medium can be reproduced based on the comparison; and a deletion portion configured to delete the information stored in the storage portion when the judgment portion judges that the information recorded on the recording medium is capable of being reproduced. | 2009-06-04 |
20090141604 | Optical disk, method for producing the same, and recording and reproducing apparatus - An optical disk includes a first area on which user information is recorded, and a second area in which a plurality of marks radially extending are arranged in a track direction in the optical disk. Information about the reflectance of the optical disk is recorded in the second area. It is intended to optimize the amplification factor of the reproduced signal on the basis of the information about the reflectance of the optical disk in the second area. Control data and user data can be reproduced quickly and highly reliably without depending on the relationship between the reflectances of a recording area and a non-recorded area of the optical disk. | 2009-06-04 |
20090141605 | OPTICAL DISC REPRODUCING DEVICE AND OPTICAL DISC REPRODUCING METHOD - An optical disc reproducing device is provided which is capable of setting an optimum PR class for the comprehensive frequency characteristic of an optical disc including the recording characteristic and reproducing characteristic. An optical disc reproducing device according to the present invention relates to an optical disc reproducing device which performs reproduction from an optical disc using the PRML method. The optical disc reproducing device comprises a Viterbi decoding unit which generates binary data using maximum likelihood decoding processing based upon multi-value reproduced data obtained by sampling a reproduced signal from the optical disc. The Viterbi decoding unit generates the binary data based upon an optimum PR class determined based upon the multi-value reproduced data and the binary data in a predetermined determination period. | 2009-06-04 |