| 23rd week of 2009 patent applcation highlights part 18 |
| Patent application number | Title | Published |
|---|
| 20090140705 | Device for Regulating Electrical Voltage - The invention relates to a device for regulating the electrical voltage in power mains, comprising a regulating transformer. Optionally interconnecting only three winding taps and a separate reactor winding with a total of four switching elements, enables five different voltage levels to be set. | 2009-06-04 |
| 20090140706 | SYSTEM METHOD AND APPARATUS FOR A MULTI-PHASE DC-TO-DC CONVERTER - A multiphase buck DC to DC converter with an input-output LC tank. The multiphase buck DC to DC converter with an input-output LC tank includes multiple synchronous buck DC to DC converter cells. Each one of the synchronous buck DC to DC converter cells having an input node, an output node and a control node. The synchronous buck DC to DC converter cells are arranged in a parallel configuration including having the input nodes of each one of the synchronous buck DC to DC converter cells connected together at a common input node. The synchronous buck DC to DC converter cells are also arranged in pairs of synchronous buck DC to DC converter cells. The output nodes of each one of the pairs of the synchronous buck DC to DC converter cells are connected to corresponding pair output node. Each one of the pairs of the synchronous buck DC to DC converter cells include a capacitor connected between the common input node and the corresponding pair output node and a corresponding output inductor connected between the corresponding pair output node and a common output node. Methods of reducing a DC input voltage are also disclosed. A multiphase buck DC to DC converter with a bypass capacitor is also disclosed. | 2009-06-04 |
| 20090140707 | Circuit for an Active Diode and Method for Operating an Active Diode - Embodiments of the invention relate to a circuit for an active diode, a method for operating an active diode, and, based thereon, an integrated active diode system, a rectifier, and a system for voltage conversion and/or regulation, comprising at least one transistor by which a current defined as positive from a first connection to a second connection of the transistor can be controlled, and at least one measuring/control circuit (for determining the current by means of which the at least one transistor can be switched on for currents under and at most up to a predetermined, non-positive threshold value (i1<=ith<=0), and can otherwise be switched off. | 2009-06-04 |
| 20090140708 | DC to DC converter with Pseudo Constant Switching Frequency - Various apparatuses, methods and systems for a DC to DC converter with a pseudo constant switching frequency are disclosed herein. For example, some embodiments provide a DC to DC converter having a switch connected to a switching node to control a voltage of the switching node, and a switching controller that is adapted to turn on and off the switch at a substantially constant frequency based at least in part on the voltage of the switching node. The switching controller includes a modulator connected to a control electrode of the switch and that is adapted to actuate and deactuate the switch, and a first timer that is connected to the switching node and to the modulator. The first timer uses the voltage of the switching node to determine an on-time for the switch. | 2009-06-04 |
| 20090140709 | CURRENT-LIMITING VOLTAGE CONVERSION DEVICE - The present invention relates to a current-limiting voltage conversion device, comprising a voltage conversion unit, a voltage signal unit, a sensor unit and a DC power loop. The voltage conversion unit and the sensor unit are electrically connected in series in the DC power loop. The voltage signal unit outputs a corresponding voltage signal to the voltage conversion unit based on the electric signal output by the sensor unit, and the voltage conversion unit controls the voltage conversion of the voltage conversion unit based on said voltage signal. The voltage signal unit includes outputting a voltage signal corresponding to the power state within a first preset range as detected by the sensor unit and outputting another voltage signal corresponding to the power state within a second preset range as detected by the sensor unit until the power state detected by the sensor unit returns to the first preset range | 2009-06-04 |
| 20090140710 | METHOD AND APPARATUS FOR A HIGH VOLTAGE POWER SUPPLY CIRCUIT - A high voltage power supply method and apparatus is disclosed. An example power supply circuit includes a rectifier circuit coupled to receive an AC input voltage. A switchmode power converter circuit is coupled to the rectifier circuit to receive a rectified input voltage to generate a regulated output voltage. A switch is coupled between the rectifier circuit and the switchmode power converter circuit. A sense circuit is coupled to detect the AC input voltage. The sense circuit is coupled to turn off the switch when an absolute value of the AC input voltage exceeds a first threshold value. The sense circuit is coupled to turn on the switch when the absolute value of the AC input voltage is below a second threshold value. | 2009-06-04 |
| 20090140711 | SWITCHING REGULATOR WITH BALANCED CONTROL CONFIGURATION WITH FILTERING AND REFERENCING TO ELIMINATE COMPENSATION - A controller for a switching regulator is disclosed including a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal, and references the filtered sense signal and the error signal to a common DC level. The comparator circuit develops a pulse control signal used to control switching of the pulse switch circuit based on comparing the error signal with the filtered sense signal. | 2009-06-04 |
| 20090140712 | SELF-SUPPLY CIRCUIT AND METHOD FOR A VOLTAGE CONVERTER - An embodiment of a self-supply circuit, for a voltage converter that converts an input voltage into an output voltage and has a main switch and a controller, designed to control switching of the main switch for controlling the output voltage; the self-supply circuit is provided with: a charge accumulator, which is connected to the controller and supplies a self-supply voltage to the same controller; a generator, which supplies a charge current to the charge accumulator; and an auxiliary switch, which has a first conduction terminal in common with a respective conduction terminal of the main switch and is operable so as to control transfer of the charge current to the charge accumulator. In particular, the self-supply circuit is provided with a precharge stage, connected to the auxiliary switch, which carries out a precharging of an intrinsic capacitance of the auxiliary switch before a turning-off transient of the main switch ends. | 2009-06-04 |
| 20090140713 | REGULATOR CIRCUIT FOR TESTING INHERENT PERFORMANCE OF AN INTEGRATED CIRCUIT - In testing the function of an integrated circuit which includes a power voltage regulator for smoothing a power voltage received on an input terminal so as to reach an adjustment target voltage level, and a voltage adjuster for adjusting the voltage level, the voltage adjuster being interconnected to a wiring which is to supply the power voltage of the adjustment target voltage level thus adjusted to internal logics produced by designing in advance for accomplishing a target function, the voltage adjuster is controlled to execute a function test with plural voltage levels, and, based on a result from the function test, the optimal voltage level is selected which is to be supplied to the internal logics. The inherent performance of the regulator circuit is measured without being affected by the parasitic resistances. | 2009-06-04 |
| 20090140714 | START-UP CIRCUIT FOR GENERATING BANDGAP REFERENCE VOLTAGE - Disclosed is a start-up circuit that can stably and rapidly start up a bandgap reference voltage generating circuit when the bandgap reference voltage generating circuit is switched from a sleep mode to an operation mode, even if a difference in electrical characteristic, such as DC offset or the like, occurs due to, e.g, a physical difference between input transistors of an operational amplifier. | 2009-06-04 |
| 20090140715 | SAFETY MECHANISMS, WAKE UP AND SHUTDOWN METHODS IN DISTRIBUTED POWER INSTALLATIONS - A distributed power system including multiple DC power sources and multiple power modules. The power modules include inputs coupled respectively to the DC power sources and outputs coupled in series to form a serial string. An inverter is coupled to the serial string. The inverter converts power input from the serial string to output power. A signaling mechanism between the inverter and the power module is adapted for controlling operation of the power modules. | 2009-06-04 |
| 20090140716 | Circuit arrangement for generating a pulse width modulated signal for driving electrical loads - What is described is a circuit arrangement for the pulse width modulated drive of a load connected to a voltage supply line, including:
| 2009-06-04 |
| 20090140717 | STRUCTURES AND METHODS FOR MEASURING BEAM ANGLE IN AN ION IMPLANTER - The present invention involves an ion beam angular measurement apparatus for providing feedback for a predetermined set ion beam angle comprising an arrangement of composite pillars formed on an insulating material and wherein the composite pillars selectively allow ion beams to penetrate a first layer of a pillar, wherein resistivity measurements are taken for each of the composite pillars before and after test ion beam implantation and wherein the resistivity measurements yield information relating to an angle of the ion beam during test. | 2009-06-04 |
| 20090140718 | WAVELENGTH METER AND ASSOCIATED METHOD - A wavelength meter, an associated method, and system are generally described. In one example, an apparatus includes a photodiode to receive an optical signal and to generate a photocurrent upon receiving the optical signal, the photodiode having an absorption edge that is substantially aligned with a band of wavelengths, wherein the absorption edge shifts toward longer wavelengths when a reverse bias is applied to the photodiode, and control electronics coupled with the photodiode to apply at least a first reverse bias and a second reverse bias to the photodiode, wherein a ratio of a first measurement of the photocurrent at the first reverse bias and a second measurement of the photocurrent at the second reverse bias provides information about the wavelength of the optical signal. | 2009-06-04 |
| 20090140719 | Smart sensors for solar panels - A solar panel smart sensor system is disclosed. The sensor system permits solar power system owners and operators to monitor the voltage of individual panels in a solar array. The system uses a low wire-count bus in which the order of sensors on the bus is automatically determined. A novel technique is used to measure DC voltages of panels that may be floating hundreds of volts above ground. Bypass diodes are monitored to detect lost power generation capacity. | 2009-06-04 |
| 20090140720 | METHOD FOR IDENTIFYING ELECTRONIC CIRCUITS AND IDENTIFICATION DEVICE - An identification device for electronic circuits comprises at least two electronic components having different electronic characteristics, a detection unit configured to detect at least one electrical parameter determining the electronic characteristics of the electronic components and an evaluation unit configured to evaluate a mismatch exhibited by the at least two electronic components with respect to each other. In order to distinguish different electronic circuits, the at least one electrical parameter of the electronic components is detected by the detection unit and is analyzed by the evaluation unit. | 2009-06-04 |
| 20090140721 | DIGITAL MULTIMETER HAVING IMPROVED RECORDING FUNCTIONALITY - A digital multimeter automatically records measurements of electrical or physical parameters. The multimeter may record the measurements based on events such as the passage of time, fluctuations or deviations in the measurements, or user inputs. In some examples, the digital multimeter operates at a reduced power setting during automatic recording operations. | 2009-06-04 |
| 20090140722 | MEASUREMENT SIGNAL PROCESSING - In order to determine amplitudes of measurement signals originating from an AC power supply and to determine the phase shift (ø) between measurement signals more simply, the measurement signals are processed in measurement signal operation devices to form auxiliary signals each having a constant AC amplitude and to obtain first measurement values (v, a, rssi, rssi | 2009-06-04 |
| 20090140723 | Method and apparatus for reducing induction noise in measurements made with a towed electromagnetic survey system - A method for reducing motion induced voltage in marine electromagnetic measurements includes measuring an electromagnetic field parameter at least one position along a sensor cable towed through a body of water. Motion of the sensor cable is measured at least one position along the cable; Voltage induced in the cable is estimated from the motion measurements. The measured electromagnetic field parameter is corrected using the estimated voltages. | 2009-06-04 |
| 20090140724 | Magnetic Field Sensor Assembly - A magnetic field sensor assembly has at least one magnetic field sensor integrated into a semiconductor chip and has at least one magnetic field source. The semiconductor chip and the at least one magnetic field source are arranged in an encapsulation material in a predetermined position relative to each other in such a way that a magnetic field generated by the magnetic field source is detectable with the aid of at least one magnetic field sensor. The magnetic field source is arranged in the semiconductor chip and/or in the plane of extension of the semiconductor chip laterally adjacent to said chip. | 2009-06-04 |
| 20090140725 | INTEGRATED CIRCUIT INCLUDING SENSOR HAVING INJECTION MOLDED MAGNETIC MATERIAL - An integrated circuit includes a magnetic field sensor and an injection molded magnetic material enclosing at least a portion of the magnetic field sensor. | 2009-06-04 |
| 20090140726 | Measurement Device for Measuring a Magnetic Field - A measuring device to measure a magnetic field having at least one measuring coil and at least one sensor to measure low-frequency magnetic fields, which measuring coil and which sensor have their planes of extension each positioned or positionable transverse to the flux direction of the magnetic field. The measuring coil and the sensor are connected to a signal processing device with which, depending on a first measurement signal provided by the measuring coil and a second measurement signal provided by the sensor, an output signal that essentially corresponds to the magnetic field can be generated. The measuring coil, the sensor, and the signal processing device are monolithically integrated into a semiconductor chip. The measuring coil may also be formed by means of traces of a printed circuit board on which the semiconductor chip that has the sensor and the signal processing device is located. | 2009-06-04 |
| 20090140727 | APPARATUS AND METHODS FOR PROXIMITY SENSING CIRCUITRY - An inductive proximity sensor is disclosed. The proximity sensor includes a source circuit with an inductive element configured to deliver energy to a resonator when a source current is changed. In various embodiments, the source current is provided a step current source. In various embodiment, the source current is provided by constant current source coupled to the inductive element by a switch. Apparatus and methods for operating the inductive proximity sensor are disclosed. | 2009-06-04 |
| 20090140728 | APPARATUS AND METHODS FOR PROXIMITY SENSING CIRCUITRY - An inductive proximity sensor is disclosed. The proximity sensor includes a resonator with a bifurcated inductance coupled to a plurality of transimpedance amplifiers. A portion of the resonator is configured to generate eddy currents in a target containing metal. In various embodiments, the transimpedance amplifiers provide signals associated with eddy currents to a synchronous detector. Apparatus and methods for operating the inductive proximity sensor are disclosed. | 2009-06-04 |
| 20090140729 | INDUCTIVE NON-CONTACT MEASUREMENT OF A RELATIVE MOVEMENT OR RELATIVE POSITIONING OF A FIRST OBJECT RELATIVE TO A SECOND OBJECT - A non-contact measurement method for a relative displacement or relative positioning of a first object relative to a second object, in which: at least one transmitting coil, placed on the first object, is excited by an alternating excitation signal, at least one alternating electronic output signal, generated by mutual inductance in at least one receiving coil, is detected; the at least one receiving coil being placed on the second object and in a magnetic field created by the at least one transmitting coil, and the relative displacement of the first object is determined relative to the second object using the at least one alternating electric output signal generated on the at least one receiving coil. | 2009-06-04 |
| 20090140730 | Linear position sensor - A sensor used to sense the position of an attached movable object. The sensor can be mounted to a pneumatic actuator. The sensor includes a housing that has a pair of cavities or pockets separated by a wall. A magnet carrier is positioned within one of the cavities and a magnet is coupled to the magnet carrier. The magnet carrier is coupled to the moveable object. A magnetic sensor is positioned in the other of the cavities. The magnetic sensor generates an electrical signal that is indicative of a position of the movable object. | 2009-06-04 |
| 20090140731 | Multiple-Rotation Absolute-Value Encoder of Geared Motor - A multiple-rotation absolute-value encoder of a geared motor, wherein the geared motor ( | 2009-06-04 |
| 20090140732 | Low cost simplified spectrum analyzer for magnetic head/media tester - An electronic component tester characterizes electronic components such as magnetic head/media components measure performance parameters such as signal-to-noise ratio and overwrite evaluation. The electronic component tester has a tester process controller and a spectrum analyzer. The tester process controller generates calibration and control signals for the electronic component tester. The spectrum analyzer is in communication with electronic components such as magnetic head or media components to receive a response characterization signal resulting from a stimulus signal applied to the electronic components. The spectrum analyzer then determines a frequency spectrum of the response characterization signal. The spectrum analyzer is also in communication with the tester process controller for transferring the frequency spectrum to the tester process controller. The spectrum analyzer receives the calibration and control signals from the tester process controller for removing effects of an image frequency of the frequency spectrum and determining noise bandwidth of the frequency spectrum. | 2009-06-04 |
| 20090140733 | MAGNETIC DEVICE AND FREQUENCY DETECTOR - A magnetic device includes: a magnetoresistive effect element having a magnetization fixed layer, a magnetization free layer, and a nonmagnetic layer sandwiched between the magnetization fixed layer and the magnetization free layer; an input terminal for feeding an AC signal to the magnetoresistive effect element in its stacking direction; and an output terminal for extracting an output voltage from the magnetoresistive effect element, wherein the nomagnetic layer includes an insulating layer portion comprising an insulating material, and a current-constricting layer portion comprising a conductive material which passes through the insulating layer portion in its film thickness direction. | 2009-06-04 |
| 20090140734 | READOUT ORDERING IN COLLECTION OF RADIAL MAGNETIC RESONANCE IMAGING DATA - In a magnetic resonance imaging apparatus, a sensor ( | 2009-06-04 |
| 20090140735 | TEMPERATURE-CONTROLLED MAGNETIC RESONANCE IMAGING METHOD AND APPARATUS - A method for improving the imaging quality of magnetic resonance imaging (MRI) equipment and MRI equipment, include obtaining a corresponding relationship between a deterioration factor of imaging quality and the cumulative energy of gradient pulses applied by successive scanning MRI sequences, then determining a predicted value of a current deterioration factor of imaging quality according to the currently applied cumulative energy of the gradient pulses and said corresponding relationship, adopting a corresponding method to carry out dynamic regulation or compensation using the predicted value of said deterioration factor of imaging quality as a reference, so as to cancel the influence produced by the heating effect of the gradient system to the imaging quality, thereby effectively improving the imaging quality of the MRI equipment. | 2009-06-04 |
| 20090140736 | METHOD AND INSTRUMENT OF LOCALLY MEASURING PROTIC SOLVENT CONTENT IN SAMPLES - Excitation-use high frequency RF generated by an RF oscillator | 2009-06-04 |
| 20090140737 | Nmr Machine Comprising Solenoid Gradient Coils - The nuclear magnetic resonance machine comprises a device ( | 2009-06-04 |
| 20090140738 | Method for adjusting an excitation and detection circuit for nuclear magnetic resonance, and circuit adapted for carrying out said method - A method of adjusting an excitation and detection circuit for nuclear magnetic resonance, the circuit comprising a probe (S) of the type comprising a single coil (L) for transmitting pulses to excite the nuclear spins of a sample immersed in a magnetic field and for detecting a resonance signal from said nuclear spins, said method being characterized by a step of tuning the resonant frequency in reception of said circuit to the Larmor frequency (f | 2009-06-04 |
| 20090140739 | ULTRA WIDE BAND WIRELESS RADIO TRANSMISSION IN MRI SYSTEMS INVOLVING CHANNEL ESTIMATION - At least one radio frequency coil ( | 2009-06-04 |
| 20090140740 | RECEIVER COIL ARRAY FOR MAGNETIC RESONANCE IMAGING - A receiver coil array for a magnetic resonance imaging system has an inductive coupling coil incorporated in the middle coil unit of the receiver coil array as its secondary coil, which serves to regulate the frequency and impedance of the middle coil unit. The secondary coil has an output regulation circuit which can output the magnetic resonance signals received by the middle coil unit to increase the number of the coil units in the receiver coil array that receive and output resonance signals while further regulating the frequency and impedance of the middle coil unit. Since this receiver coil array achieves regulation of the frequency and impedance of the middle coil unit and increases the number of the coil units in the receiver coil array that receive and output the resonance signals, it can improve the quality of the signals received by the receiver coil array. Moreover, the design is simple and is easy to achieve. | 2009-06-04 |
| 20090140741 | Receiver streamer system and method for marine electromagnetic surveying - A receiver streamer system for marine electromagnetic surveying includes a first streamer, and a second streamer disposed substantially parallel to and spaced apart from the first streamer. A first pair of electrodes is associated with the first streamer and a second pair of electrodes is associated with the second streamer. Each of the first and second pairs of electrodes is functionally associated with a voltage measuring circuit configured to measure voltage along an inline direction. At least one electrode on each of the first and second streamers is configured and associated with a voltage measuring circuit to make voltage measurements in a cross-line direction. | 2009-06-04 |
| 20090140742 | METHOD AND SYSTEM FOR DETERMINING A STATE OF CHARGE OF A BATTERY - Methods and systems are provided for determining a state of charge of a battery. The battery is subjected to a predetermined magnetic field such that the battery and the predetermined magnetic field jointly create a resultant magnetic field. The resultant magnetic field is sensed. The state of charge of the battery is determined based on the resultant magnetic field. | 2009-06-04 |
| 20090140743 | CELL VOLTAGE DETECTING APPARATUS - The present invention provides an easy to produce cell voltage detecting apparatus using a semiconductor having low voltage endurance. In the cell voltage detecting apparatus, cell modules B | 2009-06-04 |
| 20090140744 | METHOD AND DEVICE FOR DETERMINING STATE OF HEALTH OF THE BATTERY, AND BATTERY POWER SUPPLY SYSTEM - A method and the device are provided for determining state of health of the battery, in addition to the power supply system using the device, to reduce operational and processing load by expanding the data sampled at the time when the battery is caused to discharge square wave pulses into the square wave is provided. The method includes determining state of health of a battery by causing the battery to discharge square wave pulses with a prescribed cycle at a prescribed current value. Response voltages are sampled at a time of a pulse-discharge. The sampled response voltages are sampled into orthogonal square wave components. An amplitude of the square wave component is divided by the current value of the pulse-discharge to obtain a pseudo-impedance. A state of health of the battery based on the pseudo-impedance is determined. | 2009-06-04 |
| 20090140745 | Power converter current sensor testing method - A method of testing power converter current sensors is disclosed. The method may include receiving a current sensor test request and receiving measured currents from current measurements from the at least one current sensor, based on the test request. The method may further include comparing the measured current of the sensor with a stored profile and determining whether a fault exists in each current sensor being tested. The method may also include providing a user with a test report. | 2009-06-04 |
| 20090140746 | TESTING CIRCUIT BOARD - A testing circuit board used in a testing system with a tester and a handler is disclosed. The testing circuit board is used for transmitting a plurality of testing signals provided by the tester to test at least two devices under test located on the handler. The testing circuit board includes a connecting board, a load board and at least two connecting interfaces. The connecting board coupled to the handler has at least two connecting sockets for respectively connecting to the devices under testing. The load board coupled to the tester has two joining sockets located corresponding to the connecting sockets. The at least two connecting interfaces are coupled between the connecting sockets and the joining sockets for transmitting the testing signals for testing the devices under testing. | 2009-06-04 |
| 20090140747 | Detection of faults in an injector arrangement - A method and apparatus for detecting faults in an injector arrangement is described. The injector arrangement comprises a plurality of piezoelectric injectors that are located in parallel branches of an injector bank circuit of an injector drive circuit. Each branch of the injector bank circuit comprises a high side isolation switch. The high side isolation switches are each operable to enable an associated piezoelectric injector in the injector bank circuit when closed, and disable the associated piezoelectric injector in the injector bank circuit when open. The fault detection method comprises the steps of operating the high side isolation switches so as to enable one of the piezoelectric injectors and disable the other piezoelectric injector(s), and performing diagnostics to detect the presence or absence of faults on the enabled piezoelectric injector. | 2009-06-04 |
| 20090140748 | High voltage harness testing system - A wire harness testing system is disclosed. The wire harness testing system may include a voltage sensor configured to measure a voltage at a location associated with an electric load, wherein the electric load is connected with at least one wire harness. The wire harness testing system may also include a controller electrically coupled to the voltage sensor. The controller may be configured to receive a wire harness test request. The controller may be further configured to determine a voltage drop based on a voltage sensor measurement and a reference voltage and compare the voltage drop with a threshold. The controller may also be configured to adaptively update the reference voltage with the voltage measurement responsive to a voltage drop below the threshold, and generate a fault notice responsive to a voltage drop above the threshold. The wire harness testing system may further include at least one indication device configured to provide a warning signal based on the fault notice generated by the controller. | 2009-06-04 |
| 20090140749 | Device for Measuring a Load Current - A device for measuring a load current in a load circuit that has a switch that switches the load current. The switch has a control variable as a first switch variable and an output variable, which is dependent on the control variable, as a second switch variable. A setting unit keeps one of the switch variables constant at a predetermined value, and an evaluation unit determines the load current from the other switch variable. It is thus possible to dispense with an additional measuring element for measuring the load current, thus keeping the power loss low. | 2009-06-04 |
| 20090140750 | Interference Exclusion Capability Testing Apparatus - An interference exclusion capability testing apparatus is provided for use in testing interference exclusion capability of a specimen by radiating an electromagnetic wave toward the specimen from a radiating antenna. The radiating antenna includes an electromagnetic horn, and a waveguide plate that guides an electromagnetic wave radiated from the electromagnetic horn to the specimen. | 2009-06-04 |
| 20090140751 | Microwave paint thickness sensor - A microwave paint thickness sensor includes a single cylindrical cavity, a microwave source, and a signal detector. The cylindrical cavity is open at one end, the open end having a choke joint for interfacing with a painted surface. The cylindrical cavity is designed so that the electronic field is normal to the painted surface. In a preferred embodiment, this is accomplished by providing an optimally designed TM011 mode cavity. In this configuration, the resonant frequency of the cavity is linearly related to the inverse of the paint thickness. In accordance with one aspect of the present invention, the resonant cavity is optimally sized to resonate at a frequency where the sensor footprint can be minimized. Thus with the use of the choke joint, the small sensor interface area of the present invention may easily be applied to a curved surface. | 2009-06-04 |
| 20090140752 | USE OF A NANOPARTICLE FILM HAVING METAL IONS INCORPORATED - The present invention relates to the use of a nanoparticle film having metal ions incorporated wherein and to a method of detecting a gaseous or volatile or liquid analyte in a medium. | 2009-06-04 |
| 20090140753 | TEST STRIP READER SYSTEM AND METHOD - A system and method is disclosed which relates to the back biasing a photodiode and charging a capacitor to generate a pulse. The length of the pulse is proportional to the light intensity incident on the photodiode. | 2009-06-04 |
| 20090140754 | Method for determining a property of a fluid for a household device - Method for determining a property of a fluid for a household device, comprising the following steps: measurement of a physical variable of the fluid associated with the property of the fluid, in each case when a first parameter influencing the physical variable has one of at least two predetermined values, in order to obtain at least two measurement values for the said first parameter, and correlation of the at least two measurement values for the first parameter, in order to obtain a first value characterising the property of the fluid. | 2009-06-04 |
| 20090140755 | Circuit board testing system - System including backplane, and first and second circuit boards. First circuit board is attached to backplane and has first optical signal transmitter. Second circuit board is attached to backplane and has first optical signal receiver. First optical signal transmitter and first optical signal receiver are mutually configured and mutually aligned for circuit board test signal communication from first circuit board to second circuit board across free space. Method includes providing backplane and first and second circuit boards, where first circuit board has first optical signal transmitter and second circuit board has first optical signal receiver. Method further includes attaching first and second circuit boards to backplane, and mutually configuring and mutually aligning first optical signal transmitter and first optical signal receiver for circuit board test signal communication from first circuit board to second circuit board across free space. | 2009-06-04 |
| 20090140756 | PROBE MEMBER FOR WAFER INSPECTION, PROBE CARD FOR WAFER INSPECTION AND WAFER INSPECTION EQUIPMENT - Disclosed herein are a probe member for wafer inspection, a probe card for wafer inspection and a wafer inspection apparatus, by which a good electrically connected state can be surely achieved, positional deviation by temperature change can be prevented, and the good electrically connected state can be stably retained even when a wafer has a diameter of 8 inches or greater, and the pitch of electrodes to be inspected is extremely small. | 2009-06-04 |
| 20090140757 | Microdisplay Assemblies and Methods of Packaging Microdisplays - Microdisplay assemblies, methods of packaging microdisplays, and methods of testing microdisplays are disclosed. In accordance with one embodiment, a microdisplay assembly includes a support and a microdisplay disposed on the support. The microdisplay includes a semiconductor workpiece mounted to the support and an optical device region disposed over the semiconductor workpiece. A plurality of contacts is disposed over a portion of the semiconductor workpiece, wherein each of the plurality of contacts comprises a protruding feature. | 2009-06-04 |
| 20090140758 | TEST CARRIER - A test carrier includes an insert body, a first latch assembly including one or more first latches pivotally attached to the insert body, and a second latch assembly including one or more second latches pivotally attached to the insert body. The second latch assembly is configured to engage with an external connection terminal array of an electronic component during testing thereof. A method of testing a semiconductor device and a system for testing a semiconductor device are also provided. | 2009-06-04 |
| 20090140759 | IC socket having contact devices with low impedance - A contact device ( | 2009-06-04 |
| 20090140760 | PROBE CARD - The probe card includes a plurality of probes arranged on one surface side of a board. These probes belonging to any one of a first probe group including a plurality of probes contacting respective electrodes in a first electrode row of an electronic device, a second probe group including a plurality of probes contacting respective electrodes in a second electrode row of the electronic device, and a third and fourth probe groups respectively including a plurality of probes contacting respective electrodes in a middle electrode row of the electronic device alternately. | 2009-06-04 |
| 20090140761 | METHOD OF TESTING SEMICONDUCTOR DEVICE - A method of testing a semiconductor device, which can reduce a period of time for testing a packaged semiconductor chip. First, semiconductor chips to be tested are classified in a lot unit. The semiconductor chips are fist tested in units of lots. The defective semiconductor chips among the semiconductor chips of a predetermined number of lots that are first time tested are collectively retested. First test data regarding the semiconductor chips may be classified and stored for each respective lot. Retest data regarding the semiconductor chips may be classified and stored for each respective lot. Test data regarding the semiconductor chips may be classified and stored into first test data and retest data for each respective lot. | 2009-06-04 |
| 20090140762 | LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING - A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set. | 2009-06-04 |
| 20090140763 | METHOD OF MEASURING ON-RESISTANCE IN BACKSIDE DRAIN WAFER - A method of measuring on-resistance in a backside drain wafer includes providing a wafer having a first MOS transistor and a second MOS transistor each having a source and also sharing a drain provided at a backside of the wafer, and then forming a current flow path passing through the first and second MOS transistors, and then measuring a resistance between the sources of the first and second MOS transistors. Accordingly, an on-resistance in a backside drain wafer can be measured without using a chuck. | 2009-06-04 |
| 20090140764 | Latch Circuit - A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the feedback circuit section, only when the input signals or the signals having the same phase as the input signals are input to the at least two input terminals at the same time, positive feedback using a predetermined number of amplification stages is applied to the input terminals. | 2009-06-04 |
| 20090140765 | On-Die Terminators Formed of Coarse and Fine Resistors - An integrated circuit includes a semiconductor substrate; a first node; a second node; and a first plurality of resistors, each in a first plurality of resistor units. Each of the first plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The integrated circuit further includes a second plurality of resistors, each in a second plurality of resistor units. Each of the second plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The first plurality of resistors is formed of a first material. The second plurality of resistors is formed of a second material different from the first material. The integrated circuit further includes a switch in one of the first and the second plurality of resistor units and serially connected to a resistor. | 2009-06-04 |
| 20090140766 | Signal transmission circuit and characteristic adjustment method thereof, memory module, and manufacturing method of circuit board - A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a control circuit that outputs match information between an impedance of the second transmission line and the impedance stored in the first impedance storage circuit. | 2009-06-04 |
| 20090140767 | Universal circuit for secure function evaluation - An exemplary method enables implementation of a universal circuit capable of emulating each gate of a circuit designed to calculate a function. A first selection module receives inputs associated with the function. It generates outputs that are an ordered series of the inputs. A universal module receives these outputs and generates another set of outputs. A second selection module receives the outputs from the universal module and generates final function outputs that are an ordered series inputs received from the universal module. The selection modules and universal module themselves are also aspects of the present invention. | 2009-06-04 |
| 20090140768 | Low-noise PECL output driver - An integrated circuit output driver is provided that exhibits improved performance and signal integrity. In one embodiment, the integrated circuit output driver is fabricated in a process having thin-gate MOS transistors and thick-gate MOS transistors and includes a predriver circuit, a level shifter circuit, and a driver circuit. The predriver circuit is formed predominantly of thin-gate transistors, and the driver circuit is formed predominantly of thick-gate transistors. In other embodiments, a low-pass power supply filter is provided. In still other embodiments, a voltage regulator circuit is provided, wherein an operating potential of at least one of the predriver circuit and the level shifter circuit is less than the specified supply voltage. In one embodiment, the voltage regulator circuit produces: i) a reduced internal supply voltage that is applied to the predriver circuit; and ii) an elevated ground voltage that is applied to the level shifter circuit. | 2009-06-04 |
| 20090140769 | System-in-package - A System-in-Package includes a first chip to be mounted in common for a plurality of product types, a second chip having different specifications for each product type, and a wiring substrate being common to a plurality of product types, on which the first chip and the second chip are to be mounted. A setting signal is supplied from the second chip to the first chip. | 2009-06-04 |
| 20090140770 | INPUT/OUTPUT CIRCUIT - An input/output circuit, operable in an input mode and an output mode, for receiving data and an enable signal, the input/output circuit including an input/output terminal; a pull-up output transistor including a gate; a first logic circuit including an output node coupled to the gate of the pull-up output transistor; a pull-down output transistor including a gate; a second logic circuit coupled to the gate of the pull-down output transistor, and the second logic circuit inactivating the pull-down output transistor in the input mode; and a gate signal generation unit configured to generate a gate signal for inactivating the pull-up output transistor in accordance with the enable signal and an input signal provided from an external device to the input/output terminal in the input mode. | 2009-06-04 |
| 20090140771 | Current-controlled CMOS circuits with inductive broadbanding - Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C | 2009-06-04 |
| 20090140772 | ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES - Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed. | 2009-06-04 |
| 20090140773 | Phase detection apparatus and phase synchronization apparatus - A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs a third signal of a pulse width corresponding to the phase difference detected; and a LPF that outputs, as a control signal Vcontrol, the integral of the pulse width of the third signal. The control signal Vcontrol, indicative of a delay amount, is fed back the third variable delay device and input to a first variable delay device and a second variable delay device of a phase-difference detection unit. | 2009-06-04 |
| 20090140774 | SYSTEM AND METHOD FOR COMMUNICATING DATA AMONG CHAINED CIRCUITS - A system and method are provided for communicating data among chained circuits. In operation, a period of a signal communicated between a chain of circuits is identified. Additionally, a state of the signal is determined, based on the period of the signal. | 2009-06-04 |
| 20090140775 | Multiplexing circuit - A multiplexing circuit comprising an converter for converting an input voltage signal to an input current signal. A plurality of first current mirrors for mirroring the input current signal. A switching unit selectively switches each first current mirror to a corresponding output. | 2009-06-04 |
| 20090140776 | Voltage-current converter and voltage controlled oscillator - An exemplary aspect of an embodiment of the present invention is a voltage-current converter converting an input voltage input to an input terminal to a current to output the current, the voltage-current converter including a first current generating circuit including an input transistor having a gate connected to the input terminal and generating an output current according to a current flowing in the input transistor, and a second current generating circuit including a transistor having a gate having a potential different from potential of a source and a drain, the second current generating circuit generating a superimposed current according to the current flowing in the transistor to supply the superimposed current to the input transistor. | 2009-06-04 |
| 20090140777 | DIFFERENTIAL TRANSISTOR PAIR CURRENT SWITCH SUPPLIED BY A LOW VOLTAGE VCC - The invention relates to current switches using a differential pair of transistors and being able to operate under a low supply voltage Vcc. According to the invention, provision is made for the current switch to include two differential pairs of two transistors each (T | 2009-06-04 |
| 20090140778 | DIFFERENTIAL DRIVE CIRCUIT AND COMMUNICATION DEVICE - A differential drive circuit includes at least a first or second drive system. The first drive system has first and second field effect transistors, first and second resistors, and first and second circuits controlling the source voltages of the first and second field effect transistors to equal first and second drive target voltages, the first and second field effect transistors having sources connected to a power potential via the first and second resistors, respectively. The second drive system has third and fourth field effect transistors, third and fourth resistors, and third and fourth circuits controlling the source voltages of the third and fourth field effect transistors to equal third and fourth drive target voltages, the third and fourth field effect transistors having sources connected to a reference potential via the third and fourth resistors, respectively. A common-mode voltage is driven to form a constant differential signal across a load resistance. | 2009-06-04 |
| 20090140779 | METHOD AND APPARATUS FOR DRIVING CAPACITIVE LOAD, AND LCD - A potential supplied from a capacitive load drive unit to one end of a respective capacitive load is switched to an intermediate potential between a first and a second power supply potentials for a predetermined period of time prior to switching the potential of the one end of the capacitive load from the first to the second power supply potential, or vice versa, which minimizes charging and discharging currents of the load, variations of the potential supplied to the capacitive load, and hence power consumption involved, without providing a charging capacitor having a large capacitance in the capacitive load drive unit. | 2009-06-04 |
| 20090140780 | DRIVING DEVICE AND DRIVING METHOD OF CAPACITIVE LOAD AND LIQUID JET PRINTING APPARATUS - A driving device of a capacitive load includes a modulator that executes pulse modulation on a drive waveform signal. An inductor performs low-pass filtering on the modulated drive waveform signal and outputs the low-pass filtered signal as a drive signal towards a load capacitor as the capacitive load. A load selection control circuit selects a load capacitor and a dummy load capacitor to be connected to the inductor so that a sum of the capacitances of the selected load capacitor and dummy load capacitor is kept within a predetermined range. A feedback circuit executes a filtering process on the drive signal so that a frequency characteristic of a passing band of the drive signal becomes substantially flat. The resulting signal is provided to the modulator as a feedback signal. The modulator executes the pulse modulation on a difference value between the drive waveform signal and the feedback signal. | 2009-06-04 |
| 20090140781 | CIRCUIT FOR DATA SYNCHRONIZATION OF I2C TIME CONTROLLER IN DISPLAY DEVICE AND METHOD THEREOF - A method of controlling an interface between an I2C master in a time controller for a liquid crystal display and an external memory may include causing a pre-scaler to determine whether or not a first clock signal from the I2C master to the external memory is synchronized with a second clock signal from the external memory to the I2C master. If the first clock signal is not synchronized with the second clock signal, the pre-scaler stops transmission of a third clock signal for an I2C interface with the external memory to the I2C master. | 2009-06-04 |
| 20090140782 | SPREAD SPECTRUM CLOCK GENERATING APPARATUS - A spread spectrum clock generating apparatus is disclosed. The spread spectrum clock generating apparatus includes a phase lock loop module and a spread spectrum module. The phase lock loop module is used for dynamically tuning frequency of an output clock. The spread spectrum module includes a counter, a plurality of delta-sigma counters and a data shifter. These delta-sigma counters accumulate input signals, and enable a first overflow signal while accumulation of a last stage delta-sigma counter is overflowed. The frequency of the output clock can be tuned dynamically according to the first overflow signal, and the spectrum of the output clock can be spread. | 2009-06-04 |
| 20090140783 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having a delay adjusting circuit including a delay line having N stages of differential delay circuits and N stages of differential interpolators. A differential interpolator of an Mth (where M| 2009-06-04 | |
| 20090140784 | HIGH-SPEED PULSE SHAPING FILTER SYSTEMS AND METHODS - A first system and method relates to an analog current-mode method using branch systems. In the analog current-mode implementation, multiple branches systems can be scaled according to filter coefficients and switched using known data points. Positive coefficients can add current to the summing node, while negative coefficients can remove current from the summing node. Switches can be implemented with quick charge/discharge paths in order to operate at very high data rates. A second system and method relates to a digital look-up table based high-speed implementation. In the digital implementation, outputs can be pre-calculated as an n-bit output word that drives an n-bit DAC. Each bit of the n-bit word can then described as an independent function of the known data points. Each such function can be implemented as a high-speed combinational logic block. Both systems and methods enable the implementation of pulse shaping filters for multi-gigabit per second data transmission. | 2009-06-04 |
| 20090140785 | Duty detector and duty cycle corrector including the same - A duty detector includes a clock converter, a hold pulse generator, a first logic operator, and an up/down counter. The clock converter receives a clock signal to generate an up clock signal and a down clock signal having phases opposite to each other. The hold pulse generator generates a hold pulse signal that is deactivated during a counting interval corresponding to first through (N−1)-th period intervals of the clock signal and is activated during a holding interval corresponding to an N-th period interval. The first logic operator outputs a counting clock signal by performing a first logic operation on the hold pulse signal and a sampling clock signal. The up/down counter determines a logic level of the up clock signal and a logic level of the down clock signal at an edge timing of the counting clock signal, increases or decreases a counting value in response to the determination result, and outputs duty information of the clock signal, based on a final counting value. | 2009-06-04 |
| 20090140786 | PULSE WIDTH MODULATION CIRCUIT AND SWITCHING AMPLIFIER USING THE SAME - A pulse width modulation circuit includes a first electric-charge accumulator; a second electric-charge accumulator; a first current generator which generates a first current corresponding to the amplitude of an input AC voltage; a second current generator which generates a second current with a constant value; a first current supply controller which supplies the first current to the first electric-charge accumulator; a second current supply controller which supplies the second current to the first electric-charge accumulator; a third current supply controller which supplies the first current to the second electric-charge accumulator; a fourth current supply controller which supplies the second current to the second electric-charge accumulator; and a current limiter which limits the first current to a third current with a predetermined current value, if the amplitude of the AC voltage in the negative side exceeds a predetermined level. | 2009-06-04 |
| 20090140787 | Phase controller apparatus and pulse pattern generator and error detector using the phase controller apparatus - A quadrature modulator divides a first signal input as a local signal into an I channel signal and a Q channel signal orthogonal to each other and outputs a second signal having a desired phase delay corresponding to direct current voltages as for the first signal by giving the direct current voltages Vi and Vq to the I channel signal and the Q channel signal, respectively. A phase comparison unit detects a phase difference θ between the first signal and the second signal. A setting unit sets the desired phase delay. A controller section controls the direct current voltages supplied to the I channel signal and the Q channel signal respectively in the quadrature modulator so that an output value corresponding to the phase difference θ detected by the phase comparison unit is equal to a value corresponding to the desired phase delay set by the setting unit, and controls the direct current voltages to be the direct current voltages Vi and Vq satisfying the relation of Vi=cos θ and Vq=sin θ. | 2009-06-04 |
| 20090140788 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a plurality of clock tree cells arranged in a tree structure on clock signal lines transmitting a clock signal, the plurality of clock tree cells forming a clock tree. The clock tree cells include first power supply lines connected to the clock tree cells, second power supply lines connected to logic circuits receiving a clock signal supplied from the clock tree, and a plurality of power supply pads connected to the first power supply lines and the second power supply lines. | 2009-06-04 |
| 20090140789 | CALIBRATION STRATEGY FOR REDUCED INTERMODULATION DISTORTION - The present disclosure relates to a circuit and method for reducing intermodulation distortion in a non-linear device having a differential output stage. A calibration circuit is provided for adding a calibration offset voltage to at least one of one output branch of the differential output stage and a bulk terminal of a transistor of one output branch of the differential output stage to obtain a desired output offset at the differential output stage. Thereby, a certain degree of asymmetry is introduced so that both output branches of the differential output stage are matched or optimized to improve the IIP | 2009-06-04 |
| 20090140790 | ELECTRONIC DEVICE WITH COMPOUND AUDIO INTERFACE AND POWER ADAPTER - An exemplary electronic device includes a power module having an anode and a cathode; an audio module having a first audio signal terminal, a second audio signal terminal and a ground terminal; and an audio socket having a first audio signal terminal, a second audio signal terminal connected to the second audio terminal of the audio module, and a ground terminal, wherein the first audio terminal of the audio socket is selectively connected to the anode of the power module and the first audio signal terminal of the audio module via a first switch, the ground terminal of the audio socket is selectively connected to the cathode of the power module and the ground terminal of the ground module of the audio module via a second switch. Therefore, users can charge the electronic device via the audio interface. | 2009-06-04 |
| 20090140791 | Switching Element Control - An apparatus in an example comprises a switching element and diode-resistor coupling. The diode-resistor coupling controls timing characteristics of turn ON and turn OFF of the switching element. | 2009-06-04 |
| 20090140792 | TEMPERATURE COMPENSATION CIRCUIT - A temperature compensation circuit according to an embodiment of the present invention includes a bias circuit configured to output a bias current, the bias current having a current value increasing in proportion to absolute temperature, in a low temperature region in which a temperature is lower than a predetermined temperature, and having a greater current value than the current value increasing in proportion to absolute temperature, in a high temperature region in which the temperature is equal to or greater than the predetermined temperature, and a transistor having a collector connected to a power supply terminal, an emitter which is grounded, and a base supplied with the bias current. | 2009-06-04 |
| 20090140793 | INTERNAL VOLTAGE GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - An internal voltage generation circuit of a semiconductor memory device controls a dead zone voltage, in which the driving unit that supplies a power supply voltage, does not need to operate. An internal voltage having a dead zone is determined by first and second driving signals based on a level of a reference voltage, and by selectively supplying first and second voltages by means of the first and second driving signals. | 2009-06-04 |
| 20090140794 | CONSTANT-CURRENT CHARGE PUMP - The present invention discloses a constant-current charge pump, wherein a current detection circuit and a regulation circuit are arranged in the output of a pump circuit and used to control the current output by the pump circuit. When the load varies, the current variation is detected, and the regulation circuit pumps and regulates the current output by the pump circuit to stabilize the output current. Thereby, the output current will vary very slightly for different loads and input voltages. | 2009-06-04 |
| 20090140795 | HIGH-DYNAMIC RANGE LOW RIPPLE VOLTAGE MULTIPLIER - A voltage multiplier ( | 2009-06-04 |
| 20090140796 | SLEW RATE CONTROL IN OUTPUT DRIVER - A slew rate control circuit in output driver of switching circuit to prevent power ground undershoot is introduced. The gate capacitance of lower power transistor is first fast discharged to ensure the operation of the output signal. The gate capacitance of lower power transistor is then slowly discharged to limit OUT SLEW RATE. The gate capacitance of lower power transistor is further slowly discharged when the power ground level is below common ground. With above controlling, the gate voltage slew rate of lower power transistor is reduced when the lower power transistor is almost fully turned OFF. Therefore, undershoot at the power ground is avoided. Similar slew rate control circuit can also be derived in output driver of switching circuit to prevent PVCC overshoot. | 2009-06-04 |
| 20090140797 | Rapidly Activated Current Mirror System - One embodiment of the invention includes a current mirror system. The system comprises a master circuit configured to conduct a first current in response to an activation state of an activation signal. The system also comprises a slave circuit configured to generate at least one second additional current in response to the activation state of the activation signal. Each of the at least one additional current can be proportional to the first current. The system further comprises a current path circuit that is configured as a substantial copy of the master circuit, the current path circuit being configured to conduct the first current in response to a deactivation state of the activation signal. | 2009-06-04 |
| 20090140798 | SEMICONDUCTOR DEVICE INCLUDING REFERENCE VOLTAGE GENERATION CIRCUIT ATTAINING REDUCED CURRENT CONSUMPTION DURING STAND-BY - During operation, a control signal attains H level, a conventional type first reference voltage generation circuit is activated, and the first reference voltage generation circuit generates a reference voltage. During stand-by, the control signal attains L level, and the first reference voltage generation circuit is inactivated, whereby a through current does not flow through the first reference voltage generation circuit. Then, during stand-by, an internal voltage generation circuit is supplied with the reference voltage generated by a second reference voltage generation circuit including a resistance division circuit constituted of first to third resistors each having a high resistance value of T (tera) Ω order, in which a through current is extremely small. | 2009-06-04 |
| 20090140799 | INTEGRATED RC FILTER - An integrated RC filter includes a first resistor that is coupled to a first capacitor through a first node, a signal input of the integrated RC filter being coupled through one of the first resistor and the first capacitor to the first node. To allow for an increase in the RC timeconstant τ of the RC filter without losing signal transparency, an amplifier is included between the signal input and one of the first resistor and the first capacitor having a gain factor substantially larger than unity, the first node being coupled through an attenuator to a signal output, the attenuator having an attenuation factor substantially corresponding to the amplifier's gain factor. | 2009-06-04 |
| 20090140800 | INTEGRATED CIRCUIT WITH SIGNAL BUS FORMED BY CELL ABUTMENT OF LOGIC CELLS - An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells. | 2009-06-04 |
| 20090140801 | Locally gated graphene nanostructures and methods of making and using - A locally gated graphene nanostructure is described, along with methods of making and using the same. A graphene layer can include first and second terminal regions separated by a substantially single layer gated graphene nanoconstriction. A local first gate region can be separated from the graphene nanoconstriction by a first gate dielectric. The local first gate region can be capacitively coupled to gate electrical conduction in the graphene nanoconstriction. A second gate region can be separated from the graphene nanoconstriction by a second gate dielectric. The second gate region can be capacitively coupled to provide a bias to a first location in the graphene nanoconstriction and to a second location outside of the graphene nanoconstriction. Methods of making and using locally gated graphene nanostructures are also described. | 2009-06-04 |
| 20090140802 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce offset error voltage in a signal source impedance of analog input signal voltage supplied to an input terminal due to input offset voltage of an operational amplifier in a sampling circuit or a multiplexer coupled to an input terminal of an A/D converter. A semiconductor integrated circuit has an A/D converter and a sampling circuit. The sampling circuit samples an analog input signal in first and second sample modes. The A/D converter converts the sampled analog signal to a digital signal in a conversion mode. By switching of an internal circuit of an operational amplifier between the first and second sample modes, the functions of a non-inverting input terminal (+) and an inverting input terminal (−) realized by first and second input terminals are switched. Synchronously with the switching, supply of an analog signal to the non-inverting input terminal by input switches is also switched. | 2009-06-04 |
| 20090140803 | AMPLIFIERS WITH COMPENSATION - An amplifier system includes a first amplifier stage having an input and an output. A second amplifier stage has an input and an output, the input of the second amplifier stage being connected to the output of the first amplifier stage. A transistor has a control terminal, a first terminal, and a second terminal, the first terminal of the transistor being coupled to the output of the first amplifier stage and the input of the second amplifier stage. A first capacitance has a first terminal and a second terminal, the first terminal of the first capacitance being connected to the input of the first amplifier stage, the second terminal of the first capacitance being connected to the second terminal of the transistor. A first current source to source current to amplifier system, the first current source being is connected to the output of the first amplifier stage. A second current source will sink current from the amplifier system. The second current source is connected to the second terminal of the first capacitance and the second terminal of the transistor. | 2009-06-04 |
| 20090140804 | METHOD AND APPARATUS FOR IMPROVING THE PERFORMANCE OF MIMO WIRELESS SYSTEMS - Method and apparatus for efficiently providing DC power enhancement to power amplifiers each of which being arranged in a MIMO system, by suing an enhancement circuitry with a plurality of inputs and outputs. Each input has a corresponding DC enhancement output that is connected to a DC enhancement input of a power amplifier. The DC enhancement output becomes operative whenever the amplitude of the corresponding input signal exceeds a predetermined threshold. The envelope of a plurality of input signals is sampled by sampling circuitries and the sampled envelopes are fed into a summation circuitry, in which they are summed. Whenever one of the sampled envelopes exceeds the threshold, a DC enhancement power is simultaneously provided to all DC enhancement inputs of all power amplifiers. | 2009-06-04 |
