| 23rd week of 2009 patent applcation highlights part 13 |
| Patent application number | Title | Published |
|---|
| 20090140205 | NITROGEN-CONTAINING ALLOY AND METHOD FOR PRODUCING PHOSPHOR USING THE SAME - There is provided a method for industrially producing a phosphor with high performance, in particular, high brightness. There is also provided a nitrogen-containing alloy and an alloy powder that can be used for the production method. A method for producing a phosphor includes a step of heating a raw material for the phosphor under a nitrogen-containing atmosphere, in which an alloy containing two or more different metal elements constituting the phosphor is used as the whole or part of the raw material for the phosphor, and in the heating step, the heating is performed under conditions such that the temperature change per minute is 50° C. or lower. | 2009-06-04 |
| 20090140206 | Surface enhanced Raman spectroscopy (SERS)-active composite nanoparticles, methods of fabrication thereof, and methods of use thereof - Nanoparticles, methods of preparation thereof, and methods of detecting a target molecule using embodiments of the nanoparticle, are disclosed. One embodiment of an exemplary nanoparticle, among others, includes a surface-enhanced Raman spectroscopic active composite nanostructure. The surface-enhanced Raman spectroscopic active composite nanostructure includes a core, at least one reporter molecule, and an encapsulating material. The reporter molecule is bonded to the core. The reporter molecule is selected from: an isothiocyanate dye, a multi-sulfur organic dye, a multi-heterosulfur organic dye, a benzotriazole dye, and combinations thereof The encapsulating material is disposed over the core and the reporter molecule. After encapsulation with the encapsulating material, the reporter molecule has a measurable surface-enhanced Raman spectroscopic signature. | 2009-06-04 |
| 20090140207 | MICROENCAPSULATED PARTICLES AND PROCESS FOR MANUFACTURING SAME - Microencapsulated particles having improved resistance to moisture and extended release capabilities are produced by microencapsulating the particles in a film-forming, cross-linked, hydrolyzed polymer. | 2009-06-04 |
| 20090140208 | AQUEOUS CARBON BLACK FORMULATIONS FOR INK JET - Finely divided solids are highly suitable for use as stabilizers for pyrocarbonic acid diesters, it being possible to use the mixtures obtained in this manner for preserving industrial materials and foodstuff. | 2009-06-04 |
| 20090140209 | PROCESS FOR PRODUCING A CARRIER - A complex, which has been formed by at least two pieces of a ligand and a first metal ion, is bound with a carrier. A second metal ion is then added onto the carrier, a new complex being thereby formed. A substance that contains a Group-15 or Group-16 atom, which has metal coordinating capability, is then fixed to the first metal ion and the second metal ion. | 2009-06-04 |
| 20090140210 | Anisotropic Conductive Adhesive - An anisotropic conductive adhesive is provided that includes an epoxy resin, a phenoxy resin, a curing agent, an inorganic filler, and conducting particles as components. The phenoxy resin is controlled to have a glass-transition temperature (Tg) in a range of 66° C. to 100° C., so that the anisotropic conductive adhesive has an excellent fluidity in a mounting process, satisfactory electric conductive/insulation performances, and sufficient adhesiveness. Since the properties of the anisotropic conductive adhesive are almost invariant even if the adhesive is used for a long time under a high-temperature- and high-humidity condition, the anisotropic conductive adhesive can be used for applications where a high reliability is required. | 2009-06-04 |
| 20090140211 | CONVECTIVE FLOW CHEMICAL VAPOR DEPOSITION GROWTH OF NANOSTRUCTURES - The invention is directed to CVD methods and systems that can be utilized to form nanostructures. Exceptionally high product yields can be attained. In addition, the products can be formed with predetermined particle sizes and morphologies and within a very narrow particle size distribution. The systems of the invention include a CVD reactor designed to support the establishment of a convective flow field within the reactor at the expected carrier gas flow rates. In particular, the convective flow field within the reactor can include one or more flow vortices. The disclosed invention can be particularly beneficial for forming improved thermoelectric materials with high values for the figure of merit (ZT). | 2009-06-04 |
| 20090140212 | Electron Transfer Through Glassy Matrices - Provided are electron transfer compositions comprising a glassy sugar matrix. Electric batteries, electric circuits, semiconductors, solar cells, thermal detectors, and photo detectors comprising glassy sugar matrices are also provided. Additionally provided are methods of transferring electrons to a redox protein using these compositions. | 2009-06-04 |
| 20090140213 | METHOD OF MAKING AN APPLICATOR LIQUID FOR ELECTRONICS FABRICATION PROCESS - Certain spin-coatable liquids and application techniques are described, which can be used to form nanotube films or fabrics of controlled properties. A method of making an applicator liquid containing nanotubes for use in an electronics fabrication process includes characterizing an electronic fabrication process according to fabrication compatible solvents and allowable levels of metallic and particle impurities; providing nanotubes that satisfy the allowable impurities criteria for the electronics fabrication process; providing a solvent that meets the fabrication compatible solvents and allowable impurities criteria for the electronic fabrication process; and dispersing the nanotubes into the solvent at a concentration of at least one milligram of nanotubes per liter solvent to form an applicator liquid. | 2009-06-04 |
| 20090140214 | Material for negative electrode of non-aqueous electrolyte secondary battery, process for producing the same, negative electrode and battery - A negative electrode material for non-aqueous electrolyte secondary batteries, comprises: a carbon material having a sphericity of at least 0.8, and exhibiting an average (002) interlayer spacing d | 2009-06-04 |
| 20090140215 | CATALYST FOR PRODUCING CARBON NANOTUBES BY MEANS OF THE DECOMPOSITION OF GASEOUS CARBON COMPOUNDS ON A HETEROGENEOUS CATALYST - The present invention relates to a process for the production of carbon nanotubes, in particular those having a diameter of 3-150 nm and an aspect ratio of length:diameter (L:D)>100, by decomposition of hydrocarbons on a heterogeneous catalyst which comprises Mn, Co, preferably also molybdenum, and an inert support material, and the catalyst and the carbon nanotubes themselves and the use thereof. | 2009-06-04 |
| 20090140216 | Anisotropic conductive film composition, anisotropic conductive film including the same, and associated methods - An anisotropic conductive film composition includes a polymer resin, a first epoxy resin including at least one of a bisphenol epoxy resin, a novolac epoxy resin, a glycidyl epoxy resin, an aliphatic epoxy resin, and an alicyclic epoxy resin, a second epoxy resin including an acetal epoxy resin, an epoxy resin curing agent, and conductive particles. | 2009-06-04 |
| 20090140217 | ELECTROCONDUCTIVE THICK FILM COMPOSITION(S), ELECTRODE(S), AND SEMICONDUCTOR DEVICE(S) FORMED THEREFROM - The present invention is directed to an electroconductive thick film composition comprising: (a) electroconductive metal particles selected from (1) Al, Cu, Au, Ag, Pd and Pt; (2) alloy of Al, Cu, Au, Ag, Pd and Pt; and (3) mixtures thereof; (3) glass frit wherein said glass frit is Pb-free; dispersed in (d) an organic medium, and wherein the average diameter of said electroconductive metal particles is in the range of 0.5-10.0 μm. The present invention is further directed to an electrode formed from the composition as detailed above and a semiconductor device(s) (for example, a solar cell) comprising said electrode. | 2009-06-04 |
| 20090140218 | TRANSPARENT CONDUCTIVE MATERIAL AND TRANSPARENT CONDUCTOR - The present invention provides a transparent conductive material with little change in electric resistance under influence of temperature or humidity and a transparent conductive membrane using the same. | 2009-06-04 |
| 20090140219 | Selenium Containing Electrically Conductive Polymers and Method of Making Electrically Conductive Polymers - Monomeric, oligomeric and polymeric electrically conductive compounds and methods of making the compounds having a repeating unit having formula P1, as follows: | 2009-06-04 |
| 20090140220 | Photosensitive Resin Composition for Color Filter and Color Filter Using Same - The photosensitive resin composition for a color filter according to one embodiment of the present invention includes (A) a pigment including a repeating unit of the following Formula 1, (B) a binder resin, (C) a photopolymerization initiator, (D) a photopolymerizable monomer, and (E) a solvent: | 2009-06-04 |
| 20090140221 | Theater Rigging System - A theater rigging assembly having a beam, which is attached to structural support members of a theater or other performing arts venue. The assembly further includes a winch assembly and head block that can be positioned at any point along the beam and selectively fixed in position. The winch portion includes cables for raising and lowering battens or other loads. The head block includes head sheaves, which redirect the cables to loft sheaves that are selectively attached to the beam. The head sheaves are diagonally displaced to separate the cables. The winch portion includes a motor, a gear box, a drum and a brake. The brake includes a ratchet and two brake disks. It uses at least one friction surface that contacts at least one of the brake disks to cause a pawl to engage or disengage from the ratchet. | 2009-06-04 |
| 20090140222 | Method for operating a merchandise presentation arrangement, as well as a lifting device for a merchandise presentation arrangement in order to carry out said method - A merchandise presentation arrangement ( | 2009-06-04 |
| 20090140223 | Safer handrail - An improved handrail includes: an end-to-end extending, two-part cavity in the interior of the handrail, with its first part being a slot that extends from the handrails' exterior surface and its second part being a bore that is situated in the handrail's interior and joined with the slot so as to make the bore accessible from the handrail's exterior surface, and a wrist securing device that works in cooperation with the handrail's cavity for keeping the wrist of a user in close proximity to the handrail when the user is traversing a stairway. | 2009-06-04 |
| 20090140224 | Universal fencing stake - A fencing stake for securing a cord. The fencing stake of the present application creates a more usable and robust fence. The fencing stake has a shaped cross-sectional portion. The fencing stake also includes an anchor, wherein the anchor is formed from at least one shaped aperture having an insertion aperture for inserting the cord and at least two vertical apertures connected to the insertion aperture for securing the cord. The fencing stake further includes an end portion for placing the stake into the ground. | 2009-06-04 |
| 20090140225 | Damping Separator Element for Producing Delimiting or Protective Barriers - The invention concerns a damping separator element for producing delimiting or protective barriers, for example for road traffic lanes or motor sports tracks. The element includes an elongated horizontal section and a cover, preferably made of flexible plastic material. The central reinforcement or hollow core, preferably made of metal, produced in the form of a flattened sheath and extended from one end to the other of the element, is housed inside the cover. The reinforcement provides a space between the cover and the central flattened hollow reinforcement, the space being filled or to be filled with a plastic foam such as, for example, a polyethylene foam. | 2009-06-04 |
| 20090140226 | PVC GATE ASSEMBLY - A plastic gate assembly includes a plurality of rails that extend between a support post assembly and a latch rail. The gate assembly utilizes commonly available PVC rail components with the disclosed inventive PVC brackets to build a gate assembly. The post assembly includes a D-shaped profile to provide a desired clearance between the rotating support post assembly and a corresponding adjacent fixed fence post. | 2009-06-04 |
| 20090140227 | ORNAMENTAL FENCING SYSTEM AND METHOD FOR ASSEMBLING THE SAME - A fence has at least one fence section which extends between a pair of posts. Each of the fence section has an upper and lower horizontal rail extending between the posts. A plurality of channels extends transversally through the rails. Pickets are vertically inserted through the channels of the upper and lower rails, each picket having its top extremity projecting upwardly of the upper rail. Picket caps are each associated with a corresponding one of the pickets. Each picket cap has a body portion rigidly affixed to the top extremity of its corresponding picket, the picket also having a first arm and a second arm projecting on opposite sides of the body portion and extending along the upper rail of the fence section. The first arm of each picket cap is attached to the second arm of the picket cap affixed to an adjacent picket with attaching means. | 2009-06-04 |
| 20090140228 | FENCE HINGE - A hinge apparatus includes a first support member for attachment along a first surface of a vertical member such as a fence post. The first support member includes at least one flange angularly extending from the first support member for attachment along a second surface adjacent to the first surface of the vertical member. A hinge coupled to the first support member, and a second support member includes an extended element coupled to the hinge. The second support member attaches to a first surface of a swinging member, such as a fence gate, opposite the first support member. The second support member includes at least one flange angularly extending from the second support member for attachment along a second surface of the swinging member adjacent to the first surface of the swinging member. | 2009-06-04 |
| 20090140229 | Active material devices with containment layer - An active material electronic device is described with a containment layer. The device includes an active chalcogenide, pnictide, or phase-change material in electrical communication with an upper and lower electrode. The device includes a containment layer formed over the active material that prevents escape of volatilized matter from the active material when the device is exposed to high temperatures during fabrication or operation. The containment layer further prevents chemical contamination of the active material by protecting it from reactive species in the processing or ambient environment. The containment layer and intermediate layers formed between the active material and containment layer are formed at temperatures sufficiently low to prevent volatilization of the active material. Once the containment layer is formed, the device may be subjected to high temperature or chemically aggressive environments without impairing the compositional or structural integrity of the active material. Inclusion of the containment layer is shown to extend the cycle life of the device by over two orders of magnitude. | 2009-06-04 |
| 20090140230 | Memory Cell Device With Circumferentially-Extending Memory Element - A memory device comprises a contact and a pillar-shaped structure on the contact. The pillar-shaped structure includes a conductive inner element surrounded by a memory outer layer. A transition region is located at the memory outer layer above said contact. The conductive element may directly contact said contact. | 2009-06-04 |
| 20090140231 | Semiconductor device and method of manufacturing the same - It is an object of the present invention to provide a technique in which a high-performance and highly reliable semiconductor device can be manufactured at low cost with high yield. A memory device according to the present invention has a first conductive layer including a plurality of insulators, an organic compound layer over the first conductive layer including the insulators, and a second conductive layer over the organic compound layer. | 2009-06-04 |
| 20090140232 | Resistive Memory Element - An integrated circuit including a resistive memory element is described. The resistive memory element includes a first solid electrolyte layer including a metal doped glass material, the glass material being at least partially amorphous, and a second solid electrolyte layer including the metal doped glass material. The resistive memory element also includes a middle layer disposed between the first and second solid electrolyte layers, the middle layer including a carbide composition. | 2009-06-04 |
| 20090140233 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device having a large storage capacity and stabilized rewriting conditions in which a memory cell includes a nonvolatile recording material layer, a selector element and a semiconductor layer provided between the nonvolatile recording material layer and the selector element and having a thickness ranging from 5 to 200 nm. | 2009-06-04 |
| 20090140234 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film. | 2009-06-04 |
| 20090140235 | Semiconductor element and process for producing the same - The present invention provides a thin film transistor having excellent formability and processability, and particularly a thin film transistor using plastics as a substrate; an organic semiconductor as an active layer; and SiO | 2009-06-04 |
| 20090140236 | THIN FILM TRANSISTORS - A thin film transistor has a semiconducting layer comprising a semiconductor and surface-modified carbon nanotubes. The semiconducting layer has improved charge carrier mobility. | 2009-06-04 |
| 20090140237 | THIN FILM TRANSISTORS - A thin film transistor has a semiconducting layer comprising a semiconductor and a mixture enriched in metallic carbon nanotubes. The semiconducting layer has improved charge carrier mobility. | 2009-06-04 |
| 20090140238 | FLAT SCREEN DETECTOR - A flat screen detector has a substrate with a transistor matrix thereon, a photodetector, and a passivation layer. The photodetector includes a structured first electrode including a number of sub-electrodes, a second electrode, and a photoactive layer between the first and second electrodes. The passivation layer is located between the substrate having the transistor matrix and the first electrode. | 2009-06-04 |
| 20090140239 | COMPOUNDS FOR ORGANIC SEMICONDUCTOR DEVICE HAVING TRIAZINE GROUP, ORGANIC SEMICONDUCTOR THIN FILM AND ORGANIC SEMICONDUCTOR DEVICE COMPRISING THE SAME, AND METHODS OF PREPARING THEM - A compound for organic semiconductor devices having a triazine group, an organic semiconductor thin film and an organic semiconductor device comprising the same, and methods of preparing them are provided. The compound for organic semiconductor devices is represented by the following Formula: | 2009-06-04 |
| 20090140240 | ORGANIC THIN FILM TRANSISTOR - A thin film transistor comprising at least three terminals consisting of a gate electrode, a source electrode and a drain electrode; an insulator layer and an organic semiconductor layer on a substrate, which controls its electric current flowing between the source and the drain by applying a electric voltage across the gate electrode, wherein the organic semiconductor layer comprises a styryl derivative having a styryl structure expressed by C | 2009-06-04 |
| 20090140241 | ORGANIC SEMICONDUCTOR MATERIAL, ORGANIC SEMICONDUCTOR THIN FILM AND ORGANIC SEMICONDUCTOR DEVICE - An organic semiconductor material is provided. The organic semiconductor material includes a polyacene derivative expressed by the following general formula (1): | 2009-06-04 |
| 20090140242 | SEMICONDUCTOR SUBSTRATE WITH SOLID PHASE EPITAXIAL REGROWTH WITH REDUCED JUNCTION LEAKAGE AND METHOD OF PRODUCING SAME - Method of producing a semiconductor device, comprising: a) providing a semiconductor substrate, b) making a first amorphous layer in a top layer of the semiconductor substrate by a suitable implant, the first amorphous layer having a first depth, c) implanting a first dopant into the semiconductor substrate to provide the first amorphous layer with a first doping profile, d) applying a first solid phase epitaxial regrowth action to partially regrow the first amorphous layer and form a second amorphous layer having a second depth that is less than the first depth and activate the first dopant, e) implanting a second dopant into the semiconductor substrate to provide the second amorphous layer with a second doping profile with a higher doping concentration than the first doping profile, f) applying a second solid phase epitaxial regrowth action to regrow the second amorphous layer and activate the second dopant. | 2009-06-04 |
| 20090140243 | Oxide semiconductor thin film transistors and fabrication methods thereof - Oxide semiconductor thin film transistors (TFT) and methods of manufacturing the same are provided. The methods include forming a channel layer on a substrate, forming source and drain electrodes at opposing sides of the channel layer, and oxidizing a surface of the channel layer by placing an oxidizing material in contact with the surface of the channel layer, reducing carriers on the surface of the channel layer. Due to the oxidizing agent treatment of the surface of the channel layer, excessive carriers that are generated naturally, or during the manufacturing process, may be more effectively controlled. | 2009-06-04 |
| 20090140244 | SEMICONDUCTOR DEVICE INCLUDING A DIE REGION DESIGNED FOR ALUMINUM-FREE SOLDER BUMP CONNECTION AND A TEST STRUCTURE DESIGNED FOR ALUMINUM-FREE WIRE BONDING - In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon. | 2009-06-04 |
| 20090140245 | Structure for a Method and Structure for Screening NFET-to-PFET Device Performance Offsets Within a CMOS Process - A design structure of a method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not. | 2009-06-04 |
| 20090140246 | METHOD AND TEST STRUCTURE FOR MONITORING CMP PROCESSES IN METALLIZATION LAYERS OF SEMICONDUCTOR DEVICES - By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency. | 2009-06-04 |
| 20090140247 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions. | 2009-06-04 |
| 20090140248 | On-Chip Test Circuit for an Embedded Comparator - A semiconductor chip including an embedded comparator is provided with an on-chip test circuit for the comparator. The test circuit includes an analog input unit which, during a test mode of the chip, produces a range of analog voltage signals that are applied to a first input of the comparator and a threshold voltage signal that is applied to a second input of the comparator. A switch control unit is provided to control the application of a predetermined sequential pattern of these analog voltage signals to the first input of the comparator in synchrony with a clock signal supplied to the switch control unit during a predetermined test period. A digital measurement unit is provided to receive output signals from the comparator during the test period in response to the input patterns, to compare the output signals with the clock signal, and to measure and to store data relating thereto. | 2009-06-04 |
| 20090140249 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE - An object of the present invention is to provide a structure of a thin film circuit portion and a method for manufacturing a thin film circuit portion by which an electrode for connecting to an external portion can be easily formed under a thin film circuit. A stacked body including a first insulating film, a thin film circuit formed over one surface of the first insulating film, a second insulating film formed over the thin film circuit, an electrode formed over the second insulating film, and a resin film formed over the electrode, is formed. A conductive film is formed adjacent to the other surface of the first insulating film of the stacked body to be overlapped with the electrode. The conductive film is irradiated with a laser. | 2009-06-04 |
| 20090140250 | SEMICONDUCTOR DEVICE - An object is to reduce off-current of a thin film transistor. Another object is to improve electric characteristics of a thin film transistor. Further, it is still another object to improve image quality of a display device using the thin film transistor. An aspect of the present invention is a thin film transistor including a semiconductor film formed over a gate electrode and in an inner region of the gate electrode which does not reach an end portion of the gate electrode, with a gate insulating film interposed therebetween, a film covering at least a side surface of the semiconductor film, and a pair of wirings over the film covering the side surface of the semiconductor film; in which an impurity element serving as a donor is added to the semiconductor film. | 2009-06-04 |
| 20090140251 | THIN FILM TRANSISTOR, DISPLAY DEVICE INCLUDING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor having excellent electric characteristics, a display device including the thin film transistor, and a manufacturing method thereof are provided. In a thin film transistor in which a microcrystalline germanium film, a gate insulating film in contact with one surface of the microcrystalline germanium film, and a gate electrode overlap with one another and a display device including the thin film transistor, a buffer layer is formed over the other surface of the microcrystalline germanium film. By using a microcrystalline germanium film for a channel formation region, a thin film transistor with high field-effect mobility and high on-current can be manufactured, and by providing a buffer layer between the microcrystalline germanium film functioning as a channel formation region and a source and drain regions, a thin film transistor with low off-current can be manufactured, that is, a thin film transistor with excellent electric characteristics can be manufactured. | 2009-06-04 |
| 20090140252 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SENSOR - An image sensor and a method of manufacturing the sensor. A method of manufacturing an image sensor may include at least one of: Forming a gate over a semiconductor substrate. Sequentially depositing a plurality of insulating films over the semiconductor substrate and the gate. Removing an upper-most insulating film of the plurality of insulating films by dry etching, thus forming a spacer at sides of the gate. Removing other insulating films by wet etching, while maintaining a bottom-most insulating film of the plurality of insulating films over the semiconductor substrate. Attacks may be prevented on a surface of a semiconductor substrate, making it possible to reduce generation of a dark signal, prevent plasma damage by controlling the thickness of a remaining oxide film with ease, and making it possible to improve yield and resolution of an image. | 2009-06-04 |
| 20090140253 | TFT ARRANGEMENT FOR DISPLAY DEVICE - A new TFT arrangement is demonstrated, which enables prevention of TFT to be formed over a joint portion between the adjacent SOI layers prepared by the process including the separation of a thin single crystal semiconductor layer from a semiconductor wafer. The TFT arrangement is characterized by the structure where a plurality of TFTs each belonging to different pixels is gathered and arranged close to an intersection portion of a scanning line and a signal line. This structure allows the distance between regions, which are provided with the plurality of TFTs, to be extremely large compared with the distance between adjacent TFTs in the conventional TFT arrangement in which all TFTs are arranged in at a regular interval. The formation of a TFT over the joint portion can be avoided by the present arrangement, which leads to the formation of a display device with a negligible amount of display defects. | 2009-06-04 |
| 20090140254 | THIN FILM TRANSISTOR AND FLAT PANEL DISPLAY DEVICE INCLUDING THE SAME - A flat panel display device is disclosed. In one embodiment, the flat panel display device includes i) a semiconductor layer including a channel region and a groove, wherein the channel region electrically connects a source electrode and a drain electrode, and the groove is configured to separate the channel region from adjacent thin film transistors and ii) a stop layer formed below at least a portion of the semiconductor layer. According to one embodiment of the invention, a semiconductor layer can be easily patterned without using a dry or wet etching technique such as photolithography. | 2009-06-04 |
| 20090140255 | Crystalline Semicondutor Film and Method for Manufacturing the Same - An island of a crystalline semiconductor according to the present invention has an upper surface and a sloped side surface, which are joined together with a curved surface. Crystal grains in a body portion of the island, including the upper surface, and crystal grains in an edge portion of the island, including the sloped side surface, both have average grain sizes that are greater than 0.2 μm. | 2009-06-04 |
| 20090140256 | THIN FILM TRANSISTOR AND SEMICONDUCTOR DEVICE - An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region. | 2009-06-04 |
| 20090140257 | FILM FORMATION METHOD, THIN-FILM TRANSISTOR AND SOLAR BATTERY - After a gate oxide film | 2009-06-04 |
| 20090140258 | TRANSISTOR AND DISPLAY AND METHOD OF DRIVING THE SAME - A field-effect transistor including an electrically conductive substrate; a first insulating film coating the electrically conductive substrate; a gate electrode disposed on the electrically conductive substrate with the first insulating film interposed therebetween; a source electrode; a drain electrode opposing the source electrode with the channel therebetween; a second insulating film covering the gate electrode; and a semiconductor layer having a width larger than a width of the gate electrode in the channel width direction and being partly provided on the gate electrode with the second insulating film interposed therebetween so that the gate electrode, the second insulating film, and the semiconductor layer are laminated in the channel. | 2009-06-04 |
| 20090140259 | THIN FILM TRANSISTOR, DISPLAY DEVICE HAVING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device in a high yield are provided. In the thin film transistor, a gate electrode, a gate insulating film, crystal grains that mainly contain silicon and are provided for a surface of the gate insulating film, a semiconductor film that mainly contains germanium and covers the crystal grains and the gate insulating film, and a buffer layer in contact with the semiconductor film that mainly contains germanium overlap with one another. Further, the display device has the thin film transistor. | 2009-06-04 |
| 20090140260 | Liquid crystal display device and fabricating method thereof - A method for fabricating a liquid crystal display (LCD) device comprises forming an active pattern and a data line on a substrate, the active pattern including a source, a drain, and a channel regions; a first insulation film on a portion of the substrate; forming a gate electrode in a portion of the active pattern where the first insulation film is formed; a second insulation film on the substrate; forming a plurality of first contact holes exposing a portion of the source and drain regions and a second contact hole exposing a portion of the data line; forming a source electrode from a transparent conductive material connected to a source region within the respective first contact hole and a data line within the second contact hole; and forming a pixel and a drain electrodes from the transparent conductive material connected to a drain region within the respective first contact hole. | 2009-06-04 |
| 20090140261 | MOS SOLID-STATE IMAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A sidewall film | 2009-06-04 |
| 20090140262 | FIELD-EFFECT TRANSISTOR - A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film. | 2009-06-04 |
| 20090140263 | METHOD FOR DIAMOND SURFACE TREATMENT AND DEVICE USING DIAMOND THIN FILM - A method for surface treatment of diamond comprising exposing the surface of diamond to UV light containing wavelengths of 172 nm to 184.9 nm and 253.7 nm at an integrated exposure of 10 to 5,000 J/cm | 2009-06-04 |
| 20090140264 | SEMICONDUCTOR DEVICE - A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved. | 2009-06-04 |
| 20090140265 | LIGHT EMITTING DEVICE AND ELECTRONIC APPARATUS - A light emitting device includes a substrate having transparency, a light emitting element that emits light at least to the substrate side, and a light detecting element that is formed between the light emitting element and the substrate. The light detecting element is formed along an outer frame of the light emitting element in a plan view. | 2009-06-04 |
| 20090140266 | PACKAGE INCLUDING ORIENTED DEVICES - An package such as an optocoupler package is disclosed. The optocoupler package includes a leadframe structure comprising a first die attach pad comprising a first die attach pad surface and a second die attach pad with a second die attach pad surface. The optocoupler package further has an optical emitter device on the first die attach pad, and an optical receiver device on second die attach pad. The optical receiver device is oriented at an angle with respect to the optical emitter device, and an optically transmissive medium is disposed between the optical emitter device and the optical receiver device. | 2009-06-04 |
| 20090140267 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor light emitting device comprising a single crystalline buffer layer and a manufacturing method thereof. The semiconductor light emitting device comprises a single crystalline buffer layer, and a compound semiconductor structure comprising III and V group elements on the single crystalline buffer layer. | 2009-06-04 |
| 20090140268 | LED array module and method of packaging the same - An LED array module includes a drive IC structure, at least one LED array, an adhesive element, and a first conductive structure. The drive IC structure has a concave groove formed on a top side thereof. The at least one LED array is received in the at least one concave groove. The adhesive element is disposed between the at least one LED array and the drive IC structure. The first conductive structure is electrically connected between the drive IC structure and the at least one LED array. Moreover, the LED array module can be disposed on a PCB that has at least one input/output pad. A second conductive structure is electrically connected between the drive IC structure and the at least one input/output pad. | 2009-06-04 |
| 20090140269 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - In a display apparatus and a method of manufacturing the display apparatus, a gate line, a data line, and a plurality of layers are formed on an array substrate on which a pixel area, a pad area, and a peripheral area are defined. During the forming processes of the gate line, the data line, and the layers, the gate line and the data line are partially exposed in the peripheral area, or contact portions formed on the gate line and the data line in the peripheral area are exposed. Thus, the gate line and the data line may be tested using the contact portions as electrical terminals during the manufacturing process of the display apparatus. | 2009-06-04 |
| 20090140270 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THEREOF - An object is to provide a system-on-panel display device including a display portion and a peripheral circuit for controlling display on the display portion over one substrate, which can operate more accurately. The display device has a display portion provided with a pixel portion including a plurality of pixels and a peripheral circuit portion for controlling display on the display portion, which are provided over a substrate. Each of the display portion and the peripheral circuit portion includes a plurality of transistors. For semiconductor layers of the transistors, single crystal semiconductor materials are used. | 2009-06-04 |
| 20090140271 | LIGHT EMITTING UNIT - A light emitting unit has a chamber. The light emitting unit includes at least one substrate, a plurality of light emitting diode (LED) dies and a gel or a fluid. The LED dies are disposed on the substrate and in the chamber. At least two LED dies are electrically connected to each other in series or in parallel. The gel or the fluid is filled in the chamber. | 2009-06-04 |
| 20090140272 | Solid-state light source - A solid-state light source includes at least one stack of light emitting elements. The elements are an inorganic light emitting diode chip and at least one wavelength conversion chip or the elements are a plurality of light emitting diode chips and one or more optional wavelength conversion chips. The wavelength conversion chip may include an electrical interconnection means. The light emitting diode chip may include at least one GaN-based semiconductor layer that is at least ten microns thick and that is fabricated by hydride vapor phase epitaxy. A method is described for fabricating the solid-state light source. | 2009-06-04 |
| 20090140273 | Epitaxial Wafer for Semiconductor Light Emitting Diode and Semiconductor Light Emitting Diode Using Same - An epitaxial wafer for a semiconductor light emitting device according to the present invention in which at least an n-type cladding layer formed with a mixed crystal made of an AlGaInP material, an active layer, a p-type Mg-doped cladding layer, and a p-type contact layer are stacked successively in that order on an n-type GaAs substrate, and the p-type contact layer is formed as at least two layers that are an Mg-doped contact layer and a Zn-doped contact layer stacked thereon when viewed from the n-type GaAs substrate, comprises a Zn-doped layer which is inserted between the p-type Mg-doped cladding layer and the p-type contact layer. | 2009-06-04 |
| 20090140274 | III-Nitride Light Emitting Device Including Porous Semiconductor Layer - A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire. | 2009-06-04 |
| 20090140275 | NANOPARTICLE COUPLED TO WAVEGUIDE - A nanoparticle is able to emit single photons. A waveguide is coupled to the nanoparticle and able to receive the single photons. A backreflector is optically coupled to the waveguide and configured to reflect the single photons toward the waveguide. | 2009-06-04 |
| 20090140276 | OPTICAL FUNCTIONAL FILM AND METHOD OF MANUFACTURING THE SAME - A light emitting element includes a light emitting layer emitting light and a refractive index composite structure layer arranged in a light path of the light output from the light emitting layer. The refractive index composite structure layer includes a structure having characteristics (1) to (4) as follows: (1) an internal configuration includes two or more types of phases differing in refractive index; (2) at least one of the two or more types of phases includes a structural unit having a size greater than or equal to 1 nm and smaller than or equal to ¼ of a wavelength within a visible light wavelength range; (3) an average refractive index is higher than 1 and lower than a refractive index of a plurality of layers between a light emitter and the refractive index composite structure layer excepting a layer including a gas phase; and (4) the internal configuration in a thickness direction includes a plurality of interfaces between the two or more types of phases in a near-field region into which light as energy can enter from an interface between the optical functional film and another layer adjacent to the refractive index composite structure layer. | 2009-06-04 |
| 20090140277 | SOLIDE-STATE LIGHT SOURCE - A solid-state light source includes a substrate, a solid-state light-emitting chip, a plurality of micro-members and a light-permeable encapsulation. The substrate has a substantially flat surface. The solid-state light-emitting chip is arranged on the substantially flat surface of the substrate and electrically connected to the substrate. The micro-members are arranged on the surface of the substrate and parallel with the solid-state light emitting chip. The light-permeable encapsulation is arranged on the surface of the substrate and covers the solid-state light-emitting chip and the micro-members. | 2009-06-04 |
| 20090140278 | Tunable LED module - The objective of the invention is to provide with a tunable LED module capable of easily selecting a wavelength and reducing particular parts, comparing to that of prior art. The tunable LED module according to the present invention is applicable to a certain short range communication. The module comprises: an LED | 2009-06-04 |
| 20090140279 | Substrate-free light emitting diode chip - A light emitting diode (LED) chip has a multilayer semiconductor structure that is at least 10 microns thick and does not require an attached growth substrate or transfer substrate for structural rigidity or support. The multilayer semiconductor structure includes a first doped layer, a second doped layer and an active region interposed between the first doped layer and the second doped layer. Optionally, the multilayer semiconductor structure includes an undoped layer. At least one of the layers of the multilayer semiconductor structure is at least 5 microns thick and is preferably deposited by hydride vapor phase epitaxy. | 2009-06-04 |
| 20090140280 | Light-emitting device - A light-emitting device comprises a substrate, an epitaxial structure formed on the substrate including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer. A trench is formed in the epitaxial structure to expose a part of side surface of the epitaxial structure and a part of surface of the first semiconductor layer, so that a first conductive structure is formed on the part of surface of the first semiconductor layer in the trench, and a second conductive structure is formed on the second semiconductor layer. The first conductive structure includes a first electrode and a first pad electrically contacted with each other. The second conductive structure includes a second electrode and a second pad electrically contacted with each other. Furthermore, the area of at least one of the first pad and the second pad is between 1.5×10 | 2009-06-04 |
| 20090140281 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND A METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor light emitting device comprising a seed layer, a first conductive semiconductor layer into which the seed layer is partially inserted, a first electrode electrically connected to the first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, and a second electrode layer under the second conductive semiconductor layer. | 2009-06-04 |
| 20090140282 | Led structure for flip-chip package and method thereof - LED structure can be packaged by using flip-chip package. An LED structure is covered by a conduction enhancing layer. A bumping area definition layer is then formed on the conduction enhancing layer to expose bumping area portions with p-pad and n-pad underneath, and a bumping pad is then formed over the bumping area portions. The bumping area definition layer and then exposed conduction enhancing layer is removed subsequently. | 2009-06-04 |
| 20090140283 | LIGHT EMITTING DEVICE - An object of the present invention is to provide a light emitting device in which variations in an emission spectrum depending on a viewing angle with respect to a side from which luminescence is extracted are decreased. A light emitting device according to the invention has a transistor, an insulating layer covering the transistor and a light emitting element provided in an opening of the insulating layer. The transistor and the light emitting element are electronically connected through a connecting portion. Additionally, the connecting portion is connected to the transistor through a contact hole penetrating the insulating layer. Note that the insulating layer may be a single layer or a multilayer in which a plurality of layers including different substances is laminated. | 2009-06-04 |
| 20090140284 | Transparent Inorganic Oxide Dispersion and Iorganic Oxide Particle-Containing Resin Composition, Composition for Sealing Light Emitting Element and Light Emitting element, Hard Coat Film and Optical Functional Film and Optical Component, and Method for Producing Inorganic Oxide Pariticle-Containing Resin - The present invention provides a transparent inorganic oxide dispersion which makes it possible to improve the refractive index and mechanical characteristics and to maintain transparency by modifying the surface of inorganic oxide particles with a surface modifier having one or more reactive functional groups; and an inorganic oxide particle-containing resin composition in which the transparent inorganic oxide dispersion and a resin are compositely integrated by the polymerization reaction, a composition for sealing a light emitting element, a light emitting element, and a method for producing an inorganic oxide particle-containing resin composition; and a hard coat film which has high transparency and makes it possible to improve a refractive index and tenacity, an optical functional film, an optical lens and an optical component. The transparent inorganic oxide dispersion of the present invention comprises inorganic oxide particles which have a surface modified with a surface modifier having one or more reactive functional groups and have a disperse particle diameter of 1 nm or more and 20 nm or less, and a disperse medium, wherein the surface modifier is one or more kinds selected from the group consisting of a silane coupling agent, a modified silicone, and a surfactant. | 2009-06-04 |
| 20090140285 | LIGHT EMITTING DEVICE HAVING FUNCTION OF HEAT-DISSIPATION AND MANUFACTURING PROCESS FOR SUCH DEVICE - A light-emitting device of a light-emitting diode (LED) and a manufacture method thereof are provided. The light-emitting device includes a post-like metal material, a printed circuit board, conductors, insulators, light-emitting diodes, wires, and an encapsulating material. The light-emitting device has through holes, in which conductors are disposed and surrounded with the insulators. One end of each conductor is connected to the printed circuit board to form a composite structure heat-dissipation substrate. The light-emitting diodes are disposed on the post-like metal material, connected to the conductors via the wires, and encapsulated by the encapsulating material. Furthermore, the light-emitting diodes, the wires, and the encapsulating material can be combined into a light-emitting unit. Moreover, red, blue, and green light-emitting diodes can be combined and the color of output light thereof can be adjusted by controlling the input signal. | 2009-06-04 |
| 20090140286 | Production Method of Group III Nitride Semiconductor Element - An object of the present invention is to provide a production method of a Group III nitride semiconductor element having an excellent electrostatic discharge property and enhanced reliability. | 2009-06-04 |
| 20090140287 | III Nitride Crystal Substrate, and Light-Emitting Device and Method of Its Manufacture - Toward making available III nitride crystal substrates advantageously employed in light-emitting devices, and light-emitting devices incorporating the substrates and methods of manufacturing the light-emitting devices, a III nitride crystal substrate has a major face whose surface area is not less than 10 cm | 2009-06-04 |
| 20090140288 | HIGH ION/IOFF SOI MOSFET USING BODY VOLTAGE CONTROL - A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET. | 2009-06-04 |
| 20090140289 | SEMICONDUCTOR DEVICE - Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region of the N-type to form a diode and a diode electrode that is formed on an upper face of the peripheral section of the first base region, thereby electrically connecting the diode electrode and a collector electrode of each of the IGBTs. When the semiconductor device is ON, current flows at the center side of the semiconductor substrate separated from the side face. When current in a reverse direction is generated when the semiconductor device is OFF, current in a reverse direction flows in the vicinity of the side face of the semiconductor substrate. | 2009-06-04 |
| 20090140290 | SEMICONDUCTOR COMPONENT INCLUDING A SHORT-CIRCUIT STRUCTURE - A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer. | 2009-06-04 |
| 20090140291 | PHOTO-DETECTOR FOR DETECTING IMAGE SIGNAL OF INFRARED LASER RADAR AND METHOD OF MANUFACTURING THE SAME - A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region. | 2009-06-04 |
| 20090140292 | INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF - A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width. | 2009-06-04 |
| 20090140293 | HETEROSTRUCTURE DEVICE AND ASSOCIATED METHOD - A heterostructure device or article includes a carrier transport layer, a back channel layer and a barrier layer. The carrier transport layer has a first surface and a second surface opposing to the first surface. The back channel layer is secured to the first surface of the carrier transport layer and the barrier layer is secured to the second surface of the carrier transport layer. Each of the carrier transport layer, the back channel layer and the barrier layer comprises an aluminum gallium nitride alloy. The article further includes a 2D electron gas at an interface of the second surface of the carrier transport layer and a surface of the barrier layer. The 2D electron gas is defined by a bandgap differential at an interface, which allows for electron mobility. A system includes a heterostructure field effect transistor that includes the article. | 2009-06-04 |
| 20090140294 | HETERO-STRUCTURED, INVERTED-T FIELD EFFECT TRANSISTOR - The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer. | 2009-06-04 |
| 20090140295 | GaN-based semiconductor device and method of manufacturing the same - A GaN-based semiconductor device includes a silicon substrate; an active layer of a GaN-based semiconductor formed on the silicon substrate; a trench formed in the active layer and extending from a top surface of the active layer to the silicon substrate; a first electrode formed on an internal wall surface of the trench so that the first electrode extends from the top surface of the active layer to the silicon substrate; a second electrode formed on the active layer so that a current flows between the first electrode and the second electrode via the active layer; and a bottom electrode formed on a bottom surface of the silicon substrate. The first electrode is formed of a metal capable of being in ohmic contact with the silicon substrate and the active layer. | 2009-06-04 |
| 20090140296 | Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal - Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices. | 2009-06-04 |
| 20090140297 | SELF-ALIGNMENT SCHEME FOR A HETEROJUNCTION BIPOLAR TRANSISTOR - Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is also included between the first self-aligned silicide layer and the nitride etch stop layer, wherein the continuous layer can comprise oxide. The HBT further includes spacers adjacent the continuous layer, wherein the spacers and the continuous layer separate the extrinsic base from an emitter contact. In addition, an emitter is provided, wherein the height of the emitter is less than or equal to the height of the extrinsic base. Moreover, a second self-aligned silicide layer is over the emitter, wherein the height of the second silicide layer is less than or equal to the height of the first silicide layer. | 2009-06-04 |
| 20090140298 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - Embodiments relate to a layout structure of a dual port SRAM and a method for forming a SRAM. According to embodiments, a structure where a plurality lines and vias are electrically connected may include first lines that may be electrically connected to a cell region of a memory cell, and a first via, a second line, a second via, a third line, a third via, and a fourth line on and/or over an upper side of the first line,. According to embodiments, the fourth lines arranged on the upper side of the cell region may be formed in a substantially straight form parallel with each other. According to embodiments, the fourth lines may be formed and positioned to prevent bit lines positioned in a cell region of the dual port SRAM from becoming electrically connected to each other. | 2009-06-04 |
| 20090140299 | MEMORY WITH HIGH DIELECTRIC CONSTANT ANTIFUSES ADAPTED FOR USE AT LOW VOLTAGE - A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and by using a diode having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective. | 2009-06-04 |
| 20090140300 | ELECTRONIC TAG CHIP - In order to extend the communication distance of an electronic tag chip, it is required to reduce power consumption of the electronic tag chip. After having formed capacitors and diodes on an SOI (Silicon on Insulator), remove a silicon substrate of the SOI. It becomes possible to reduce the capacitors and diodes of the electronic tag chip in parasitic capacitance relative to the ground, which makes it possible to reduce the power consumption of the electronic tag chip, thereby enabling the electronic tag chip to increase in communication distance thereof. | 2009-06-04 |
| 20090140301 | REDUCING CONTACT RESISTANCE IN P-TYPE FIELD EFFECT TRANSISTORS - Reducing contact resistance in p-type field effect transistors is generally described. In one example, an apparatus includes a first semiconductor substrate, a first noble metal film including palladium (Pd) coupled with the first semiconductor substrate, a second noble metal film including platinum (Pt) coupled with the first noble metal film, and a third metal film including an electrically conductive metal coupled with the second noble metal film, wherein the first, second, and third metal films form one or more contacts having reduced specific contact resistance between the first semiconductor substrate and the one or more contacts. | 2009-06-04 |
| 20090140302 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device according to one embodiment of the invention includes: forming a gate electrode on a semiconductor substrate through a gate insulating film; forming offset spacers on side surfaces of the gate electrode, respectively; etching the semiconductor substrate with a channel region below the offset spacers and the gate electrode being left by using the offset spacers as a mask; forming a first epitaxial layer made of a crystal having a lattice constant different from that of a crystal constituting the semiconductor substrate on the semiconductor substrate thus etched; etching at least a portion of the first epitaxial layer adjacent to the channel region to a predetermined depth from a surface of the first epitaxial layer toward the semiconductor substrate side; and forming a second epitaxial layer containing therein a conductivity type impurity on the first epitaxial layer thus etched. | 2009-06-04 |
| 20090140303 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same includes forming a via pattern having a matrix form in a dielectric layer. The via pattern includes a via slit provided at the center of the via pattern and a plurality of via holes provided at an outer periphery of the via pattern and surrounding the via slit. Metal plugs are formed in the via holes. | 2009-06-04 |
| 20090140304 | SOLID-STATE IMAGING DEVICE AND CAMERA - Disclosed is a solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element. | 2009-06-04 |
