| 22nd week of 2010 patent applcation highlights part 47 |
| Patent application number | Title | Published |
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| 20100136685 | METHOD FOR TRANSFERRING CELLS TO CARRIERS AND APPLICATION THEREOF - The invention provides a method for transferring cells to carriers, including: (a) providing a hydrophobic cell culture container or a cell culture container coated with a hydrophobic material on a bottom thereof; (b) adding carriers which are more hydrophilic than the hydrophobic cell culture container or hydrophobic materials and a culture medium containing cells into the hydrophobic cell culture container or the cell culture container coated with the hydrophobic material on the bottom thereof; and (c) culturing the cells, wherein the cells attach to the carriers and grow. | 2010-06-03 |
| 20100136686 | APPARATUS AND METHOD FOR CULTURING AND PRESERVING TISSUE CONSTRUCTS - A disclosure is made of various apparatus and methods for culturing and preserving cells and tissue in ways that minimize contamination potential, direct cells to reside in desired areas, allow uniform cell distribution during seeding, provide optimal growth conditions by controlling the amount of medium residing in proximity of cells, allow desired compounds and molecules to reside in proximity of the cells, allow co-culture, provide for efficient scale up, allow a desired shape of tissue to be created while retaining a closed system, and allow cryopreservation and reconstitution of cell and tissue while retaining a closed system. The apparatus and methods can be combined to prevent the need to remove the tissue from the enclosure at any point during the sterilization, seeding, culturing, cryopreservation, shipping, or restoration process. Also disclosed is an apparatus and method of pipette interface with a container in a manner that blocks contaminants from entering the container. | 2010-06-03 |
| 20100136687 | Methods for Enhanced Propagation of Cells - The present invention relates generally to methods for the isolation and propagation of cells. For example, embodiments of the present invention relate to isolation and propagation methods for the manufacture of a large number of cells for use, for example, in biotherapeutic devices, such as devices for renal replacement therapy for the treatment of acute renal failure (ARF), acute tubular necrosis (ATN), multi-organ failure (MOF), sepsis, cardiorenal syndrome (CRS) and end-stage renal disease (ESRD). | 2010-06-03 |
| 20100136688 | METHOD OF DIFFERENTIATING MAMMALIAN PROGENITOR CELLS INTO INSULIN PRODUCING PANCREATIC ISLET CELLS - The invention relates to methods for differentiating progenitor cells into insulin producing pancreatic islet cells and compositions and methods for using such cells. | 2010-06-03 |
| 20100136689 | METHOD FOR DECOMPOSING BIOLOGICAL TISSUE - A biological tissue is decomposed in a short time, and cells are obtained at a high yield without interfering with the health of the cells obtained through the decomposition. There is provided a method for decomposing biological tissue which decomposes a biological tissue under an action of a digestive enzyme, wherein a digestive juice containing the digestive enzyme is additionally supplied with the digestive enzyme either continuously or stepwisely over a predetermined time within a period from start of the decomposition until termination of the decomposition while the biological tissue is being immersed in the digestive juice. | 2010-06-03 |
| 20100136690 | SLICING DEVICE - The invention relates to a biological microglia comprising at least two pores having a size adopted to allow cells, cell aggregates, tissue or other biological material to pass through said pores, and one or several slicing beams separating said pores from each other, wherein biological material is split/sliced/cleaved into at least two parts when passing said microgrid, a slicing device, an apparatus comprising said slicing device as well as the use of said microgrid, slicing device and apparatus. | 2010-06-03 |
| 20100136691 | PROCESS FOR THE PRODUCTION OF A STRUCTURE COMPRISING CRYSTALLINE CELLULOSE - In a process for the production of a structure comprising crystalline cellulose ( | 2010-06-03 |
| 20100136692 | PLASMIDS AND PHAGES FOR HOMOLOGOUS RECOMBINATION AND METHODS OF USE - Lambda phages that can be used to introduce recombineering functions into host cells are disclosed. Also disclosed are plasmids that can be used to confer recombineering functions to a variety of strains of | 2010-06-03 |
| 20100136693 | Mutants of Deoxycytidine Kinase Having Extended Enzymatic Activity - The invention relates to a method for artificial in vivo evolution of proteins, said method making it possible to bring about the evolution of a protein X by complementation of a relative protein Y, X and Y both belonging to the same class of enzyme commission (EC) nomenclature or belonging to related classes. The mutants D133E and R104Q of desoxycytidine kinase (DCK) were obtained; both of said mutations result in acquisition of thymidine kinase activity by DCK. | 2010-06-03 |
| 20100136694 | Cone-Shaped Adapter for a Gene Gun - A cone-shaped adapter for attachment to a muzzle of a gene gun is generally provided. The cone-shaped adapter comprises sidewalls that taper from a base plane at one end and to an apex aperture at an opposite end and a fitting. The sidewalls form a base angle of from about 85° to about 45° with the base plane. The fitting is attached to the sidewalls at the base plane and is configured to connect the cone-shaped adapter to the muzzle of the gene gun. Methods of using the cone-shaped adapter with a gene gun are also provided. | 2010-06-03 |
| 20100136695 | DOUBLE-STRANDED OLIGONUCLEOTIDES - Antisense sequences, including duplex RNAi compositions, which possess improved properties over those taught in the prior art are disclosed. The invention provides optimized antisense oligomer compositions and method for making and using the both in in vitro systems and therapeutically. The invention also provides methods of making and using the improved antisense oligomer compositions. | 2010-06-03 |
| 20100136696 | APPARATUS AND METHOD FOR THE ENHANCEMENT OF CONTAMINANT DETECTION - An apparatus and method for detecting contaminants in a food product having an irregular shape is described. The apparatus comprises a contaminant detection device constructed and arranged to detect contaminants in a food product when the food product enters a zone of operation relative to the contaminant detection device. A conveyor belt is electrically coupled to the contaminant detector. The contour filler is operably connected to the conveyor bell and contaminant detector, and positions the food product within the zone of operation. The contour filler may retain the food product and fill the cross sectional area of the zone of operation to enhance contaminant detection. The contour filler may rotate the food product relative to the contaminant detector. | 2010-06-03 |
| 20100136697 | APPARATUS AND METHOD OF MEASURING CONCENTRATION OF FUEL - An apparatus of measuring concentration of fuel including a catalyst layer, a diffusion layer, a fuel chamber, a reactive gas chamber, and a sensor is provided. The diffusion layer is connected to the catalyst layer. The fuel chamber is suitable for containing a fuel. The diffusion layer is between the fuel chamber and the catalyst layer. The reactive gas chamber is suitable for containing a reactive gas. The catalyst layer is between the reactive gas chamber and the diffusion layer. The fuel diffuses to the catalyst layer via the diffusion layer such that a combustion reaction of the fuel and the reactive gas is conducted in the catalyst layer to consume the reactive gas and generate a gaseous product. The sensor is disposed on the reactive gas chamber for measuring the concentration of the reactive gas or the concentration of the gaseous product in the reactive gas chamber. | 2010-06-03 |
| 20100136698 | SAMPLE PLATE - A sample plate for a portable analysis apparatus for analysis of a solid precipitated from a fluid sample, which sample plate comprises a sample inlet, a precipitation zone, a filter and an analysis zone, the sample plate being adapted to allow: (i) a fluid sample to be fed through the sample inlet into the precipitation zone; (ii) a precipitant to be fed to the precipitation zone; (iii) conditions within the precipitation zone to be maintained such that precipitation occurs when the fluid sample and precipitant mix to form a suspension; (iv) separation of the solid in the suspension by the filter; (v) addition of a solvent to the filter to dissolve the solid and form a solution; and (vi) analysis of the solution in the analysis zone. | 2010-06-03 |
| 20100136699 | SAMPLE PLATE - A sample plate, portable analysis apparatus and method of analysing sulphur and/or nitrogen compounds in a sample fluid, the method comprising feeding a sample fluid to a sample plate having a sample inlet, a reaction zone, an analysis zone, and at least one separation zone, the sample plate being adapted to allow; (a) a sample fluid to be fed to the sample plate through the inlet to the reaction zone or optionally to a separation zone, which separation zone separates the sample fluid into two or more fractions at least one of which is fed to the reaction zone; (b) a reactant to be fed to the reaction zone; (c) the reaction zone to be maintained under conditions that enable reaction to occur between the reactant and the sample fluid or fraction thereof to produce a product fluid; and (d) transfer of the product fluid to the analysis zone or optionally to a separation zone in which the product fluid is separated into two or more fractions, at least one of which is transferred to the analysis zone. | 2010-06-03 |
| 20100136700 | METABOLIC SYNDROME AND HPA AXIS BIOMARKERS FOR MAJOR DEPRESSIVE DISORDER - Materials and methods for using combinations of metabolic syndrome and HPA axis biomarkers for monitoring major depressive disorder. | 2010-06-03 |
| 20100136701 | Device including a dissolvable structure for flow control - A diagnostic device is provided that includes a plurality of retainment regions, with the retainment regions that are separated by at least one dissolvable barrier. The retainment regions can be interconnected through at least one fluid processing passageway. A retainment region can include a container such as a retainment region, well, chamber, or other receptacle, or a retainment region such as a surface on which the material is retained. The retainment regions can include a reaction retainment region, one or more reagent retainment regions, each containing unreacted reagents, and a sample retainment region. A pressure-actuated valve can be positioned in each fluid processing passageway interconnecting the one or more reagent retainment regions with the respective intermediate retainment regions interposed between each of the one or more reagent retainment regions and the reaction retainment region. The dissolvable barrier can be a fluid flow modulator in the at least one fluid processing passageway. | 2010-06-03 |
| 20100136702 | METHODS AND COMPOSITIONS FOR DETECTION AND ANALYSIS OF POLYNUCLEOTIDES USING LIGHT HARVESTING MULTICHROMOPHORES - Methods, compositions and articles of manufacture for assaying a sample for a target polynucleotide are provided. A sample suspected of containing the target polynucleotide is contacted with a polycationic multichromophore and a sensor polynucleotide complementary to the target polynucleotide. The sensor polynucleotide comprises a signaling chromophore to receive energy from the excited multichromophore and increase emission in the presence of the target polynucleotide. The methods can be used in multiplex form. Kits comprising reagents for performing such methods are also provided. | 2010-06-03 |
| 20100136703 | Thyroxine-Containing Compound Analysis Methods - The present teachings provide methods for analyzing one or more thyroxine compounds in one or more samples using isobaric labels and parent-daughter ion transition monitoring (PDITM). In various embodiments, the methods comprise the steps of: (a) labeling one or more thyroxine compounds with different isobaric tags from a set of isobaric tags, each isobaric tag comprising a reporter ion portion; (b) combining at least a portion of each of the isobarically labeled thyroxine compounds to produce a combined sample; (c) subjecting at least a portion of the combined sample to PDITM; (d) measuring the ion signal of one or more of the transmitted reporter ions; and (e) determining the concentration of one or more of the isobarically labeled thyroxine compounds based at least on a comparison of the measured ion signal of the corresponding reporter ion to one or more measured ion signals of a standard compound. | 2010-06-03 |
| 20100136704 | Process for Detecting Gaseous Halogenated Compounds - Process for detecting a gaseous compound of BX | 2010-06-03 |
| 20100136705 | METHOD FOR MEASURING CONCENTRATION OF PEROXYCARBOXYLIC ACID AND APPARATUS THEREFOR - A method for measuring only a concentration of a peroxycarboxylic acid in an equilibrium mixture containing peroxycarboxylic acid and hydrogen peroxide, comprising the following steps a) and b); a) adding potassium iodide to the equilibrium mixture to cause the generation of iodine and providing the resulting mixture as a measurement sample; and b) measuring the amount of light that goes through the measurement sample to determine only the concentration of a peroxycarboxylic acid. | 2010-06-03 |
| 20100136706 | MOLECULE-RESPONSIVE GEL PARTICLES, METHOD OF PRODUCTION OF THE SAME, AND USE THEREOF - The invention provides molecule-responsive gel particles which change in size in response to specific molecules and a method of production of the same. A polymer gel particle with a crosslinked structure has fixed thereto a plurality of clathrate compound-forming host molecules. two or more of the plurality of host molecules clathrate different atomic groups in a target molecule so that the two or more host molecules and the target molecule can form a crosslink in the molecule-responsive gel particle. | 2010-06-03 |
| 20100136707 | METHODS FOR MONITORING PATHOLOGICAL CONDITIONS IN A FEMALE SUBJECT - A method for identifying physiological conditions associated with the pH or the buffer capacities of biological fluid secreted from a person, by providing a secretion-monitoring article of a body that includes an absorbent material for absorbing a biological fluid secreted from a person and an indicator system having a hydrophobic chemical composition that includes an indicator agent and an ion-balance reagent, at specific relative amounts. Optionally, a competitive agent for establishing a pre-set threshold of an analyte of interest in a tested bodily fluid, is added to the indicator system, wherein the indicator reagent being charged oppositely to the analyte of interest and the competitive reagent having the same charge as the indicator reagent. | 2010-06-03 |
| 20100136708 | ANALYSIS DEVICE AND METHOD FOR TESTING THE CATALYTIC ACTIVITY OF SURFACES - In an analysis device and a method for testing the catalytic activity of surfaces, a reaction cell is provided that has a recess for a sample that is provided with the catalytic surface. In the analysis device, an optical test of the reaction occurring in the reaction cell may occur. The reaction cell has a closed channel that is part of a fluid circuit. The reaction cell may be advantageously designed in a very space-saving manner in its scale, such that a portable use of the analysis cell is possible as well. Here, a simple measurement process of the absorption capacity of the sample fluid located in the reaction cell is conducted. To this end, a laser diode is provided, the measurement stream of which is directed into the reaction cell and reflected multiple times. The light intensity is measured by means of a photodetector. | 2010-06-03 |
| 20100136709 | RECEPTACLE AND METHOD FOR THE DETECTION OF FLUORESCENCE - The invention relates to a liquid receptacle comprising a bottom and sidewalls for holding a liquid. The bottom encompasses a flat sensor surface that is in contact with the liquid when the receptacle is filled, a light-incident area that is located below the sensor surface and is suitable for focusing light onto the sensor surface, a light emergence area, and a cover area that is suitable for reflecting light from the sensor surface such that the light can emerge through the light emergence area. The invention further relates to a method for qualitatively or quantitatively determining an analyte in such a liquid receptacle. In said method, excitation light is focused onto the sensor surface via the light-incident area such that a luminescent marker which characterizes the analyte is excited, and the generated luminescence is then reflected onto the cover surface and is detected after emerging through the light emergence area. The invention also relates to an analysis device comprising a holder for a liquid receptacle, a light source that is disposed such that the light thereof can be focused onto the sensor surface of the liquid receptacle via the light-incident area, and a detector which is arranged in such a way as to be able to detect the light emerging from the light emergence area of the liquid receptacle. | 2010-06-03 |
| 20100136710 | RNA processing protein complexes and uses thereof - The invention provides human protein complexes with endonuclease activity. In particular, the invention provides human protein complexes with tRNA splicing endonuclease activity and/or 3′ end pre-mRNA endonuclease activity. The invention also provides a splice variant of human Sen2, namely human Sen2deltaEx8, and human protein complexes comprising human Sen2deltaEx8. The human Sen2deltaEx8 complexes have pre-tRNA cleavage activity and/or 3′ end pre-mRNA endonuclease activity. The invention also provides human protein complexes with pre-ribosomal RNA cleavage activity. The invention also provides antibodies that immunospecifically bind to a complex described herein or a component thereof, and methods of diagnosing, preventing, treating, managing or ameliorating a disorder utilizing such antibodies. The present invention also provides methods utilizing the complexes described herein, inter alia, in screening, diagnosis, and therapy. The invention further provides methods of preparing and purifying the complexes. The present invention further provides methods of identifying a compound that modulates the expression of a component of a complex described herein, the formation of a complex described herein or the activity of a complex described herein, and methods of preventing, treating, managing or ameliorating a disorder, such as a proliferative disorder, or a symptom thereof utilizing a compound identified in accordance with the methods. | 2010-06-03 |
| 20100136711 | IMMUNOASSAY METHOD FOR PRO-GASTRIN-RELEASING PEPTIDE - To provide a more convenient and more accurate method of assaying ProGRP by improving the stability of ProGRP which is known to be unstable in a biological sample. | 2010-06-03 |
| 20100136712 | COMPOUND AND METHOD FOR PRODUCING THE SAME - The invention provides a Ti doped lead barium zirconate dielectric material which could be applied to high frequency devices. The material comprises a compound with the chemical formula (Pb | 2010-06-03 |
| 20100136713 | Hafnium doped cap and free layer for mram device - A high performance MTJ, and a process for manufacturing it, are described. A capping layer of NiFeHf is used to getter oxygen out of the free layer, thereby increasing the sharpness of the free layer-tunneling layer interface. The free layer comprises two NiFe layers whose magnetostriction constants are of opposite sign, thereby largely canceling one another. | 2010-06-03 |
| 20100136714 | Device for processing substrate and method of manufacturing semiconductor device - Provided is a substrate processing apparatus and a method of manufacturing a semiconductor device, which are hard to cause a defect in processing a substrate owing to that a pressure inside a process chamber is not kept constant, and which enable a better processing of a substrate. The substrate processing apparatus has: a process chamber for processing a substrate; a reactive gas-supplying module for supplying a reactive gas into the process chamber; a reactive gas-supplying line for supplying the reactive gas from the reactive gas-supplying module into the process chamber; an exhaust line for exhausting an inside of the process chamber; a pump provided in the exhaust line for vacuumizing the inside of the process chamber; a pressure-adjusting valve provided in the exhaust line for adjusting a pressure in the process chamber; a first pressure-measuring instrument for measuring an inside pressure of the process chamber; a second pressure-measuring instrument for measuring a differential pressure between the inside pressure of the process chamber and an outside pressure thereof; and a controller which controls the pressure-adjusting valve based on a value of the inside pressure of the process chamber measured by the first pressure-measuring instrument so as to keep the inside pressure of the process chamber constant, and controls the reactive gas-supplying module based on a value of the differential pressure measured by the second pressure-measuring instrument so as to allow supply of the reactive gas into the process chamber in a case of the inside pressure of the process chamber being smaller than the outside pressure thereof, and so as to preclude supply of the reactive gas into the process chamber in a case of the inside pressure of the process chamber being larger than the outside pressure thereof when processing the substrate. | 2010-06-03 |
| 20100136715 | Screening of Silicon Wafers Used in Photovoltaics - A method for screening silicon-based wafers used in the photovoltaic industry is provided herewith. | 2010-06-03 |
| 20100136716 | Manufacturing apparatus for semiconductor device and manufacturing method for semiconductor device - A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solution, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated. | 2010-06-03 |
| 20100136717 | APPARATUS AND METHOD TO INSPECT DEFECT OF SEMICONDUCTOR DEVICE - An apparatus and method to inspect a defect of a semiconductor device. The amount of secondary electrons generated due to a scanning electron microscope (SEM) may depend on the topology of a pattern of a semiconductor substrate. The amount of secondary electrons emitted from a recess of an under layer is far smaller than that of secondary electrons emitted from a projection of a top layer. Since the recess is darker than the projection, a ratio of a value of a secondary electron signal of the under layer to a value of a secondary electron signal of the top layer may be increased in order to improve a pattern image used to inspect a defect in the under layer. To do this, a plurality of conditions under which electron beams (e-beams) are irradiated may be set, at least two may be selected out of the set conditions, and the pattern may be scanned under the selected conditions. Thus, secondary electron signals may be generated according to the respective conditions and converted into image data so that various pattern images may be displayed on a monitor. Scan information on the pattern images may be automatically stored in a computer storage along with positional information on a predetermined portion of the semiconductor substrate. When calculation conditions are input to a computer, each of scan information on the pattern images may be calculated to generate a new integrated pattern image. | 2010-06-03 |
| 20100136718 | METHODS AND APPARATUS FOR ALIGNING A SET OF PATTERNS ON A SILICON SUBSTRATE - A method of aligning a set of patterns on a substrate, the substrate including a substrate surface, is disclosed. The method includes depositing a set of silicon nanoparticles on the substrate surface, the set of nanoparticles including a set of ligand molecules including a set of carbon atoms, wherein a first set of regions is formed where the silicon nanoparticles are deposited and the remaining portions of the substrate surface define a second set of regions. The method also includes densifying the set of silicon nanoparticles into a thin film wherein a set of silicon-organic zones are formed on the substrate surface, wherein the first set of regions has a first reflectivity value and the second set of regions has a second reflectivity value. The method further includes illuminating the substrate surface with an illumination source, wherein the ratio of the second reflectivity value to the first reflectivity value is greater than about 1.1. | 2010-06-03 |
| 20100136719 | THIN FILM TRANSISTOR SUBSTRATE HAVING ELECTRODE LAYERS THAT ARE FORMED ON INSULATING LAYER TO COVER COMMON VOLTAGE LINE AND GROUNDING LINE - According to an embodiment, there is provided a fabricating method for a thin film transistor substrate divided into a display area displaying images and a non-display area beside the display area, the fabricating method comprising: forming a gate wire in the display area, a common voltage line for a MPS (mass production system) test in the non-display area, and a grounding line for the MPS test in the non-display area with same material at the same time; forming a gate insulating layer covering the gate wire and a first insulating layer covering the common voltage line for the MPS test and the grounding line for the MPS test with same material at the same time; forming a data wire crossing the gate wire and defining a pixel area in the display area; and forming a pixel electrode in the pixel area and an electrode layer on the first insulating layer corresponding to the common voltage line for the MPS test and the grounding line for the MPS test with same material at the same time. | 2010-06-03 |
| 20100136720 | MANUFACTURING METHOD OF PIXEL STRUCTURE - A method of manufacturing the pixel structure is provided. The method includes forming a gate, a scan line connected to the gate, and at least one auxiliary pattern on a substrate. An insulating layer, a semiconductor layer, an ohmic contact layer, and a photoresist layer are formed in sequence. Afterwards, a single exposure and development is performed on the photoresist layer to form a first portion and a second portion. Next, the ohmic contact layer and the semiconductor layer which are not covered by the photoresist layer are removed to expose a part of the insulating layer. Next, the second portion of the photoresist layer is removed. Subsequently, a part of the thickness of the semiconductor layer not covered by the first portion is removed and the exposed insulating layer is removed, so as to faun a channel layer and an insulating layer. | 2010-06-03 |
| 20100136721 | NITRIDE-BASED WHITE LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device includes an n-type cladding layer. a p-type cladding layer. an active layer interposed between the n-type cladding layer and the p-type cladding layer and an ohmic contact layer contacting the p-type cladding layer or the n-type cladding layer. The ohmic contact layer includes a first film that includes a transparent conductive zinc oxide doped with a rare earth metal and including a one-dimensional nano structure. The one-dimensional nano structure is one of a nano-column, a nano rod and a nano wire. | 2010-06-03 |
| 20100136722 | ORGANIC ELECTRO LUMINESCENCE DEVICE AND FABRICATION METHOD THEREOF - An organic electro luminescence device and a fabrication method thereof are provided. An array element is formed on a first substrate and an electro luminescent diode is formed on a second substrate. The array element and the electro luminescent diode are electrically connected together by a spacer. A separator divides a sub pixel into a first region and a second region. In the electro luminescent diode, an anode electrode is formed over the first and second regions. An organic electro luminescent layer and a cathode electrode are formed on the anode electrode of one of the first and second regions. | 2010-06-03 |
| 20100136723 | DUAL PANEL-TYPE ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - A dual panel-type organic electroluminescent display device includes a first substrate on which gate and data lines cross each other to define sub-pixels. Array elements are disposed at the sub-pixels on the first substrate. A first electrode is disposed on substantially the entire surface of a second substrate opposing the first substrate. An insulating pattern is disposed on the first electrode, an organic electroluminescent layer is disposed on the first electrode, and a second electrode is disposed on the organic electroluminescent layer at each sub-pixel. A connection pattern connects the array element and the second electrode at each sub-pixel. The connection pattern contacts the second electrode under the insulating pattern. | 2010-06-03 |
| 20100136724 | METHOD FOR FABRICATING A NANOSTRUCTURED SUBSTRATE FOR OLED AND METHOD FOR FABRICATING AN OLED - Method for fabricating a substrate comprising a nanostructured surface for an organic light emitting diode OLED, in which a layer of an organic resin or of a mineral material having a first nanostructuration is prepared by nano-imprint; the organic resin or mineral material is heated to a temperature equal to or higher than its glass transition temperature Tg or its melting point, and the organic resin or the mineral material is maintained at this temperature for a time t | 2010-06-03 |
| 20100136725 | THERMAL MANAGEMENT FOR LED - A method and system for removing heat from an LED facilitates the fabrication of LEDs having enhanced brightness. A thermally conductive interposer can be attached to the top of the LED. Heat can flow through the top of the LED and into the interposer. The interposer can carry the heat away from the LED. Light can exit the LED though an at least partially transparent substrate of the LED. By removing heat from an LED, the use of more current through the LED is facilitated, thus resulting in a brighter LED. | 2010-06-03 |
| 20100136726 | LED ARRAY - An illuminator ( | 2010-06-03 |
| 20100136727 | PRODUCTION METHOD FOR NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - The present invention provides a production method for a nitride semiconductor light emitting device, which warps less after removing the substrate, and which can emit light from the side thereof; specifically, the present invention provides a production method for a nitride semiconductor light emitting device comprising: forming stacked layers by stacking at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a substrate in this order; forming grooves which divide the stacked layers so as to correspond to nitride semiconductor light emitting devices to be produced; filling the grooves with a sacrifice layer; and forming a plate layer on the p-type semiconductor layer and the sacrifice layer by plating. | 2010-06-03 |
| 20100136728 | LIGHT-EMITTING DIODE CHIP WITH HIGH LIGHT EXTRACTION AND METHOD FOR MANUFACTURING THE SAME - This invention provides a light-emitting diode chip with high light extraction, which includes a substrate, an epitaxial-layer structure for generating light by electric-optical effect, a transparent reflective layer sandwiched between the substrate and the epitaxial-layer structure, and a pair of electrodes for providing power supply to the epitaxial-layer structure. A bottom surface and top surface of the epitaxial-layer structure are roughened to have a roughness not less than 100 nm root mean square (rms). The light generated by the epitaxial-layer structure is hence effectively extracted out. A transparent reflective layer not more than 5 μm rms is formed as an interface between the substrate and the epitaxial-layer structure. The light toward the substrate is more effectively reflected upward. The light extraction and brightness are thus enhanced. Methods for manufacturing the light-emitting diode chip of the present invention are also provided. | 2010-06-03 |
| 20100136729 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A liquid crystal display device includes a plurality of gate lines and data lines on a first substrate defining a plurality of pixel regions, a thin film transistor within the pixel regions, a pixel electrode within the pixel regions, and at least one TiOx layer provided with the thin film transistor. | 2010-06-03 |
| 20100136730 | THIN FILM DEVICES FOR FLAT PANEL DISPLAYS AND METHODS FOR FORMING THE SAME - Methods of forming thin film devices with different electrical characteristics on a substrate comprising a driver circuit region and a pixel region. A first and a second polysilicon pattern layers are formed on the driving circuit region and the pixel region of the substrate, respectively. A first ion implantation is performed on the second polysilicon pattern layer using a masking layer covering the first polysilicon pattern layer as an implant mask, such that the first polysilicon pattern layer has an impurity concentration different from the second polysilicon pattern layer. After removal of the masking layer, a gate dielectric layer and a gate are successively formed on each of the first and second polysilicon pattern layers and a source/drain region is subsequently formed in each of the first and second polysilicon pattern layers to define a channel region therein. | 2010-06-03 |
| 20100136731 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND FABRICATION METHOD THEREOF - A method of fabricating a nitride semiconductor light-emitting device providing a nitride semiconductor light-emitting device with a GaN layer, bringing the nitride semiconductor light-emitting device into contact with hydrogen separation metal, vibrating the nitride semiconductor light-emitting device and the hydrogen separation metal, removing hydrogen from the GaN layer of the nitride semiconductor light-emitting device and separating the hydrogen separation metal from the nitride semiconductor light-emitting device. | 2010-06-03 |
| 20100136732 | LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF - A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1-x)N and a range of x is given by 0| 2010-06-03 | |
| 20100136733 | SILICIDE STRAPPING IN IMAGER TRANSFER GATE DEVICE - A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage. | 2010-06-03 |
| 20100136734 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are methods of manufacturing a semiconductor device. The method of manufacturing one semiconductor device includes forming a transistor structure on a semiconductor substrate, forming a metal interconnection layer on the transistor structure, forming a protective layer on the metal interconnection layer, and implanting hydrogen ions into the semiconductor substrate having the protective layer by using a hydrogen ion implanter. Hydrogen ions are stably and effectively implanted into a selected region by using a hydrogen ion implanter in the manufacturing process of the semiconductor device, thereby facilitating the manufacturing process and improving the performance of the semiconductor device. | 2010-06-03 |
| 20100136735 | METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A method for manufacturing a photoelectric conversion device typified by a solar cell, having an excellent photoelectric conversion characteristic with a silicon semiconductor material effectively utilized. The point is that the surface of a single crystal semiconductor layer bonded to a supporting substrate is irradiated with a pulsed laser beam to become rough. The single crystal semiconductor layer is irradiated with the pulsed laser beam in an atmosphere containing an inert gas and oxygen so that the surface thereof is made rough. With the roughness of surface of the single crystal semiconductor layer, light reflection is suppressed so that incident light can be trapped. Accordingly, even when the thickness of the single crystal semiconductor layer is equal to or greater than 0.1 μm and equal to or less than 10 μm, path length of incident light is substantially increased so that the amount of light absorption can be increased. | 2010-06-03 |
| 20100136736 | METHOD FOR MANUFACTURING THIN FILM TYPE SOLAR CELL - A method for manufacturing a thin film type solar cell is disclosed, which is capable of reducing degradation of solar cell by decreasing the number of dangling bonding sites or SiH | 2010-06-03 |
| 20100136737 | METHOD OF MAKING CMOS IMAGE SENSOR-HYBRID SILICIDE - Techniques for manufacturing a CMOS image sensor are provided. A semiconductor substrate is provided, and at least one isolation region can be formed between a periphery region of the substrate and a photo-sensing region of the substrate. A first well in the periphery region and a second well in the photo-sensing region of the substrate are formed. A third well associated with a photodiode is also formed. A gate oxide layer, polysilicon layer, and first metal layer are respectively deposited. The polysilicon layer and first metal layer are etched to form an least one gate in the photo-sensing region and at least one gate in the periphery region. At least two doped regions in the first well are formed, as well as a doped region in the second well. A silicide block layer is deposited over the photo-sensing region of the substrate. A second metal layer is deposited at least over the periphery region after deposition of the silicide block. The substrate is exposed to a thermal environment to form silicide. The second metal layer is removed by etching. | 2010-06-03 |
| 20100136738 | SOLID-STATE IMAGING DEVICE, SOLID-STATE IMAGING APPARATUS AND METHODS FOR MANUFACTURING THE SAME - To arrange diffusion-inhibitory films | 2010-06-03 |
| 20100136739 | Embossing Printing for Fabrication of Organic Field Effect Transistors and its Integrated Devices - A method of fabricating an organic field effect transistor (OFET) includes forming at least one OFET structure by ultraviolet (UV) transfer embossing printing, where, in an example embodiment, the method includes providing ink material on at least part of a patterned surface of a mold, where the mold | 2010-06-03 |
| 20100136740 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to form an organic transistor including an organic semiconductor having high crystallinity without loosing an interface between an organic semiconductor of a channel where carriers are spread out and a gate insulating layer and deteriorating a yield. A semiconductor device according to the present invention has a stacked structure of organic semiconductor layers, and at least the upper organic semiconductor layer is in a polycrystalline or a single crystalline state and the lower organic semiconductor layer is made of a material serving as a channel. Carrier mobility can be increased owing to the upper organic semiconductor layer having high crystallinity; thus, insufficient contact due to the upper organic semiconductor layer can be compensated by the lower organic semiconductor layer. | 2010-06-03 |
| 20100136741 | BRANCHED PHENYLENE-TERMINATED THIOPHENE OLIGOMERS - A composition comprising a plurality of molecules. Each of the molecules has a core comprising at least one aromatic ring and at least three pendant arms chemically bonded to the core. The pendant arms comprise a phenylene-terminated thiophene oligomer. | 2010-06-03 |
| 20100136742 | PHASE CHANGE MEMORY WITH OVONIC THRESHOLD SWITCH - A phase change memory includes a memory element and a selection element. The memory element is embedded in a dielectric and includes a resistive element having at least one sublithographic dimension and a storage region in contact with the resistive element. The selection element includes a chalcogenic material embedded in a dielectric. The chalcogenic material and the storage region are part of a stack having a common etched edge. | 2010-06-03 |
| 20100136743 | Semiconductor Device and Manufacturing Method Thereof - An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region. | 2010-06-03 |
| 20100136744 | METHOD FOR MAKING SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING DIE AND INVERTED LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE - A method for making a multipackage module that has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. | 2010-06-03 |
| 20100136745 | POP PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a package-on-package (POP) package is disclosed. The method includes preparing a first semiconductor package including a first substrate having external contact electrodes and a first semiconductor chip mounted on the first substrate, and preparing a second semiconductor package including a second substrate having external contact electrodes and a second semiconductor chip mounted on the second substrate. The method further includes forming lead lines in the second semiconductor package, the lead lines being electrically connected to the external contact electrodes of the second substrate, and stacking the second semiconductor package on the first semiconductor package and electrically connecting the external contact electrodes of the first substrate to the external contact electrodes of the second substrate using the lead lines. | 2010-06-03 |
| 20100136746 | METHOD FOR PRODUCING A SET OF CHIPS MECHANICALLY INTERCONNECTED BY MEANS OF A FLEXIBLE CONNECTION - The method relates to production of a set of chips mechanically interconnected by means of a flexible connection. The chips, integrated on a substrate, each comprise a receiving area. The chips of the set are connected in series in the receiving areas by a connecting element. The chips are then released, the connecting element forming a flexible connection. | 2010-06-03 |
| 20100136747 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Provided is a method for manufacturing a semiconductor package. The method includes providing a first substrate having a first top surface on which a chip pad is formed and a first bottom surface opposite to the first top surface. The method additionally includes removing a portion of the first top surface to form a sawing groove, and forming a conductive pattern on the first substrate. Also, the method includes removing a portion of the first bottom surface to divide the first substrate into a plurality of semiconductor chips having a redistribution pattern formed of a portion of the conductive pattern, and mounting a selected one of the plurality of semiconductor chips on a second substrate having a second top surface on which a lead is formed. The method further includes forming an interconnector electrically connecting the lead to the redistribution pattern. | 2010-06-03 |
| 20100136748 | Flexible diode package and method of manufacturing - A single step packaging process that both melts a solder and also cures an adhesive about a microelectronic circuit. The process finds technical advantages by simplifying packaging of a die that may be coupled to a planar flexible lead, which leads to a lower production cost and quicker manufacturing time. The planar flexible lead may be adapted to bend and flex during mechanical stress and during extreme temperature cycling, and allow direct mounting of the device to a member by easily welding or soldering. The invention may comprise a flexible solar cell diode that can be closely positioned on solar panels at an extremely low cost. | 2010-06-03 |
| 20100136749 | MICROARRAY PACKAGE WITH PLATED CONTACT PEDESTALS - A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 μm to about 35 μm. | 2010-06-03 |
| 20100136750 | Etched Leadframe Structure - A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess. | 2010-06-03 |
| 20100136751 | METHOD FOR MAKING A P-I-N DIODE CRYSTALLIZED ADJACENT TO A SILICIDE IN SERIES WITH A DIELECTRIC ANTIFUSE - A method is described for monolithically forming a first memory level above a substrate, the method including: (a) forming a plurality of first substantially parallel, substantially coplanar conductors above the substrate, the first conductors extending in a first direction; (b) forming a plurality of vertically oriented contiguous p-i-n diodes above the first conductors, the contiguous p-in diode comprising semiconductor material crystallized in contact with a silicide, silicide-germanide, or germanide layer; (c) forming a plurality of second substantially parallel, substantially coplanar conductors, the second conductors above the contiguous p-i-n diodes, the second conductors extending in a second direction different from the first direction, each contiguous p-i-n diode vertically disposed between one of the first conductors and one of the second conductors; (d) and forming a plurality of dielectric rupture antifuses, each dielectric rupture antifuse disposed between one of the contiguous p-i-n diodes and one of the first conductors or between one of the contiguous p-i-n diodes and one of the second conductors, wherein the dielectric rupture antifuses comprise dielectric material, the dielectric material having a dielectric constant greater than about 8. Other aspects are provided. | 2010-06-03 |
| 20100136752 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a Si substrate, an insulating film formed on one part of the Si substrate, a bulk Si region grown on other part of the Si substrate other than the insulating film, Si1-xGex (0| 2010-06-03 | |
| 20100136753 | FABRICATING METHOD OF THIN FILM TRANSISTOR - A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer. | 2010-06-03 |
| 20100136754 | THIN FILM TRANSISTOR AND METHOD OF FABRICATING THIN FILM TRANSISTOR SUBSTRATE - Provided are a thin film transistor (TFT) capable of increasing ON current and decreasing OFF current values, a TFT substrate having the polysilicon TFT, a method of fabricating the polysilicon TFT, and a method of fabricating a TFT substrate having the polysilicon TFT. The polysilicon TFT substrate includes a gate line and a data line defining a pixel region, a pixel electrode formed in the pixel region, and a TFT including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a polysilicon active layer forming a channel between the source and drain electrodes. The polysilicon active layer includes a channel region on which the gate electrode is superposed, source and drain regions connected to the source and drain electrode, respectively, and at least two lightly doped drain (LDD) regions y formed between the source region and the channel region and between the drain region and the channel region. The LDD regions have an impurity concentration different from each other. | 2010-06-03 |
| 20100136755 | Method for fabricating thin film transistor - A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode; sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound; and forming source and drain electrodes at both sides of the semiconductor layer. | 2010-06-03 |
| 20100136756 | Thin film transistor, method for fabricating the same and display device - A method for fabricating a TFT on a substrate includes forming a gate electrode; forming a semiconductor layer insulated from the gate electrode and partially overlapped with the gate electrode; forming a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a sol-gel compound; and forming source and drain electrodes at both sides of the semiconductor layer. | 2010-06-03 |
| 20100136757 | METHOD FOR ALIGNING ELONGATED NANOSTRUCTURES - A method of depositing elongated nanostructures that allows accurate positioning and orientation is described. The method involves printing or otherwise depositing elongated nanostructures in a carrier solution. The deposited droplets are also elongated, usually by patterning the surface upon which the droplets are deposited. As the droplet evaporates, the fluid flow within the droplets is controlled such that the nanostructures are deposited either at the edge of the elongated droplet or the center of the elongated droplet. The described deposition technique has particular application in forming the active region of a transistor. | 2010-06-03 |
| 20100136758 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method includes forming an active region on a surface layer of a semiconductor substrate, forming a first word line extending in a first direction on the gate insulating film in the first memory cell array region, and forming a second word line extending in a second direction crossing the first direction on the gate insulating film in the second memory cell array region, wherein the ion implantation into the active region is performed from a direction that is inclined from a direction vertical to the surface of the semiconductor substrate and is oblique with respect to both the first direction and the second direction. | 2010-06-03 |
| 20100136759 | METHOD OF FABRICATING A DYNAMIC RANDOM ACCESS MEMORY - A method of fabricating a dynamic random access memory is provided. First, a substrate at least having a memory device area and a peripheral device area is provided, wherein an isolation structure and a capacitor are formed in the substrate of the memory device area, and an isolation structure and a well are formed in the substrate of the peripheral device area. A first oxide layer is formed on the substrate of the peripheral device area, and a passing gate isolation structure is formed on the substrate of the memory device area at the same time. A second oxide layer is formed on the substrate of the memory device area. And a first transistor is formed on the substrate of the memory device area, a passing gate is formed on the passing gate isolation structure, and a second transistor is formed on the substrate of the peripheral device area. | 2010-06-03 |
| 20100136760 | Silicon Carbide Semiconductor Device and Manufacturing Method Thereof - A silicon carbide semiconductor device is fabricated by forming an amorphous layer in a semiconductor layer of a silicon carbide substrate at a boundary between a cell forming area and an outer peripheral area, forming an outer peripheral insulating film over the semiconductor layer in the outer peripheral area, and thermally oxidizing an upper surface of the semiconductor layer in the cell forming area and at least a portion of the amorphous layer exposed by the outer peripheral insulating film to form a gate oxide film including a stepped portion of increased thickness adjacent the outer peripheral insulating film. The gate electrode layer is then formed which extends from the gate oxide film to above the outer peripheral insulating film. | 2010-06-03 |
| 20100136761 | Semiconductor Devices and Methods of Manufacturing Thereof - Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region. | 2010-06-03 |
| 20100136762 | ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY PROTECTING A LINER AT THE GATE BOTTOM DURING GATE HEAD EXPOSURE - Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided. | 2010-06-03 |
| 20100136763 | METHODS OF FORMING SEMICONDUCTOR DEVICE - Provided are methods of forming a semiconductor device, the method including: forming an insulation region on a substrate region, and an active region on the insulation region; patterning the active region to form an active line pattern; forming a gate pattern to surround an upper portion and lateral portions of the active line pattern; separating the gate pattern into a plurality of sub-gate regions, and separating the active line pattern into a plurality of sub-active regions, in order to form a plurality of memory cells that are each formed of the sub-active region and the sub-gate region and that are separated from one another; and forming first and second impurity doping regions along both edges of the sub-active regions included in each of the plurality of the memory cells, wherein the forming of the first and second impurity doping regions comprises doping lateral portions of the sub-active regions via a space between the memory cells. | 2010-06-03 |
| 20100136764 | METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area. | 2010-06-03 |
| 20100136765 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - When printing is performed on a base substrate with a laser after a single crystal silicon layer is transferred to the base substrate, there are problems such as ablation of the single crystal silicon layer in the peripheral portion of a printed dot or attachment of glass chips or the like to the surface of the single crystal silicon layer. After printing is performed on the bonding surface of a silicon wafer with a laser, the surface of the silicon wafer is polished by CMP (chemical mechanical polishing), so that the projection in the peripheral portion of the printed dot is removed. After that, the silicon wafer is bonded to the base substrate. Since the depression of the printed dot remains to some extent by a chemical etching effect even after the polishing by CMP, the single crystal silicon layer is not transferred only at the depression portion at the time of the transfer; accordingly, the information is left on the base substrate. | 2010-06-03 |
| 20100136766 | WORKING METHOD FOR CUTTING - An object to be processed is reliably cut along a line to cut. An object to be processed is irradiated with laser light while locating a converging point at the object, so as to form a modified region in the object along a line to cut. The object formed with the modified region is subjected to an etching process utilizing an etching liquid exhibiting a higher etching rate for the modified region than for an unmodified region, so as to etch the modified region. This can etch the object selectively and rapidly along the line to cut by utilizing a higher etching rate in the modified region. | 2010-06-03 |
| 20100136767 | METHOD FOR PRODUCTION OF THIN FILM AND APPARATUS FOR MANUFACTURING THE SAME - A method for manufacturing a thin film is provided. A substrate is loaded into a chamber. A first reaction gas and a second reaction gas are supplied into the chamber. The first reaction gas is dissociated to form crystalline nanoparticles. An amorphous material is inhibited from being formed on the substrate using the second reaction gas. Thereafter, a crystalline thin film is formed from the crystalline nanoparticles provided on the substrate. | 2010-06-03 |
| 20100136768 | METHOD FOR SIMULTANEOUS DOPING AND OXIDIZING SEMICONDUCTOR SUBSTRATES AND THE USE THEREOF - The invention relates to a method for simultaneous doping and oxidizing semiconductor substrates and also to doped and oxidized semiconductors substrates produced in this manner. Furthermore, the invention relates to the use of this method for producing solar cells. | 2010-06-03 |
| 20100136769 | GERMANIUM-BASED POLYMERS AND PRODUCTS FORMED FROM GERMANIUM-BASED POLYMERS - Germanium-based polymers are described. In one embodiment, a germanium-based polymer includes a structure given by the formula: | 2010-06-03 |
| 20100136770 | GROUP-III METAL NITRIDE AND PREPARATION THEREOF - A method for forming a group-III metal nitride material film attached to a substrate including subjecting the substrate to an ambient pressure of no greater than 0.01 Pa, and heating the substrate to a temperature of between approximately 500° C.-800° C. The method further includes introducing a group III metal vapor to the surface of the substrate at a base pressure of at least 0.01 Pa, until a plurality of group III metal drops form on the surface, and introducing active nitrogen to the surface at a working pressure of between 0.05 Pa and 2.5 Pa, until group III metal nitride molecules form on the group III metal drops. The method also includes maintaining the working pressure and the active nitrogen until the group III metal nitride molecules diffuse into the group III metal drops, forming nitride/metal solution drops, and until the nitride/metal solution drops turn into a wetting layer on the substrate, and continuing to increase the concentration of group III metal nitride molecules in the wetting layer until all the group III metal atoms contained in the wetting layer are exhausted, and the wetting layer transforms into a group III metal nitride film. | 2010-06-03 |
| 20100136771 | SUB-CRITICAL SHEAR THINNING GROUP IV BASED NANOPARTICLE FLUID - A Group IV based nanoparticle fluid is disclosed. The nanoparticle fluid includes a set of nanoparticles—comprising a set of Group IV atoms, wherein the set of nanoparticles is present in an amount of between about 1 wt % and about 20 wt % of the nanoparticle fluid. The nanoparticle fluid also includes a set of HMW molecules, wherein the set of HMW molecules is present in an amount of between about 0 wt % and about 5 wt % of the nanoparticle fluid. The nanoparticle fluid further includes a set of capping agent molecules, wherein at least some capping agent molecules of the set of capping agent molecules are attached to the set of nanoparticles. | 2010-06-03 |
| 20100136772 | DELIVERY OF VAPOR PRECURSOR FROM SOLID SOURCE - A method is disclosed that uses solid precursors for semiconductor processing. A solid precursor is provided in a storage container. The solid precursor is transformed into a liquid state in the storage container. The liquid state precursor is transported from the storage container to a liquid holding container. The liquid state precursor is transported from the liquid holding container to a reaction chamber. The molten precursor allows the precursor to be metered in the liquid state. The storage container can be heated only when necessary to replenish the liquid holding container, thereby reducing the possibility of thermal decomposition of the precursor. | 2010-06-03 |
| 20100136773 | Semiconductor Device Manufacturing Method and Substrate Processing Apparatus - A semiconductor device manufacturing method comprises the steps of loading a substrate into a processing chamber, mounting the substrate on a support tool in the processing chamber, processing the substrate mounted on the support tool by supplying process gas into the processing chamber, purging the interior of the processing chamber after the substrate processing step, and unloading the processed substrate from the processing chamber after the step of purging the interior of the processing chamber, wherein in the step of purging the interior of the processing chamber, exhaust is performed toward above the substrate and toward below the substrate in the processing chamber, and the exhaust rate toward above the substrate is set larger than the exhaust rate toward below the substrate. | 2010-06-03 |
| 20100136774 | METHOD OF FABRICATING A DIODE - A method of fabricating a diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a heavily n-doped zone, a weakly n-doped zone, a weakly p-doped zone and a heavily p-doped zone. In the vertical direction, the weakly p-doped zone has a thickness of at least 25% and at most 50% of the thickness of the semiconductor body. | 2010-06-03 |
| 20100136775 | METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE - Provided is a method for manufacturing a thin-film transistor substrate, in which the etching characteristics of an insulating film and a passivation layer are enhanced. The insulating film and the passivation layer are deposited by low temperature chemical vapor deposition. The method includes disposing a gate wiring on an insulating substrate; disposing a gate insulating film on the gate wiring; disposing a data wiring on the gate insulating film; disposing a passivation layer on the data wiring; and forming a contact hole by etching at least one of the gate insulating film and the passivation layer, wherein at least one of the gate insulating film and the passivation layer is disposed at a temperature of about 280° C. or below, and the forming of the contact hole is performed at a pressure of about 60 mT or below. | 2010-06-03 |
| 20100136776 | SELECTIVE DEPOSITION OF NOBLE METAL THIN FILMS - Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal compound while avoiding deposition on a lower k insulator such as silicon oxide. The ability to deposit on a first surface, such as a high-k material, while avoiding deposition on a second surface, such as a silicon oxide or silicon nitride surface, may be utilized, for example, in the formation of a gate electrode. | 2010-06-03 |
| 20100136777 | FLEXIBLE SUBSTRATE WITH ELECTRONIC DEVICES FORMED THEREON - A method of manufacturing an electronic device ( | 2010-06-03 |
| 20100136778 | Semiconductor Memory Device and a Method of Manufacturing the Same, A Method of Manufacturing a Vertical MISFET and a Vertical MISFET, and a Method of Manufacturing a Semiconductor Device and a Semiconductor Device - Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film. | 2010-06-03 |
| 20100136779 | Sidewall SONOS Gate Structure with Dual-Thickness Oxide and Method of Fabricating the Same - A SONOS gate structure has an oxide structure on a substrate having gate pattern thereon. The oxide structure has a relatively thinner oxide portion on the substrate for keeping good program/erase efficiency, and a relatively thicker oxide portion on sidewalls of the gate pattern for inhibiting gate disturb. Trapping dielectric spacers are on formed the oxide structure laterally adjacent to said sidewalls of said gate pattern respectively. | 2010-06-03 |
| 20100136780 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, wherein forming the second insulating film comprises forming an insulating film containing silicon using source gas not containing chlorine, and forming an insulating film containing oxygen and a metal element on the insulating film containing silicon. | 2010-06-03 |
| 20100136781 | SIMULTANEOUS VIA AND TRENCH PATTERNING USING DIFFERENT ETCH RATES - One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal. | 2010-06-03 |
| 20100136782 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conductive material containing Ag is dropped into the opening. Further, a first conductive layer is formed by baking the conductive material dropped into the opening by selective irradiation with laser light. Subsequently, a metal film is formed over the entire surface by sputtering, and the mask is removed thereafter to have only the metal film remain over the first conductive layer, thereby forming an embedded wiring layer formed with a stack of the first conductive layer containing Ag and the second conductive layer (metal film). | 2010-06-03 |
| 20100136783 | METHOD OF MANUFACTURING THROUGH-VIA - Disclosed is a method of manufacturing a through-via. The through-via manufacturing method includes forming a core-via hole in a wafer, forming a suction-via hole adjacent to the core-via hole in the wafer, forming a via core in the core-via hole, forming a polymer-via hole connected to the suction-via hole in the wafer, filling the polymer-via hole with polymer solution by creating a vacuum inside the polymer-via hole by drawing air out of the suction-via hole, and polishing the wafer such that the via core formed in the core-via hole is exposed. | 2010-06-03 |
| 20100136784 | SELF ALIGNED DOUBLE PATTERNING FLOW WITH NON-SACRIFICIAL FEATURES - Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned double patterning (SADP) process. A conformal layer of non-sacrificial material is formed over features of sacrificial structural material patterned near the optical resolution of a photolithography system using a high-resolution photomask. An anisotropic etch of the non-sacrificial layer leaves non-sacrificial ribs above a substrate. A gapfill layer deposited thereon may be etched or polished back to form alternating fill and non-sacrificial features. No hard mask is needed to form the non-sacrificial ribs, reducing the number of processing steps involved. | 2010-06-03 |
