| 22nd week of 2010 patent applcation highlights part 16 |
| Patent application number | Title | Published |
|---|
| 20100133585 | GROWTH OF GERMANIUM EPITAXIAL THIN FILM WITH NEGATIVE PHOTOCONDUCTANCE CHARACTERISTICS AND PHOTODIODE USING THE SAME - A method of growing a germanium (Ge) epitaxial thin film having negative photoconductance characteristics and a photodiode using the same are provided. The method of growing the germanium (Ge) epitaxial thin film includes growing a germanium (Ge) thin film on a silicon substrate at a low temperature, raising the temperature to grow the germanium (Ge) thin film, and growing the germanium (Ge) thin film at a high temperature, wherein each stage of growth is performed using reduced pressure chemical vapor deposition (RPCVD). The three-stage growth method enables formation of a germanium (Ge) epitaxial thin film characterized by alleviated stress on a substrate, a lowered penetrating dislocation density, and reduced surface roughness. | 2010-06-03 |
| 20100133586 | HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME - Provided are a heterojunction bipolar transistor and a method of forming the same. The method includes forming an emitter electrode on an emitter capping pattern, a base electrode on a base pattern, and a collector electrode on a subcollector pattern, the subcollector pattern, the base pattern, an emitter pattern, and the emitter capping pattern being provided to a substrate; patterning a protection insulation layer and a first dummy pattern covering the emitter electrode, the base electrode, and the collector electrode, to expose the emitter electrode, the base electrode, and the collector electrode; forming a second dummy pattern to electrically separate the emitter electrode, the base electrode, and the collector electrode; forming, on the substrate provided with the second dummy pattern, an emitter electrode interconnection connected to the emitter electrode, a base electrode interconnection connected to the base electrode, and a collector electrode interconnection connected to the collector electrode; and removing the first and second dummy patterns. | 2010-06-03 |
| 20100133587 | THREE-DIMENSIONAL ARCHITECTURE FOR INTEGRATION OF CMOS CIRCUITS AND NANO-MATERIAL IN HYBRID DIGITAL CIRCUITS - A hybrid CMOL stack enables more efficient design of CMOS logical circuits. The hybrid CMOL structure includes a first substrate having a CMOS device layer on the substrate, a first interconnect layer with interface pins over the CMOS device layer of the first substrate, a first array of nanowires connected to the interface pins of the first interconnect layer, a layer of nanowire junction material over the first array of nanowires, a second array of nanowires over the nanowire junction material, a second interconnect layer having interface pins disposed over the second array of nanowires, the interface pins being connected to the second array of nanowires, and a second substrate, the second substrate including a second CMOS device layer disposed over the second interconnect layer. | 2010-06-03 |
| 20100133588 | SEMICONDUCTOR DEVICE HAVING DUMMY POWER LINE - A semiconductor device includes a plurality of circuit blocks respectively arranged both in a first direction and in a second direction that intersects the first direction. A plurality of signal lines extend in one direction of the first direction and the second direction to correspond to and extend over the circuit blocks arranged in the one direction among the plurality of circuit blocks, the signal lines being spaced apart in the other direction of the first direction and the second direction. A plurality of power lines are arranged over the circuit blocks, each power line extending along at least one of the signal lines in the one direction. A dummy power line is arranged between one of the power lines and a signal line adjacent to the one of the power lines in the other direction. | 2010-06-03 |
| 20100133589 | ANALOG CIRCUIT CELL ARRAY AND ANALOG INTEGRATED CIRCUIT - An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use. | 2010-06-03 |
| 20100133590 | SHARED PHOTODIODE IMAGE SENSOR - An image sensor with a shared photodiode is provided. The image sensor includes at least two unit pixels, each of which includes a photodiode, a diffusion region which gathers electrons from the photodiode, a transfer transistor which connects the photodiode with the diffusion region, and a readout circuit which reads out a signal from the diffusion region. Photodiodes of neighboring unit pixels are disposed symmetrically to be adjacent to one another to form a shared photodiode. The image sensor does not have a STI region which causes a dark current restricting its performance and does not require a basic minimum design factor (a distance or an area) related to a STI region. A region corresponding to a STI region may be used as a region of a photodiode or for additional pixel scaling. Therefore, a limitation in scaling of a photodiode is overcome, and pixel performance is improved in spite of pixel scaling. | 2010-06-03 |
| 20100133591 | METHOD FOR PASSIVATING A FIELD-EFFECT TRANSISTOR - The present invention relates to a method for passivating a semiconductor component having at least one chemosensitive electrode that is blinded by the application of a glass layer. The present invention also relates to a device for detecting at least one substance included in a fluid stream, including at least one semiconductor component acting as a measuring sensor as well as at least one semiconductor component acting as a reference element, the semiconductor components each having a chemosensitive electrode, and the chemosensitive electrode of the semiconductor component acting as the reference element being passivated. For the passivation, a glass layer may be applied at least to the chemosensitive electrode of the semiconductor component acting as reference element. | 2010-06-03 |
| 20100133592 | SOLID-STATE IMAGING DEVICE - A plurality of pixel portions ( | 2010-06-03 |
| 20100133593 | Junction Field Effect Transistor Having a Double Gate Structure and Method of Making Same - A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region. | 2010-06-03 |
| 20100133594 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure including a substrate, a gate dielectric layer, a gate, a source region and a drain region is provided. The gate dielectric layer is disposed on the substrate. At least one recess is disposed in the substrate. The gate is disposed on the gate dielectric layer and in the recess. The source and drain regions are respectively disposed in the substrate beside the gate. | 2010-06-03 |
| 20100133595 | FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS - Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type. | 2010-06-03 |
| 20100133596 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes pixels arranged in a matrix on a semiconductor substrate, the pixels each including: a photodiode for photoelectric-converting an incident light beam; a readout transistor for reading out a signal charge from the photodiode; and a floating diffusion region for converting the read out signal charge into a voltage, wherein the semiconductor substrate is of an n-type, a first p-type well is provided below an n-type forming layer of the photodiode so as to be located at a distant position from a surface of the n-type substrate at the photodiode side, and partially or entirely below the readout transistor, the first p-type well is formed so as to reach the surface of the semiconductor substrate. | 2010-06-03 |
| 20100133597 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device including a ferroelectric capacitor, the ferroelectric capacitor includes a lower electrode having a plurality of protrusions; a ferroelectric film on the lower electrode, the ferroelectric film having a plurality of protrusions engaging with the protrusions of the lower electrode; and an upper electrode on the ferroelectric film, the upper electrode having a plurality of protrusions engaging with the protrusions of the lower electrode. | 2010-06-03 |
| 20100133598 | Nonvolatile memory device and method for fabricating the same - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material. | 2010-06-03 |
| 20100133599 | Nonvolatile memory device and method for fabricating the same - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. | 2010-06-03 |
| 20100133600 | Semiconductor devices having increased sensing margin - One transistor (1-T) dynamic random access memories (DRAM) having improved sensing margins that are relatively independent of the amount of carriers stored in a body region thereof. | 2010-06-03 |
| 20100133601 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region. | 2010-06-03 |
| 20100133602 | NON-VOLATILE MEMORY CELL WITH BURIED SELECT GATE, AND METHOD OF MAKING SAME - A memory device, and method of making the same, in which a trench is formed into the surface of a semiconductor substrate. Source and drain regions define a channel region there between. The drain is formed under the trench. The channel region includes a first portion that extends along a bottom wall of the trench, a second portion that extends along a sidewall of the trench, and a third portion that extends along the surface of the substrate. The floating gate is disposed over the channel region third portion. The control gate is disposed over the floating gate. The select gate is at least partially disposed in the trench and adjacent to the channel region first and second portions. The erase gate disposed adjacent to and insulated from the floating gate. | 2010-06-03 |
| 20100133603 | EEPROM - An EEPROM according to the present invention includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. A first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and a fifth impurity region of a second conductive type are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, a first floating gate, and a second floating gate are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, a first tunnel window and a second tunnel window are respectively formed at portions in contact with the first floating gate and the second floating gate. A sixth impurity region of the second conductive type, which is connected to the second impurity region, is formed in a portion of the top layer portion of the semiconductor layer that opposes the second tunnel window. | 2010-06-03 |
| 20100133604 | Semiconductor Devices Having Gate Structures with Conductive Patterns of Different Widths and Methods of Fabricating Such Devices - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern. | 2010-06-03 |
| 20100133605 | SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE - A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate. | 2010-06-03 |
| 20100133606 | Three-dimensional semiconductor memory device - A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers. | 2010-06-03 |
| 20100133607 | Recessed Channel Negative Differential Resistance-Based Memory Cell - Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode (source; p-type region) is connected to the bit line and cathode (drain; n-type region) is connected to the word line. Aside from the recessed enable gate, the disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As a result, and as facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. Moreover, the disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell, while not required in all useful embodiments, assists in improving the data retention of the cell and extends the time needed between cell refresh. | 2010-06-03 |
| 20100133608 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess. | 2010-06-03 |
| 20100133609 | METHODS OF PROVIDING ELECTRICAL ISOLATION AND SEMICONDUCTOR STRUCTURES INCLUDING SAME - Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“L | 2010-06-03 |
| 20100133610 | METHOD OF FORMING AN INTEGRATED POWER DEVICE AND STRUCTURE - In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor. | 2010-06-03 |
| 20100133611 | Isolated transistor - A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. | 2010-06-03 |
| 20100133612 | ELECTRONIC DEVICE WITH ASYMMETRIC GATE STRAIN - The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode. | 2010-06-03 |
| 20100133613 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a supporting substrate; an insulation film provided on the supporting substrate; a source layer provided on the insulation film; a drain layer provided on the insulation film; a body region provided between the source layer and the drain layer and being in an electrically floating state, the body region accumulating electric charges or discharging electric charges in order to store data; a boundary gate dielectric film provided at least on a boundary portion between the body region and the source layer and on a boundary portion between the body region and the drain layer; and a center gate dielectric film provided adjacently to the boundary gate dielectric film on the body region, the center gate dielectric film having more interface states than the boundary gate dielectric film has. | 2010-06-03 |
| 20100133614 | MULTIPLE GATE TRANSISTOR HAVING HOMOGENOUSLY SILICIDED FIN END PORTIONS - In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas. | 2010-06-03 |
| 20100133615 | MULTIPLE GATE TRANSISTOR HAVING FINS WITH A LENGTH DEFINED BY THE GATE ELECTRODE - The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process. | 2010-06-03 |
| 20100133616 | METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR - Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. | 2010-06-03 |
| 20100133617 | FIN FIELD EFFECT TRANSISTOR - Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si | 2010-06-03 |
| 20100133618 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electrostatic discharge (ESD) protection device for protecting an internal circuitry from being damaged during electrostatic discharge, and a method for manufacturing the ESD protection circuit are provided. The electrostatic discharge (ESD) protection device includes: a gate electrode over a substrate; first and second doping regions provided in the substrate exposed at both sides of the gate electrode, the first and second doping regions having the same conductivity type; a third doping region provided in the second doping region and having an opposite conductivity type to that of the second doping region; and fourth and fifth doping regions spaced apart from the gate electrode and provided in the substrate exposed at both sides of the gate electrode, the fourth and fifth doping regions having the same conductivity type as the first and second doping regions. | 2010-06-03 |
| 20100133619 | SEMICONDUCTOR DEVICE HAVING A FIN TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV. | 2010-06-03 |
| 20100133620 | REDUCED TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF TWO DIFFERENT STRESS-INDUCING LAYERS IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, stress-inducing materials may be provided above the basic transistor devices without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines. Furthermore, an additional stress-inducing material may be provided on the basis of the superior surface topography, thereby providing a highly efficient strain-inducing mechanism in performance-driven transistor elements. | 2010-06-03 |
| 20100133621 | RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element. | 2010-06-03 |
| 20100133622 | Semiconductor device including MOSFET with controlled threshold voltage, and manufacturing method of the same - Provided is a semiconductor device including an N-MOSFET and a P-MOSFET on a semiconductor substrate. The N-MOSFET is formed on the semiconductor substrate, and includes a first gate insulating film including a first high-dielectric-constant film having a higher dielectric constant than a silicon oxide film. The P-MOSFET is formed on the semiconductor substrate, and includes a second gate insulating film including a second high-dielectric-constant film having a higher dielectric constant than a silicon oxide film. The first high-dielectric-constant film contains a first metal, and a concentration of the first metal increases from a surface of the first high-dielectric-constant film toward the semiconductor substrate. The second high-dielectric-constant film contains a second metal, and a concentration of the second metal decreases from a surface of the second high-dielectric-constant film toward the semiconductor substrate. | 2010-06-03 |
| 20100133623 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon oxynitride film is formed on entire surface of a semiconductor substrate, a lanthanum oxide film is formed on the silicon oxynitride film and the lanthanum oxide film is removed from a pMOS region. Then, a nitrided hafnium silicate film serving as a highly dielectric film is formed on the entire surface, an aluminum-containing titanium nitride film is formed, a polysilicon film is formed, and the stacked films are patterned into a gate electrode configuration. Next, impurities are introduced into a source/drain region, and an annealing for activating the impurities is utilized to diffuse the aluminum included in the aluminum-containing titanium nitride film to the interface between the silicon oxynitride film and the nitrided hafnium aluminum silicate film in the pMOS region. | 2010-06-03 |
| 20100133624 | CMOS Fabrication Process - Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm | 2010-06-03 |
| 20100133625 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit having a first p-type MOS transistor; a first n-type MOS transistor; a second p-type MOS transistors; a and second n-type MOS transistors having fourth gate electrodes disposed so as to be adjacent to the second diffused regions of the first n-type MOS transistor. The semiconductor integrated circuit further having an absolute value of a threshold voltage of the second p-type MOS transistor being higher than an absolute value of a threshold voltage of the first p-type MOS transistor, and an absolute value of a threshold voltage of the second n-type MOS transistor being higher than an absolute value of a threshold voltage of the first n-type MOS transistor. | 2010-06-03 |
| 20100133626 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device according to one embodiment includes: laying out a first region, a second region, a third region and a fourth region on a semiconductor substrate by forming an element isolation region in the semiconductor substrate; forming a first insulating film on the first region and the second region; forming a first semiconductor film on the first insulating film; forming a second insulating film and an aluminum oxide film thereon on the fourth region after forming of the first semiconductor film; forming a third insulating film and a lanthanum oxide film thereon on the third region after forming of the first semiconductor film; forming a high dielectric constant film on the aluminum oxide film and the lanthanum oxide film; forming a metal film on the high dielectric constant film; forming a second semiconductor film on the first semiconductor film and the metal film; and patterning the first insulating film, the first semiconductor film, the second insulating film, the aluminum oxide film, the third insulating film, the lanthanum oxide film, the high dielectric constant film, the metal film and the second semiconductor film. | 2010-06-03 |
| 20100133627 | DEPLETION-TYPE NAND FLASH MEMORY - A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage. | 2010-06-03 |
| 20100133628 | HIGH-K GATE ELECTRODE STRUCTURE FORMED AFTER TRANSISTOR FABRICATION BY USING A SPACER - During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability. | 2010-06-03 |
| 20100133629 | INTEGRATED SENSOR INCLUDING SENSING AND PROCESSING DIE MOUNTED ON OPPOSITE SIDES OF PACKAGE SUBSTRATE - An integrated circuit (IC) device includes a lead frame having a first and a second opposing surface and a plurality of lead fingers. A first die including a signal processor is mounted on the first surface of the lead frame while a second die is mounted on the second surface of the lead frame. The second die includes at least one sensor that senses at least one non-electrical parameter and has at least one sensor output that provides a sensing signal for the parameter. The sensor output is coupled to the signal processor for processing the sensing signal. | 2010-06-03 |
| 20100133630 | METHOD FOR PRODUCING A MICROMECHANICAL COMPONENT HAVING A TRENCH STRUCTURE FOR BACKSIDE CONTACT - A method for manufacturing a micromechanical component is proposed. In this context, at least one trench structure having a depth less than the substrate thickness is to be produced in a substrate. In addition, an insulating layer and a filler layer are produced or applied on a first side of the substrate. The filler layer comprises a filler material that substantially fills up the trench structure. A planar first side of the substrate is produced by way of a subsequent planarization within a plane of the filler layer or of the insulating layer or of the substrate. A further planarization of the second side of the substrate is then accomplished. A micromechanical component that is manufactured in accordance with the method is also described. | 2010-06-03 |
| 20100133631 | DIFFERENTIAL-PRESSURE SENSOR SYSTEM AND CORRESPONDING PRODUCTION METHOD - A differential-pressure sensor system and a corresponding production method. The differential-pressure sensor system includes: a differential-pressure sensor chip having a first pressure application region for applying a first pressure, as pressure to be detected, to the differential-pressure sensor chip, and a second pressure application region for applying a second pressure, as reference pressure, to the differential-pressure sensor chip; a housing that partially surrounds the differential-pressure sensor chip; the housing having a through hole, through which the first pressure application region is exposed to the outside; and the housing having an input opening, through which the second pressure application region is exposed to the outside. | 2010-06-03 |
| 20100133632 | VERTICAL HALL SENSOR - A vertical Hall sensor which is integrated in a semiconductor chip has at least 6 electric contacts which are arranged along a straight line on the surface of the semiconductor chip. The electric contacts are wired according to a predetermined rule, namely such that when the contacts are numbered through continuously and repeatedly with the numerals | 2010-06-03 |
| 20100133633 | BEAM STEERING ELEMENT WITH BUILT-IN DETECTOR AND SYSTEM FOR USE THEREOF - An all-optical cross-connect switching system provides optical switching that may reduce processing requirements by three orders of magnitude over conventional techniques by associating at least one optical detector with an optical beam steering element. In one embodiment, a first beam steering element, having a reflective surface in optical association with a first optical fiber array, and a second beam steering element, having a reflective surface in optical association with a second optical fiber array, are optically arranged to direct an optical beam from a first optical fiber in the first optical fiber array to a second optical fiber in the second optical fiber array. The optical detector provides information about a first position of the optical beam on the second beam steering element. Based on this information, the angle of the first beam steering element may be adjusted to cause the optical beam to change to a second position on the second beam steering element. | 2010-06-03 |
| 20100133634 | PRODUCTION OF A SELF-ALIGNED CUSIN BARRIER - A semiconductor product includes a portion made of copper, a portion made of a dielectric and a self-aligned barrier between the copper portion and the dielectric portion. The self-aligned barrier includes a first copper silicide layer comprising predominantly first copper silicide molecules, and a second copper silicide layer comprising predominantly second copper silicide molecules. The proportion of the number of silicon atoms is higher in the second silicide molecules than in the first silicide molecules. The second copper silicide layer is positioned between the copper portion and the first copper silicide layer. A nitride layer may overlie at least part of the first copper silicide layer. | 2010-06-03 |
| 20100133635 | image sensor and image sensing system including the same - The image sensor and an image sensing system including the same are provided. The image sensor includes a semiconductor substrate, a pixel array formed at a pixel area located in the semiconductor substrate and comprising a plurality of photoelectric converts, a plurality of driver circuits formed at a circuit area defined in the semiconductor substrate. The image sensor includes at least one heat blocker or heat shield. The at least one heat blocker may be formed between the pixel area and the circuit area in the semiconductor substrate. The heat blocker or heat shield may block or dissipate heat generated at the circuit area from being transferred to the pixel area through the semiconductor substrate. The heat blocker or heat shield may be used in image sensors using a back-side illumination sensor (BIS) structure or image sensors using a silicon on insulator (SOI) semiconductor substrate. | 2010-06-03 |
| 20100133636 | SINGLE PHOTON DETECTOR AND ASSOCIATED METHODS FOR MAKING THE SAME - A semiconductor device includes a semiconductor substrate, a photon avalanche detector in the semiconductor substrate. The photon avalanche detector includes an anode of a first conductivity type and a cathode of a second conductivity type. A guard ring is in the semiconductor substrate and at least partially surrounds the photon avalanche detector. A passivation layer of the first conductivity type is in contact with the guard ring to reduce an electric field at an edge of the photon avalanche detector. | 2010-06-03 |
| 20100133637 | AVALANCHE PHOTODIODE - An avalanche photodiode comprises: a substrate; a semiconductor layer of a first conductivity type on the substrate; and an avalanche multiplication layer, a light absorption layer, and a window layer which are sequentially formed on the semiconductor layer, wherein apart of the window layer is a region of a second conductivity type, and the light absorption layer includes a first light absorption layer, and a second light absorption layer which has higher electric conductivity than electric conductivity of the first light absorption layer. | 2010-06-03 |
| 20100133638 | Image sensors and methods of manufacturing the same - An image sensor includes a plurality of photodiodes, a plurality of wells isolating the plurality of photodiodes from each other, and a plurality of conductive layers or conductive lines for suppressing a dark current generated at the surface of the photodiodes and in the wells in response to a bias voltage. | 2010-06-03 |
| 20100133639 | Photosensitive Semiconductor Component - A semiconductor component that includes a photosensitive doped semiconductor layer, in which electrical charge carriers are released during absorption of electromagnetic radiation is disclosed. The photosensitive semiconductor layer has a structured interface and at least one layer which generates an electric field for separating the released charge carriers disposed downstream of the structured interface. The electric field extends over the structured interface. The photosensitive semiconductor component is distinguished by a high efficiency of the charge carrier separation, in particular, for generating an electric current. | 2010-06-03 |
| 20100133640 | PACKAGING METHOD AND PACKAGING STRUCTURE - The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure. | 2010-06-03 |
| 20100133641 | Image Sensor and Method for Manufacturing the Same - Provided are an image sensor and a method for manufacturing the same. The image sensor comprises a semiconductor substrate, an interconnection and an interlayer dielectric, a lower electrode layer, an image sensing device, a first via hole, a barrier pattern, a second via hole, and a metal contact. The semiconductor substrate comprises a readout circuitry. The interconnection and the interlayer dielectric are formed on the semiconductor substrate. The lower electrode layer is disposed over the interlayer dielectric. The image sensing device is disposed on the lower electrode layer. The first via hole is formed through the image sensing device. The barrier pattern is formed on a sidewall of the first via hole. The second via hole is formed through the lower electrode layer and the interlayer dielectric under the first via hole. The metal contact is formed in the first and second via holes. | 2010-06-03 |
| 20100133642 | SYSTEM AND METHOD FOR FORMING METAL INTERCONNECTION IN IMAGE SENSOR - A method for forming a metal interconnection in an image sensor includes forming a first interlayer dielectric (ILD) layer having a contact plug over a substrate, forming a diffusion barrier layer over the first ILD layer, performing a forming gas annealing, forming a second ILD layer over the diffusion barrier layer, etching the second ILD layer and the diffusion barrier layer to form a trench, forming a conductive layer to fill the trench, and planarizing the conductive layer to form a metal interconnection electrically connected to the contact plug | 2010-06-03 |
| 20100133643 | IMAGE SENSOR PIXEL AND METHOD THEREOF - A method of manufacturing a pixel of an image sensor including a protruded photodiode capable of improving photosensitivity and reducing crosstalk between neighboring pixels and a pixel of an image sensor formed using the method are provided. The pixel of the semiconductor image sensor includes a protrudedly shaped photodiode on a surface of a semiconductor substrate. A surface area of the photodiode with respect to a surface area of the image sensor pixel increases to improve photosensitivity, and a microlens is not needed due to the improvement of the fill factor. In addition, the crosstalk of neighboring pixels can be removed. | 2010-06-03 |
| 20100133644 | Bottom anode Schottky diode structure and method - This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current. | 2010-06-03 |
| 20100133645 | METHOD FOR STACKING AND INTERCONNECTING INTEGRATED CIRCUITS - A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas. | 2010-06-03 |
| 20100133646 | SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY - A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers. | 2010-06-03 |
| 20100133647 | Semiconductor devices and semiconductor device manufacturing methods - Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure. | 2010-06-03 |
| 20100133648 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES - In sophisticated metallization systems, air gaps may be formed on the basis of a self-aligned patterning regime during which the conductive cap material of metal lines may be protected by providing one or more materials, which may subsequently be removed. Consequently, the etch behavior and the electrical characteristics of metal lines during the self-aligned patterning regime may be individually adjusted. | 2010-06-03 |
| 20100133649 | Contact efuse structure, method of making a contact efuse device containing the same, and method of making a read only memory containing the same - A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse device or a read only memory. A method of making a contact efuse device and a method of making a read only memory are also disclosed. | 2010-06-03 |
| 20100133650 | Semiconductor device - A semiconductor device includes an electric fuse formed on a substrate. The electric fuse includes: a first interconnect formed on one end side thereof; a second interconnect formed in a layer different from a layer in which the first interconnect is formed; a first via provided in contact with the first interconnect and the second interconnect to connect those interconnects; a third interconnect formed on another end side thereof, the third interconnect being formed in the same layer in which the first interconnect is formed, as being separated from the first interconnect; and a second via provided in contact with the third interconnect and the second interconnect to connect those interconnects, the second via being lower in resistance than the first via. The electric fuse is disconnected by a flowing-out portion to be formed of a conductive material forming the electric fuse which flows outwardly during disconnection. | 2010-06-03 |
| 20100133651 | SEMICONDUCTOR STRUCTURE PROCESSING USING MULTIPLE LATERALLY SPACED LASER BEAM SPOTS WITH JOINT VELOCITY PROFILING - A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N≧2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate along N respective beam axes until incident upon selected structures in N respective distinct rows. The method determines a joint velocity profile for simultaneously moving in the lengthwise direction the N laser beam axes substantially in unison relative to the semiconductor substrate so as to process structures in the N rows with the respective N series of laser pulses, whereby the joint velocity profile is such that the throughput benefit is achieved while ensuring that the joint velocity profile represents feasible velocities for each of the N series of laser pulses and for each of the respective N rows of structures processed with the N series of laser pulses. A semiconductor substrate is designed to have a structure layout that takes advantage of the N-fold processing parallelism provided by the N laser beams. | 2010-06-03 |
| 20100133652 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device capable of increasing the capacitance of a capacitor, while reducing an area occupied by the capacitor and inductor on a substrate. The semiconductor device includes a first line; an interlayer insulating film that is formed on the first line and has a recess formed at a location corresponding to the first line; and a second line formed in the recess of the interlayer insulating film. The first line, the second line, and an insulating film formed between the first line and the second line constitute a capacitor. At least one of the first line and the second line constitutes an inductor. | 2010-06-03 |
| 20100133653 | INTEGRATED CIRCUIT DEVICES INCLUDING PASSIVE DEVICE SHIELDING STRUCTURES AND METHODS OF FORMING THE SAME - Integrated circuit devices include a semiconductor substrate and a flux line generating passive electronic element on the semiconductor substrate. A dummy gate structure is arranged on the semiconductor substrate in a region below the passive electronic element. The dummy gate includes a plurality of segments, each segment including a first longitudinally extending part and a second longitudinally extending part. The second longitudinally extending part extends at an angle from an end of the first longitudinally extending part. Ones of the segments extend at a substantially same angle and are arranged displaced from each other in an adjacent nested relationship. | 2010-06-03 |
| 20100133654 | METHOD FOR MANUFACTURING CAPACITOR OF SEMICONDUCTOR - The present invention relates to a method of producing a semiconductor capacitor, and more particularly, to a method of producing a semiconductor capacitor, in which an electroless plating is performed during the production of a lower electrode to form a lower electrode. | 2010-06-03 |
| 20100133655 | SEMICONDUCTOR DEVICE HAVING A CAPACITANCE ELEMENT AND METHOD OF MANUFACTURING THE SAME - A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then heat-treating a laminated film of the amorphous strontium oxide film and the amorphous titanium oxide film at a temperature close to a crystallization start temperature, thereby converting the laminated film to a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein. The laminated film may have a plurality of amorphous strontium oxide films and a plurality of amorphous titanium oxide films that are alternately laminated. A semiconductor device includes a capacitor having as its dielectric film a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein. | 2010-06-03 |
| 20100133656 | Method Using Multiple Layer Annealing Cap for Fabricating Group III-Nitride Semiconductor Device Structures and Devices Formed Thereby - A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor. | 2010-06-03 |
| 20100133657 | GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE PRODUCTION METHOD, AND GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE - A group III nitride semiconductor substrate production method includes preparing a bulk crystal formed of a group III nitride semiconductor single crystal. The group III nitride semiconductor single crystal has one crystalline plane and an other crystalline plane. Hardness of the other crystalline plane is smaller than hardness of the one crystalline plane. The prepared bulk crystal is cut from the other crystalline plane to the one crystalline plane of the bulk crystal. | 2010-06-03 |
| 20100133658 | NITRIDE SEMICONDUCTOR COMPONENT LAYER STRUCTURE ON A GROUP IV SUBSTRATE SURFACE - The invention relates to nitride semiconductor component having a Group III nitride layer structure which is deposited on a substrate having a Group IV substrate surface made of a Group IV substrate material with a cubical crystal structure. The Group IV substrate surface has an elementary cell with C2 symmetry, but not with a higher rotational symmetry than C2 symmetry, when any surface reconstruction is ignored. The Group III nitride layer structure has a seeding layer of ternary or quaternary Al | 2010-06-03 |
| 20100133659 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP - A semiconductor device including a plurality of circuit regions formed in a semiconductor substrate and a scribe region formed around the circuit regions for separating the respective circuit regions, the scribe region having a plurality of laminated interlayer films including a plurality of metal films and an optically-transparent insulation film formed between and on the plurality of metal films, wherein a first metal film included in a first upper interlayer film of the plurality of interlayer films is positionally offset in a vertical direction to a second metal film included in a second lower interlayer film under the first interlayer film. | 2010-06-03 |
| 20100133660 | METHOD FOR PRODUCING INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS - The present disclosure is related to method for producing a semiconductor device comprising the steps of: providing a semiconductor substrate ( | 2010-06-03 |
| 20100133661 | METHODS FOR FORMING CONDUCTIVE VIAS IN SEMICONDUCTOR DEVICE COMPONENTS - A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole. | 2010-06-03 |
| 20100133662 | SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES - Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies. | 2010-06-03 |
| 20100133663 | TECHNIQUE FOR THE GROWTH OF PLANAR SEMI-POLAR GALLIUM NITRIDE - A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 | 2010-06-03 |
| 20100133664 | MODULE AND MOUNTED STRUCTURE USING THE SAME - A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module ( | 2010-06-03 |
| 20100133665 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; and removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed. | 2010-06-03 |
| 20100133666 | DEVICE INCLUDING A SEMICONDUCTOR CHIP AND METAL FOILS - A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner. | 2010-06-03 |
| 20100133667 | POWER SEMICONDUCTOR MODULE - A wiring process between the provided power semiconductor module and the external circuit is simple. In the power semiconductor module, a power semiconductor element and a cylindrical conductor are joined to one surface of a lead frame. An opening of the cylindrical conductor is exposed at a surface of transfer molding resin. Sealing with the transfer molding resin is performed such that terminal portions of the lead frame protrude from peripheral side portions of the transfer molding resin. The cylindrical conductor is conductive with a control circuit. The terminal portions of the lead frame are each conductive with a main circuit. | 2010-06-03 |
| 20100133668 | Semiconductor device and manufacturing method thereof - The present invention relates to a semiconductor device, and more particularly to a manufacturing method for said semiconductor device. The semiconductor device comprises a die that connects with a substrate or a lead frame via an adhesion layer, a metal layer, and/or a back metal layer. Furthermore, the adhesion layer can be made of aluminum, and the die can connect with the substrate or the lead frame by ultrasonic bonding technology, which can avoid heat damaging the die during the manufacturing process. | 2010-06-03 |
| 20100133669 | CRACK STOPPING STRUCTURE AND METHOD FOR FABRICATING THE SAME - A crack stopping structure is disclosed. The crack stopping structure includes a semiconductor substrate having a die region, a die seal ring region, and a scribe line region; a metal interconnect structure disposed on the semiconductor substrate of the scribe line region; and a plurality of dielectric layers disposed on the semiconductor substrate of the die region, the die seal ring region, and the scribe line region. The dielectric layers include a first opening exposing the surface of the metal interconnect structure of the scribe line region and a second opening exposing the dielectric layer adjacent to the metal interconnect structure such that the metal interconnect structure and the exposed portion of the dielectric layer form a step. | 2010-06-03 |
| 20100133670 | Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method - A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang. | 2010-06-03 |
| 20100133671 | Flip-chip package structure and the die attach method thereof - A flip-chip package structure comprises a carrier, a block bump, and a die. The carrier is a lead frame or substrate that comprises a lead pattern side, and an electrode pin is disposed on the lead pattern side. The die comprises an active side, and a bond pad is disposed on the active side. The block bump is bonded to the electrode pin; the bond pad of the die is attached on the carrier through the block bump, so that the die and the carrier joint together to form the flip chip package structure. Besides, the block bump is formed by the wedge bonding, and therefore in bumping size and shapes can easily form larger bump, which will increase the compactness between the die and the carrier. | 2010-06-03 |
| 20100133672 | DUAL-SIDED SUBSTATE INTEGRATED CIRCUIT PACKAGE INCLUDING A LEADFRAME HAVING LEADS WITH INCREASED THICKNESS - An integrated circuit package includes a first non-conductive substrate having a first inner surface and a second non-conductive substrate having a second inner surface. A die having a first thickness is disposed between the first and second inner surfaces. A leadframe includes a member having a proximal end and a distal end. The proximal end has a second thickness less than the first thickness. The distal end is disposed between the first and second inner surfaces. The distal end is undulated such that the distal end has an effective thickness greater than the second thickness. | 2010-06-03 |
| 20100133673 | FLASH MEMORY CARD - A Flash memory card is disclosed comprising a substrate, a Flash memory die on top of the substrate, a controller die on top of the Flash memory die, and an interposer coupled to with the controller die and on top of the Flash memory die wherein the interposer results in substantial reduced wire bonding to the substrate. The interposer can surround or be placed side by side with the controller die. A system and method in accordance with the present invention achieves the following objectives: (1) takes advantage of as large of a Flash memory die as possible, to increase the density of the Flash card by reducing the number of wire bond pads on the substrate and enabling insertion of the largest die possible that can fit inside a given card interior boundary; (2) more efficiently stacks Flash memory dies to increase density of the Flash card; and (3) has a substantially less number of bonding wires to the substrate as possible, to improve production yield. | 2010-06-03 |
| 20100133674 | Compact Semiconductor Package with Integrated Bypass Capacitor and Method - A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance. | 2010-06-03 |
| 20100133675 | PACKAGE-ON-PACKAGE DEVICE, SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a substrate, a chip, an interposer and a molding compound. The chip is electrically connected to the upper surface of the substrate. The interposer is disposed on the chip, and electrically connected to the upper surface of the substrate. The interposer includes an embedded component and a plurality of electric contacts, wherein the embedded component is located between the upper and lower surfaces of the interposer, and the electric contacts are located on the upper surface of the interposer. The molding compound seals the chip and covers the upper surface of the substrate and the lower surface of the interposer. | 2010-06-03 |
| 20100133676 | A POWER SEMICONDUCTOR ARRANGEMENT AND A SEMICONDUCTOR VALVE PROVIDED THEREWITH - A power semiconductor arrangement including a clamping device including a first clamping element and a second clamping element. A plurality of power semiconductor elements are stacked on each other between the first and second clamping elements of the clamping device. The first clamping element receives a clamping force in an axial direction of the stack of the power semiconductor elements. At least one spring element is arranged between the first clamping element and the power semiconductor elements. The at least one spring element presents at least one support surface with which the at least one spring element bears against at least one corresponding support surface of an adjacent element. The at least one spring element includes a helical spring. A center axis of the at least one spring element coincides with a center of the clamping force, or the at least one spring element includes a plurality of helical springs arranged in parallel with each other, which are arranged symmetrically in relation to a point in which a center of the clamping force is introduced into the first clamping element. | 2010-06-03 |
| 20100133677 | SEMICONDUCTOR CHIP STACKED BODY AND METHOD OF MANUFACTURING THE SAME - A plurality of chip sealing bodies stacked on a wiring substrate with a connection terminal. The chip sealing body includes a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip. The chip sealing body is shaped into a cubic form in which a portion of the conductive connecting material except an end portion located on an external device side and all surfaces of semiconductor chip is sealed by the resin and the end portion of the conductive connecting material located on the external device side is exposed from the cubic form. A conductive bonding wire connects the end portions of the conductive connecting materials and the connection terminal respectively. A resin sealing material seals the plurality of chip sealing bodies, the conductive bonding wire, and the wiring substrate. | 2010-06-03 |
| 20100133678 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection circuit also provided on the predetermined semiconductor substrate. In the device, wiring resistance between the electrostatic discharge protection circuit and the through electrode is smaller than wiring resistance between the circuit element and the through electrode. | 2010-06-03 |
| 20100133679 | COMPLIANT INTEGRATED CIRCUIT PACKAGE SUBSTRATE - An integrated circuit package may include a plurality of interconnects, and an integrated package substrate coupled to the plurality of interconnects and comprising an integrated circuit package substrate core. A first surface of the integrated circuit package substrate core may define a depression. | 2010-06-03 |
| 20100133680 | Wafer level package and method of manufacturing the same and method of reusing chip - The present invention relates to a wafer level package and a method of manufacturing the same and a method of reusing a chip and provides a wafer level package including a chip; a removable resin layer formed to surround side surfaces and a lower surface of the chip; a molding material formed on the lower surface of the removable resin layer; a dielectric layer formed over the removable resin layer including the chip and having via holes to expose portions of the chip; redistribution lines formed on the dielectric layer including insides of the via holes to be connected to the chip; and a solder resist layer formed on the dielectric layer to expose portions of the redistribution lines. Also, the present invention provides a method of manufacturing a wafer level package and a method of reusing a chip. | 2010-06-03 |
| 20100133681 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a power semiconductor module having cylindrical conductors which are joined to a wiring pattern so as to be substantially perpendicular to the wiring pattern and whose openings are exposed at a surface of transfer molding resin, and an insert case having a ceiling portion and peripheral walls, the ceiling portion being provided with external terminals that are fitted into, and passed through, the ceiling portion, the external terminals having outer-surface-side connecting portions at the outer surface side of the ceiling portion and inner-surface-side connecting portions at the inner surface side of the ceiling portion. The power semiconductor module is set within the insert case such that the inner-surface-side connecting portions of the external terminals are inserted into the cylindrical conductors. | 2010-06-03 |
| 20100133682 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, an electrically insulating element separated from the semiconductor chip by a space, and encapsulation material disposed in the space. The semiconductor chip includes a first face having a contact, and the electrically insulating element defines at least one through-hole. The encapsulation material is disposed around the semiconductor chip and around the electrically insulating element. Electrically conducting material is deposited in the through-hole of the electrically insulating element and communicates with the contact. | 2010-06-03 |
| 20100133683 | SYSTEM AND APPARATUS FOR VENTING ELECTRONIC PACKAGES AND METHOD OF MAKING SAME - An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers. | 2010-06-03 |
| 20100133684 | POWER SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF - A power semiconductor module includes: a circuit board having a metal base plate, a high thermal conductive insulating layer, and a wiring pattern; power semiconductor elements electrically connected to the wiring pattern; tubular external terminal connection bodies provided to the wiring pattern for external terminals; and a transfer mold resin body encapsulated to expose through-holes in the metal base plate and used to fixedly attach cooling fins to the face of the metal base plate on the other side with attachment members, the face of the metal base plate on the other side, and top portions of the tubular external terminal connection bodies, to form insertion holes for the attachment members communicating with the through-holes and having a larger diameter than the through-holes, and to cover the one side and side faces of the metal base plate and the power semiconductor elements. | 2010-06-03 |
