| 22nd week of 2011 patent applcation highlights part 51 |
| Patent application number | Title | Published |
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| 20110131343 | PROVIDING INDIRECT DATA ADDRESSING IN AN INPUT/OUTPUT PROCESSING SYSTEM WHERE THE INDIRECT DATA ADDRESS LIST IS NON-CONTIGUOUS - Systems, methods and computer program products for providing indirect data addressing at an I/O subsystem of an I/O processing system. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a control word for an I/O operation. The control word includes an indirect data address for data associated with the I/O operation. The indirect data address includes a starting location of a list of storage addresses that collectively specify the data, the list spans two or more non-contiguous storage locations. Data is gathered responsive to the list. The gathered data is transmitted to a control unit in the I/O processing system. | 2011-06-02 |
| 20110131344 | TERMINAL APPARATUS AND METHOD FOR CONTROLLING USB APPARATUS THEREOF - A terminal apparatus connected to an external apparatus controls a universal serial bus (USB) apparatus that is connected to the external apparatus through the external apparatus. The terminal apparatus is connected to the external apparatus through a communication interface including a data channel. The terminal apparatus requests the external apparatus to use the USB apparatus through the data channel. If the USB apparatus is connected to the external apparatus, a controller executes a driver program corresponding to the USB apparatus and accesses the USB apparatus through the data channel. Accordingly, the USB apparatus, which is connected to the external apparatus, is controlled by the terminal apparatus. | 2011-06-02 |
| 20110131345 | APPARATUS FOR DETECTING A USB HOST - A multi-interface integrated circuit (IC) comprises a plurality of transistors, and a level detection block. At least one transistor of the plurality of transistors is in communication with a first terminal and either a first or a second lead of the multi-interface IC, and at least one of the plurality of transistors is in communication with the first terminal, a second terminal and either the first or a second lead of the multi-interface IC. The level detection block is in communication with at least one of the plurality of transistors and the first and second leads. | 2011-06-02 |
| 20110131346 | Context Processing for Multiple Active Write Commands in a Media Controller Architecture - Described embodiments provide a method of transferring data from host devices to a media controller. The media controller generates a transfer context for each write request received from a host device. Receive-data threads corresponding to data transfer contexts for each transfer context are generated, each receive-data thread corresponding to a data transfer between a host device and the media controller. Buffer threads corresponding to data transfer contexts for each transfer context are generated, each buffer thread corresponding to a data transfer between the receive data path and a buffer subsystem. The receive-data and buffer threads are tracked for each transfer context. For each tracked transfer context, data from the receive datapath is iteratively transferred to the buffer subsystem for a previous data transfer context of the buffer thread while data from the host device is transferred to the receive datapath for a subsequent data transfer context of the receive-data thread. | 2011-06-02 |
| 20110131347 | DIRECT MEMORY ACCESS CONTROLLER WITH MULTIPLE TRANSACTION FUNCTIONALITY - A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers. | 2011-06-02 |
| 20110131348 | CONTROL SYSTEM AND CPU UNIT - In the disclosed control system, loops of 1st path and 2nd path are formed connecting an active CPU unit and each of RIO units, the direction of data frame transfer through the loop of 1st path being opposite to that of the data frame transfer through the loop 2nd path. Reflective electro-optical transducer modules are used in the RIO units which are connected with the active CPU unit so that a standby CPU unit can also be connected. Further, the loop of 1st path and the loop of 2nd path are formed connecting the standby CPU module and each of the RIO modules. The data frame transfer directions through the loops connecting the active CPU unit and each of the RIO units are opposite to the data frame transfer directions through the corresponding loops connecting the standby CPU unit and each of the RIO units. | 2011-06-02 |
| 20110131349 | DATA PROCESSING SYSTEM AND DATA PROCESSOR - One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor. | 2011-06-02 |
| 20110131350 | ASYNCHRONOUS UPSIZING CIRCUIT IN DATA PROCESSING SYSTEM - An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation. | 2011-06-02 |
| 20110131351 | Coalescing Multiple Contexts into a Single Data Transfer in a Media Controller Architecture - Described embodiments provide for transferring data between a host device and a storage media. A host data transfer request is received and a total size of the data transfer is determined. One or more contexts corresponding to the total size of the requested transfer are generated and are associated with transfers of data. If the data transfer is a write operation, one or more data segments from the host device are transferred into a buffer. The combined size of the data segments corresponds to the total size of the data transfer. In accordance with the contexts, the one or more data segments are transferred from the buffer to the storage media. If the requested data transfer is a read operation, in accordance with the contexts, data from the storage media is retrieved into a buffer and grouped into one or more segments, which are transmitted to the host device. | 2011-06-02 |
| 20110131352 | Ring Buffer - A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer. | 2011-06-02 |
| 20110131353 | ANALOG DATA GENERATING AND PROCESSING DEVICE FOR USE WITH A PERSONAL COMPUTER - An interface device ( | 2011-06-02 |
| 20110131354 | Apparatus and Method of Generating Universal Memory I/O - A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function. | 2011-06-02 |
| 20110131355 | Method for Reading and Writing Non-Standard Register of Serial Advanced Technology Attachment (SATA) Device - A method for reading non-standard register of Serial Advanced Technology Attachment (SATA) devices discloses an unused input parameter of standard command setting up as an executive parameter. While receiving the standard command, a SATA host controller converts the executive parameter and the standard command into input frame information structure (FIS) that is sent to the SATA devices for the SATA devices to detect the executive parameter for reading corresponding value of non-standard register and saving the value into an output register of the SATA devices. The value of the non-standard register is converted into output frame information structure for being sent to the SATA host controller and the value of the non-standard register is saved to the output register of the SATA host controller. Then by reading the value of the output register of the SATA host controller, the value of the non-standard register is learned. | 2011-06-02 |
| 20110131356 | METHOD AND SYSTEM FOR HIGH-SPEED DETECTION HANDSHAKE IN UNIVERSAL SERIAL BUS BASED DATA COMMUNICATION SYSTEM - A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation. | 2011-06-02 |
| 20110131357 | Interrupt Queuing in a Media Controller Architecture - Described embodiments provide a media controller for servicing contexts corresponding to data transfer requests from host devices. The media controller includes a context generator for generating contexts corresponding to the data transfer requests and a buffer for storing one or more context pointers, each pointer corresponding to a context and an action by a system module associated with the context. A context processor is configured to complete a context when the action by a media controller module associated with the context is complete, remove each pointer from the buffer associated with the completed context, and determine whether an interrupt corresponds to the completed context and removed pointer. If no interrupt corresponds to the completed context, the completed context is cleared. If an interrupt corresponds to the completed context, the interrupt is provided to a master processor and a completed context recycler for recycling the completed context pointer to the context generator. | 2011-06-02 |
| 20110131358 | Wireless Communication with a Dock - In general, the subject matter described in this specification can be embodied in methods, system and program products. A mobile computing device determines that the mobile computing device has physically paired with a docking system. Wireless communication between the mobile computing device and the docking system is automatically established in response to said determining that the mobile computing device has physically paired with the docking system. Data that encodes an audio signal is transmitted, by the mobile computing device and to the docking system as part of the wireless communication, so as to cause speakers of the docking system to audibly output the audio signal from the mobile computing device. | 2011-06-02 |
| 20110131359 | PROGRAMMABLE BRIDGE HEADER STRUCTURES - A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers. | 2011-06-02 |
| 20110131360 | Context Execution in a Media Controller Architecture - Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media. | 2011-06-02 |
| 20110131361 | COMPUTER APPARATUS, COMPUTER SYSTEM AND ADAPTER CARRY-OVER METHOD - To obtain a computer that can change over from the active system to the standby system without reconnecting the I/O adapters. The computer according to the present invention carries over the identifiers logically identifying connection paths between computer modules and I/O adapters from active computers to standby computers. | 2011-06-02 |
| 20110131362 | Flexibly Integrating Endpoint Logic Into Varied Platforms - In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed. | 2011-06-02 |
| 20110131363 | MECHANISM FOR REMAPPING POST VIRTUAL MACHINE MEMORY PAGES - According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses. | 2011-06-02 |
| 20110131364 | REPROGRAMMING A NON-VOLATILE SOLID STATE MEMORY SYSTEM - A non-volatile memory system ( | 2011-06-02 |
| 20110131365 | Data Storage System and Method - A data storage system and method are disclosed. The data storage system includes a first and a second memory and a memory control unit. The first memory is non-volatile, and the second memory is designed to store dynamic information of the first memory. The memory control unit includes a snapshot module, a recording module and a power-off recovery module, and is operative to handle the data loss of the second memory when an unexpected power-off occurs. When the power of the system is recovered, an initial address stored in the first memory by the snapshot module and link information and updating information recorded in the first memory by the recording module are obtained by the power-off recovery module to recovery the second memory. | 2011-06-02 |
| 20110131366 | MEMORY MANAGEMENT UNIT AND MEMORY MANAGEMENT METHOD - According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory. | 2011-06-02 |
| 20110131367 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND WEAR LEVELING METHOD FOR NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a selected region of the memory cell, and stores the wear level of the selected region in an erase count table. | 2011-06-02 |
| 20110131368 | METHOD AND APPARATUS FOR MANAGING ERASE COUNT OF MEMORY DEVICE - A non-volatile memory device having a hidden cell located separate from data storage cells, and a method of effectively managing an erase count of the non-volatile memory device. The method includes preparing the non-volatile memory device that includes a hidden cell located separate from data storage cells and is not accessible to users of the data storage cells, and increasing an erase count stored in an erase count storing region of the hidden cell corresponding to at least one erased data storage cell when the at least one data storage cell is erased. | 2011-06-02 |
| 20110131369 | LOGIC DEVICE - A logic device for communicating with a memory package with a first protocol, communicating with a memory controller with a second protocol, and for performing a protocol conversion between the first and the second protocol. | 2011-06-02 |
| 20110131370 | DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 2011-06-02 |
| 20110131371 | METHOD AND SYSTEM FOR REFRESHING DYNAMIC RANDOM ACCESS MEMORY - A method and system for refreshing DRAM having a plurality of banks, each of the banks including a plurality of rows includes dividing all banks in DRAM into a plurality of groups of banks, each of the groups having n banks, wherein n is an integer greater than or equal to 1. A threshold of available retention time for each group of banks is determined. Each row of banks in each group of banks is refreshed. Refreshing one row of a bank in one group of banks includes determining whether a refresh operation for the row of the bank conflicts with an access operation for the bank where the row of the bank is located. If there is a conflict, then it is determined whether to perform the refresh operation or the access operation for the current row of the bank. If it is determined to perform the access operation, the access operation is continued. If it is determined to perform the recess operation, the current row of the bank is refreshed. DRAM access performance is improved. | 2011-06-02 |
| 20110131372 | OPTIMIZING SEGMENT ACCESS IN BINARY TRANSLATION - A mechanism for a binary translator to emit code that will pre-generate information about a memory segment when a segment selector is assigned to a segment register. The binary translator emits code that will be executed when a memory access using that segment register is encountered and the emitted code will access the pre-generated information when evaluating the memory access request. Memory accesses, where a number of bytes being accessed is less than or equal to a predetermined value, are validated with a minimal number of steps in the code emitted by the binary translator. | 2011-06-02 |
| 20110131373 | Mirroring Data Between Redundant Storage Controllers Of A Storage System - In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed. | 2011-06-02 |
| 20110131374 | Direct Memory Access for Loopback Transfers in a Media Controller Architecture - Described embodiments provide for transferring data from one location to another location in a memory of a media controller. A transmit data path and a receive data path of the media controller are linked with a generic direct memory access (GDMA). The transmit data path includes a transmit (TX) buffer and the receive data path includes a receive (RX) buffer. The GDMA is programmed with a total transfer count and a transfer mode. The GDMA processes the movable data based on the total transfer count and the transfer mode by converting one or more portions of the movable data in the TX buffer into a predefined frame structure defined with status entries, which translates frames of the moveable data between the TX data path and the RX data path and synchronizes the movable data between the TX buffer and the RX buffer with the status entries. | 2011-06-02 |
| 20110131375 | Command Tag Checking in a Multi-Initiator Media Controller Architecture - Described embodiments provide a method of allocating resources of a media controller for a data transfer. A data transfer request is received from at least one host device, and includes a host device ID and a data transfer request ID. The media controller generates a Tag ID of the data transfer request based on the host device ID and the data transfer request ID, and generates a starting memory address of a tag table based on the Tag ID of the data transfer request. A tag count value is read from the starting memory address of the tag table. If the tag count value reaches a threshold, an absence of a tag overlap is determined and the Tag ID of the data transfer request is added to the tag table at the starting memory address. | 2011-06-02 |
| 20110131376 | METHOD AND APPARATUS FOR TILE MAPPING TECHNIQUES - An approach for improving tile-map caching techniques is provided. Whether a tile object is stored in a first cache that is configured to store a plurality of tile objects associated with a map is determined. It is also determined whether a resource locator associated with the tile object is stored in a second cache, if the tile object is not in the first cache. The tile object is retrieved based on the resource locator if the resource locator is stored in the second cache. | 2011-06-02 |
| 20110131377 | MULTI-CORE PROCESSING CACHE IMAGE MANAGEMENT - A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores. | 2011-06-02 |
| 20110131378 | Managing Access to a Cache Memory - Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular cache area can update that cache area. | 2011-06-02 |
| 20110131379 | PROCESSOR AND METHOD FOR WRITEBACK BUFFER REUSE - A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writeback data has been evicted from the writeback cache and before the writeback data has been sent to the lower-level memory. After the writeback data has been sent from the writeback buffer to the lower-level memory, and before the lower-level memory has acknowledged completion of the first writeback operation, the writeback cache may perform a second writeback operation to store different writeback data in the writeback buffer in response to eviction of the different writeback data, such that a total size of the writeback data for the concurrently outstanding writeback operations exceeds a total size of writeback data that the writeback buffer is capable of concurrently storing. | 2011-06-02 |
| 20110131380 | ALTERING PREFETCH DEPTH BASED ON READY DATA - A system comprises a controller and a buffer accessible to the controller. The controller is configured to prefetch data from a storage medium in advance of such prefetch data being requested by a host device, some of such prefetch data being retrieved from the storage medium and stored in the buffer ready for access by the host device (“ready data”) and a remainder of such prefetch data in process of being retrieved from the storage medium but not yet stored in the buffer (“not ready data”). The controller alters a depth of the prefetch data based on a ratio of the ready data to a combined total of the ready data and not ready data. | 2011-06-02 |
| 20110131381 | CACHE SCRATCH-PAD AND METHOD THEREFOR - An address containing data to be accessed is determined in response to executing an instruction received at a processor core of a microprocessor. During a scratch-pad mode of operation, it is determined whether a set of cache lines of a data cache is accessible based upon the memory location from which the instruction was retrieved. The address space of the data cache during scratch-pad mode can be isolated from other address spaces. | 2011-06-02 |
| 20110131382 | Extract Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 2011-06-02 |
| 20110131383 | MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM - A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus. | 2011-06-02 |
| 20110131384 | SYSTEMS AND METHODS FOR INTEGRATING STORAGE RESOURCES FROM STORAGE AREA NETWORK IN MACHINE PROVISIONING PLATFORM - Embodiments relate to systems and methods for integrating storage resources from a storage area network in a machine provisioning platform. A provisioning platform can communicate generate and maintain a provisioning profile encoding the software, hardware, and/or other resources to be provisioned to a target physical and/or virtual machine. The provisioning profile can include a set of storage allocations for each target machine to be provisioned by the platform, indicating the high-level amounts, types, availability, so forth to be associated with each target. The provisioning profile can likewise include a set of storage specifications indicating specific disk types, manufacturers, and specific sources or pools in the set of storage resources available to the storage area network to transparently fulfill the storage allocations. The target(s) can be assigned an alias to identify them to the SAN, and the provisioning platform can mount the corresponding storage resources during the provisioning or updating process. | 2011-06-02 |
| 20110131385 | DATA PROCESSING CIRCUIT WITH ARBITRATION BETWEEN A PLURALITY OF QUEUES - Requests from a plurality of different agents ( | 2011-06-02 |
| 20110131386 | DEVICE, CONTROL METHOD THEREOF, AND PROGRAM - An unmount state storing unit configured to store a state of unmount processing to end access processing to a memory card attached to a device from a host computer is provided. During a period from immediately after a host computer executes the unmount processing until detaching of the memory card is detected, a value of the host computer unmount state storing unit is stored as “true”. During the period in which this value is “true”, a host computer mount request from another host computer is denied. Consequently, after the access processing to the memory card attached to a device by the host computer has ended, contents of the memory card cannot be read from the other host computer while the memory card is still attached. | 2011-06-02 |
| 20110131387 | MANAGING UNALLOCATED STORAGE SPACE USING EXTENTS AND BITMAPS - A computing device executing a file system maintains a search tree that includes extents for managing first regions of unallocated storage space and bitmaps for managing second regions of unallocated storage space. For each region of unallocated storage space, the file system determines whether to manage that region using an extent or a bitmap based on one or more space management criteria. | 2011-06-02 |
| 20110131388 | ACCESSING MULTIPLE PAGE TABLES IN A COMPUTER SYSTEM - A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access. | 2011-06-02 |
| 20110131389 | METHOD FOR UPDATING DATA IN MEMORIES USING A MEMORY MANAGEMENT UNIT - A method for updating, in the background, data stored in physical memories without affecting the current operations performed by the microprocessor. When the update is completely terminated, the application switches from an old version to a new version. This switching occurs by a reconfiguration of the page table during which a first sub-tree structure of pointers accessing the old version of data stored in memories is replaced by a second sub-tree structure of pointers thus allowing access to the new version of data. This update method prevents incoherent transitory states of the system as the latter works with the previous data version until the installation of the new version becomes usable. In the case of an interruption to the update process, the application can always reinitialize the update since the old version of data can be reactivated by returning to the previous configuration of the page table. | 2011-06-02 |
| 20110131390 | Deduplication of Data on Disk Devices Using Low-Latency Random Read Memory - Deduplication of data using a low-latency random read memory (LLRRM) is described herein. Upon receiving a block, if a matching block stored on a disk device is found, the received block is deduplicated by producing an index to the address location of the matching block. In some embodiments, a matching block having a predetermined threshold number of associated indexes that reference the matching block is transferred to LLRRM, the threshold number being one or greater. Associated indexes may be modified to reflect the new address location in LLRRM. Deduplication may be performed using a mapping mechanism containing mappings of deduplicated blocks to matching blocks, the mappings being used for performing read requests. Deduplication described herein may reduce read latency as LLRRM has relatively low latency in performing random read requests relative to disk devices. | 2011-06-02 |
| 20110131391 | Integrated Circuit with Stacked Computational Units and Configurable through Vias - A technique for manufacturing a three-dimensional integrated circuit includes stacking a memory unit on a first die that includes a first computational unit. In this case, the memory unit is included in a second die. A second computational unit that is included in a third die is stacked on the second die. Sets of vertical vias that extend through the first, second, and third dies are connected to connect components of the first and second computational units and the memory unit. Multiplexers of the first and second computational units are configured to selectively couple the components to different ones of the sets of vertical vias responsive to respective control words for each of the first and third dies. | 2011-06-02 |
| 20110131392 | Method and apparatus for scalable and super-scalable information processing using binary gate circuits structured by code-selected pass transistors - A processing space comprises an array of transistors empowered by forming connections through circuit pass transistors to power and data input/output means and connections therebetween through signal pass transistors. By structuring the needed circuits at the site(s) of the data the von Neumann bottleneck is eliminated, which increases the computing power of the apparatus substantially, thus to enable non-stop Information Processing on steady streams of data and code, with no repetitive instruction and data transfers required. That code will identify the physical locations of every transistor in the processing space, and will enable only the pass transistors therein needed to structure the circuits of any arithmetical/logical algorithm in a processing space of any size, speed, and level of computer power. By joining one processing space to another the apparatus also exhibits super-scalability. | 2011-06-02 |
| 20110131393 | Programmable processor architecture - One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations. | 2011-06-02 |
| 20110131394 | APPARATUS AND METHOD FOR USING BRANCH PREDICTION HEURISTICS FOR DETERMINATION OF TRACE FORMATION READINESS - A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored. | 2011-06-02 |
| 20110131395 | METHOD AND PROCESSOR UNIT FOR IMPLEMENTING A CHARACTERISTIC-2-MULTIPLICATION - The method for implementing a characteristic-2-multiplication of at least two input bit strings each having a number N of bits by means of a processor unit suitable for carrying out an integer multiplication, having the following steps:
| 2011-06-02 |
| 20110131396 | TIMING ANALYSIS - One aspect of the present invention provides processor comprising: an execution unit arranged to execute a sequence of instructions each comprising a respective opcode; and a counter coupled to the execution unit and arranged to generate a periodically updated counter value during execution. The execution unit comprises logic configured to identify an opcode representing a trap-if-late instruction in said sequence, and in response to execute the trap-if-late instruction by comparing a target value to the counter value and generating an exception on condition that the counter value represents a time that is late relative to said target value. Another aspect provides a compiler for inserting trap-if-late instructions based on timing constraints in higher-level code. | 2011-06-02 |
| 20110131397 | MULTIPROCESSOR SYSTEM AND MULTIPROCESSOR CONTROL METHOD - A multiprocessor system includes a memory that stores a program; an address notification register; a first processor; and a second processor, in which the first processor stores address information indicating an address from which the program is executed in the address notification register, when the first processor notifies an interrupt request to the second processor and causes the second processor to execute the program, and the second processor obtains the interrupt request notified from the first processor and the address information stored in the address notification register, and starts to execute the program from the address indicated by the obtained address information. | 2011-06-02 |
| 20110131398 | GENERATING DEVICE-SPECIFIC CONFIGURATIONS - An approach to generating device-specific configurations is described. In one approach, a method of generating a device-specific configuration for a target device is described. The method involves receiving a configuration parameter, and receiving command syntax information. A state description is generated from the configuration parameter, with reference to a configuration library. Device information is retrieved from the target device, and the device-specific configuration is generated with reference to the command syntax information, the device information, the state description, and a command library. | 2011-06-02 |
| 20110131399 | Accelerating Wake-Up Time of a System - A method for accelerating a wake-up time of a system is disclosed. The method includes scrubbing and making available for allocation a minimum amount of memory, executing a boot-up operation of an operating system stored on the system, and scrubbing and making available for allocation an additional amount of memory in parallel with and subsequent to the boot-up operation of the operating system. The system may include one or more nodes, each of the nodes having a minimum node resource configuration associated therewith that corresponds to a minimum number of processors included in a node that are required to be activated in order to activate the node. The system may further include one or more partitions, where each partition encompasses at least one node. Each partition may be assigned a priority in relation to other partitions, and the partitions may be successively activated based on the assigned priorities. | 2011-06-02 |
| 20110131400 | METHOD AND COMPUTER SYSTEM FOR THERMAL THROTTLING PROTECTION - An automatic thermal throttling protection method is described. a computer system executes a main BIOS for initializing an embedded controller when the computer system is power on or boots. And the sub BIOS of the embedded controller is also executed. The sub BIOS of the embedded controller obtains an upper temperature limit and a lower temperature limit set by the main BIOS, and obtains a temperature of the CPU through a thermal sensor. The sub BIOS of the embedded controller compares the temperature of the CPU with the upper temperature limit. When the temperature of the CPU is higher than the upper temperature limit, the sub BIOS sends a system control interrupt event to the main BIOS through the embedded controller. When receiving the SCI event, the main BIOS enables a throttling function to perform a throttling operation on the CPU or shuts down the computer system. | 2011-06-02 |
| 20110131401 | AUTHENTICATION SYSTEM FOR GAMING MACHINES AND RELATED METHODS - Various embodiments disclosed herein are directed to gaming devices having a secured basic input/output system (BIOS) and methods for determining the validity of the gaming device's BIOS. According to one embodiment, the gaming device includes a secured module for authenticating the BIOS of the gaming device. During the boot-up process, the secured module selects a challenge from a plurality of challenges, and the selected challenge is issued to the BIOS. The BIOS generates a response to the challenge, and the secured module determines whether the BIOS response matches the calculated response of the secured module. If the BIOS response matches the secured module response, the gaming device continues the boot process. Otherwise, the boot process is halted by the gaming device. | 2011-06-02 |
| 20110131402 | METHOD AND APPARATUS FOR SECURE EXECUTION USING A SECURE MEMORY PARTITION - A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code. | 2011-06-02 |
| 20110131403 | VERIFYING FIRMWARE - Systems, methods, and other embodiments associated with updating firmware for a chip are described. One example method may include performing an external verification of updated firmware received and stored external to the chip to determine if the updated firmware is authentic. Upon determining that the updated firmware is authentic, the updated firmware is loaded into the chip. An internal verification of the updated firmware within the chip is performed to determine that the updated firmware is authentic. The internal verification is assured to succeed based on the external verification. Because the internal verification will succeed, the chip avoids reverting to a default firmware. | 2011-06-02 |
| 20110131404 | APPARATUS AND METHOD FOR VISUALIZING GAME PACKET DATA - An apparatus for visualizing game packet data, includes a packet capturing unit for capturing game packet data transmitted and received during a game service; a decryption unit for decrypting the captured game packet data; and a packet filtering unit for extracting packet data having a valid protocol ID from the game packet data and extracting visualization data from the extracted packet data. Further, the apparatus for visualizing game packet data includes a virtual map creation unit for creating a virtual map using the extracted visualization data; and a visualization unit for displaying the visualization data in the created virtual map. | 2011-06-02 |
| 20110131405 | INFORMATION PROCESSING APPARATUS - An information processing apparatus includes a monitoring unit configured to monitor transition of Web pages displayed by a browser, a determination unit configured to determine whether a current Web page is a page of a particular type when the transition of the Web pages displayed by the browser has occurred, an extraction unit configured to extract a feature quantity from the current Web page when the current Web page is not the page of the particular type, and a providing unit configured to provide a supplementary service related to the current Web page, using the extracted feature quantity. | 2011-06-02 |
| 20110131406 | Secure Communication System For Mobile Devices - A comprehensive solution for providing secure mobile communication is provided. The system includes techniques for authentication and control of communication end-points; chain of trust to ensure devices are certified as authentic; contact list management; peer-to-peer encrypted voice, email, and texting communication; and a technique for bypassing an IP PBX to ensure high levels of security. The system is able to support use of commodity mobile communication devices (e.g., smart phones, laptops) over public carrier networks. | 2011-06-02 |
| 20110131407 | USING A PKCS MODULE FOR OPENING MULTIPLE DATABASES - A security initialization system obtains load data that identifies a first database storing security data to be opened. The initialization system determines that a PKCS-based module for opening the first database is already initialized, where the PKCS-based module is already initialized from previously opening a second database. The initialization system causes the PKCS-based module to create a slot to open the first database, without shutting down the PKCS-based module, in response to determining that the PKCS-based module is already initialized. | 2011-06-02 |
| 20110131408 | DOCUMENT LINK SECURITY - A method, system, and computer usable program product for document link security are provided in the illustrative embodiments. A link is created to a document stored in a data storage device accessible from a data processing system. A characteristic of the document is encrypted in the link. The link with the encrypted characteristic forms an encrypted locator. The encrypted locator may be embedded into another data, such as a page, which may be transmitted with the embedded encrypted locator. A request for the document may be received. The request may include encrypted information. The encrypted information may be the encrypted locator, the encrypted characteristic, or a combination thereof. The encrypted information is decrypted. The document is accessed using the decrypted information. The document is provided in response to the request. | 2011-06-02 |
| 20110131409 | Conditionally intercepting data indicating one or more aspects of a communique to obfuscate the one or more aspects of the communique - A computationally implemented method includes, but is not limited to: intercepting communiqué aspect data that is directed to an end user entity and that indicates one or more aspects of a communiqué directed to the end user entity and that is affiliated with a particular source entity, the intercepting of the communiqué aspect data being in accordance with one or more conditional directives of the end user entity to conditionally obfuscate the communiqué affiliated with the source entity; and transmitting to the end user entity, in response to intercepting the communiqué aspect data and in lieu of transmitting direct indication of the communiqué to the end user entity, covert indicator data that upon reception by the end user entity covertly indicates the one or more aspects of the communiqué. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present disclosure. | 2011-06-02 |
| 20110131410 | WIDE AREA NETWORK ACCESS MANAGEMENT COMPUTER - A system and method for connecting a classified internet protocol (IP) network to a public IP network including an unclassified computing device. The unclassified computing device is a wide area network access management computer which directly connects to a National Security Agency (NSA) High Assurance Internet Protocol Encryptor (HAIPE) device and interfaces between the IP network and the classified IP network. The wide area network access management computer includes a graphical user interface, an internal data network communications interface, an external data network communications interface and a processing unit. The processing unit operates the network interfaces and presents information to the graphical user interface and interprets user input from the graphical user interface. The processing unit also performs the processing and protocols associated with the internal and external networks, performs client processing and allows the user to interact with services on any of the attached networks. | 2011-06-02 |
| 20110131411 | Secure content based routing in mobile ad hoc networks - The present invention describes methods and systems for information dissemination in mobile ad hoc networks founded on Content Based Routing. The method comprises generating a first data packet at a source node, encoding, via an encoding logic within the source node, a plurality of information categories associated with the first data packet in a header of the first data packet, encrypting the first data packet with an encryption key unique to the plurality of information categories, generating a second data packet having a unique dissemination group identity in its header and the encrypted first data packet as a payload of the second data packet, disseminating the second data packet across a dissemination mesh, and receiving the second data packet at a destination node. The system comprises a host within the source node that generates a first data packet comprising a first packet header and the content within a first payload of the first data packet, an identity generator within the source node to receive the first data packet and to generate a dissemination group identity for a dissemination group, an encoding unit to encode within the first packet header a plurality of information categories associated with the content, an encryption unit for encrypting the first data packet with an encryption key unique to the dissemination group identity, such that a second data packet is formed, the second data packet having in a second header the dissemination group identity and in a second payload the encrypted first data packet, and a routing unit to disseminate the second data packet to the dissemination mesh. | 2011-06-02 |
| 20110131412 | HTTP HEADER COMPRESSION - Techniques for HTTP header compression are described herein. In an implementation, an electronic device may be configured to enable compression/decompression of HTTP messages, including compression/decompression of information in the headers of the messages. A HTTP message is generated that contains at least a header and a body. The HTTP message is reformatted to place at least some of the header information into the body. Then, the body of the reformatted message having the header information is compressed to form a compressed HTTP message. Decompression may be applied by a recipient of the compressed HTTP message to reconstruct the original HTTP message. | 2011-06-02 |
| 20110131413 | APPARATUS AND METHOD FOR DYNAMIC UPDATE OF SOFTWARE-BASED IPTV CONDITIONAL ACCESS SYSTEM - The apparatus for dynamic update of a software-based IPTV conditional access system includes: a server master key manager managing a master key and encrypting a conditional access code ID; a conditional access server manager generating and managing a server list, linking and storing an update policy with the conditional access server IDs included in the server list, and controlling execution of the conditional access server; and a conditional access code download server generating an ID map of set of conditional access codes by combining the plurality of conditional access codes and the plurality of conditional access code IDs that are encrypted, and transmitting the ID map of set of conditional access codes and the conditional access code to a receiver. | 2011-06-02 |
| 20110131414 | METHODS AND SYSTEMS FOR END-TO-END SECURE SIP PAYLOADS - Methods, systems and communication nodes for protecting Session Initiation Protocol (SIP) message payloads are described. Different protection techniques can be used to protect SIP payloads depending upon, for example, whether a recipient client application resides in a user equipment or an application server and/or whether a recipient client application resides in a same SIP/IP domain as the target SIP application server which is sending the SIP payloads. | 2011-06-02 |
| 20110131415 | MULTIFACTOR USERNAME BASED AUTHENTICATION - A hashed value is computed from an encrypted password value and a displayed code value from a hardware token at a client. The encrypted password value is based on a username, a context identifier, and a password. The client provides the username and the hashed value to a server. The encrypted password value associated with the username is retrieved at the server. An expected hashed value is computed at the server. The client is validated based on a comparison of the hashed value and the expected hashed value. | 2011-06-02 |
| 20110131416 | MULTIFACTOR VALIDATION OF REQUESTS TO THW ART DYNAMIC CROSS-SITE ATTACKS - An apparatus and a method for validating requests to thwart cross-site attacks is described. A user identifier token, a request identifier token, and a timestamp, are generated at a web application of a server. A Message Authentication Code (MAC) value is formed based on the user identifier token, the request identifier token, and the timestamp using a secret key of the web application. Names of the form elements are enciphered. Fake form elements can also be added to the dynamic form. The entire page also can be enciphered. The dynamic form is sent with the MAC value and the time stamp to a client. A completed form comprising a returned MAC value and a returned timestamp is received from the client. The completed form is validated at the server based on the returned MAC value and the returned timestamp. | 2011-06-02 |
| 20110131417 | IDENTITY BASED NETWORK POLICY ENABLEMENT - Enhanced network data transmission security and individualized data transmission processing can be implemented by intermediaries in a communication path between two endpoint peers individually having the capability to identify and authenticate one or both of the endpoint peers. Communication session establishment, endpoint peer identity processing and authentication and data traffic encryption protocols are modified to allow intermediaries to track the communications between endpoint peers for a particular communication session and obtain information to authenticate the endpoint peers and identify data traffic transmitted between them. Intermediaries can use the identities of one or both of the endpoint peers to enforce identity based rules for processing data traffic between the endpoint peers for a communication session. | 2011-06-02 |
| 20110131418 | METHOD OF PASSWORD MANAGEMENT AND AUTHENTICATION SUITABLE FOR TRUSTED PLATFORM MODULE - A password management and authentication method suitable for an electronic device with a trusted platform module (TPM) is provided. An authentication code is automatically generated according to a TPM password, and the authentication code is stored into an authentication device selected by a user. The authentication device storing the authentication code is directly served as an electronic key of the TPM so that the user needs not to memorize any password and can access data or a hard disk (HD) encrypted by the TPM by simply connecting the authentication device to the electronic device. Thereby, it is very convenient to the user. | 2011-06-02 |
| 20110131419 | SEARCHING DATA - A device or “dongle” ( | 2011-06-02 |
| 20110131420 | COMPUTING ENTITIES, PLATFORMS AND METHODS OPERABLE TO PERFORM OPERATIONS SELECTIVELY USING DIFFERENT CRYPTOGRAPHIC ALGORITHMS - Described herein is a computing platform incorporating a trusted entity, which is controllable to perform cryptographic operations using selected ones of a plurality of cryptographic algorithms and associated parameters, the entity being programmed to record mode of operation information, which is characterised by the algorithms and associated parameters that are selected to perform an operation. | 2011-06-02 |
| 20110131421 | METHOD FOR INSTALLING AN APPLICATION ON A SIM CARD - A method of installing an application on a SIM card is disclosed. A host agent in a host device installs an application on a Subscriber Identity Module card from a non-volatile storage device. The host agent coordinates mutual authentication between the non-volatile storage device and a Subscriber Identity Module card in the host device. If the mutual authentication is successful, the host agent reads an application from the non-volatile storage device and installs the application on the Subscriber Identity Module card, wherein installing the application enables the Subscriber Identity Module card to execute the application. The application may be protected from tampering or unauthorized copying during the host agent transfer by creation of a secure communication channel or transferring encrypted applications. The Subscriber Identity Module card may verify the signature associated with an application before installation to prevent the installation of unauthorized or tampered applications. | 2011-06-02 |
| 20110131422 | Systems and Methods Using Cryptography to Protect Secure Computing Environments - Secure computation environments are protected from bogus or rogue load modules, executables and other data elements through use of digital signatures, seals and certificates issued by a verifying authority. A verifying authority—which may be a trusted independent third party—tests the load modules or other executables to verify that their corresponding specifications are accurate and complete, and then digitally signs the load module or other executable based on tamper resistance work factor classification. Secure computation environments with different tamper resistance work factors use different verification digital signature authentication techniques (e.g., different signature algorithms and/or signature verification keys)—allowing one tamper resistance work factor environment to protect itself against load modules from another, different tamper resistance work factor environment. Several dissimilar digital signature algorithms may be used to reduce vulnerability from algorithm compromise, and subsets of multiple digital signatures may be used to reduce the scope of any specific compromise. | 2011-06-02 |
| 20110131423 | SYSTEM AND METHOD FOR SECURING A USER INTERFACE - The invention relates to a method for securing a user interface that comprises a user interface including one or more peripheral hardware devices of the user interface for interaction with said interface, said peripheral hardware devices being driven by driver software, and one or more applications using the user interface. The invention also relates to a method for securing such an interface. The system of the invention is characterised in that the same further comprises a hypervisor and one or more virtual machines, the drivers of the peripheral hardware devices of the user interface being divided into two portions, i.e. a main portion of said drivers under the control of the hypervisor and a front-end portion of said drivers under the control of the virtual machines, wherein the front-end portion of the securing software component is in charge of managing the front-end portion of the drivers and the main portion of the securing software component is in charge of managing the main portion of the drivers. The invention can particularly be used in onboard systems. | 2011-06-02 |
| 20110131424 | ZERO DIVISORS PROTECTING EXPONENTIATION - The invention relates to a method and to an electronic device for securing the computation of a modular exponentiation x=m | 2011-06-02 |
| 20110131425 | SYSTEMS AND METHODS FOR POWER MANAGEMENT IN A HIGH PERFORMANCE COMPUTING (HPC) CLUSTER - Embodiments of the invention broadly contemplate systems, methods, apparatuses and program products providing a power management technique for an HPC cluster with performance improvements for parallel applications. According to various embodiments of the invention, power usage of an HPC cluster is reduced by boosting the performance of one or more select nodes within the cluster so that the one or more nodes take less time to complete. Embodiments of the invention accomplish this by selectively identifying the appropriate node(s) (or core(s) within the appropriate node(s)) in the cluster and increasing the computing capacity of the selected node(s) (or core(s) within the appropriate node(s)). | 2011-06-02 |
| 20110131426 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF THE INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a connector, a switching module and a controller. The connector is configured to connect an external device. The switching module is configured to switch between output of electric power to a power supply line, which is connected to the connector, and input of electric power from the power supply line. The controller is configured to make the switching module switch to output of electric power to the power supply line and determine whether the external device includes an electric power supply function when the external device is connected to the connector, and to make the switching module switch to input of electric power from the power supply line when the external device includes an electric power supply function. | 2011-06-02 |
| 20110131427 | POWER MANAGEMENT STATES - Utilizing software-based power management states to determine changes in a processing demand and provide changes in energy to be delivered to an electronic system. | 2011-06-02 |
| 20110131428 | Intelligent Power Over Ethernet Power Management for Personal Computing Devices in Enterprise Environments - A Power-over-Ethernet (PoE) communication system dynamically provides power and data communications over a communications link. In an enterprise environment made up of one or more personal computing devices (e.g., personal or laptop computers), a switch determines an allocated amount of power to be supplied to each device. The system includes a switch, a power supply, and one or more personal computing devices having a PoE control module. The PoE control module can be part of, for example, a Power Source Equipment/Powered Device (PSE/PD) system or a LAN-On-Motherboard/Powered Device (LOM/PD) system. A method of dynamically providing power to personal computing devices includes determining the power requirements of each device based on one or more factors, which can include, for example, battery charge status, power load, power mode, etc., of each device. Various algorithms can be used to decide priority in providing power to the devices. | 2011-06-02 |
| 20110131429 | ELECTRIC POWER SUPPLY DEVICE, ELECTRIC POWER SUPPLY METHOD AND ELECTRIC POWER SUPPLY SYSTEM - There is provided an electric power supply device including an electric power supply portion that continuously supplies, to another device with which an agreement about electric power supply has been made, electric power agreed with the other device until one of a time at which the agreement becomes unnecessary and a time determined in advance, the electric power being supplied via a bus line formed by a pair of conductors, and an information communication portion that transmits and receives an information signal indicating information to and from the other device to which the electric power supply portion supplies the electric power, such that the information signal is superimposed on the electric power supplied from the electric power supply portion. The electric power supply portion determines whether to change the electric power to be supplied, in accordance with one of connection of a new device to the bus line and disconnection of the new device from the bus line. | 2011-06-02 |
| 20110131430 | MANAGING ACCELERATORS OF A COMPUTING ENVIRONMENT - Accelerators of a computing environment are managed in order to optimize energy consumption of the accelerators. To facilitate the management, virtual queues are assigned to the accelerators, and a management technique is used to enqueue specific tasks on the queues for execution by the corresponding accelerators. The management technique considers various factors in determining which tasks to be placed on which virtual queues in order to manage energy consumption of the accelerators. | 2011-06-02 |
| 20110131431 | SERVER ALLOCATION TO WORKLOAD BASED ON ENERGY PROFILES - Assigning a server among a plurality of servers to a workload. A workload distributor generates at least one energy profile for each server among the plurality of servers. The workload distributor receives a request to assign a workload, the request having a resource requirement. The workload distributor selects a subset of servers by comparing, for each server at least one energy profile to the resource requirement. The workload distributor selects from the subset of servers a selected server based on the workload and/or energy profile. The workload distributor dispatches the workload to the selected server. | 2011-06-02 |
| 20110131432 | System and Method for Reducing Power Consumption of Memory - Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable. | 2011-06-02 |
| 20110131433 | METHOD FOR COUNTING VECTORS IN REGULAR POINT NETWORKS - The disclosure relates to a method for estimating the number of leader vectors with norm I | 2011-06-02 |
| 20110131434 | IMAGE FORMING APPARATUS AND POWER CONTROL METHOD - A fixing unit fixes a toner image transferred onto a recording medium to the recording medium by heating and pressurizing the toner image. An auxiliary power supply unit includes a charging element that is charged by a power supplied from a main power supply unit. Each of the main power supply unit and the auxiliary power supply unit supplies a power to the fixing unit. A power control unit controls the main power supply unit and the auxiliary power supply unit, so that the power supplied from at least one of the main power supply unit and the auxiliary power supply unit to the fixing unit is kept sufficient. | 2011-06-02 |
| 20110131435 | INFORMATION PROCESSING APPARATUS AND METHOD OF OPERATION OF DATA TRANSFER CIRCUIT - An information processing apparatus transferring data between at least a plurality of processors through first and second routes running through first and second data transfer circuits, which retires the first and second routes so as to reduce the power consumption under the control of a system control device. The system provides a unit for measuring the amounts of data transfer on the first and second routes and measures the usage rates of the first and second routes. It monitors the measured usage rates by the system control device and, when the usage rates are below a predetermined value, controls the first or second data transfer circuit to make it retire the first or second route. | 2011-06-02 |
| 20110131436 | IMAGE FORMING DEVICE AND METHOD THEREFOR - An image forming device that forms an image on a print medium includes a power saving mode shifting part that shifts a mode of the image forming device to a power saving mode, in which power consumption is decreased, when a set power saving mode shifting time has elapsed during a standby mode, an idle time watching part that measures an idle time in the standby mode from a time of a completion of a previous printing to a time of starting a subsequent printing, a counting part that counts a number of times that the idle time has been equal to or longer than a preset idle reference time, wherein the number of times is a count value, and a shifting time setting part that sets the power saving mode shifting time in response to the count value. | 2011-06-02 |
| 20110131437 | INFORMATION PROCESSING DEVICE - According to one embodiment, an information processing apparatus includes a controller, a wakeup controller, a power source, an input controller, and a switch. The controller configured to perform communications with an external device. The wakeup controller configured to wake up a system in accordance with a request from the external device. The power source configured to generate a driving power to drive the controller and to supply the driving power to the controller. An input controller configured to output a signal according to an operation of an input device. The switch configured to instruct the power source to switch between supply and non-supply of the driving power when a predetermined signal is output from the input controller in a state in which the system is not woken up. | 2011-06-02 |
| 20110131438 | Saving Power by Powering Down an Instruction Fetch Array Based on Capacity History of Instruction Buffer - Mechanisms for saving power by powering down an instruction fetch array based on capacity history information of an instruction buffer are provided. The mechanisms operate to receive a current access to an instruction buffer of a processor. The current access is a fetch of a group of one or more instructions to be stored in the instruction buffer. A determination is made, for one or more prior accesses occurring prior to the current access, if a predetermined pattern of capacity availability of the instruction buffer indicates that the instruction buffer is likely to have available capacity to store the group of one or more instructions of the current access. An instruction fetch unit array is powered down in response to a determination that the instruction buffer is not likely to have available capacity to store the group of one or more instructions of the current access. | 2011-06-02 |
| 20110131439 | Jitter Precorrection Filter in Time-Average-Frequency Clocked Systems - Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word. | 2011-06-02 |
| 20110131440 | SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUIT AND DIGITAL CIRCUIT - A semiconductor device includes an analog circuit with a first delay variation in response to a variation in a power supply potential, and a digital circuit with a second delay variation smaller than the first delay variation. The analog circuit is connected to a first power supply potential. The digital circuit includes a detecting circuit detecting a first delay caused by a first circuit connected to the first power supply potential, and a second circuit generating a control signal to control the analog circuit, the second circuit being connected to a second power supply potential whose potential variation is smaller than the first power supply potential. A second delay caused by the second circuit is controlled in correlation to the first delay. | 2011-06-02 |
| 20110131441 | SYSTEM INCLUDING PLURALITY OF STORAGE DEVICES AND DATA TRANSMISSION METHOD FOR THE SAME - A system includes a plurality of storage devices and a controller. The plurality of storage devices are bus-connected to one clock signal line and one data signal line connected to the controller. Each of the plurality of storage devices stores identification information in advance to distinguish the storage devices from each other. The controller transmits data using an identification information transmission period in which one storage device is selected from the plurality of storage devices by transmitting the identification information of the one storage device to the plurality of storage devices via the data signal line and a data transmission period in which the data is transmitted to the one selected storage device. A frequency of a clock signal during the identification information transmission period is set to be lower than a frequency of the clock signal during the data transmission period. | 2011-06-02 |
| 20110131442 | TRACING APPARATUS AND TRACING SYSTEM - A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of the processing units: a counting unit configured to obtain and output a counter value for the corresponding processing unit, the counter value obtained by counting clock signals that are input to the processing unit at an operating frequency thereof; a counter value conversion unit configured to obtain and output a converted counter value for the corresponding processing unit, the converted counter value obtained by converting the counter value based on the assumption that the processing unit has a given reference operating frequency; and an adding unit configured to acquire an operational information set from the corresponding processing unit, and to add the converted counter value to the operational information set. | 2011-06-02 |
