| 22nd week of 2011 patent applcation highlights part 25 |
| Patent application number | Title | Published |
|---|
| 20110128738 | ION GENERATING UNIT AND LIGHTING APPARATUS - In an ion generating unit configured to control driving of a plurality of ion generating elements for generating ions by a controller, the controller drives the ion generating elements upon start up, and is configured to keep driving for a predetermined time period; thereby, the ion concentration of a space upon start up is quickly raised to a predetermined concentration. Further, the controller is configured to drive the ion generating elements intermittently and one after another in order after the predetermined time period has elapsed; the product life is elongated while maintaining the predetermined ion concentration and shortening the driving time of the ion generating elements. | 2011-06-02 |
| 20110128739 | ILLUMINATION SYSTEM, LIGHT SOURCE AND BEAM-CONTROL ELEMENT - The invention relates to an illumination system ( | 2011-06-02 |
| 20110128740 | Mount Adjustable End Cap Clamp Lock for Lighting Systems - A mount adjustable end cap clamp lock used with an adjustable light source with one or both ends collared by a barrel-type end, which is rotatable within an end cap. The end cap has a mounting surface that works in conjunction with a fastener to secure the lighting system to an object. The clamp pad, which may extend beyond the mounting surface, is slidable relative to the end cap. When the fastener is tightened, the clamp pad slides relative to the end cap to press against the barrel to lock the barrel in angular position and secure the light source from rotating when the fastener is tightened to secure the lighting system to an object. The end cap in conjunction with the clamp pad serves a dual purpose. | 2011-06-02 |
| 20110128741 | LIGHTING APPARATUS - A lighting apparatus including a stationary support, a lighting body, a transparent cover, and a self-cleaning layer is provided. The lighting body pivotally connects to the stationary support and includes a holder and a light-emitting diode module. The holder has a first portion and a second portion. The light-emitting diode module is installed in the first portion of the holder. The transparent cover is located between the first portion and the second portion and covers the light-emitting diode module. The self-cleaning layer covers the surface of the transparent cover to filter UV light from the environment. | 2011-06-02 |
| 20110128742 | High efficiency low cost safety light emitting diode illumination device - An illumination device of high intensity light emitting diodes, produces broad illumination with high efficiency, electromagnetic compatibility, and human safety, at low manufacturing cost. Special structures of the device simultaneously provide highly efficient heat sinking, human safety protection, electromagnetic shielding, optical optimization, and 3-dimensional compatibility with traditional incandescent lamp fixtures and applications. Structures, shape, and layers of materials of the device enable industry standard safety requirements to be met. | 2011-06-02 |
| 20110128743 | METHOD FOR PRODUCING LIQUID CRYSTALLINE POLYESTER, LIQUID CRYSTALLINE POLYESTER COMPOSITION, REFLECTOR PLATE AND LIGHT-EMITTING DEVICE - The present invention provides a method for producing a liquid crystalline polyester, the method comprising the steps of reacting monomers to obtain a polycondensate corresponding thereto, granulating the polycondensate to obtain a granule, and subjecting the granule to solid-phase polymerization to obtain a liquid crystalline polyester, wherein the content of iron in the granule to be subjected to the step (C) is 5 ppm by weight or less. According to the present invention, a liquid crystalline polyester having high whiteness and excellent heat resistance can be produced with satisfactory operability. | 2011-06-02 |
| 20110128744 | LIGHT EMITTING DIODE ELEMENT AND LIGHT THEREOF - A LED (light emitting diode) element and a LED light thereof are revealed. The LED element includes a resin base, a LED chip embedded in the resin base and at least two leads formed by an upper part and a lower part. A top end of the upper part is mounted in the resin base and is electrically connected with the LED chip so as to make the LED chip emit light. A bottom end of the upper part extends out of the resin base and connects with a top end of the lower part. The LED element is combined with a light housing to be used. Thereby the lead will not rust easily and break due to bending. This is suitable for outdoor use, environmental protection and energy savings. | 2011-06-02 |
| 20110128745 | LENS AND LED MODULE USING THE SAME - An LED module includes a printed circuit board, an LED mounted on the printed circuit board, and a lens fixed on the printed circuit board and covering the LED for refracting light emitted by the LED. The lens has a concaved inner face for incidence of the light and an opposite convex outer face for the light refracting out thereof. The inner face is aspherical. The outer face is spherical. The inner and outer faces are centrosymmetrical relative to axes, respectively, which are coincident with each other. A curvature of the inner face is gradually reduced from a center to an edge thereof. | 2011-06-02 |
| 20110128746 | LED LAMP - An LED lamp includes a bracket and an LED module. The bracket includes a mounting body configured for fixing the LED lamp at a desired position and a heat dissipation portion extending from the body. The LED module includes a circuit board thermally attached to the heat dissipation portion and an LED connected to the circuit board. A lamp cover is secured to the heat dissipation portion and covers the LED module. | 2011-06-02 |
| 20110128747 | Lamp Holder with an Improved Electric Wire Securing Structure - A lamp holder includes an electrically insulative holder base for holding a lamp bulb, a plastic bracket fastened to the rear side of the holder base, the plastic bracket having a transverse extension lug, a wire hole cut through the transverse extension lug and two wire notches at two sides relative to the transverse extension lug, and two insulated electric wires inserted through the wire hole on the transverse extension lug and turned backwardly apart and respectively attached to the wire notches for electrically connecting two metal terminals in the holder base to an external power source. | 2011-06-02 |
| 20110128748 | METHOD OF CONTROLLING ADAPTIVE HEADLAMP - A method of controlling an adaptive head lamp including a control unit for detecting a driving signal of a vehicle to control an actuator which controls the head lamp in a horizontal or vertical direction in accordance with a control signal of the control unit, may include steps of, a) verifying whether an ignition of the vehicle is turned on or off, b) after the ignition of the vehicle is verified, driving the actuator to move the head lamp to a rightmost or leftmost position in the horizontal direction, or a lowermost or uppermost position in the vertical direction, c) driving the actuator by a predetermined number of pulses previously set in a micro stepping manner in a direction opposite to a driving direction of the headlamp at the step b), and d) setting a position of the head lamp determined at the step c) as an initial position. | 2011-06-02 |
| 20110128749 | LAMP RETAINER FOR CURTAIN SIDE AIRBAG DEPLOYMENT - The present invention provides an automotive interior lamp assembly mounted to an automotive headliner further including a curtain side airbag mounted about the headliner. As the curtain side airbag quickly deploys and forces through the vehicle headliner, the lamp assembly can be forcibly detached from the headliner at a high rate of speed. The present invention provides an improved retainer to better attach the light assembly to the headliner thereby preventing detachment of the lamp assembly from the headliner. The lamp assembly includes a lamp housing having a lamp receiving configured to accept a lamp. The housing further includes a retainer receiving side configured to accept a retainer. The retainer attached to the housing by means of a plurality of attachment members provided on the retainer, and at least one snap member also provided on the retainer. The housing has a plurality of attachment member receiving cavities and at least one snap member receiving cavity. The retainer configured to slidably connect to the lamp housing. The retainer comprised of a generally U-shaped mid-section and at least one extended member sufficiently extending over the headliner as to prevent accidental dislodgment of the lamp assembly. As the curtain side airbag deploys, the extended side members of the retainer prevent dislodgment of the lamp assembly from the headliner. | 2011-06-02 |
| 20110128750 | VEHICULAR LAMP - A vehicular lamp includes a light source; a light guide that guides the light from the light source; and a reflector. The light guide includes an incident portion to which light from the light source is incident, wherein light entering from the incident portion is guided through the light guide; and a plurality of reflection portions that internally reflect a portion of the guided light toward the reflector. The reflector reflects, in a lamp illumination direction, reflection light that is emitted from the light guide following internal reflection by the plurality of reflection portions. | 2011-06-02 |
| 20110128751 | HEADLAMP FOR VEHICLE - Disclosed is a headlamp assembly for a vehicle. The headlamp assembly may include an LED module arranged in a housing of the headlamp, a reflector disposed in the housing and receiving a light from the LED module, wherein the reflector has uneven parts to disperse and reflect the light in a forward direction of the reflector, and a lens arranged in the front of the reflector. | 2011-06-02 |
| 20110128752 | APPARATUS AND METHOD FOR ATTACHING A FAN OF A LIGHTING APPARATUS AND LIGHTING APPARATUS - The present invention relates to a device for attaching a fan of a lighting apparatus, characterized in that the device comprises at least one mounting element for mounting the fan and at least one mounting device for mounting the device inside the lighting apparatus. The invention further relates to a lighting apparatus of a vehicle, comprising a light source, a fan and a housing, wherein the light source is mounted inside and/or on the housing and wherein the lighting apparatus comprises an fan attachment device of the aforementioned type. | 2011-06-02 |
| 20110128753 | SYSTEM AND METHOD FOR HEAT DISSIPATION FROM AN AUTOMOTIVE LIGHTING ASSEMBLY HAVING A LIQUID COOLING CIRCUIT - An automotive headlamp assembly having a closed-loop cooling circuit. The headlamp assembly includes a housing cooperating with a transparent lens cover to define a chamber. At least one light source is located within the chamber. The cooling circuit has at least one cold plate thermally coupled to the light source. A radiator is fluidly coupled to the cold plate by a plurality of tubes. The tubes are oriented at least partially upwardly and configured to circulate a fluid through the cooling circuit as a result of heating and cooling of the fluid therein. | 2011-06-02 |
| 20110128754 | LIGHT SOURCE UNIT AND VEHICULAR LAMP - A vehicular lamp includes a light source unit that is attached to one of a lamp body and a reflector. The light source unit includes a semiconductor light emitting element that is a light source; a plurality of conductive members formed into a predetermined three-dimensional shape by press working a conductive metal material; and a housing that is formed of an insulating material. The plurality of conductive members each include: an element mounting portion to which the semiconductor light emitting element is mounted, a heat dissipating portion that dissipates heat generated when the semiconductor light emitting element emits light, and a connecting portion to which a connector that supplies power to the semiconductor light emitting element is connected. The housing holds the plurality of conductive members in a spaced apart state. | 2011-06-02 |
| 20110128755 | AMBIENT MOOD LIGHT IN A SUNROOF OPENING TRIM RING - The present invention provides a lighting assembly wherein a trim ring, containing a lighting assembly, is mounted on a vehicle headliner. The lighting assembly contains a lighting element having a light engine. The light engine having a housing and a light source mounted within the housing. The housing optionally containing a circuit board adapted to control light emitting from the light source. The light source contained within the housing may either be an LED or a traditional light bulb. The light source may optionally be colored, or textured, to provide unique ambient mood light options. The assembly further provides a light pipe having at least one light pipe aperture. The lighting element positioned adjacent, or connected to, the light pipe aperture. The light source in the lighting element directs light down the light pipe thereby creating a uniform output of light along the light pipe. Light from the light pipe is directed into the vehicle interior, mainly onto the vehicle headliner, thereby creating ambient mood lighting within the automotive interior. | 2011-06-02 |
| 20110128756 | BACKLIGHT ASSEMBLY - A backlight assembly includes a plurality of point light sources, a light guide plate (“LGP”) and a printed circuit board (“PCB”). The LGP has a light incident face in which light is incident, a side surface extending from an edge portion of the light incident face, and a fixing groove which is formed from the side surface toward an inner portion thereof. The PCB includes a point light source disposing portion in which the point light sources are disposed along a first direction, an extending portion extending from the point light disposing portion along a second direction substantially perpendicular to the first direction, and a protrusion which is fixed at an end portion of the extending portion. The protrusion of the PCB is coupled with the fixing groove of the LGP. | 2011-06-02 |
| 20110128757 | Backlight Module Having a Light Guide Plate with Prismatic Structures and Manufacturing Method Thereof - A backlight module having a light guide plate with prismatic structures and a manufacturing method thereof are provided. The backlight module includes a light guide plate, a brightness enhancement film, and a light source module. The light guide plate includes a first surface and a second surface opposite to each other. The first surface has prismatic structures disposed side by side thereon. Each of the prismatic structures includes a first slope and a second slope being adjacent to each other and having an included angle with respect to the first surface, respectively. The included angles are equivalent. The brightness enhancement film includes a third surface and a fourth surface opposite to each other. The third surface faces the second surface. The fourth surface has prisms disposed side by side thereon along the extending direction of the prismatic structure. The brightness enhancement film has an optimum incident angle associated with an angle of the prism and corresponding to the included angles. The light source module is disposed beside the light guide plate along the extending direction of the prismatic structure. | 2011-06-02 |
| 20110128758 | SERIES RESONANT CONVERTER - A series resonant converter circuit that reduces power loss is provided that includes an inverter circuit having at least a pair of first and second switching elements that is connected between DC input terminals, a transformer connected to this inverter circuit, a resonant inductance means that are connected in series to a primary winding wire or a secondary winding wire of the transformer, a primary-side resonant capacitor that is connected in series to the resonant inductance means through the first or second switching element, first and second secondary-side resonant capacitors that are connected to each other in series between the DC input terminals, first and second unidirectional elements that are connected to each other in series between the DC output terminals, and a resonant inductance means that cooperates with resonant capacitance from the primary-side resonant capacitor and the first and second secondary-side resonant capacitors to resonate in series. | 2011-06-02 |
| 20110128759 | BI-DIRECTIONAL DC-DC CONVERTER AND METHOD FOR CONTROLLING THE SAME - A bi-directional DC-DC converter has a transformer for connecting a voltage type full bridge circuit connected to a first power source and a current type switching circuit connected to a second power source. A voltage clamping circuit constructed by switching elements and a clamping capacitor is connected to the current type switching circuit. The converter has a control circuit for cooperatively making switching elements operative so as to control a current flowing in a resonance reactor. | 2011-06-02 |
| 20110128760 | APPARATUS AND METHOD FOR DC/AC SYSTEMS TO RIDE THROUGH GRID TRANSIENTS - A converter system comprises a DC to AC converter, a maximum power point tracking device, and an array-side control. The DC link converts DC from a photovoltaic array to AC for a grid. The maximum power point tracking device is coupled to the array. The array-side control, which is coupled to the DC to AC converter and the device, prevents overvoltage in the DC bus of the DC to AC converter using array voltage and current data from the device and DC bus voltage data from the DC to AC converter during a grid transient by adjusting a maximum power point of the array to increase array voltage. | 2011-06-02 |
| 20110128761 | CONTINUOUSLY VARIABLE SWITCHED CAPACITOR DC-DC VOLTAGE CONVERTER - A voltage converter is switched among two or more modes to produce an output voltage matching a reference voltage that can be of an intermediate level between discrete levels corresponding to the modes. The output voltage is compared with the reference voltage to determine whether to adjust the mode. | 2011-06-02 |
| 20110128762 | VOLTAGE CONVERSION METHOD IN A CONTINUOUSLY VARIABLE SWITCHED CAPACITOR DC-DC VOLTAGE CONVERTER - In a voltage converter, a mode configuration is selected in response to a mode control signal using a switch matrix having two or more mode configurations. Each mode configuration corresponds to one of two or more output signal voltages. The output signal is compared with a reference signal to produce a direction comparison signal. The direction comparison signal is used to produce the mode control signal. | 2011-06-02 |
| 20110128763 | POWER CONVERTING APPARATUS - A power converting apparatus is provided with three sets of half-bridge inverters ( | 2011-06-02 |
| 20110128764 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device includes a first amplifier circuit, a second amplifier circuit, first and second bit lines coupled to the first amplifier circuit, third and fourth bit lines coupled to the second amplifier circuit, a first equalizer circuit being coupled to the first and second bit lines, and a second equalizer circuit being coupled between the second and third bit lines. The second equalizer circuit being closer to the second amplifier circuit than the first equalizer circuit, the first equalizer circuit being closer to the first amplifier circuit than the second equalizer circuit. | 2011-06-02 |
| 20110128765 | IDENTIFYING AND ACCESSING INDIVIDUAL MEMORY DEVICES IN A MEMORY CHANNEL - In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register. | 2011-06-02 |
| 20110128766 | Programmable Resistance Memory - A nonvolatile integrated circuit memory includes mode control circuitry that allows it to be configured as any of a plurality of memory types. | 2011-06-02 |
| 20110128767 | Memory With Intervening Transistor - Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition. | 2011-06-02 |
| 20110128768 | MEMORY INTERFACE CIRCUIT - According to one embodiment, a differential circuit receives, as differential inputs, a readout signal read out from a semiconductor storage element and a reference voltage. An equalizing circuit controls, taking into account a state of a past input signal output from the differential circuit, the potential of the present differential signal output from the differential circuit. A sense amplifier detects a state of the differential signal output from the equalizing circuit. A state holding circuit holds a past state of the differential signal detected by the sense amplifier and supplies the state to the equalizing circuit. | 2011-06-02 |
| 20110128769 | DATA HOLDING DEVICE - A data holding device comprises a loop structure part (LOOP) that holds data by use of logic gates connected in a loop (e.g., inverters INV | 2011-06-02 |
| 20110128770 | STORED MULTI-BIT DATA CHARACTERIZED BY MULTIPLE-DIMENSIONAL MEMORY STATES - Subject matter disclosed herein relates to enhancing data storage density of a memory device. | 2011-06-02 |
| 20110128771 | Resistance Based Memory Circuit With Digital Sensing - A method of sensing a data value stored at a resistance based memory is disclosed. The method includes receiving a data signal from a data cell. The data cell includes a resistance based memory element. A reference signal is received from a reference circuit. The reference circuit includes a resistance based memory element. The data signal is converted to a data output signal having a first frequency. The reference signal is converted to a reference output signal having a second frequency. A first output signal is generated when the first frequency exceeds the second frequency. A second output signal is generated when the second frequency exceeds the first frequency. | 2011-06-02 |
| 20110128772 | Nonvolatile memory cells and nonvolatile memory devices including the same - A nonvolatile memory cell may include a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series. A state of resistance of the variable resistor may be controlled according to voltage applied to the variable resistor. A sum of a magnitude of the first threshold voltage and a magnitude of the second threshold voltage may be greater than a write voltage that is used to perform a write operation on the variable resistor. | 2011-06-02 |
| 20110128773 | NONVOLATILE VARIABLE RESISTANCE MEMORY ELEMENT WRITING METHOD, AND NONVOLATILE VARIABLE RESISTANCE MEMORY DEVICE - To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element ( | 2011-06-02 |
| 20110128774 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element. | 2011-06-02 |
| 20110128775 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA WRITING METHOD THEREFOR - A nonvolatile semiconductor storage device comprises: a first wire and a second wire intersecting each other; a memory cell which is disposed at each intersection of the first wire and the second wire and electrically rewritable and in which a variable resistor for memorizing a resistance value as data in a nonvolatile manner and a rectifying device are connected in series; and a control circuit which applies a voltage necessary for writing of data to the first and second wires. The control circuit precharges a non-selected second wire up to a standby voltage larger than a reference voltage prior to a set operation for programming only a variable resistor connected to selected first and second wires by supplying the reference voltage to a non-selected first wire and the selected second wire, applying a program voltage necessary for programming of the selected variable resistor based on the reference voltage to the selected first wire and applying a control voltage which prevents the rectifying device from turning ON based on the program voltage to the non-selected second wire. | 2011-06-02 |
| 20110128776 | NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING DATA TO NONVOLATILE MEMORY DEVICE - A resistance variable layer has a characteristic in which the resistance variable layer changes to a second resistance state (RL) in such a manner that its resistance value stops decreasing when an interelectrode voltage reaches a first voltage (V | 2011-06-02 |
| 20110128777 | SEMICONDUCTOR DEVICE - The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer. | 2011-06-02 |
| 20110128778 | Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells - A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address. | 2011-06-02 |
| 20110128779 | MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY CELL - Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed. | 2011-06-02 |
| 20110128780 | SEMICONDUCTOR DEVICE - At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved. | 2011-06-02 |
| 20110128781 | SEMICONDUCTOR MEMORY CIRCUIT - A semiconductor memory circuit includes a memory cell array having a plurality of memory cells arranged in a row direction and a column direction; a row selecting unit for selecting the memory cells of the memory cell array aligned in the row direction; a column selecting unit for selecting the memory cells of the memory cell array aligned in the column direction; a plurality of main bit lines for outputting data of the memory cells; a data reading unit for reading data of one of the memory cells selected with the row selecting unit and the column selecting unit; a first multiplexer for connecting one of the main bit lines connected to the memory cell to the data reading unit; and a second multiplexer for connecting an adjacent main bit line situated adjacently outside the main bit line to a charging/discharging voltage source for setting at a specific voltage. | 2011-06-02 |
| 20110128782 | REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE - Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase. | 2011-06-02 |
| 20110128783 | METHOD OF READING NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of reading a nonvolatile memory device may include, after an n | 2011-06-02 |
| 20110128784 | NON-VOLATILE MEMORY DEVICE - An electronic memory device is presented. The device comprises at least one basic unit (FIG. | 2011-06-02 |
| 20110128785 | APPARATUS AND METHOD FOR PROTECTING DATA IN FLASH MEMORY - An apparatus for securely protecting data in a flash memory upon power off is disclosed. In the apparatus, a power detector monitors a voltage output from a power supply unit, and outputs a power fail signal when the voltage drops by a predetermined reference voltage or more. A Programmable Logic Device (PLD) outputs a Write Protect (WP) signal for performing write protection on the flash memory upon receiving the power fail signal from the power detector. A WP controller outputs the WP signal output from the PLD to the flash memory, according to a Ready/Busy (R/B) state of the flash memory. | 2011-06-02 |
| 20110128786 | MEMORY DEVICE - A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines, wherein a first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source. | 2011-06-02 |
| 20110128787 | RIPPLE PROGRAMMING OF MEMORY CELLS IN A NONVOLATILE MEMORY - An electrically erasable programmable read-only memory (EEPROM) with a ripple programming mode. Memory cells in an the EEPROM array include floating-gate transistors with control gates coupled to corresponding word lines, and drain electrodes coupled to corresponding bit lines. A memory cell is programmed by applying a high programming voltage to its control gate along with applying a high programming voltage to its drain. Multiple memory cells within a row can be programmed by applying the programming voltage to the word line of that row, during which multiple bit lines receive their programming voltage, without removing the word line programming voltage when changing the programming from one bit line to another. | 2011-06-02 |
| 20110128788 | NAND FLASH MEMORY - A NAND flash memory having a memory cell array formed of a plurality of blocks including memory cell transistors arranged in a matrix form. The NAND flash memory has a first bit line; a first sense amplifier connected to the first bit line, the first sense amplifier sensing or controlling a potential on the first bit line; a second bit line; and a second sense amplifier connected to the second bit line to sense or control a potential on the second bit line. The NAND flash memory has a first drain side selection gate line; a second drain side selection gate line; a third drain side selection gate line; a fourth drain side selection gate line; a first source side selection gate line; and a second source side selection gate line. The NAND flash memory has a first block; a second block; and a decoder which turns on one of the first and third drain side selection MOS transistors and turns off the other, and which turns on one of the third and fourth drain side selection MOS transistors and turns off the other. | 2011-06-02 |
| 20110128789 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURAL MEMORY CELLS AND A DUMMY CELL COUPLED TO AN END OF A MEMORY CELL - A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells. | 2011-06-02 |
| 20110128790 | ANALOG SENSING OF MEMORY CELLS IN A SOLID-STATE MEMORY DEVICE - A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal. | 2011-06-02 |
| 20110128791 | Method and Apparatus of Performing an Erase Operation on a Memory Integrated Circuit - Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines. | 2011-06-02 |
| 20110128792 | SEMICONDUCTOR STORAGE DEVICE AND BOOSTING CIRCUIT - A boosting circuit includes first to fourth rectification elements, first to fourth MOS transistors, first to fourth capacitors, and a switch circuit. The switch circuit has a low level terminal connected to a first connection node between the first end of the third rectification element and the first end of the fourth rectification element, and a high level terminal connected to a second connection node between a second end of the third MOS transistor and a second end of the fourth MOS transistor. The switch circuit conducts changeover between a voltage at the low level terminal and a voltage at the high level terminal to output a resultant voltage to the output terminal. | 2011-06-02 |
| 20110128793 | PREAMBLE DETECTION AND POSTAMBLE CLOSURE FOR A MEMORY INTERFACE CONTROLLER - A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit. | 2011-06-02 |
| 20110128794 | APPARATUS AND METHOD FOR CONTROLLING OPERATION TIMING IN SEMICONDUCTOR MEMORY DEVICE - An apparatus for controlling an operation timing in a semiconductor memory device, comprising: a shift information generator configured to generate shift information based on data path delay information and latency information; and a shift register configured to shift a command based on the shift information and produce a shifted command to control an operation timing. | 2011-06-02 |
| 20110128795 | SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER - A sense amplifier prevents a reduction in sensing margin occurring when data forms an island pattern. The sense amplifier includes a first inverter having an input terminal connected to a bit line and an output terminal connected to a bar bit line, and a second inverter having an input terminal connected to the bar bit line and an output terminal connected to the bit line. The first and second inverters are configured to receive a pull-up voltage through different pull-up voltage lines, respectively. | 2011-06-02 |
| 20110128796 | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL - A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line. | 2011-06-02 |
| 20110128797 | SENSE AMPLIFYING CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier. | 2011-06-02 |
| 20110128798 | POWER SOURCE CIRCUIT AND SEMICONDUCTOR MEMORY CIRCUIT USING THE SAME - A semiconductor memory circuit includes: a plurality of memory regions; a plurality of driving units configured to be enabled in response to a plurality of enable signals, respectively, and generate a predetermined voltage used for operations of the plurality of memory regions; and an enable control unit configured to count a control pulse and activate one or more enable signals among the plurality of enable signals. | 2011-06-02 |
| 20110128799 | LEVEL SHIFTING CIRCUIT AND NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A nonvolatile semiconductor memory apparatus includes a control unit configured to generate a select signal and a driving control signal in response to a first enable signal and a second enable signal; a level shifting unit configured to enable a first shifting signal or a second shifting signal to a level of a pumping voltage in response to the select signal and the driving control signal; a first switching unit configured to apply a program voltage to a word line when the first shifting signal is enabled to the level of the pumping voltage; and a second switching unit configured to apply a pass voltage to the word line when the second shifting signal is enabled to the level of the pumping voltage. | 2011-06-02 |
| 20110128800 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: an address pad; an address pad buffer section configured to selectively receive a signal of the address pad; a data input buffer section configured to selectively receive the signal of the address pad; and a signal control section configured to selectively provide a path of the signal of the address pad to the address buffer section and the data input buffer section. | 2011-06-02 |
| 20110128801 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - In an organic memory which is included in a radio chip formed from a thin film, data are written to the organic memory by a signal inputted with a wired connection, and the data is read with a signal by radio transmission. A bit line and a word line which form the organic memory are each selected by a signal which specifies an address generated based on the signal inputted with a wired connection. A voltage is applied to a selected memory element. Thus writing is performed. Reading is performed by a clock signal or the like which are generated from a radio signal. | 2011-06-02 |
| 20110128802 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in response to a falling DLL clock signal, the second rising strobe signal having an opposite phase to the first rising strobe signal and being activated at the same timing as the first rising strobe signal; a third strobe signal generation unit configured to generate a first falling strobe signal in response to the falling DLL clock signal; and a fourth strobe signal generation unit configured to generate a second falling strobe signal in response to the rising DLL clock signal, the second falling strobe signal having an opposite phase to the first falling strobe signal and being activated at the same timing as the first falling strobe signal. | 2011-06-02 |
| 20110128803 | CORE VOLTAGE DISCHARGER AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information. | 2011-06-02 |
| 20110128804 | TEST CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME, AND TEST METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS - A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state. | 2011-06-02 |
| 20110128805 | TEST CIRCUIT, NONVOLATILE SEMICONDUCTOR MEMORY APPRATUS USING THE SAME, AND TEST METHOD - A test circuit of a nonvolatile semiconductor memory apparatus includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit is configured to selectively interrupt application of a pumping voltage for a sense amplifier to a sense amplifier input node. The second switching unit is configured to selectively decouple the sense amplifier input node and a sub input/output node. The sub input/output node is coupled with a data storage region. The third switching unit is configured to selectively connect a voltage applying pad and the sense amplifier input node. | 2011-06-02 |
| 20110128806 | SEMICONDUCTOR INTEGRATED CIRCUIT TEST METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit having multiple memory macros, a memory macro test is carried out with high accuracy within a short period of time. A semiconductor integrated circuit test method according to one aspect of the present invention is applicable to inspection of a semiconductor integrated circuit having multiple memory macros, wherein the number of memory macros to be selected in execution of a simultaneous read-out operation for simultaneously reading out written test data is smaller than the number of memory macros to be selected in execution of a simultaneous write-in operation for simultaneously writing in input test data. | 2011-06-02 |
| 20110128807 | MEMORY DEVICE AND SENSE CIRCUITRY THEREFOR - A memory device includes a memory array, sense circuitry coupled to the memory array, and timing circuitry coupled to the sense circuitry. The timing circuitry generates a sense trigger signal to enable the sense circuitry. A strap region is formed adjacent the memory array. A reference word line is coupled to the timing circuitry. The reference word line formed in the strap region. | 2011-06-02 |
| 20110128808 | CURRENT SENSE AMPLIFIER WITH FEEDBACK LOOP - A sensing circuit ( | 2011-06-02 |
| 20110128809 | Method and Apparatus of Addressing A Memory Integrated Circuit - A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes. | 2011-06-02 |
| 20110128810 | MEMORY DEVICE AND MEMORY CONTROL FOR CONTROLLING THE SAME - A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes the internal address and selects a memory unit region. The plurality of memory unit regions store data arranged in a first direction from among two-dimensionally arranged data according to a least-significant bit group of the internal address and store data arranged in a second direction from among the two-dimensionally arranged data according to a most-significant bit group of the address. The internal address control unit successively generates an internal address corresponding to the scan direction according to a scan direction control signal which controls a plurality of scan directions including at least an oblique direction of the two-dimensionally arranged data. | 2011-06-02 |
| 20110128811 | INTERNAL COMMAND GENERATION CIRCUIT - The internal command generation circuit includes a burst pulse generation unit and a pulse shifting unit. The burst pulse generation unit is configured to receive a command for a read or write operation, and generate a first burst pulse. The pulse shifting unit is configured to shift the first burst pulse and generate an internal command. | 2011-06-02 |
| 20110128812 | MULTIPLE-SCREW EXTRUDER - An improved multiple-screw extruder, in particular a twin-screw extruder comprises a housing. Several housing bores are located in at least one section within the housing. The housing bores overlap at least along a partial axial length of the housing. One extruder screw is arranged in each of the several housing bores. At least two motors are provided for the at least two extruder screws. A synchronizing and torsion transmitting device, by means of which both cooperating extruder screws can be synchronized, is provided on both the inlet side and the discharge side. | 2011-06-02 |
| 20110128813 | FLUID MIXER WITH ROTARY SHAFTS AND RELATIVE SEAL UNIT - A fluid mixer comprising a tank designed to contain the fluid to be mixed, a rotary shaft ( | 2011-06-02 |
| 20110128814 | FLUID MIXER AND APPARATUS USING FLUID MIXER - A fluid mixer which can mix fluid while making the distribution of concentration or distribution of temperature of the fluid in the direction of flow uniform without any unevenness and which is both compact and easy to install piping for is provided. This fluid mixer has a fluid inlet, a first flow path connected to the fluid inlet, a spiral flow path connected to the first flow path, a plurality of branch flow paths branched from the spiral flow path, a second flow path to which the plurality of branch flow paths are connected, and a fluid outlet connected to the second flow path, the plurality of branch flow paths branching from different positions of the spiral flow path and being connected with the second flow path at different positions of the second flow path. | 2011-06-02 |
| 20110128815 | CART FOR ULTRASONIC IMAGING APPARATUS AND ULTRASONIC IMAGING SYSTEM - A cart for use with an ultrasonic imaging apparatus, comprising: a supporting part, a cart body and a bottom part; said cart body is connected to the supporting part and the bottom part; said supporting part is provided with an interface thereon for supporting and connecting the ultrasonic imaging apparatus; said cart body is an elevator structure provided with a power cable therein for supplying power to the ultrasonic imaging apparatus; the lower portion of the supporting part and the upper portion of the bottom part are both provided with a power socket; said power cable is a coiled cord structure, and its two ends are connected to the two power sockets; a stretchable elastic component having elastic recovery is provided inside the coiled cord structure of the power cable. | 2011-06-02 |
| 20110128816 | RECEIVED DATA PROCESSING APPARATUS OF PHOTOACOUSTIC TOMOGRAPHY - There is provided a received data processing apparatus of photoacoustic tomography including a minimum constitution unit data composition unit that sequentially reads receiving digital signals from first storage units and composes minimum constitution unit data of the acoustic wave of the minimum constitution units by performing a delay-and-sum process; a second storage unit that stores the minimum constitution unit data of the entire region of the specimen; an image construction unit that constructs an image of the specimen based on the minimum constitution unit data stored in the second storage unit; and a control unit that sequentially stores the minimum constitution unit data calculated by the minimum constitution unit data composition unit in the second storage unit and reads the stored minimum constitution unit data of the entire region of the specimen to transmit the minimum constitution unit data to the image construction unit. | 2011-06-02 |
| 20110128817 | GEOPHYSICAL SIGNAL PROCESSING - A method of processing geophysical signals obtained by monitoring the response of the earth to an source using a plurality of receivers is described including the evaluation of sums or integrals of functions of weighted signal values over a one or multidimensional domain such that the domain is split into a plurality of simplices and the signal values are interpolated across the simplices using a non-linear approximation of the function, the approximation including signals and gradients of the signals, and the evaluated sums or integrals are used to obtain a representation of characteristics of the earth. | 2011-06-02 |
| 20110128818 | EXTRACTION OF DISCRETE RECORDS FROM CONTINUOUS SEISMIC RECORDINGS - An adaptive signal separation is provided that isolates signal data and listening data from multiple continuous overlapping seismic signals. | 2011-06-02 |
| 20110128819 | ACTIVE SONAR SYSTEM AND ACTIVE SONAR METHOD USING FUZZY LOGIC - A computer-implemented method of sonar processing includes identifying, with a processor, a detection having a detection probability value, the detection in a selected beam, wherein the detection is associated with a detection range cell having detection range cell data. The method also includes comparing, with the processor, the detection range cell data with range cell data from a corresponding range cell from at least one overlapping beam overlapping the selected beam. The method also includes updating, with the processor, the detection probability value based upon the comparing. A sonar system uses the above-described method. A computer readable storage medium has instructions thereon to achieve the above-described method. | 2011-06-02 |
| 20110128820 | SYSTEM AND METHOD FOR DISCRIMINATING A SUBSURFACE TARGET IN THE WATER FROM A SURFACE TARGET IN THE WATER - A computer-implemented method of discriminating a surface from a subsurface sound-generating target in the water includes identifying an arrival angle of sound generated by the sound-generating target and received by a sound receiver at a known depth in the water. The method also includes generating a probability density function about the measured arrival angle having a corresponding plurality sound arrival angles and mapping the probability density function about the measured arrival angle to a probability density function of vertex depths. The method also includes calculating a probability that the depth of the sound-generating target is greater than a threshold depth by integrating the probability density function of vertex depth. A computer readable storage medium has instructions for implementing the above method and a system has modules for implementing the above method. | 2011-06-02 |
| 20110128821 | SIGNAL PROCESSING APPARATUS AND METHOD FOR REMOVING REFLECTED WAVE GENERATED BY ROBOT PLATFORM - Disclosed herein is a signal processing apparatus and method for removing a reflected wave generated by a robot platform. The signal processing apparatus includes a transfer function measuring unit for measuring an inter-channel transfer function (IcTF) from signals of a plurality of channels; an impulse response obtaining unit for obtaining an inter-channel impulse response (IcIR) from the IcTF measured by the transfer function measuring unit; and reflected wave removing unit for removing the reflected wave by differentiating a direct wave directly generated by a sound source and the reflected wave with a time delay from the IcIR obtained by the impulse response obtaining unit. The signal processing method of removing a reflected wave includes measuring an IcTF from signals of a plurality of channels; obtaining an IcIR from the measured IcTF; and removing the reflected wave by differentiating a direct wave directly generated by a sound source and a the reflected wave with a time delay from the obtained IcIR. | 2011-06-02 |
| 20110128822 | Underwater Communications - A method of underwater communication between a link initiator and a link receptor, by transmitting a link acquisition waveform from the initiator to the receptor, and establishing communications channel parameters from such a received waveform. Data is then transmitted according to these parameters, which may include range, direction, frequency band and Doppler, with greater efficiency and robustness. | 2011-06-02 |
| 20110128823 | SECURE ELECTRONICS TIMER - A lockable timing apparatus for multiple electronic devices includes an enclosure having a bottom, two side walls, an end wall, and a lid, with a door member opposing the end wall and hingedly attached to a side wall, the bottom, or the lid. At least one notch is in an exposed edge of at least one of the door member and the lid. Inside the enclosure are at least one electrical timer with a power supply cord, and at least two electrical outlets electrically connected to the at least one electrical timer. A locking means is disposed at least in part on the door member for denying unauthorized persons access to the electrical timer and the at least two electrical outlets. | 2011-06-02 |
| 20110128824 | SWIM WATCH - A watch device for use by a swimmer while swimming in a body of water. The watch device may generally comprise a housing, a location determining component disposed within the housing and operable to receive one or more satellite signals to determine a current geographic location of the housing, and a processing system. The processing system may synchronize the location determining component with the swimmer's arm movement so that the location determining component can determine the current geographic location of the housing. | 2011-06-02 |
| 20110128825 | Image Visualizing Device - Electronic paper display comprises analyzer for a plurality of picture image data and controller for automatically changing the term, during which picture is visualized. Analyzer counts number of pictures in one month or one season to have controller automatically change the term per one picture to be visualized. Number of pictures for visualization is reduced when the term per one picture is less than one day. Analyzer checks the attribute data of picture to change the term for visualization. Controller substitutes a temporal anniversary picture for the regular calendar picture for a term and gets back regular picture upon expiration of the term. Electronic paper calendar prepares calendar layouts for horizontally long picture and vertically long picture, respectively, with picture sizes different from each other. Electronic paper calendar prepares calendar layout with even month arranged on the left side and odd month on the right side beneath common picture. | 2011-06-02 |
| 20110128826 | Chronograph timepiece - In a chronograph timepiece of a construction in which chronograph hands are electrically drive-controlled and mechanically zero-restoring-controlled, even when backlash is generated due to zero-restoring, the chronograph hands are normally moved at the time of the next time measurement start. A chronograph timepiece includes a drive control unit starting a time measurement operation in response to a start operation of a start/stop button, electrically hand-movement-driving chronograph hands by driving a chronograph hand movement motor according to the time measured, and resetting the time measurement operation in response to a reset operation of a reset button, and a mechanical structure mechanically zero-restoring and setting the chronograph hands in response to the reset operation, wherein the drive control unit drives the chronograph hand movement motor by a predetermined amount even after the reset operation has been performed. | 2011-06-02 |
| 20110128827 | LIGHT SOURCE UNIT FOR THERMALLY-ASSISTED MAGNETIC RECORDING - Provided is a light source unit the weight of which can be reduced while ensuring power supply to the light source. The light source is configured to form a thermally-assisted magnetic recording head by being joined with a slider including an optical system that propagates light for thermal assist. The light source unit comprises: a unit substrate including a joining surface that faces an power-supply electrode of the slider; a first electrode provided on the joining surface; a second electrode provided on a source-installation surface and electrically connected to the first electrode; and a light source that includes two electrode layers and a light-emission center located in a light-emitting surface. The first and second electrodes eliminate the provision of a terminal electrode for light source on the source-integration surface. As a result, the weight of the light source unit can be reduced. | 2011-06-02 |
| 20110128828 | THERMALLY ASSISTED MAGNETIC RECORDING HEAD - A thermally assisted magnetic recording head is formed of a slider and a magnetic head. The magnetic head includes a main pole, a reader, a coil, a near-field transducer, and a waveguide. A metal film with high thermal conductivity is formed at both sides of the near-field transducer in a width direction of the magnetic head. The use of the metal film as a radiator plate ensures to prevent the temperature of the near-field transducer from becoming locally high. | 2011-06-02 |
| 20110128829 | Optical Recording Head And Optical Recording Apparatus - An optical recording head to record information onto a recording medium utilizing light including; a slider provided to move relatively to the recording medium; a light propagation element provided on a side surface of the slider substantially vertical against a recording surface of the recording medium so as to cause propagation of light incident with a predetermined angle to be irradiated on the recording medium; and, a prism provided on the light propagation element so as to oppose to the side surface of the slider having the light propagation element and to deflect the incident light to be incident into the light propagation element with a predetermined angle. | 2011-06-02 |
| 20110128830 | RECORDING DEVICE AND METHOD, AND COMPUTER PROGRAM - A recording apparatus includes: a recording device for recording content data onto a recordable recording medium with a first recording layer including a first data area and a second recording layer including a second data area; a first reading device reading the address of the position corresponding to the maximum capacity of the first data area; a second reading device reading an address of a layer jump position of the content data; a calculating device for calculating a position to start the recording of the content data such that the layer jump position of the content data is recorded at the position corresponding to the maximum capacity of the first data area; and a first controlling device for controlling the recording device to record first padding data into an area from a start position of the first data area to the position to start the recording of the content data. | 2011-06-02 |
| 20110128831 | METHOD OF USING BACKUP IMAGE OF OPTICAL DISC - This document relates to a method of using a backup image of an optical disc. In an embodiment of this document, data of an optical disc inserted into an Optical Disc Drive (ODD), included in a disc drive integrated with a Solid State Drive (SSD), may be backed up in the SSD in the form of an image file, and access to the optical disc may be bypassed to the backup image file. Backing up the data and bypassing the access may be executed by an application program in the operating system of a host coupled to the disc drive. The application program may be automatically executed when the optical disc is inserted into the ODD or by manipulation of a predetermined button provided in the disc drive. Furthermore, the application program may set the backup image file of the SSD to a virtual drive for the optical disc. | 2011-06-02 |
| 20110128832 | OPTICAL HEAD DEVICE AND OPTICAL DISC APPARATUS - An optical head device and an optical disc apparatus of a simple structure capable of canceling an offset in a tracking error signal caused when an objective lens shifts; in the optical head device, a polarizing hologram | 2011-06-02 |
| 20110128833 | OPTICAL DRIVE DEVICE - An optical drive apparatus that reproduces an optical disk having a land and a groove, the optical drive apparatus including a first tracking-error-signal generating unit that generates a first tracking error signal by using a DPD method, a second tracking-error-signal generating unit that generates a second tracking error signal by using a DPP method, a tracking servo unit that controls the optical system, and a determining unit that determines that an irradiation point of an optical beam is in a non-recorded area. The tracking servo unit switches over to a control based on the second tracking error signal in response to a result of determination by the determining unit during performing a control based on the first tracking error signal. | 2011-06-02 |
| 20110128834 | FILTER AND FILTERING METHOD THEREOF - A filter, including a direct-current (DC) tracking unit, a subtracter and a control unit, is provided. The DC tracking unit extracts a DC component of a radio-frequency (RF) signal and accordingly generates a level signal. The subtracter subtracts the level signal from the RF signal to generate a RF coupling signal. The control unit determines whether to transmit a setting signal to the DC tracking unit according to the level variation of the RF coupling signal, so as to adjust a characteristic parameter of the DC tracking unit. | 2011-06-02 |
| 20110128835 | DRIVING DEVICE AND METHOD, PROGRAM, AND RECORDING MEDIUM - A driving device includes: n pickups; n first control means for respectively controlling the pickups; and a second control means for controlling the n first control means so as to divide data into n pieces of data and to write divided data on a predetermined disc through the n pickups, wherein, when a notification that defect is detected is received from at least one first control means from among the n first control means while data is being written on the disc, the second control means determines a replacement destination, notifies information regarding the replacement destination to the n first control means, and determines the replacement destination in a region where data is continuously read at the time of reproducing of the disc. | 2011-06-02 |
| 20110128836 | OPTICAL RECORDING METHOD AND OPTICAL RECORDING DEVICE - In a dye-type optical recording medium, a write strategy for use in recording is determined based on recommended write strategy parameters recorded on an optical disk ( | 2011-06-02 |
| 20110128837 | METHODS AND DEVICES FOR RECORDING MARKS IN AN INFORMATION LAYER OF AN OPTICAL RECORD CARRIER, AND RECORD CARRIERS FOR USE THEREIN - Methods and devices or writing an optical record carrier, in which a mark representing recorded data is written in a phase-change layer of a record carrier by a sequence of radiation pulses. A rear heating pulse is introduced after a last write pulse and a front heating pulse is introduced before the first write pulse. The power level of the front heating pulse and the power level of the rear heating pulse may be dependent on the length of the mark to be recorded and on properties of the record carrier. | 2011-06-02 |
