| 22nd week of 2011 patent applcation highlights part 13 |
| Patent application number | Title | Published |
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| 20110127536 | ACTIVE MATRIX SUBSTRATE, DISPLAY DEVICE, METHOD FOR INSPECTING THE ACTIVE MATRIX SUBSTRATE, AND METHOD FOR INSPECTING THE DISPLAY DEVICE - An active matrix substrate ( | 2011-06-02 |
| 20110127537 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - A display device comprises: a wiring layer ( | 2011-06-02 |
| 20110127538 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode (OLED) display device, including a first substrate and a second substrate facing each other, a sealant arranged between the first and second substrates to adhere the first and second substrates together, a plurality of interconnections arranged on one of the first and second substrates and a plurality of cladding parts covering at least a portion of each of the plurality of interconnections at a location that corresponds to the sealant, each of the cladding parts including a material having a higher melting point than that of the interconnections. By including the cladding parts, a short circuit between the interconnections caused by heat applied to the sealant can be prevented, and safety and reliability of the OLED display device can be improved. | 2011-06-02 |
| 20110127539 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride semiconductor light-emitting device includes an n type nitride semiconductor layer, a light-emitting layer formed on the n type nitride semiconductor layer, a first p type nitride semiconductor layer formed on the light-emitting layer, an intermediate layer formed on the first p type nitride semiconductor layer to alternately cover and expose a surface of the first p type nitride semiconductor layer, and a second p type nitride semiconductor layer formed on the intermediate layer. The intermediate layer is made of a compound containing Si and N as constituent elements. | 2011-06-02 |
| 20110127540 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate on which a GaN channel layer, an AlGaN electron supply layer and a GaN cap layer are stacked in this order, a gate electrode formed on the GaN cap layer, and a source electrode and a drain electrode formed on the AlGaN electron supply layer so as to interpose the gate electrode. A first recess is formed in the GaN cap layer and being located between the gate electrode and the source electrode. A thickness of the GaN cap layer in a bottom of the first recess is less than that of the GaN cap layer located under the gate electrode. | 2011-06-02 |
| 20110127541 | SEMICONDUCTOR HETEROSTRUCTURE DIODES - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 2011-06-02 |
| 20110127542 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device contains a gate electrode, SiGe layers, Si layers, source/drain regions, and silicide layers. The gate electrode is formed on a semiconductor substrate via a gate insulating film. The SiGe layers are formed on both sides of the gate electrode on the semiconductor substrate. Over half of a region of the SiGe layers is higher than an interface between the semiconductor substrate and the gate insulating film. The Si layers are formed on the SiGe layers. The source/drain regions are formed on both sides of the gate electrode in the Si layers, the SiGe layers and the semiconductor substrate. The silicide layers are formed on the Si layers. | 2011-06-02 |
| 20110127543 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor element disposed on the main surface of the substrate and generating a heat of 200° C. or more, an enclosure surrounding the semiconductor element, and a liquid sealant containing a heat-resistant oil. The enclosure controls the flow of the sealant and seals the semiconductor element. | 2011-06-02 |
| 20110127544 | GROUP III NITRIDE TEMPLATES AND RELATED HETEROSTRUCTURES, DEVICES, AND METHODS FOR MAKING THEM - A templated substate includes a base layer, and a template layer disposed on the base layer and having a composition including a single-crystal Group Ill nitride. The template layer includes a continuous sublayer on the base layer and a nanocolumnar sublayer on the first sublayer, wherein the nanocolumnar sublayer includes a plurality of nano-scale columns. | 2011-06-02 |
| 20110127545 | COMPOUND SEMICONDUCTOR DEVICE WITH T-SHAPED GATE ELECTRODE - A compound semiconductor device includes a compound semiconductor substrate; epitaxially grown layers formed over the compound semiconductor substrate and including a channel layer and a resistance lowering cap layer above the channel layer; source and drain electrodes in ohmic contact with the channel layer; recess formed by removing the cap layer between the source and drain electrodes; a first insulating film formed on an upper surface of the cap layer and having side edges at positions retracted from edges, or at same positions as the edges of the cap layer in a direction of departing from the recess; a second insulating film having gate electrode opening and formed covering a semiconductor surface in the recess and the first insulating film; and a gate electrode formed on the recess via the gate electrode opening. | 2011-06-02 |
| 20110127546 | REFLECTIVE SECONDARY LENS SYSTEM AND SEMICONDUCTOR ASSEMBLY AND ALSO METHOD FOR THE PRODUCTION THEREOF - The present invention relates to a reflective and/or refractive secondary lens system for focusing sunlight onto semiconductor elements, the secondary lens system being characterised according to the invention by a projection which is disposed around the basic body forming the secondary lens system. Furthermore, the present invention relates to a semiconductor assembly which includes the secondary lens system according to the invention, and also to a method for the production of this semiconductor assembly. In particular, this semiconductor assembly represents a concentrating solar cell module. | 2011-06-02 |
| 20110127547 | CAVITY-ENHANCED MULTISPECTRAL PHOTONIC DEVICES - A multispectral pixel structure is provided that includes a plurality of stacked cavity arrangements for emitting or detecting a plurality of specified wavelengths, wherein each stacked cavity arrangement having a photoactive layer for spectral emission or detection of one of the specified wavelengths. The photoactive layer is positioned within a resonant cavity stack and the resonant cavity stack being positioned between two adjacent mirror stacks. A plurality of coupling-matching layers are positioned between one or more of the stack mirror arrangements for controlling optical phase and coupling strength between emitted or incident light and resonant modes in each of the stacked cavity arrangements. | 2011-06-02 |
| 20110127548 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode (OLED) display device, including: a base substrate, on which OLEDs are formed; and an encapsulation substrate disposed on the base substrate, to cover the OLEDs; and a bonding member connecting the base substrate and the encapsulating substrate. The base substrate and/or the encapsulation substrate include bonding grooves, in which the bonding member is disposed. | 2011-06-02 |
| 20110127549 | LIGHT EMITTING DIODE CHIP HAVING DISTRIBUTED BRAGG REFLECTOR AND METHOD OF FABRICATING THE SAME - Exemplary embodiments of the present invention disclose a light emitting diode chip including a substrate having a first surface and a second surface, a light emitting structure arranged on the first surface of the substrate and including an active layer arranged between a first conductive-type semiconductor layer and a second conductive-type semiconductor layer, a distributed Bragg reflector arranged on the second surface of the substrate, the distributed Bragg reflector to reflect light emitted from the light emitting structure, and a metal layer arranged on the distributed Bragg reflector, wherein the distributed Bragg reflector has a reflectivity of at least 90% for light of a first wavelength in a blue wavelength range, light of a second wavelength in a green wavelength range, and light of a third wavelength in a red wavelength range. | 2011-06-02 |
| 20110127550 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Provided is a light emitting device, which includes a second conductive type semiconductor layer, an active layer, a first conductive type semiconductor layer, and a intermediate refraction layer. The active layer is disposed on the second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed on the active layer. The intermediate refraction layer is disposed on the first conductive type semiconductor layer. The intermediate refraction layer has a refractivity that is smaller than that of the first conductive type semiconductor layer and is greater than that of air. | 2011-06-02 |
| 20110127551 | Method for enhancing electrical injection efficiency and light extraction efficiency of light-emitting devices - A method for enhancing electrical injection efficiency and light extraction efficiency of a light-emitting device is disclosed. The method includes the steps of: providing a site layer on the light-emitting device; placing a protection layer on the site layer; forming a cavity through the protection layer and the site layer; and growing a window layer in the cavity. The shape of the window layer can be well controlled by adjusting reactive temperature, reactive time, and N | 2011-06-02 |
| 20110127552 | LIGHT OUTPUT DEVICE - The present invention relates to a light output device ( | 2011-06-02 |
| 20110127553 | LED UNIT - An LED (light emitting diode) unit includes an LED and a lens mounted on the LED. The lens defines a passageway at a central portion thereof. The passageway runs through the lens. The lens includes a concave light emitting surface at a top thereof. Light output from the LED with a small light-emission angle travels directly through the passageway, without a loss of light intensity. | 2011-06-02 |
| 20110127554 | Light emitting device and method of manufacturing the same - A light emitting device may include a substrate, an n-type clad layer, an active layer, and a p-type clad layer. A concave-convex pattern having a plurality of grooves and a mesa between each of the plurality of grooves may be formed on the substrate, and a reflective layer may be formed on the surfaces of the plurality of grooves or the mesa between each of the plurality of grooves. Therefore, light generated in the active layer may be reflected by the reflective layer, and extracted to an external location. | 2011-06-02 |
| 20110127555 | SOLID STATE LIGHT EMITTER WITH PHOSPHORS DISPERSED IN A LIQUID OR GAS FOR PRODUCING HIGH CRI WHITE LIGHT - A solid state white light emitting device includes a semiconductor chip for producing electromagnetic energy and may additionally include a reflector forming an optical integrating cavity. Phosphors, such as semiconductor nanophosphors dispersed in a light transmissive liquid or gas material, within the chip packaging of the solid state device itself, are excitable by the energy from the chip. The device produces output light that is at least substantially white and has a color rendering index (CRI) of 75 or higher. The white light output of the device may exhibit color temperature in one of the following specific ranges along the black body curve: 2,725±145° Kelvin; 3,045±175° Kelvin; 3,465±245° Kelvin; 3,985±275° Kelvin; 4,503±243° Kelvin; 5,028±283° Kelvin; 5,665±355° Kelvin; and 6,530±510° Kelvin. | 2011-06-02 |
| 20110127556 | ORGANIC LIGHT EMITTING DIODE LIGHTING APPARATUS - An organic light emitting diode lighting apparatus includes: a substrate main body including a sealing area and a sealing line surrounding the sealing area; a plurality of first line electrodes of which both ends are located within the sealing area; a plurality of second line electrodes, at least one end of which is located outside the sealing area; an encapsulating member disposed to face the substrate main body; a sealant disposed on the sealing line to bond the substrate main body and the encapsulating member and seal the sealing area; a first connection member coupled to the ends of the plurality of first line electrodes within the sealing area; and a second connection member coupled to the ends of the plurality of second line electrodes outside the sealing area. | 2011-06-02 |
| 20110127557 | LIGHT FIXTURE USING NEAR UV SOLID STATE DEVICE AND REMOTE SEMICONDUCTOR NANOPHOSPHORS TO PRODUCE WHITE LIGHT - For general lighting applications, a semiconductor chip produces near ultraviolet (UV) electromagnetic energy in a range of 380-420 nm, e.g. 405 nm. Semiconductor nanophosphors, typically doped semiconductor nanophosphors, are remotely positioned in an optic of a light fixture. Each phosphor is of a type or configuration that when excited by energy in the 380-420 nm range, emits light of a different spectral characteristic. The nanophosphors together produce light in the fixture output that is at least substantially white and has a color rendering index (CRI) of 75 or higher. In some examples, the fixture optic includes an optical integrating cavity. In the examples using doped semiconductor nanophosphors, the visible white light output exhibits a color temperature in one of the following ranges along the black body curve: 2,725±145° Kelvin; 3,045±175° Kelvin; 3,465±245° Kelvin; and 3,985±275° Kelvin. | 2011-06-02 |
| 20110127558 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF MANUFACTURING THE SAME - There is provided a light emitting diode package and a method of manufacturing the same. A light emitting diode package according to an aspect of the invention may include: an LED chip; a body part having the LED chip mounted thereon; a pair of reflective parts extending from the body part to face each other while interposing the LED chip therebetween, and reflecting light emitted from the LED chip; and a molding part provided between the pair of reflective parts to encapsulate the LED chip and having a top surface whose central region is curved inwards. | 2011-06-02 |
| 20110127559 | LIGHT EMISSION DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A light emission device package including a substrate, an opening portion on the substrate, a heat radiation frame on the opening portion, the heat radiation frame protruding from the substrate, a light emission device chip on the heat radiation frame, and a sealant member on the light emission device chip. | 2011-06-02 |
| 20110127560 | LIGHT-EMITTING DIODE CHIP AND METHOD OF MANUFACTRURING THE SAME - An LED chip includes a substrate and a p-n junction type semiconductor light-emitting structure. The substrate has a first surface and a second surface opposite to the second surface. The p-n junction type semiconductor light-emitting structure is arranged on the first surface of the substrate. A plurality of blind holes is defined in the second surface of the substrate and extends from the second surface towards the first surface. A heat conductive material is filled in each of the plurality of blind holes thereby forming a plurality of heat conductive poles in the plurality of blind holes. | 2011-06-02 |
| 20110127561 | ORGANIC ELECTROLUMINESCENCE DEVICE AND METHOD OF FABRICATING THE SAME - [Problem] The present invention aims to provide an electroluminescence device with an improved intermediate layer, for achieving a superior durability and sustainability performance thereof. | 2011-06-02 |
| 20110127562 | Electronic Substrate Having Low Current Leakage and High Thermal Conductivity and Associated Methods - Electrical substrates having low current leakage and high thermal conductivity, including associated methods, are provided. In one aspect for example, a multilayer substrate having improved thermal conductivity and dielectric properties can include a metal layer having a working surface with a local Ra of greater than about 0.1 micron, a dielectric layer coated on the working surface of the metal layer, and a thermally conductive insulating layer disposed on the dielectric layer, wherein the multilayer substrate has a minimum resistivity between the metal layer and the thermally conductive insulating layer across all of the working surface of at least 1×10 | 2011-06-02 |
| 20110127563 | DIE-BONDING METHOD OF LED CHIP AND LED MANUFACTURED BY THE SAME - A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid-solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time, so as to perform a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C. | 2011-06-02 |
| 20110127564 | METHOD FOR PRODUCING A PLURALITY OF RADIATION-EMITTING COMPONENTS AND RADIATION-EMITTING COMPONENT - A method for producing a plurality of radiation-emitting components includes A) providing a carrier layer having a plurality of mounting regions separated from one another by separating regions; B) applying an interlayer to the separating regions; C) applying a respective radiation-emitting device to each of the plurality of mounting regions; D) applying a continuous potting layer to the radiation-emitting device and the separating regions; E) severing the potting layer and partially severing the interlayer in the separating regions of the carrier layer in a first separating step; and F) partially severing the interlayer and severing the carrier layer in a second separating step, wherein the interlayer is completely severed by the first and the second separating step. | 2011-06-02 |
| 20110127565 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Disclosed is a light emitting device including a second conductive semiconductor layer; an active layer on the second conductive semiconductor layer; a first semiconductor layer on the active layer, the first semiconductor layer having at least one lateral side with a step portion; and a lateral electrode on the step portion formed at the at least one lateral side of the first semiconductor layer. | 2011-06-02 |
| 20110127566 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a light emitting device and a method of manufacturing the same. The light emitting device includes a body, a first electrode installed in the body and a second electrode separated from the first electrode, a light emitting chip formed on one of the first and second electrodes, and electrically connected to the first and second electrodes, and a protective cap projecting between the first and second electrodes. | 2011-06-02 |
| 20110127567 | SUPPORTING SUBSTRATE FOR PREPARING SEMICONDUCTOR LIGHT-EMITTING DEVICE AND SEMICONDUCTOR LIGHT-EMITTING DEVICE USING SUPPORTING SUBSTRATES - The present invention is related to a supporting substrate for preparing a semiconductor light-emitting device employing a multi-layered light-emitting structure thin-film and a method for preparing a semiconductor light-emitting device employing the supporting substrate for preparing a semiconductor light-emitting device. The supporting substrate for preparing a semiconductor light-emitting device is formed by successively laminating a sacrificial layer, a heat-sink layer and a bonding layer on a selected supporting substrate. A method for preparing a semiconductor light-emitting device employing the supporting substrate for preparing a semiconductor light-emitting device includes: preparing a first wafer in which a semiconductor multi-layered light-emitting structure is laminated/grown on an upper part of an initial substrate; preparing a second wafer which is a supporting substrate for preparing a semiconductor light-emitting device; bonding the second wafer on an upper part of the first wafer; separating the initial substrate of the first wafer from a result of the bonding; performing passivation after forming a first ohmic contact electrode on an upper part of the first wafer from which the initial substrate is separated; and preparing a single-chip by severing a result of the passivation. | 2011-06-02 |
| 20110127568 | LATERAL SEMICONDUCTOR LIGHT EMITTING DIODES HAVING LARGE AREA CONTACTS - Light emitting diodes include a diode region having first and second opposing faces that include therein an n-type layer and a p-type layer, an anode contact that ohmically contacts the p-type layer and extends on the first face, and a cathode contact that ohmically contacts the n-type layer and also extends on the first face. The anode and cathode contacts extend on the first face to collectively cover substantially all of the first face. A small gap may be provided between the contacts. | 2011-06-02 |
| 20110127569 | LED MODULE - An LED module A | 2011-06-02 |
| 20110127570 | ORGANIC LIGHT EMITTING DIODE DISPLAY - Disclosed is an organic light emitting diode (OLED) device, which includes: an organic light emitting diode including a first electrode, a second electrode, and an emission layer interposed between the first electrode and the second electrode; a base substrate supporting the organic light emitting diode; and a sealing member disposed on the base substrate while covering the organic light emitting diode. Herein, the sealing member includes a fluorinated epoxy sealing material including a fluorinated epoxy resin. | 2011-06-02 |
| 20110127571 | MIXED SOURCE GROWTH APPARATUS AND METHOD OF FABRICATING III-NITRIDE ULTRAVIOLET EMITTERS - A device for forming a Group III-V semiconductor on a substrate. The device has a primary chamber comprising a substrate and a heat source for heating the substrate to a first temperature. A secondary chamber comprises a metal source and a second heat source for heating the secondary chamber to a second temperature. A first source is provided which is capable of providing HCl to the secondary chamber wherein the HCl and the metal form metal chloride. A metal-organic source is provided. A metal chloride source is provided which comprises a metal chloride. At least one of the metal chloride, the metal-organic and the second metal chloride react with the nitrogen containing compound to form a Group III-V semiconductor on the substrate. | 2011-06-02 |
| 20110127572 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 2011-06-02 |
| 20110127573 | BI-DIRECTIONAL TRANSISTOR WITH BY-PASS PATH AND METHOD THEREFOR - In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction. | 2011-06-02 |
| 20110127574 | DEVICE FOR PREVENTING CURRENT-LEAKAGE - A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem. | 2011-06-02 |
| 20110127575 | SEMICONDUCTOR DEVICE | 2011-06-02 |
| 20110127576 | Bipolar Power Semiconductor Component Comprising a P-type Emitter and More Highly Doped Zones in the P-type Emitter, and Production Method - A bipolar power semiconductor component configured as an IGBT includes a semiconductor body, in which a p-doped emitter, an n-doped base, a p-doped base and an n-doped main emitter are arranged successively in a vertical direction. The p-doped emitter has a number of heavily p-doped zones having a locally increased p-type doping. | 2011-06-02 |
| 20110127577 | Latch-up free vertical TVS diode array structure using trench isolation - A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types. | 2011-06-02 |
| 20110127578 | Manufacturing method for semiconductor device and semiconductor device - A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp (21541/T). | 2011-06-02 |
| 20110127579 | STACKED OXIDE MATERIAL, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming a first oxide component over a base component, causing crystal growth which proceeds from a surface toward an inside of the first oxide component by first heat treatment to form a first oxide crystal component at least partly in contact with the base component, forming a second oxide component over the first oxide crystal component; and causing crystal growth by second heat treatment using the first oxide crystal component as a seed to form a second oxide crystal component. | 2011-06-02 |
| 20110127580 | CAPACITOR-LESS MEMORY DEVICE - Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability. | 2011-06-02 |
| 20110127581 | HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR PHOTOVOLTAIC COMPONENTS - The present invention relates to a support for the epitaxy of a layer of a material of composition Al | 2011-06-02 |
| 20110127582 | MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER - A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to foam at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed. | 2011-06-02 |
| 20110127583 | SEMICONDUCTOR COMPONENT WITH INTEGRATED HALL EFFECT SENSOR - A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration. | 2011-06-02 |
| 20110127584 | METHOD FOR MANUFACTURING INFRARED IMAGE SENSOR AND INFRARED IMAGE SENSOR - In the method for manufacturing the infrared image sensor, first, a thermal insulation layer ( | 2011-06-02 |
| 20110127585 | LATERAL JUNCTION FIELD-EFFECT TRANSISTOR - A lateral junction field-effect transistor capable of preventing the occurrence of leakage current and realizing a sufficient withstand voltage can be provided. In a lateral JFET according to the present invention, a buffer layer is located on a main surface of a SiC substrate and includes a p-type impurity. A channel layer is located on the buffer layer and includes an n-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer. A source region and a drain region are of n-type and formed to be spaced from each other in a surface layer of the channel layer, and a p-type gate region is located in the surface layer of the channel layer and between the source region and the drain region. A barrier region is located in an interface region between the channel layer and the buffer layer and in a region located under the gate region and includes a p-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer. | 2011-06-02 |
| 20110127586 | Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode - A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate. | 2011-06-02 |
| 20110127587 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode. | 2011-06-02 |
| 20110127588 | ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES - A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures. | 2011-06-02 |
| 20110127589 | SEMICONDUCTOR STRUCTURE HAIVNG A METAL GATE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening. | 2011-06-02 |
| 20110127590 | INCREASING STABILITY OF A HIGH-K GATE DIELECTRIC OF A HIGH-K GATE STACK BY AN OXYGEN RICH TITANIUM NITRIDE CAP LAYER - In a replacement gate approach, the oxygen contents of a cap material may be increased, thereby providing more stable characteristics of the cap material itself and of the high-k dielectric material. Consequently, upon providing a work function adjusting metal species at a very advanced manufacturing stage, corresponding additional treatments may be reduced in number or may even be completely avoided, while at the same time threshold voltage variations may be reduced. | 2011-06-02 |
| 20110127591 | METHOD FOR PROGRAMMING AN ANTI-FUSE ELEMENT, AND SEMICONDUCTOR DEVICE - A method for programming an anti-fuse element in which the ratio between current values before and after writing is increased to ensure accuracy in making a judgment about how writing has been performed on the anti-fuse element. The method for programming the anti-fuse element as a transistor includes the steps of applying a prescribed gate voltage to a gate electrode to break down a gate dielectric film, and moving the silicide material of a silicide layer formed on a surface of at least one of a first impurity diffusion region and a second impurity diffusion region, into the gate dielectric film in order to couple the gate electrode with at least the one of the first impurity diffusion region and the second impurity diffusion region electrically through the silicide material. | 2011-06-02 |
| 20110127592 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND SOLID-STATE IMAGING APPARATUS - A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor. | 2011-06-02 |
| 20110127593 | PHOTOELECTRIC CONVERSION DEVICE AND ITS MANUFACTURING METHOD - A photoelectric conversion device in accordance with an aspect of the present invention includes a thin-film transistor formed on a substrate, and a photo diode electrically connected to the thin-film transistor, wherein the photo diode includes a lower electrode connected to a drain electrode of the thin-film transistor, a photoelectric conversion layer formed on the lower electrode, an upper electrode formed from a transparent conductive film on the photoelectric conversion layer, the upper electrode being formed so as to be contained within an upper surface of the photoelectric conversion layer as viewed from a top, and a protective film (compound layer or the like) formed so as to protect a part of an upper surface of the photoelectric conversion layer located outside the upper electrode. | 2011-06-02 |
| 20110127594 | SEMICONDUCTOR DEVICE AND MANUFACTURING THE SAME - A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film. | 2011-06-02 |
| 20110127595 | INTEGRATED CIRCUIT DEVICES INCLUDING A MULTI-LAYER STRUCTURE WITH A CONTACT EXTENDING THERETHROUGH - Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer. | 2011-06-02 |
| 20110127596 | MEMORY STRUCTURE HAVING VOLATILE AND NON-VOLATILE MEMORY PORTIONS - A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells. | 2011-06-02 |
| 20110127597 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device with charge storage layers with high reliability is provided. A plurality of insulating films and a plurality of electrode films 14 are alternately stacked on a substrate 11, and a plurality of selection gate electrodes 17 extending in the X direction and a plurality of bit lines BL extending in the Y direction are provided thereon. U-shaped silicon members 33 are provided, each of which is constituted by a plurality of silicon pillars 31 passing through the electrode films 14 and the selection gate electrode 17, whose upper ends are connected to the bit lines BL, and a connective member 32 connecting lower parts of one pair of the silicon pillars 31 disposed in diagonal positions. The electrode film 14 of each layer is divided for the respective selection gate electrodes 17. One pair of the silicon pillars 31 connected to one another through the connective member 32 are caused to pass through the different electrode films 14 and the different selection gate electrodes 17. All of the U-shaped silicon members 33 connected commonly to one bit line BL are commonly connected to another bit line BL. | 2011-06-02 |
| 20110127598 | FLASH MEMORY DEVICE HAVING A GRADED COMPOSITION, HIGH DIELECTRIC CONSTANT GATE INSULATOR - A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate. | 2011-06-02 |
| 20110127599 | Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing - An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency. | 2011-06-02 |
| 20110127600 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating thereof, including preparing a substrate including a first and second region; forming first and second conductive lines on the first and second region, respectively, the first conductive lines being spaced apart at a first interval and the second conductive lines being spaced apart at a second interval wider than the first interval; forming a dielectric layer in spaces between the first and second conductive lines; etching the dielectric layer until a top surface thereof is lower than top surfaces of the first conductive lines and the second conductive lines; forming a spacer on the etched dielectric layer such that the spacer covers an entire top surface of the etched dielectric layer between the first conductive lines and exposes portions of the etched dielectric layer between the second conductive lines; and removing portions of the etched dielectric layer between the second conductive lines. | 2011-06-02 |
| 20110127601 | Semiconductor Devices and Methods for Making the Same - Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described. | 2011-06-02 |
| 20110127602 | Dual Channel Trench LDMOS Transistors and BCD Process with Deep Trench Isolation - A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor. | 2011-06-02 |
| 20110127603 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region. | 2011-06-02 |
| 20110127604 | SEMICONDUCTOR DEVICE - A semiconductor device having a field plate structure shows a high electric field relaxation effect. The semiconductor device comprises a nitride semiconductor layer formed on a substrate, a source electrode formed so as to electrically contact the nitride semiconductor layer, a drain electrode formed so as to electrically contact the nitride semiconductor layer, a gate electrode formed between the source electrode and the drain electrode on the nitride semiconductor layer, a cap layer formed between the gate electrode and the drain electrode on the surface of the nitride semiconductor layer, a passivation layer covering the cap layer and a field plate formed as part of the gate electrode on the layer formed by the cap layer and the passivation layer, the cap layer being made of a composition containing part of the composition of the material of the nitride semiconductor layer and having a thickness of 2 to 50 nm, the end of the cap layer at the side of the gate electrode being provided with a taper angle of not greater than 60° to form a slope. | 2011-06-02 |
| 20110127605 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a semiconductor substrate configured to include a plurality of trenches therein; a plurality of buried bit lines each configured to fill a portion of each trench; a plurality of active pillars each formed in an upper portion of each buried bit line; a plurality of vertical gates each configured to surround each active pillar; and a plurality of word lines configured to couple neighboring vertical gates with each other. | 2011-06-02 |
| 20110127606 | Lateral super junction device with high substrate-drain breakdwon and built-in avalanche clamp diode - This invention discloses configurations and methods to manufacture lateral power device including a super junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance. | 2011-06-02 |
| 20110127607 | STEPPED-SOURCE LDMOS ARCHITECTURE - A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate. | 2011-06-02 |
| 20110127608 | EXTREMELY THIN SEMICONDUCTOR ON INSULATOR SEMICONDUCTOR DEVICE WITH SUPPRESSED DOPANT SEGREGATION - A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin semiconductor-on-insulator (ETSOI) layer, i.e., a semiconductor layer having a thickness of less than 20 nm. In one embodiment, the method begins with forming a first semiconductor layer and epitaxially growing a second semiconductor layer on a handling substrate. A first gate structure is formed on a first surface of the second semiconductor layer and source regions and drain regions are formed adjacent to the gate structure. The handling substrate and the first semiconductor layer are removed to expose a second surface of the second semiconductor layer that is opposite the first surface of the semiconductor layer. A second gate structure or a dielectric region is formed in contact with the second surface of the second semiconductor layer. | 2011-06-02 |
| 20110127609 | SEMICONDUCTOR MEMORY DEVICE - The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line. | 2011-06-02 |
| 20110127610 | Multiple-Gate Semiconductor Device and Method - A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region. | 2011-06-02 |
| 20110127611 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises an active region having an upper portion and a sidewall portion which are protruded from the top surface of a device isolation region, and a silicide film disposed in the upper portion and the sidewall portion of the active region, thereby effectively reducing resistance in a source/drain region of the semiconductor device. As a result, the entire resistance of the semiconductor device comprising a fin-type gate can be reduced to improve characteristics of the semiconductor device. | 2011-06-02 |
| 20110127612 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region. | 2011-06-02 |
| 20110127613 | HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS USING A MASKING REGIME PRIOR TO GATE PATTERNING - In a replacement gate approach in sophisticated semiconductor devices, the place-holder material of gate electrode structures of different type are separately removed. Furthermore, electrode metal may be selectively formed in the resulting gate opening, thereby providing superior process conditions in adjusting a respective work function of gate electrode structures of different type. In one illustrative embodiment, the separate forming of gate openings in gate electrode structures of different type may be based on a mask material that is provided in a gate layer stack. | 2011-06-02 |
| 20110127614 | REDUCING THE SERIES RESISTANCE IN SOPHISTICATED TRANSISTORS BY EMBEDDING METAL SILICIDE CONTACT REGIONS RELIABLY INTO HIGHLY DOPED SEMICONDUCTOR MATERIAL - In sophisticated transistor elements, an additional silicon-containing semiconductor material may be provided after forming the drain and source extension regions, thereby reducing the probability of forming metal silicide regions, such as nickel silicide regions, which may extend into the channel region, thereby causing a significant increase in series resistance. Consequently, an increased degree of flexibility in adjusting the overall transistor characteristics may be achieved, for instance, by selecting a reduced spacer width and the like. | 2011-06-02 |
| 20110127615 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A high-performance semiconductor apparatus which can be easily introduced into the MOS process, reduces the leakage current (electric field strength) between the emitter and the base, and is insusceptible to noise or surge voltage, and a manufacturing method of the semiconductor apparatus. The emitter | 2011-06-02 |
| 20110127616 | WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE - In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies. | 2011-06-02 |
| 20110127617 | PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY AN EARLY EXTENSION IMPLANTATION - In sophisticated transistor elements, integrity of sensitive gate materials may be enhanced while, at the same time, the lateral offset of extension regions may be reduced. To this end, at least a portion of the extension regions may be implanted at an early manufacturing stage, i.e., in the presence of a protective liner material, which may, after forming the extension regions, be patterned into a protective spacer structure used for preserving integrity of the sensitive gate electrode structure. | 2011-06-02 |
| 20110127618 | PERFORMANCE ENHANCEMENT IN PFET TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY INCREASING DOPANT CONFINEMENT - In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events. | 2011-06-02 |
| 20110127619 | BIOSENSOR DEVICES AND METHOD FOR FABRICATING THE SAME - A biosensor device is provided, including a first semiconductor layer formed over an interconnect structure. A plurality of detection elements are formed in the first semiconductor layer. An optical filter layer is formed over and physically contacts the first semiconductor layer. A second semiconductor layer is formed over the optical filter layer, having opposing first and second surfaces, wherein the first surface physically contacts the optical filter layer. A plurality of isolation walls are formed over the second semiconductor layer from the second surface thereof, defining a plurality of micro-wells over the second semiconductor layer, wherein the isolation walls and the second semiconductor layer comprises the same material, and the micro-wells are correspondingly arranged with the detection elements. An immobilization layer is formed over the second semiconductor layer exposed by the micro-wells and a plurality of capture molecules are formed over the immobilization layer in the mirco-wells. | 2011-06-02 |
| 20110127620 | MEMS INTEGRATED CHIP AND METHOD FOR MAKING SAME - The present invention discloses a MEMS (Micro-Electro-Mechanical System) chip and a method for making the MEMS chip. The MEMS chip comprises: a first substrate having a first surface and a second surface opposing each other; a microelectronic device area on the first surface; a first MEMS device area on the second surface; and a conductive interconnection structure electrically connecting the microelectronic device area and the first MEMS device area. | 2011-06-02 |
| 20110127621 | Electrostatic vibrator and electronic apparatus - A silicon oxide film | 2011-06-02 |
| 20110127622 | Method for Capping a MEMS Wafer and MEMS Wafer - The invention relates to a method for capping a MEMS wafer ( | 2011-06-02 |
| 20110127623 | MEMS Microphone Packaging and MEMS Microphone Module - A method for producing a microphone module includes arranging a MEMS microphone structure on a first surface of a first substrate, the first substrate further including a second surface, which is opposite to the first surface. Furthermore, a cap is arranging on the first surface of the first substrate such that the cap and the first surface enclose the MEMS microphone structure. A readout device for the MEMS microphone structure is arranged on a first surface of a second substrate which further includes a second surface, which is opposite to the first surface. The second surface of the first substrate is attached to the second surface of the second substrate. | 2011-06-02 |
| 20110127624 | MEMS SENSOR - An MEMS sensor is described. The MEMS sensor may include a substrate, a lower thin film provided in contact with a surface of the substrate, and an upper thin film opposed to the lower thin film at an interval on the side opposite to the substrate. | 2011-06-02 |
| 20110127625 | RESONATOR - A resonator comprising a beam formed from a first material having a first Young's modulus and a first temperature coefficient of the first Young's modulus, and a second material having a second Young's modulus and a second temperature coefficient of the second Young's modulus, a sign of the second temperature coefficient being opposite to a sign of the first temperature coefficient at least within operating conditions of the resonator, wherein the ratio of the cross sectional area of the first material to the cross sectional area of the second material varies along the length of the beam, the cross sectional areas being measured substantially perpendicularly to the beam. | 2011-06-02 |
| 20110127626 | Fabrication and Integration of Devices with Top and Bottom Electrodes Including Magnetic Tunnel Junctions - An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs). | 2011-06-02 |
| 20110127627 | SENSING ENVIRONMENTAL PARAMETER THROUGH STRESS INDUCED IN IC - A sensor is provided for sensing a value of a physical parameter characteristic of the sensor's environment. The sensor is implemented in semiconductor technology. A behavior of the sensor's electronic circuitry is affected by stress. The stress is induced by a film covering the circuitry or only part thereof. The stress is caused by the film's material, whose dimensions depend on a value of the parameter. This dependence is different from the 5 dependence of the circuitry's substrate on the same parameter. | 2011-06-02 |
| 20110127628 | ION IMPLANTATION TO CHANGE THE OPTICAL PROPERTIES OF THE PASSIVATION FILMS IN CMOS IMAGER DEVICES - Imager sensor pixels, image sensor and methods for forming image sensors. An image sensor pixel includes a photosensor, a microlens that receives incident light, at least one fabrication layer between the photosensor and the microlens and a passivation layer between the microlens and the at least one fabrication layer. The passivation layer includes a plurality of impurities and passes the incident light from the microlens to the photosensor without substantially redirecting the incident light. | 2011-06-02 |
| 20110127629 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid state imaging device including a semiconductor layer, an insulating material in an opening penetrating a surface of the semiconductor layer, and a protective film that is resistant to etching covering one end of the insulating material on an interior side of the semiconductor layer. | 2011-06-02 |
| 20110127630 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes a trench formed by a shallow trench isolation (STI) process, a channel stop layer formed over a substrate in the trench, an isolation structure filled in the trench, and a photodiode formed in the substrate adjacent to a sidewall of the trench. In more detail of the image sensor, a trench is formed in a substrate through a STI process, and a channel stop layer is formed over the substrate in the trench. An isolation structure is formed in the trench, and a photodiode is fanned in the substrate adjacent to a sidewall of the trench. | 2011-06-02 |
| 20110127631 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT, AND SEMICONDUCTOR DEVICE - A solid-state imaging device includes a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element, a wiring layer that is formed to be layered on the semiconductor substrate, a support substrate that is formed to be layered on the wiring layer, and a groove that is provided between a blade region in the scribe line region and the solid-state imaging element, in the semiconductor substrate and penetrates through the semiconductor substrate. | 2011-06-02 |
| 20110127632 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor memory device includes a substrate, a patterned dielectric layer on the substrate, a patterned conductive layer on the patterned dielectric layer, and a plurality of isolation structures to provide electrical isolation for the patterned conductive layer. Each of the isolation structures includes a base in the substrate, a first bank extending from the base to the patterned conductive layer, and a second bank extending from the base to the patterned conductive layer, the first bank and the second bank being separated from each other over the substrate. | 2011-06-02 |
| 20110127633 | Slotted Configuration for Optimized Placement of Micro-Components using Adhesive Bonding - An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas. | 2011-06-02 |
| 20110127634 | Isolation Structure in a Memory Device - An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner layer comprising a silicon nitride layer is formed on the first and second trenches. A spin on dielectric (SOD) layer comprising polysilazane is formed on the liner layer so as to fill the first and second trenches. A portion of the SOD layer filling the second trench is removed. A portion of the silicon nitride layer, which is disposed on the second trench and is exposed after the removing of the portion of the SOD layer, is oxidized using oxygen plasma and heat generated from the plasma. A high density plasma (HDP) oxide layer is formed to fill the second trench. | 2011-06-02 |
| 20110127635 | Integrated BEOL Thin Film Resistor - In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers. | 2011-06-02 |
