22nd week of 2012 patent applcation highlights part 54 |
Patent application number | Title | Published |
20120137029 | DMA (DIRECT MEMORY ACCESS) COALESCING - In general, in one aspect, a method includes determining a repeated, periodic DMA (Direct Memory Access) coalescing interval based, at least in part, on a power sleep state of a host platform. The method also includes buffering data received at the device in a FIFO (First-In-First-Out) queue during the interval and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval. | 2012-05-31 |
20120137030 | REDUCED PIN COUNT INTERFACE - An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices. | 2012-05-31 |
20120137031 | COMMUNICATION BUS WITH SHARED PIN SET - Bus communications are effected. In accordance with one or more example embodiments, a bus circuit is configured for communicating data in accordance with a main protocol (e.g., as a default), and for communicating with an alternate protocol when signals corresponding to the main protocol are not present. In some implementations, a sense circuit is used with input pins to sense a type of signal for bus communications, and to control communications on the bus with a protocol appropriate for the sensed signals, and for a main protocol when main protocol signals are sensed (e.g., for a default bus operation, or for test operation). | 2012-05-31 |
20120137032 | Digital Device Interconnect Interface and System - A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features. | 2012-05-31 |
20120137033 | MONITOR CIRCUIT, BUS SYSTEM, AND BUS BRIDGE - By connecting, to a bus bridge according to a configuration of a bus system, a monitor circuit including an activation control circuit generating a counter activation signal from an input monitor activation signal, a counter circuit, activated by the counter activation signal, counting the transfer number using a signal of bridge transfer completion indicating an issuance of one transfer from a bus bridge, and outputting a count completion signal when the transfers of the same number as that stuck in the bus bridge indicated by the signal of the transfer number stuck in the bridge is issued when being activated, and a completion control circuit outputting a monitor completion signal upon receiving the count completion signal from the counter circuit, consistency of data may be guaranteed in any bus system without changing the configuration of the bus bridge based on the number of masters accessing the bus bridge. | 2012-05-31 |
20120137034 | COMMUNICATION SYSTEM, MASTER NODE, AND SLAVE NODE - In a node communicably coupled to alternative nodes through a bus, a transmitting unit receives first designation information from an alternative node. When the first designation information designates the node, the transmitting unit successively transmits, on the bus, the first designation information and data. When a request of an active communication occurs in the node, a request unit determines whether to receive a former part of the first identification information indicative of start timing of an active communication mode on the bus. When determining to receive the former part of the first identification information, the request unit transmits, on the bus, collision information at a timing that allows the collision information to collide with a latter part of the first identification information, resulting in rewrite of the first identification information based on bus arbitration, and transmits second designation information meeting the request of the active communication. | 2012-05-31 |
20120137035 | COMPUTING DEVICE AND SERIAL COMMUNICATION METHOD OF THE COMPUTING DEVICE - A serial communication method is applied in a computing device to communicate serially with any external serial device. The computing device includes a baseboard management controller (BMC) and an operating system (OS). The BMC includes at least one physical serial port. The method generates a virtual serial port for the OS by emulating serial port functionality of the physical serial port. When the BMC is initializing the physical serial port and a serial device is connected to the physical serial port, an interrupt handler is activated to handle an interrupt triggered to the BMC by the serial device. The interrupt handler is deactivated when the physical serial port has been initialized by the BMC. | 2012-05-31 |
20120137036 | BASIC INPUT OUTPUT SYSTEM REFRESH APPARATUS - A basic input output system (BIOS) refresh apparatus includes a jumper device, which includes a first pin, a second pin connected to a power source through a resistor, a third pin, and a grounded fourth pin. A master BIOS socket includes a voltage pin connected to the power source and a signal pin connected to the first pin of the jumper device. A slave BIOS socket includes a voltage pin connected to the power source and a signal pin connected to the third pin of the jumper device. Other pins of the master BIOS socket are correspondingly connected to other pins of the slave BIOS socket. The signal pin of the master BIOS socket or the slave BIOS socket receives high level signal to make a corresponding BIOS chip mounted thereon work when the first or third pin is connected to the second pin of the jumper device. | 2012-05-31 |
20120137037 | Data Acquisition Card, Expansion Control System For Data Acquisition Card And Method Thereof - A data acquisition card, an extension control system of data acquisition cards and method thereof are disclosed. The method includes: presetting a card address for each data acquisition card, and presetting a channel address for each data channel in the data acquisition card; the data acquisition card generating a corresponding card address signal after receiving a card beat signal from a user circuit, and judging whether the data acquisition card is gated; and if the data acquisition card is gated, then generating a corresponding channel address signal after receiving a channel beat signal from the user circuit, and gating a data channel corresponding to the channel address signal. The data acquisition card, the extension control system of the data acquisition cards and method thereof have the strong extensibility and high stability. | 2012-05-31 |
20120137038 | ELECTRONIC SYSTEMS SUPPORTING MULTIPLE OPERATION MODES AND OPEARATION METHODS THEREOF - Electronic systems supporting multiple operation modes are provided, wherein the electronic system includes a portable device and a docking system. The portable device at least includes one processing unit and a first operation module, wherein the processing unit includes a plurality of operation frequencies and is operable in a plurality of operation modes, and each operation mode corresponds to an operation frequency. The docking system includes a container for containing the portable device and a second operation module. When the portable device is plugged into the container of the docking system, the portable device receives a signal from the docking system, determines an operation mode of the portable device according to the received signal, adjusts the operation frequency of the processing unit corresponding to the operation mode and selectively applies the first modules or second modules to control the electronic system. | 2012-05-31 |
20120137039 | INFORMATION PROCESSING APPARATUS - An information processing apparatus includes information holding circuits provided respectively for a plurality of transfer source bus control devices, an exclusive bus configured to be capable of mutually connecting the plurality of information holding circuits, and bus selection circuits provided respectively for the plurality of transfer source bus control devices and configured to select one of the exclusive bus and the hierarchical bus as a connection destination of each of the transfer source bus control devices. | 2012-05-31 |
20120137040 | MULTI CHANNEL SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided. | 2012-05-31 |
20120137041 | NETBOOK SYNCHRONIZATION CHIP DEVICE - The present invention discloses a netbook synchronization chip device for data communication and power line connection between a netbook and an external device, including: a first USB interface, coupled to a USB host of the netbook; a second USB interface, coupled to the external device; a memory unit, used for buffering transmission data and storing an application software and a firmware, wherein the application software can be downloaded and executed by the netbook and the external device to transform a peripheral device into a USB device with an accessible root directory; and a synchronization chip controller, used for identifying the external device and performing data communication and power line connection between the netbook and the external device according to the firmware. | 2012-05-31 |
20120137042 | METHOD AND SYSTEM FOR TAKING OVER DEVICES - A method and system for taking over devices are provided. In a solution, a first control board first performs topology discovery on a Peripheral Component Interconnect Express (PCIE) bus, and reserves resources for a Switch (SW) where a NON-Transparent (NT) bridge is located and devices connected to down ports of the SW according to a set resource reservation policy when the topology discovery proceeds to the NT bridge, where the SW and the devices are currently controlled by a second control board. After the SW and the devices are taken over from the second control board, the resource reserved in advance may be allocated to the SW and the devices, so that the devices that are taken over operate normally under control of the first control board. Dual control is implemented through direct taking over devices, and a response speed for processing a device request is improved. | 2012-05-31 |
20120137043 | SECURITY CONFIGURATION FOR MEMORY ACCESS CONTROL - A system for controlling access to resources in an apparatus when the apparatus is not active. Emerging technologies may allow information to be accessed in an apparatus memory without the operating system of the apparatus facilitating the access. In such instances, a subsystem in the apparatus may become active upon reception of wireless signals, and may grant direct access to memory. An access control configuration for the subsystem may be implemented in order to control memory access even when other software systems are inactive. The subsystem access control configuration may be configured (e.g., by the user) when the apparatus is active, and may be established (e.g., installed or updated) upon subsystem activation. | 2012-05-31 |
20120137044 | METHOD AND APPARATUS FOR PROVIDING PERSISTENT COMPUTATIONS - An approach is provided for providing persistent computations. A persistent computation manager determines at least one non-volatile memory space of a device. The persistent computation manager also determines at least one other non-volatile memory space of at least one other device. The persistent computation manager further determines to form a persistent memory address space based, at least in part, on the at least one non-volatile memory space and the at least one other non-volatile memory space. | 2012-05-31 |
20120137045 | EFFICIENTLY DETERMINING IDENTICAL PIECES OF MEMORY USED BY VIRTUAL MACHINES - Efficiently determining identical pieces of memory within a computer memory area, which is occupied by a virtual machine manager hosting multiple guests and the computer memory area being logically separated into memory pages of a unique size. Each guest is inspected for its structural characteristics by the virtual machine manager. The structural characteristics of each guest are compared by the virtual machine manager, wherein memory regions of guests having a similar structure are identified; and the identical memory pages are identified by the virtual machine manager by comparing hash values of memory pages located within memory regions of guests having a similar structure, wherein identical memory pages are determined by comparing hash values calculated over the contents of the memory pages. | 2012-05-31 |
20120137046 | BLOCK CONTROL DEVICE OF SEMICONDUCTOR MEMORY AND METHOD FOR CONTROLLING THE SAME - A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse. | 2012-05-31 |
20120137047 | MEMORY SANITATION USING BIT-INVERTED DATA - Method and apparatus for sanitizing a memory using bit-inverted data. In accordance with various embodiments, a memory location is sanitized by sequential steps of reading a bit value stored in a selected memory cell of the memory, inverting the bit value, and writing the inverted bit value back to the selected memory cell. The memory cell may be erased between the reading and writing steps, as well as after the writing step. Random bit values may be generated and stored to the memory cell, and run-length limited constraints can be used to force bit-inversions. | 2012-05-31 |
20120137048 | METHOD AND APPARATUS FOR IMPROVING ENDURANCE OF FLASH MEMORIES - A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module. | 2012-05-31 |
20120137049 | CODE PATCHING FOR NON-VOLATILE MEMORY - Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored n a trap address register. | 2012-05-31 |
20120137050 | ELECTRONIC DEVICES WITH IMPROVED FLASH MEMORY COMPATIBILITY AND METHODS CORRESPONDING THERETO - An electronic device with improved flash memory compatibility and a method corresponding thereto are disclosed. The electronic device has a NAND flash, a processing unit and a program memory. The program memory stores application software and codes of an operating system, to be retrieved and executed by the processing unit. The application software requests for NAND flash access in accordance with a specific page size. The operating system acts as an intermediary between the application software and the NAND flash and provides a device driver which allocates a number of physical pages of the NAND flash to each virtual page of the specific page size for responding to NAND flash access requests from the application software by referring to the virtual pages. | 2012-05-31 |
20120137051 | MEMORY DEVICE CONFIGURED TO EXECUTE PLURAL ACCESS COMMANDS IN PARALLEL AND MEMORY ACCESS METHOD THEREFOR - According to one embodiment, a memory device includes a memory, a memory interface, a command generator, an access command returning module and a command progress manager. The memory interface accesses the memory in parallel in accordance with access commands. The command generator speculatively issues access commands to the memory interface. The access command returning module returns access commands already issued to the memory interface and unexecuted at a time of occurrence of an error, through corresponding purge responses. The command progress manager updates command progress management information such that the command progress management information indicates the oldest one of the unexecuted access commands. The command generator reissues the returned unexecuted access commands to the memory interface based on the updated command progress management information. | 2012-05-31 |
20120137052 | STORAGE DEVICE AND CONTROL METHOD - According to one embodiment, a storage device includes identification information storage module, location information storage module, determination module, and control module. The identification information storage module stores identification information identifying nonvolatile memories. The location information storage module stores location information identifying bad area in the nonvolatile memories. The determination module determines whether each of pieces of identification information stored in each of the nonvolatile memories matches with any one of the pieces of identification information stored in the identification information storage module. The control module controls one of the nonvolatile memories to prevent one of the pieces of location information from being used, and to prevent access from the host, when the determination module determines that the one of the pieces of identification information of the one of the nonvolatile memories does not match with any one of the pieces of identification information stored in the identification information storage module. | 2012-05-31 |
20120137053 | MICROPROCESSOR - A microprocessor to be connected with an external device is disclosed. The microprocessor includes a non-rewritable memory including a first interrupt vector table storing addresses of plural programs that allow plural types of interrupts, and an area storing a processing program in an address indicated by each of vectors in the first interrupt vector table; a rewritable non-volatile memory including a second interrupt vector table that includes contents identical to contents of the first interrupt vector table; an address changing section that conducts address change from an address for accessing the first interrupt vector table to another address for accessing the second interrupt vector table; a writing section that writes an address of an arbitrary vector of the second interrupt vector table and a processing program stored in the address indicated by the arbitrary vector in the rewritable non-volatile memory upon instruction supplied from the external device. | 2012-05-31 |
20120137054 | METHODS AND SYSTEMS FOR OBJECT LEVEL DE-DUPLICATION FOR SOLID STATE DEVICES - In one aspect, the present disclosure relates to a method of de-duplicating data in a solid state storage device. The method can include receiving a block of data to be written to a solid state storage device, wherein the block of data comprises header portion and a payload, wherein the header portion comprises context information; and determining whether the payload should be de-duplicated prior to storage, based on the context information stored within the header portion; if the payload is determined to be de-duplicated, de-duplicating the payload; and storing the de-duplicated payload to the solid state storage device. | 2012-05-31 |
20120137055 | HYBRID MEMORY SYSTEM AND METHOD MANAGING THE SAME - A hybrid memory system includes a central processing unit, a storage device configured to store user data and code data, and a main memory including a volatile memory and a nonvolatile memory, the main memory being configured to receive data necessary to perform an operation of the central processing unit from the storage device and to store the data, a part of the volatile memory being allocated for a cache for data stored in the nonvolatile memory. | 2012-05-31 |
20120137056 | METHODS AND APPARATUS READING ERASE BLOCK MANAGEMENT DATA - Methods of operating memory devices, and memory devices configured to perform such methods, including reading Erase Block Management (EBM) data from an erase block of an array of memory cells. The EBM data, corresponding to a state of the particular erase block, is stored in control data spaces of a subset of sectors of the particular erase block. | 2012-05-31 |
20120137057 | MEMORY DEVICE - A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer. | 2012-05-31 |
20120137058 | SEMICONDUCTOR DEVICE - A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period. When the second storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a second period. By such a structure, the first period is shorter than the second period. | 2012-05-31 |
20120137059 | CONTENT LOCALITY-BASED CACHING IN A DATA STORAGE SYSTEM - A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like. | 2012-05-31 |
20120137060 | Multi-stage TCAM search - A method to divide a database of TCAM rules includes selecting a rule of the database having multiple don't care values and selecting a bit of the rule having a don't care value, generating two distributor rules based on the selected rule, where the selected bit has a 1 value in one of the distributor rules and a 0 in the other of the distributor rules, associating rules of the database which match each of the distributor rules with the distributor rule they match thereby to create associated databases, and repeating the steps of selecting, generating and associating on the database and the associated databases until the average number of rules in each associated database is at or below a predefined amount. A search unit includes a distributor TCAM and a DRAM search unit having a DRAM storage unit and an associated DRAM search logic unit. The DRAM storage unit has a section for each associated database, where each section is pointed to by a different distributor rule. The DRAM search unit matches the input key to one of the rules in the section pointed to by the matched distributor rule. | 2012-05-31 |
20120137061 | PRE-CACHE SIMILARITY-BASED DELTA COMPRESSION FOR USE IN A DATA STORAGE SYSTEM - A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like. | 2012-05-31 |
20120137062 | LEVERAGING COALESCED MEMORY - Embodiments of the invention relate to efficiently processing read transactions in a shared file system having multiple virtual machines. Each virtual machine in the file system has access to disk storage and local disk cache. At the same time, each virtual machine in the file system has access to remote disk cache of a remote virtual machine. For each read transaction, the local and/or remote disk cache employed for data blocks to support the transaction. Disk storage is employed to support the transaction in the event that the data blocks are not available in the local and/or remote disk cache. | 2012-05-31 |
20120137063 | AUXILIARY STORAGE DEVICE AND PROCESSING METHOD THEREOF - A storage device that receives writing data with a first data size from a host, and writes data with a second data size that is greater than the first data size. The storage device includes a storage area unit formatted and managed by a file format including user data and specific management data, the user data and specific management data having a size smaller than the second data size, a cache memory having a capacity of not less than the second data size and that stores the specific management data, and a controller that controls reading and writing data from and into the storage area unit and the cache memory, when receiving an instruction from the host. | 2012-05-31 |
20120137064 | EFFICIENT DISCARD COMMANDS ON RAID STORAGE DEVICES - A method and system for efficiently freeing storage in a Redundant Array of Independent Disks (RAID) system. A computer system is coupled to storage devices that are organized as a RAID with block-level striping. Each storage device is partitioned into multiple physical sectors. The computer system receives a request to free a contiguous range of logical sectors that are mapped to the storage devices. In response, the computer system issues, for each storage device, a discard command to free contiguous physical sectors in the storage device that correspond to non-contiguous logical sectors. | 2012-05-31 |
20120137065 | Virtual Port Mapped RAID Volumes - Embodiments of the invention provide a method associated with a RAID configuration, wherein RAID storage volumes are created by RAID controllers from a shared pool of disk drives. A specified RAID volume is mapped to a virtual target port, and is accessed by each of one or more servers via the virtual target address. One embodiment of the invention is directed to a method associated with multiple RAID controllers, and a pool of disk drives that comprises multiple storage disks. The method comprises operating one or more of the RAID controllers to each configure one or more RAID volumes from selected storage disks. A unique identifier is assigned to each of the RAID volumes, wherein a specified RAID volume is assigned a specified unique identifier, and a particular RAID controller is provided with ownership of the specified RAID volume at a particular time. The method further comprises using the specified unique identifier in an address to route an I/O message at the particular time between a selected host and the specified RAID volume, wherein the unique identifier includes no information that identifies the particular RAID controller. | 2012-05-31 |
20120137066 | DYNAMIC USE OF RAID LEVELS RESPONSIVE TO WORKLOAD REQUIREMENTS - Data associated with a workload is stored in a first composite array of data storage devices that meets first data storage requirements of the workload, and is automatically stored in a second composite array in response to detecting second data storage requirements of the workload, wherein the second composite array of data storage devices meets the second data storage requirements. The data may be stored in the second composite array by either converting the first array or migrating the data to another array that more closely meets the current data storage requirements of the workload. Alternatively, the array conversion or the data migration may be performed in response to a predictive failure alert from one of the data storage devices in the first composite array. | 2012-05-31 |
20120137067 | Non-Volatile Memory Device And Read Method Thereof - In one embodiment, the method includes receiving a request to read data stored in a first memory cell associated with a first word line, and performing a first read operation on at least one memory cell associated with a second word line in response to the request. The second word line follows the first word line in a word line programming order, and the first read operation is performed over a first time period. The method further includes performing a second read operation on the first memory cell based on output from the first read operation. The second read operation is performed for a second time period, and the first time period is shorter than the second time period if output from performing the first read operation indicates the first memory cell is not coupled. | 2012-05-31 |
20120137068 | COMPUTING DEVICE AND METHOD FOR IDENTIFYING HARD DISKS - A method for identifying hard disks connected to one or more ports of a computing device. The computing device comprises a controller. A first serial-number of each of the hard disks read by the controller is received. A second serial-number corresponding to each drive letter of the hard disk assigned by an operating system of the computing device is read. The first serial-number and the second serial-number is compared to determine associations between the drive letters and the hard disks. The associations are displayed on a display device connected to the computing device. | 2012-05-31 |
20120137069 | Method and System for Initializing Storage in a Storage System - Embodiments of systems and methods for a high availability storage system are disclosed. More particularly, in certain embodiments desired locations of storage devices may be zeroed out during operation of the storage system and areas that have been zeroed out allocated to store data when commands pertaining to that data are received. Specifically, in one embodiment a distributed RAID system comprising a set of data banks may be provided where each data bank in the set of data banks may execute a background process which zeroes areas of the storage devices of the data bank. When a command pertaining to a logical location is received a zeroed area of the physical storage devices on the data bank may be allocated to store data associated with that logical location. | 2012-05-31 |
20120137070 | METHOD AND APPARATUS FOR PROVIDING A PACKET BUFFER RANDOM ACCESS MEMORY - The present invention generally provides a packet buffer random access memory (PBRAM) device including a memory array, a plurality of input ports, and a plurality of serial registers associated with the input ports. The plurality of input ports permit multiple devices to concurrently access the memory in a non-blocking manner. The serial registers enable receiving data from the input ports and concurrently packet data to the memory array. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching. | 2012-05-31 |
20120137071 | Methods for Implementation of an Active Archive in an Archiving System and Managing the Data in the Active Archive - According to the disclosure, a unique and novel archiving system that provides one or more application layer partitions to archive data is disclosed. Embodiments include an active archive including a fixed storage. The active archive can create application layer partitions that associate the application layer partitions with portions of the fixed storage. Each application layer partition, in embodiments, has a separate set of controls that allow for customized storage of different data within a single archiving system. Further, embodiments of methods for ensuring storage capacity in the active archive and the application layer partitions within the active archive is also disclosed. | 2012-05-31 |
20120137072 | HYBRID ACTIVE MEMORY PROCESSOR SYSTEM - In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization. | 2012-05-31 |
20120137073 | Extract Cache Attribute Facility and Instruction Therefore - A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register. | 2012-05-31 |
20120137074 | METHOD AND APPARATUS FOR STREAM BUFFER MANAGEMENT INSTRUCTIONS - A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy. | 2012-05-31 |
20120137075 | System and Method for a Cache in a Multi-Core Processor - The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data. | 2012-05-31 |
20120137076 | Control of entry of program instructions to a fetch stage within a processing pipepline - A processing pipeline | 2012-05-31 |
20120137077 | MISS BUFFER FOR A MULTI-THREADED PROCESSOR - A multi-threaded processor configured to allocate entries in a buffer for instruction cache misses is disclosed. Entries in the buffer may store thread state information for a corresponding instruction cache miss for one of a plurality of threads executable by the processor. The buffer may include dedicated entries and dynamically allocable entries, where the dedicated entries are reserved for a subset of the plurality of threads and the dynamically allocable entries are allocable to a group of two or more of the plurality of threads. In one embodiment, the dedicated entries are dedicated for use by a single thread and the dynamically allocable entries are allocable to any of the plurality of threads. The buffer may store two or more entries for a given thread at a given time. In some embodiments, the buffer may help ensure none of the plurality of threads experiences starvation with respect to instruction fetches. | 2012-05-31 |
20120137078 | Multiple Critical Word Bypassing in a Memory Controller - In one embodiment, a memory controller may be configured to transmit two or more critical words (or beats) corresponding to two or more different read requests prior to returning the remaining beats of the read requests. Such an embodiment may reduce latency to the sources of the memory requests, which may be stalled awaiting the critical words. The remaining words may fill a cache block or other buffer, but may not be required by the sources as quickly as the critical words in order to support higher performance. In some embodiments, once a remaining beat of a block is transmitted, all of the remaining beats may be transmitted contiguously. In other embodiments, additional critical words may be forwarded between remaining beats of a block. | 2012-05-31 |
20120137079 | CACHE COHERENCY CONTROL METHOD, SYSTEM, AND PROGRAM - In a system for controlling cache coherency of a multiprocessor system in which a plurality of processors share a system memory, each of the plurality of processors including a cache and a TLB, the processor includes a TLB controller including a TLB search unit that performs a TLB search and a coherency handler that performs TLB registration information processing when no hit occurs in the TLB search and a TLB interrupt occurs. The coherency handler includes a TLB replacement handler that searches a page table in the system memory and that replaces the TLB registration information, a TLB miss exception handling unit, and a storage exception handling unit. | 2012-05-31 |
20120137080 | SYSTEM AND METHOD FOR CREATING ORDERING POINTS - A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses include an indication that at least a second node includes a shared copy of the data. The F-state enabling the first node to serve as an ordering point in the system capable of responding to requests from other nodes in the system with a shared copy of the data. | 2012-05-31 |
20120137081 | SYSTEM AND METHOD FOR MANAGING A CACHE USING FILE SYSTEM METADATA - Systems and methods for management of a cache are disclosed. In general, embodiments described herein store access counts in file system metadata associated with files in the cache. By encoding access counts in the file system metadata, file I/O operations are reduced. Preferably, the reference count is encoded in an access count timestamp in the file system metadata. The access counts can be decoded based on the difference between the access count time stamp and a base time value, with larger differences reflecting a larger access count. The cache can be aged by advancing the base time value, thereby causing the access count for a file to drop. The base time value can also be stored in file system metadata, thereby reducing file I/O operations when performing aging. | 2012-05-31 |
20120137082 | GLOBAL AND LOCAL COUNTS FOR EFFICIENT MEMORY PAGE PINNING IN A MULTIPROCESSOR SYSTEM - Embodiments of the disclosure relate to the management of memory pages available for pin operations by groups of processors in a multiprocessor system to reduce cache contention and improve system performance. An exemplary embodiment comprises a system that may include interconnected processors, a global count of the number of pages available for pinning, and a plurality of local counts of pages available for pinning by groups of processors. Each local count may be in proximity to a processor group and include a subset of the pages allocated from the global count that are available for pinning by processors in the group. The local counts are adjusted accordingly in response to page pinning and unpinning by processors in the respective processor groups. | 2012-05-31 |
20120137083 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, an update data control circuit is provided, which selectively couples a physical address input data line or an effective address input data line to a common input data line coupled to a physical address cell that stores a physical address page number. A control terminal of an update circuit of the physical address cell is coupled to a page size cell that stores page size information via an update control circuit, to control a write port of the physical address cell with the page size cell. | 2012-05-31 |
20120137084 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device includes: an internal clock signal generation unit configured to generate an internal clock signal in response to an external clock signal; an internal data strobe signal generation unit configured to generate an internal data strobe signal in response to an external data strobe signal; a phase comparison unit configured to compare phases of the internal clock signal and the internal data strobe signal that are used in an enabled write path in response to an internal dummy write command with each other; and an output unit configured to output an output signal of the phase comparison unit. | 2012-05-31 |
20120137085 | COMPUTER SYSTEM AND ITS CONTROL METHOD - Provided is a computer system capable of migrating processing authority for accessing a logical volume between multiple storage apparatuses without causing any overhead in the performance of the path between the multiple storage apparatuses. | 2012-05-31 |
20120137086 | NON-TRANSITORY MEDIUM, ACCESS CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - A file server has a conversion table that stores therein, in a corresponding manner, logical addresses specified by a higher-level layer and physical addresses specified by a disk driver that are address information indicative of a storage area in a disk device. The file server accesses the disk device with a storage area indicated by a physical address as an access destination and counts up the number of access requests to each storage area in a given period of time for each of the logical addresses. The file server then updates the conversion table such that the physical addresses are lined up in a descending order of the logical addresses of a higher number of the access requests counted. Thereafter, the file server changes storage areas of data stored in the storage device based on the conversion table updated. | 2012-05-31 |
20120137087 | STORAGE AREA MANAGEMENT APPARATUS FOR MANAGING STORAGE AREAS PROVIDED FROM UPPER APPARATUSES, AND CONTROL METHOD AND STORAGE MEDIUM THEREFOR - A storage area management apparatus capable of preventing a particular one or ones of storage units of upper apparatuses from being concentratedly accessed, thereby equalizing remaining lifetimes of the storage units. The management apparatus is connected to upper apparatuses through a network, computes lifetime values representing lifetimes of provided areas respectively provided from the storage units of the upper apparatuses, and controls the upper apparatuses based on the computed lifetime values such that provided areas having longer remaining lifetimes are used for data storage with higher priorities. | 2012-05-31 |
20120137088 | ELECTRONIC COMPONENT - An electronic component is provided having a plurality of functionalities. The electronic component comprises a control logic, and a non-volatile storage element. The control logic is coupled to the non-volatile storage element and is adapted for storing values in the non-volatile storage element based on an external input signal to the electronic component, each value being indicative for one or more functionalities of the plurality of functionalities. The control logic is adapted for controlling the availability of the plurality of functionalities based on one or more values stored in the non-volatile storage element and for outputting a confirmation signal being indicative for the availability of the plurality of functionalities. | 2012-05-31 |
20120137089 | STORAGE DEVICE, ELECTRONIC DEVICE, AND ACCESS CONTROL METHOD FOR STORAGE DEVICE - According to one embodiment, a storage device electrically connected to a host includes a storage module, an access restriction module, a first restricted access open module, and a second restricted access open module. The storage module is configured to store therein data. The access restriction module is configured to restrict an access from the host to the storage module after power of the storage device is turned on. The first restricted access open module is configured to open the restricted access from the host to the storage module based on a first command for opening the restricted access from the host. The second restricted access open module is configured to open the restricted access from the host to the storage module based on a second command for carrying out an operation different from the opening of the restricted access from the host. | 2012-05-31 |
20120137090 | Programmable Interleave Select in Memory Controller - In one embodiment, a memory controller may be configured to perform a logic operation, such as a hash function, on selected address bits to produce a bit of channel or bank select. The selected address bits for each select bit may differ, and may be programmable in some embodiments. By combining selected address bits to produce the select bits, the distribution of addresses in a set of regular access patterns may be somewhat randomized to the channels/banks. In one implementation, each select bit may have a corresponding programmable bit vector that specifies the address bits to be included for that select bit. Accordingly, any subset of the address bits may be included in any select bit generation. | 2012-05-31 |
20120137091 | SELECTING A MEMORY FOR STORAGE OF AN ENCODED DATA SLICE IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving an encoded data slice for storage. The method continues with the processing module obtaining metadata associated with the encoded data slice and interpreting the metadata to determine whether the encoded data slice is to be stored in a first access speed memory or a second access speed memory, wherein the first access speed memory has a higher data access rate than the second access speed memory. The method continues with the processing module storing the encoded data slice in a memory device of the first access speed memory when the encoded data slice is to be stored in the first access speed memory and storing the encoded data slice in a memory device of the second access speed memory when the encoded data slice is to be stored in the second access speed memory. | 2012-05-31 |
20120137092 | REMOTE COPY SYSTEM - When performing asynchronous remote copying, whether or not a disaster has occurred at a main site is judged at a remote site; and if the disaster has occurred, recovery processing is immediately started at the remote site. When asynchronous remote copying is performed between a controller and a controller, the controller transfers remote copy target data in a storage apparatus and command information via a remote copy channel to the controller; and after receiving the remote copy target data, the controller stores the remote copy target data in a storage apparatus; and if the controller fails to receive the command information within a set time period, the controller judges that a disaster has occurred, and then outputs the judgment result to a backup center server; and the backup center server executes recovery processing based on data in the storage apparatus when the disaster has occurred. | 2012-05-31 |
20120137093 | RELIABLE WRITE FOR NON-VOLATILE MEMORY - Example embodiments described herein may relate to performing reliable right commands for non-volatile memory devices. | 2012-05-31 |
20120137094 | SNAPSHOT BASED REPLICATION - Embodiments of the invention relate to data replication and block allocation in a file system to support write transactions. Regions in a cluster file system are defined to support a block allocation. Blocks in the defined regions are allocated to support the data replication. A pipeline manager is provided to schedule population of the blocks in the allocated region(s) based upon network characteristics. | 2012-05-31 |
20120137095 | PARTITIONING DATA FOR STORAGE IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving data for storage and determining whether to partition the data in accordance with a data partitioning dispersed storage scheme. When the data is to be partitioned, the method continues with the processing module partitioning the data into a local data portion and a remaining data portion in accordance with the data partitioning dispersed storage scheme, dispersed storage encoding the local data portion to produce a plurality of local encoded data elements in accordance with dispersed storage encoding parameters, sending the plurality of local encoded data elements to an associated dispersed storage network (DSN) memory for storage therein, and sending the remaining data portion to another DS module. | 2012-05-31 |
20120137096 | DUAL WRITING DEVICE AND ITS CONTROL METHOD - A computer system and method which stores path definition information including a storage ID, a volume ID, and validities of paths between a host computer and a first or second storage system identified by the storage ID for accessing a volume identified by the volume ID in one of the storage systems, sends an I/O request via the paths, based on the path definition information, receives information indicating the storage and volume IDs, and updates the path definition information. During initial copying from the second to the first volume, validity corresponding to a first path is set to “Invalid” and validity corresponding to a second path is set to “Valid”. After completion of initial copying, the validity corresponding to the first path included in the path definition information is changed to “Valid.” | 2012-05-31 |
20120137097 | COMMUNICATING CHUNKS BETWEEN DEVICES - An apparatus, for connection to a storage device, comprising: a module for communication with a software application and operable to receive instructions to copy data to the storage device; a chunking and identifier generation module operable to receive the data, to process the data into one or more chunks, to generate a first chunk identifier, representative of the identity of a first of the or each chunk of data and, upon processing of the data, to initiate the issuance of a confirmation signal to the software application indicating that the data has been copied to the storage device; and an interface for communication with the storage device, wherein the interface is operable to send the first chunk identifier to the storage device, and to send the first chunk of data to the storage device upon receipt of a transfer instruction from the storage device. | 2012-05-31 |
20120137098 | VIRTUAL STORAGE MIGRATION METHOD, VIRTUAL STORAGE MIGRATION SYSTEM AND VIRTUAL MACHINE MONITOR - A virtual storage migration method is provided, including: starting a data migration process, and copying, from a source storage device to a destination storage device, a data block in a virtual disk to be migrated; when a VM front-end I/O read request is received, directly reading, corresponding data from the source storage device; when a VM front-end I/O write request is received, determining whether a migration data block that corresponds to the write request is being migrated, if yes, executing a write operation that corresponds to the write request after the migration of the migration data block is completed, if no, executing a write operation that corresponds to the write request; and after all the data blocks in the virtual disk to be migrated are copied to the destination storage device, stopping the data migration, and switching the virtual disk from the source storage device to the destination storage device. | 2012-05-31 |
20120137099 | STORAGE SYSTEM AND STORAGE SYSTEM DATA MIGRATION METHOD - This storage system modifies the migration plan in accordance with the state of the migration destination when a plurality of volumes are migrated all at once. Migration-source volumes are migrated collectively to volumes inside the migration-destination storage apparatus. The user can make settings related to migration-source volumes and migration-destination volumes in a migration plan, and can establish a mid-process control plan for modifying the migration plan in the middle of processing. If a failure occurs in the migration-destination storage apparatus subsequent to the commencement of data migration processing, a processing method controller either cancels or temporarily halts the data migration processing, or changes the migration destination, on the basis of the mid-process control plan. When changing the migration destination, a previously selected alternate storage apparatus is selected as the new migration-destination storage apparatus. When a failure occurs in the alternate storage apparatus, yet another alternate storage apparatus is selected. | 2012-05-31 |
20120137100 | SYSTEM AND METHOD FOR ALLOCATION OF ORGANIZATIONAL RESOURCES - System and methods for storing electronic data is provided, where the system comprises a storage manager component and a management module associated with the storage manager component. The management module is configured to receive information related to storage activities associated with one or more storage operation components within the storage operation system under the direction of the storage manager component. The management module is adapted to predict storage operation resource allocations based on the received information related to the storage activities. | 2012-05-31 |
20120137101 | OPTIMIZING MEMORY MANAGEMENT OF AN APPLICATION RUNNING ON A VIRTUAL MACHINE - A method, system and computer program product for optimizing memory usage of an application running on a virtual machine. A virtual machine memory block is pre-allocated and the average memory usage of the virtual machine is periodically computed using statistics collected from the virtual machine through an API. If the memory usage average becomes higher than a maximum threshold, then a recovery mode is entered by releasing the virtual machine memory block and forcing the running application to reduce its processing activity; optionally, a garbage collector cycle can be forced. If the computed memory usage average becomes lower than a minimum threshold value, which is lower than the maximum threshold value, then a normal mode is entered by re-allocating the virtual machine memory block and forcing the running application to resumes its normal processing activity. Optionally, when the virtual machine is idle, a deep garbage collection is forced. | 2012-05-31 |
20120137102 | CONSUMER APPROACH BASED MEMORY BUFFER OPTIMIZATION FOR MULTIMEDIA APPLICATIONS - A multimedia storage method is provided in which the memory allocations to applications are just the sufficient or right amount and do not over allocate or waste memory resources, thereby ensuring that other applications that need memory can operate properly and efficiently. | 2012-05-31 |
20120137103 | AUTOMATED PAGING DEVICE MANAGEMENT IN A SHARED MEMORY PARTITION DATA PROCESSING SYSTEM - Automated paging device management is provided for a shared memory partition data processing system. The automated approach includes managing a paging storage pool defined within one or more storage devices for holding logical memory pages external to physical memory managed by a hypervisor of the processing system. The managing includes: responsive to creation of a logical partition within the processing system, automatically defining a logical volume in the paging storage pool for use as a paging device for the new logical partition, the automatically defining occurring absent use of a filesystem, with the resultant paging device being other than a file in a filesystem; and automatically specifying the logical volume as a paging space device for the new logical partition and binding the paging space device to the new logical partition, wherein the logical volume is sized to accommodate a defined maximum memory size of the new logical partition. | 2012-05-31 |
20120137104 | ALLOCATION METHOD AND APPARATUS OF MODERATE MEMORY - An allocation method comprises: partitioning moderate memory into a plurality of physical memory pages having predetermined page size according to the predetermined page size; scanning the moderate memory using the predetermined page size and recording the physical address and damage degree of each physical memory page; obtaining the allocation information of the physical memory pages when a memory request is received and allocating physical memory to the request based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information. A moderate memory is scanned and the physical address and damage degree of each physical memory page are recorded, then the physical memory is allocated based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information. | 2012-05-31 |
20120137105 | MEMORY SYSTEM AND RELATED METHOD OF OPERATION - A memory system comprises a translation lookaside buffer (TLB) configured to receive a virtual address and to search for a TLB entry matching the virtual address, and a translation information buffer (TIB) configured to be connected to the TLB and determine whether a physical address corresponding to the virtual address falls into a continuous mapping area if the TLB entry matching the virtual address is not found. | 2012-05-31 |
20120137106 | Dynamic Address Translation With Translation Table Entry Format Control for Identifying Format of the Translation Table Entry - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory. | 2012-05-31 |
20120137107 | METHOD OF DECAYING HOT DATA - Reserve a plurality of blocks in a flash. Write a plurality of hot data into the plurality of blocks in a cyclic and sequential manner. After completing a cycle of writing data and hot data is to be written into the plurality of blocks, send a logic block address corresponding to hot data of a page to a cold/hot data identifying engine if the hot data of the page of a decay block are not updated. And the cold/hot data identifying engine decays a count of a counter corresponding to the logic block address according to the logic block address. | 2012-05-31 |
20120137108 | SYSTEMS AND METHODS INTEGRATING BOOLEAN PROCESSING AND MEMORY - The present disclosure relates to placing a Boolean Processor on a chip with memory to eliminate memory latency issues in computing systems. An asynchronous implementation of a Boolean Processor Switched Memory can theoretically operate at terahertz speed and vastly improve the rate at which computationally relevant data is fed to a microprocessor or microcontroller. Boolean Processor Enhanced Memories hold the promise of increasing memory throughput by several orders of magnitude and shifting the burden of “catching up” to microprocessors and microcontrollers. | 2012-05-31 |
20120137109 | METHOD AND APPARATUS FOR PERFORMING STORE-TO-LOAD FORWARDING FROM AN INTERLOCKING STORE USING AN ENHANCED LOAD/STORE UNIT IN A PROCESSOR - A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and the load do not match, or when a data size of the store is smaller than a data size of the load. The LSU detects a load that interlocks with a store, and determines whether all or only a portion of data bytes needed by the load can be provided by the interlocking store. If it is determined that only a portion of the data bytes needed by the load can be provided by the interlocking store, then that portion of the data bytes is provided by a store data buffer (SDB) and the remaining portion of the data bytes needed by the load is provided by a data cache (DC). Otherwise, the SDB provides all of the data bytes. | 2012-05-31 |
20120137110 | HARDWARE DEVICE FOR PROCESSING THE TASKS OF AN ALGORITHM IN PARALLEL - A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary decisions, includes a plurality of task units for processing data, making decisions and/or processing data and making decisions, including source task units and destination task units. A task interconnection logic means interconnect the task units for communicating actions from a source task unit to a destination task unit. Each of the task units includes a processor for executing only a particular single task of the fixed set of predetermined tasks associated with the algorithm in response to a received request action, and a status manager for handling the actions from the source task units and building the actions to be sent to the destination task units. | 2012-05-31 |
20120137111 | LOOP DETECTION APPARATUS, LOOP DETECTION METHOD, AND LOOP DETECTION PROGRAM - A loop detection method, system, and article of manufacture for determining whether a sequence of unit processes continuously executed among unit processes in a program is a loop by means of computational processing performed by a computer. The method includes: reading address information on the sequence of unit processes; comparing an address of a unit process as a loop starting point candidate with an address of a last unit process in the sequence of unit processes; reading call stack information on the sequence of unit processes; comparing a call stack upon execution of the unit process as the loop starting point candidate with a call stack upon execution of the last unit process; outputting a determination result indicating that the sequence of unit processes forms a loop if the respective comparison results of the addresses and the call stacks match with each other. | 2012-05-31 |
20120137112 | System and Method for Expressing Platform Configuration Dependencies for Local and Remote System Management - A computer implemented method includes identifying a first question that is associated with an object at an information handling system. The first question represents an opportunity to select a first configuration setting having a first value. A second question associated with the object is identified, the second question representing an opportunity to select a second configuration setting having a second value. The method further includes determining that relevance of the second question depends on the first value. A first dependency modifier is associated with the second question based on determining the relevance. The first dependency modifier identifies the first question, the first value, and an action keyword. The action keyword identifies a first action to be associated with a presentation of the second question. | 2012-05-31 |
20120137113 | METHOD OF POWERING ON SERVER - A method of powering on a server is provided, wherein the server includes power consumption modules with the same functions, connectors, and a BIOS (Basic Input/Output System). The power consumption modules are connected to the server via the connectors respectively. This method includes the steps as follows. At first, the BIOS detects a delay power-up setting. When the delay power-up setting is detected, the BIOS staggers initialization times of the connectors, so that the connectors can be initialized respectively. When one of the connectors has been initialized, the connector is electrically connected to the corresponding power consumption module, so that the power consumption module can be delayed to be powered on. | 2012-05-31 |
20120137114 | METHOD AND CIRCUIT FOR RESETTING REGISTER - A method for reset a register includes the following step: a computer starts to be booted and perform a booting procedure. Wherein, the computer includes at least one register. Power is supplied to the at least one register. Determine if the computer is booted successfully. If it is determined that the computer fails to be booted, the at least one register is kept to be grounded for a predetermined period of time to reset the at least one register. After the at least one register is grounded, power is supplied to the at least one register again, and the computer is rebooted. | 2012-05-31 |
20120137115 | METHOD AND DEVICE FOR SIMULATING A RESET SIGNAL IN A SIMULATED SYSTEM ON CHIP - A method and system for simulating a reset signal in a modeled system comprises a reset control module and a module to be reset. Operations of the system include emitting by a control thread of the control module a reset signal, receiving by the module to be reset the reset signal, waking up a thread of the module to be reset, and waiting for a reset signal. If the thread is woken up by the reset signal further operations include activating a reset exception by the thread, and if a reset exception is raised, making the thread wait for a reboot signal, transmitting the reboot signal by the control thread to the module to be reset, and after receiving the reboot signal, activating the thread which executes and waits for a reset signal. | 2012-05-31 |
20120137116 | COMPUTER SYSTEM AND CONTROL METHOD OF THE SAME - A computer system includes a device which transmits data through a predetermined interface and outputs first recognition information in response to a predetermined power on self test (POST) control signal, a device controller which has second recognition information about whether the device is mounted, and a system controller which outputs the POST control signal to the device when powering on, and recognizes the device on the basis of the first recognition information and the second recognition information. | 2012-05-31 |
20120137117 | SYSTEM AND METHOD FOR PROVIDING SECURE VIRTUAL MACHINES - The present invention provides improved security in a virtual machine. By extending the capabilities of modern secure processors, privacy of computation is provided from both the owner of the equipment and other users executing on the processor, which is an advantageous feature for rentable, secure computers. In addition to the hardware extensions required to secure a virtualizable computer, an infrastructure for the deployment of such processors is also provided. Furthermore, a signaling flow to establish the various relationships between the owner, user and manufacturer of the equipment is disclosed. | 2012-05-31 |
20120137118 | Automatic Configuration Sampling for Managing Configuration Parameters of a Computer System - A computer configuration utility automatically alters system configuration parameters to sample multiple different configurations. At least one workrate metric is measured at each sampled configuration. The workrate measurements for the multiple different configurations are compared to determine the effect of different configurations with respect to at least one optimization criterion. System configuration is automatically adjusted to the optimum configuration. Preferably, the workrate metric is (non-idle) instructions executed per unit of time. | 2012-05-31 |
20120137119 | Disabling Communication in a Multiprocessor System - Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration. | 2012-05-31 |
20120137120 | METHOD AND APPARATUS FOR ESTABLISHING SAFE PROCESSOR OPERATING POINTS - A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information. | 2012-05-31 |
20120137121 | METHOD AND DEVICE FOR STORING SECURED SENT MESSAGE DATA - Methods and devices for storing sent message data are described. The sent message data corresponds to a message sent to a destination by a communication device via a server. The method includes compiling a first portion of the message which has a plurality of components; applying security encoding to the first portion; and storing the first portion. The first portion includes at least one but not all of the plurality of components in the message, and pointers to the components not included in the first portion. | 2012-05-31 |
20120137122 | Data File Decryption Method, Decryption Device and Data Broadcasting System - A data file decryption method, a decryption device and a data broadcasting system are disclosed, which are applied to a data broadcasting service. Among them, the data file decryption method includes the steps of: receiving the file delivery information which includes a data file identification and a key file identification corresponding to the data file; receiving the corresponding data file and key file according to the data file identification and the key file identification; and decrypting the data file according to the key file. According to the data file decryption method, decryption device and the data broadcasting system of the present invention, by setting the data file identification and the corresponding key file identification in the file delivery information and receiving the corresponding file according to the data file identification and the key file identification, the resource dissipation due to a large quantity of useless information received at a terminal is avoided, and the file to be received can be quickly located by the terminal, so that the time delay due to the decryption of a data file is avoided, and the service experience for users is improved. | 2012-05-31 |
20120137123 | ENCRYPTION/DECRYPTION COMMUNICATION SYSTEM - The present disclosure relates to an encryption/decryption device and method and a communication system including the encryption/decryption device. The device includes a receiving part; an address analyzing part; a judging part; an encrypting/decrypting part and a sending part. The judging part is adapted to judge whether an encryption/decryption process needs to be performed in accordance with the source address and/or the destination address of the data package. Thus, a safe network transmission of the user data is achieved without the need of installing and configuring software and the user is easy to realize the security of data transmission. | 2012-05-31 |
20120137124 | MULTI-VERSION MESSAGE CONDITION BASED DELIVERY - A method for condition-based message delivery may be provided. The method may comprise receiving a first message, a second message and a condition on a sending message server at a first time instance. The method may also comprise encrypting the first message with a first encryption key and encrypting the second message with a second encryption key, as well as sending the first and the second message to a recipient message system. Moreover, the method may comprise receiving a request from the recipient message system at a second time instance for sending one of the decryption keys corresponding to either the first or the second encryption key, and sending the first decryption key or the second decryption key depending on the condition to the recipient message system. | 2012-05-31 |
20120137125 | METHODS AND APPARATUS FOR TRANSMITTING AND RECEIVING SECURE AND NON-SECURE DATA - Devices, methods, and systems capable of an enabling transmission and receipt of secure and non-secure data are discussed in this document. According to some embodiments, a network apparatus can transmit ciphered and unciphered data. The network apparatus transmits a first signal indicating a cipher to be used and transmits a second signal indicating that non-secure data is to be transmitted and received unciphered. The network apparatus can cipher secure data and transmits ciphered-secure data and unciphered-non-secure data. A wireless terminal can receive the first and second signals, the ciphered secure data, and the unciphered non-secure data. The wireless terminal can deciphers the received secure data and does not decipher the received non-secure data. System embodiments can include both network-side and network terminal components. Embodiments of the present invention enable secure transmission of data in concert with efficient processing. Other aspects, embodiments, and features are also claimed and described. | 2012-05-31 |
20120137126 | SMART METER AND METER READING SYSTEM - The present invention provides a smart meter for use in automatic meter reading of power, gas, and the like, preventing falsification of a program and data and assuring security in a communication path. A smart meter has: a data processor receiving a measurement signal according to a use amount, computing meter read data, and performing communication control by a communication unit coupled to a network; and a secure processor having tamper resistance for internally held information and performing secure authenticating process for a remote access. The data processor encrypts computed meter read data with a public key unique to the smart meter and supplies the encrypted data to the secure processor. The secure processor decrypts the encrypted meter read data with the secret key unique to the smart meter and stores the decrypted or encrypted meter read data into a nonvolatile storage region. | 2012-05-31 |
20120137127 | DEVICE CERTIFICATE INDIVIDUALIZATION - A method of generating a device certificate. A method of generating a device certificate comprising, constructing a device certificate challenge at a device, sending information to a device certificate individualization server in response to the device certificate challenge, validating the device certificate challenge by the device certificate individualization server, and validating the device certificate response by the device. | 2012-05-31 |
20120137128 | System and Method for Securing a Credential via User and Server Verification - Systems and methods for securing a credential generated by or stored in an authentication token during an attempt to access a service, application, or resource are provided. A secure processor receives a credential from an authentication token and securely stores the credential. The secure processor then verifies the identity of the individual attempting to use the authentication token and cryptographically verifies the identity of the server being accessed. The credential is only released for transmission to the server if both the identity of the individual and the identity of the server are successfully verified. Alternatively, a secure connection is established between the secure processor and the server being accessed and a secure connection is established between the secure processor and a computing device. The establishment of the secure connections verifies the identity of the server. After the secure connections are established, the identity of the user is verified. | 2012-05-31 |