22nd week of 2012 patent applcation highlights part 13 |
Patent application number | Title | Published |
20120132917 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate having a low resistance signal line and a method of manufacturing the display substrate are provided. The display substrate includes an insulation substrate, a gate line, a data line and a pixel electrode. The gate line gate line is formed through a sub-trench and an opening portion. The sub-trench is formed in the insulation substrate and the opening portion is formed through a planarization layer on the insulation substrate at a position corresponding to the position of the sub-trench. The data line crosses the gate line. The pixel electrode is electrically connected to the gate line and the data line through a switching element. Thus, a signal line is formed through a trench formed by using a planarization layer and an insulation substrate, so that a resistance of the signal line may be reduced. | 2012-05-31 |
20120132918 | Display Device and Manufacturing Method of the Same - A display device free of contact resistance between a drain electrode (or a source electrode) and a pixel electrode. The display device includes a gate electrode, a gate insulating layer covering the gate electrode, a semiconductor layer formed over the gate insulating layer, and a source electrode and a drain electrode separated from each other and in partial-contact with and over the semiconductor layer, and one of the source electrode and the drain electrode also serves as a pixel electrode, the other of the source electrode and the drain electrode also serves as a signal line, and a low resistant conductive layer is preferably formed over the other of the source electrode and the drain electrode. The low resistant conductive layer can be formed by an electroplating method or the like. | 2012-05-31 |
20120132919 | SEMICONDUCTOR DEVICE - It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed between a source region and a drain region, and a high concentration impurity region is formed between the two channel regions; the channel length of the channel region adjacent to the source region is longer than the channel length of the channel region adjacent to the drain region. | 2012-05-31 |
20120132920 | Organic Light Emitting Display Device and Method for Manufacturing the Same - In an organic light emitting diode (OLED) display and a manufacturing method, an organic light emitting diode (OLED) display includes: a substrate; a semiconductor layer pattern formed on the substrate and including a first capacitor electrode; a gate insulating layer covering the semiconductor layer pattern; a first conductive layer pattern formed on the gate insulating layer and including a second capacitor electrode having at least a portion overlapping the first capacitor electrode; an interlayer insulating layer having a capacitor opening exposing a portion of the second capacitor electrode and covering the second capacitor electrode; and a second conductive layer pattern formed on the interlayer insulating layer, wherein the capacitor opening includes a first transverse side wall parallel to and overlapping the second capacitor electrode, a second transverse side wall parallel to and not overlapping the second capacitor electrode, and a longitudinal side wall connecting the first transverse side wall and the second transverse side wall to each other and overlapping the first capacitor electrode. | 2012-05-31 |
20120132921 | REDUCING WAFER DISTORTION THROUGH A HIGH CTE LAYER - Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon ( | 2012-05-31 |
20120132922 | COMPOSITE SUBSTRATE WITH CRYSTALLINE SEED LAYER AND CARRIER LAYER WITH A COINCIDENT CLEAVAGE PLANE - A structure and a method can provide a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction. | 2012-05-31 |
20120132923 | SUBSTRATE FOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME - The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer. | 2012-05-31 |
20120132924 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 μm from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak. | 2012-05-31 |
20120132925 | METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE, AND A CORRESPONDING SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure is provided which includes the following steps: a crystalline semiconductor substrate ( | 2012-05-31 |
20120132926 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film. | 2012-05-31 |
20120132927 | OHMIC ELECTRODE AND METHOD OF FORMING THE SAME - An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti | 2012-05-31 |
20120132928 | OHMIC ELECTRODE FOR USE IN A SEMICONDUCTOR DIAMOND DEVICE - In a semiconductor diamond device, there is provided an ohmic electrode that is chemically, and thermally stable, and is excellent in respect of low contact resistance, and high heat resistance. A nickel-chromium alloy, or a nickel-chromium compound, containing Ni, and Cr such as Ni | 2012-05-31 |
20120132929 | PHOSPHOR BLEND FOR AN LED LIGHT SOURCE AND LED LIGHT SOURCE INCORPORATING SAME - A phosphor blend for an LED light source is provided wherein the phosphor blend comprises from about 7 to about 12 weight percent of a cerium-activated yttrium aluminum garnet phosphor, from about 3 to about 6 weight percent of a europium-activated strontium calcium silicon nitride phosphor, from about 15 to about 20 weight percent of a europium-activated calcium silicon nitride phosphor, and from about 55 to about 80 weight percent of a europium-activated calcium magnesium chlorosilicate phosphor. An LED light source in accordance with this invention has a B:G:R ratio for a 3200 K tungsten balanced color film of X:Y:Z when directly exposed through a nominal photographic lens, wherein X, Y and Z each have a value from 0.90 to 1.10. | 2012-05-31 |
20120132930 | DEVICE COMPONENTS WITH SURFACE-EMBEDDED ADDITIVES AND RELATED MANUFACTURING METHODS - Active or functional additives are embedded into surfaces of host materials for use as components in a variety of electronic or optoelectronic devices, including solar devices, smart windows, displays, and so forth. Resulting surface-embedded device components provide improved performance, as well as cost benefits arising from their compositions and manufacturing processes. | 2012-05-31 |
20120132931 | LED MODULE - According to one embodiment, an LED module includes a substrate, an interconnect layer, a light emitting diode (LED) package, and a reflection member. The interconnect layer is provided on the substrate. The LED package is mounted on the interconnect layer. The reflection member is provided on a region in the substrate where the LED package is not mounted and has a property of reflecting light emitted from the LED package. The LED package includes a first lead frame, a second lead frame, an LED chip, and a resin body. The first lead frame and the second lead frame are arranged apart from each other on the same plane. The LED chip is provided above the first lead frame and the second lead frame, with one terminal connected to the first lead frame and one other terminal connected to the second lead frame. The resin body covers the LED chip, covers an upper surface, a part of a lower surface, and a part of an end surface of each of the first lead frame and the second lead frame, and exposes a remaining part of the lower surface and a remaining part of the end surface. | 2012-05-31 |
20120132932 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display is disclosed. The organic light emitting diode display includes: a substrate, an organic light emitting diode positioned on the substrate, a metal layer positioned on the substrate with the organic light emitting diode interposed therebetween, and a resin layer positioned on the metal layer and configured to reinforce a strength of the metal layer. | 2012-05-31 |
20120132933 | LED MODULE AND ILLUMINATION APPARATUS - According to one embodiment, an LED module includes a substrate, an interconnect layer, an LED package, and a resin. The resin is provided on the substrate to cover the LED package. The resin has a refractive index higher than a refractive index of air. The resin is transmissive with respect to light emitted from the LED package. The LED package includes first and second leadframes, an LED chip, and a resin body. The first and second leadframes are disposed on a plane. An exterior form of the resin body is used as an exterior form of the LED package. | 2012-05-31 |
20120132934 | ORGANIC EL ELEMENT, DISPLAY APPARATUS, AND LIGHT-EMITTING APPARATUS - An organic EL element has an anode, a cathode, a hole injection layer and at least one functional layer disposed between the anode and the cathode. The at least one functional layer contains an organic material. Holes are injected into the functional layer from the hole injection layer, which contains a tungsten oxide. A Ultraviolet Photoelectron Spectroscopy (UPS) spectrum obtained from a UPS measurement has a protrusion near a Fermi surface and within a region corresponding to a binding energy range lower than a top of the valence band. The tungsten oxide contained in the hole injection layer satisfies a condition, determined from an X-ray Photoelectronic Spectroscopy measurement, that a ratio in a number density of atoms other than tungsten and oxygen atoms to the tungsten atoms does not exceed approximately 0.83. | 2012-05-31 |
20120132935 | METHOD OF MANUFACTURING AN ORGANIC LIGHT-EMITTING ELEMENT, ORGANIC LIGHT-EMITTING ELEMENT, DISPLAY PANEL, AND DISPLAY DEVICE - A method of manufacturing an organic light-emitting element. A first layer is formed above a substrate, and exhibits hole injection properties. A bank material layer is formed above the first layer using a bank material. Banks are formed by patterning the bank material layer, and forming a resin film on a surface of the first layer by attaching a portion of the bank material layer to the first layer, the banks defining apertures corresponding to light-emitters, the resin material being the same as the bank material. A functional layer is formed by applying ink to the apertures that contacts the resin film. The ink contains an organic material. The functional layer includes an organic light-emitting layer. A second layer is formed above the functional layer and exhibits electron injection properties. The hole injection properties of the first layer are then degraded by applying electrical power to an element structure. | 2012-05-31 |
20120132936 | NITRIDOSILICATE PHOSPHOR TUNABLE LIGHT-EMITTING DIODES BY USING UV AND BLUE CHIPS - The present disclosure provides a radiation device. The radiation device includes a first light emitting diode (LED) operable to emit light having a first central wavelength; a second LED configured adjacent the first LED and operable to emit light having a second central wavelength substantially less than the first central wavelength; and a luminescent material disposed on the first LED and the second LED. The luminescent material includes a strontium silicon nitride (SrSi | 2012-05-31 |
20120132937 | WATERPROOF SURFACE MOUNT DEVICE PACKAGE AND METHOD - The present invention is directed to LED packages and methods utilizing waterproof and UV resistant packages with improved structural integrity. In some embodiments, the improved structural integrity is provided by various features in the lead frame that the casing material encompasses to improve the adhesion between the lead frame and the casing for a stronger, waterproof package. Moreover, in some embodiments the improved structural integrity and waterproofing is further provided by improved adhesion between the encapsulant and the casing. Some embodiments also provide for improved wire bonds, with the length, thickness, and loop height of the wire bonds controlled and optimized for improved adhesion between the wire bonds and the encapsulant as well as improved reliability. | 2012-05-31 |
20120132938 | LED PACKAGE - According to one embodiment, an LED package includes a first, a second, and a third lead frame separated from one another. The LED package includes a first LED chip of a top surface terminal type having one terminal connected to the second lead frame, and having one other terminal connected to the third lead frame, the first LED chip is mounted on the first lead frame. The LED package includes a first protection chip of a top surface terminal type having one terminal connected to the second lead frame, and having one other terminal connected to the third lead frame, the first protection chip is mounted on the first lead frame. And, a resin body covers a part of the first, second and third lead frames, the first LED chip, and the first protection chip, An outer shape of the resin body forms an outer shape of the LED package. | 2012-05-31 |
20120132939 | LIGHT EMITTING DEVICE EMPLOYING NON-STOICHIOMETRIC TETRAGONAL ALKALINE EARTH SILICATE PHOSPHORS - Disclosed is a light emitting device employing non-stoichiometric tetragonal Alkaline Earth Silicate phosphors. The light emitting device comprises a light emitting diode emitting light of ultraviolet or visible light, and non-stoichiometric luminescent material disposed around the light emitting diode. The luminescent material adsorbs at least a portion of the light emitted from the light emitting diode and emits light having a different wavelength from the absorbed light. The non-stoichiometric luminescent material has tetragonal crystal structure, and contains more silicon in the crystal lattice than that in the crystal lattice of silicate phosphors having stoichiometric crystal structure. The luminescent material is represented as the formula (Ba | 2012-05-31 |
20120132940 | OPTICAL SEMICONDUCTOR DEVICE - According to one embodiment, an optical semiconductor device includes an n-type semiconductor layer, a p-type semiconductor layer, and a functional part. The functional part is provided between the n-type semiconductor layer and the p-type semiconductor layers. The functional part includes a plurality of active layers stacked in a direction from the n-type semiconductor layer toward the p-type semiconductor layer. At least two of the active layers include a multilayer stacked body, an n-side barrier layer, a well layer and a p-side barrier layer. The multilayer stacked body includes a plurality of thick film layers and a plurality of thin film layers alternately stacked in the direction. The n-side barrier layer is provided between the multilayer stacked body and the p-type layer. The well layer is provided between the n-side barrier layer and the p-type layer. The p-side barrier layer is provided between the well layer and the p-type layer. | 2012-05-31 |
20120132941 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a light emitting device and a method for manufacturing a light emitting device. The light emitting device includes a base, an LED inversely mounted on the base. The LED includes an LED chip connected to the base and a buffer layer located on the LED. The buffer layer includes a plurality of depressions with complementary pyramid structure on a surface of the buffer layer not face the LED, the surface being a light-exiting surface of the LED. The buffer layer is made from silicon carbide. The light emitting device has a large area of the light-exiting surface and provides a reflecting film on a base, thus improving the luminous efficiency of the light emitting device. Inversely mounting mode is adopt, which is easy to implement. | 2012-05-31 |
20120132942 | LIGHT EMITTING DIODE PACKAGE - An exemplary LED package includes first and second electrodes, an LED chip and two electrically conductive wires. The first electrode has a top surface and an opposite bottom surface. A recess is defined in the top surface of the first electrode. The second electrode has a top surface and an opposite bottom surface. A recess is defined in the top surface of the second electrode. The LED chip has a bottom surface attached to the top surface of the first electrode, and a top surface on which a first pad and a second pad are formed. One of the electrically conductive wires has an end connecting to the first pad and an opposite end joining with a bottom of the recess of the first electrode. The other has an end connecting to the second pad and an opposite end joining with a bottom of the recess of the second electrode. | 2012-05-31 |
20120132943 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, an electrode, a p-type semiconductor layer and a light emitting layer. The p-type semiconductor layer is provided between the n-type semiconductor layer and the electrode and includes a p-side contact layer contacting the electrode. The light emitting layer is provided between the n-type and the p-type semiconductor layers. The p-side contact layer includes a flat part having a plane perpendicular to a first direction from the n-type semiconductor layer toward the p-type semiconductor layer and multiple protruding parts protruding from the flat part toward the electrode. A height of the multiple protruding parts along the first direction is smaller than one-fourth of a dominant wavelength of light emitted from the light emitting layer. A density of the multiple protruding parts in the plane is 5×10 | 2012-05-31 |
20120132944 | LIGHT-EMITTING DEVICE, LIGHT MIXING DEVICE AND MANUFACTURING METHODS THEREOF - Disclosed is a light-emitting device comprising: a carrier; a light-emitting element disposed on the carrier; a first light guide layer covering the light-emitting element, and disposed on the carrier; a wavelength conversion and light guide layer covering the first light guide layer and the light-emitting element, and disposed on the carrier; and a low refractive index layer disposed between the first light guide layer and the wavelength conversion and light guide layer; wherein the first light guide layer comprises a gradient refractive index, the wavelength conversion and light guide layer comprises a dome shape structure and is used to convert a wavelength of light emitted from the light-emitting element and transmit light, and the low refractive index layer is used to reflect light from the wavelength conversion and light guide layer. | 2012-05-31 |
20120132945 | OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP - An optoelectronic semiconductor chip includes a semiconductor layer sequence. The semiconductor layer sequence contains at least one active layer for generating primary radiation. In addition, the semiconductor layer sequence includes a plurality of conversion layers, the conversion layers being designed to absorb the primary radiation at least partially and to convert it into secondary radiation of a longer wavelength than the primary radiation. Furthermore the semiconductor layer sequence comprises a roughening which extends at least into the conversion layers. | 2012-05-31 |
20120132946 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE INCLUDING THE SAME - A light emitting device is disclosed. The light emitting device includes a first electrode and a second electrode, which have different areas, thereby achieving enhanced bonding reliability. | 2012-05-31 |
20120132947 | LIGHT-EMITTING DIODE AND METHOD FOR PRODUCING A LIGHT-EMITTING DIODE - A light-emitting diode includes a carrier having a mounting surface; at least one light-emitting diode chip fixed to the mounting surface; and a reflective element provided for reflecting electromagnetic radiation, wherein the reflecting element is fixed to the carrier and includes porous polytetrafluoroethylene. | 2012-05-31 |
20120132948 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a light emitter, a first and a second electrode layer, a pad electrode and an auxiliary electrode portion. The emitter includes a first semiconductor layer provided on one side of the emitter, a second semiconductor layer provided on one other side of the emitter, and a light emitting layer provided between the first and second semiconductor layers. The first electrode layer is provided on opposite side of the second semiconductor layer from the first semiconductor layer and includes a metal layer and a plurality of apertures penetrating through the metal layer. The second electrode layer is electrically continuous with the first semiconductor layer. The pad electrode is electrically continuous with the first electrode layer. The auxiliary electrode portion is electrically continuous with the first electrode layer and extends in a second direction orthogonal to the first direction. | 2012-05-31 |
20120132949 | LED PACKAGE - According to one embodiment, an LED package includes mutually-separated first and second leadframes, an LED chip, and a resin body. One selected from the first leadframe and the second leadframe includes a base portion, and an extending portion. The base portion has an end surface covered with the resin body. The extending portion extends from the base portion and has an unevenness provided in a surface of the extending portion. A lower surface of the extending portion is covered with the resin body. A tip surface of the extending portion is exposed from the resin body. An exterior form of the resin body is used as an exterior form of the LED package. | 2012-05-31 |
20120132950 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device includes a base plate, an organic light-emitting body formed on the base plate, a heat-transferring filling material formed around the organic light-emitting body to cover the organic light-emitting body, the heat-transferring filling material having an electrically insulating property, and a sealing plate arranged on the heat-transferring filling material. | 2012-05-31 |
20120132951 | LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - The disclosed light emitting diode includes a substrate provided, at a surface thereof, with protrusions, a buffer layer formed over the entirety of the surface of the substrate, a first semiconductor layer formed over the buffer layer, an active layer formed on a portion of the first semiconductor layer, a second semiconductor layer formed over the active layer, a first electrode pad formed on another portion of the first semiconductor layer, except for the portion where the active layer is formed, and a second electrode pad formed on the second semiconductor layer. Each protrusion has a side surface inclined from the surface of the substrate at a first angle, and another side surface inclined from the surface of the substrate at a second angle different from the first angle. | 2012-05-31 |
20120132952 | LIGHT-EMITTING DIODE LAMP WITH LOW THERMAL RESISTANCE - A light-emitting diode (LED) structure with an improved heat transfer path with a lower thermal resistance than conventional LED lamps is provided. For some embodiments, a surface-mountable light-emitting diode structure is provided having an active layer deposited on a substrate directly bonded to a metal plate that is substantially exposed for low thermal resistance by positioning the metal plate at the bottom of the light-emitting diode structure. This metal plate may then be soldered to a printed circuit board (PCB) that includes a heat sink. For some embodiments of the invention, the metal plate is thermally and electrically conductively coupled through several heat conduction layers to a large heat sink that may be included in the structure. | 2012-05-31 |
20120132953 | Thin-Layer Encapsulation for an Optoelectronic Component, Method for the Production Thereof, and Optoelectronic Component - A thin-layer encapsulation ( | 2012-05-31 |
20120132954 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate with a first surface and a second surface. The semiconductor substrate has an element region including an IGBT region and a diode region located adjacent to the IGBT region. An IGBT element is formed in the IGBT region. A diode element is formed in the diode region. A heavily doped region of first conductivity type is located on the first surface side around the element region. An absorption region of first conductivity type is located on the second surface side around the element region. A third semiconductor region of second conductivity type is located on the second surface side around the element region. | 2012-05-31 |
20120132955 | SEMICONDUCTOR DEVICE - A diode region and an IGBT region are formed in a semiconductor layer of a semiconductor device. A lifetime controlled region is formed in the semiconductor layer. In a plan view, the lifetime controlled region has a first lifetime controlled region located in the diode region and a second lifetime controlled region located in a part of the IGBT region. The second lifetime controlled region extends from a boundary of the diode region and the IGBT region toward the IGBT region. In the plan view, a tip of the second lifetime controlled region is located in a forming area of the body region in the IGBT region. | 2012-05-31 |
20120132956 | SEMICONDUCTOR COMPONENT WITH HIGH BREAKTHROUGH TENSION AND LOW FORWARD RESISTANCE - A semiconductor component having a semiconductor body is disclosed. In one embodiment, the semiconductor component includes a drift zone of a first conductivity type, a drift control zone composed of a semiconductor material which is arranged adjacent to the drift zone at least in places, a dielectric which is arranged between the drift zone and the drift control zone at least in places. A quotient of the net dopant charge of the drift control zone, in an area adjacent to the accumulation dielectric and the drift zone, divided by the area of the dielectric arranged between the drift control zone and the drift zone is less than the breakdown charge of the semiconductor material in the drift control zone. | 2012-05-31 |
20120132957 | HIGH PERFORMANCE STRAINED SOURCE-DRAIN STRUCTURE AND METHOD OF FABRICATING THE SAME - A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour. | 2012-05-31 |
20120132958 | High performance transistor - A novel semiconductor transistor is presented. The semiconductor structure has a gate region forming a channel with repetitive patterns in the direction perpendicular to the current flow, so that the portion of its channel that is not strictly planar contributes to a significant reduction of the silicon area occupied by the device. It offers the advantage of lower on-resistance for the same silicon area while improving on its dynamic performances. The additional cost to shape the channel region of the device in periodic repetitive patterns is minimum, which makes the present invention easy to implement in any conventional CMOS process technology and very cost effective. | 2012-05-31 |
20120132959 | WIDE BANDGAP TRANSISTOR DEVICES WITH FIELD PLATES - A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance L | 2012-05-31 |
20120132960 | REGROWN HETEROJUNCTION BIPOLAR TRANSISTORS FOR MULTI-FUNCTION INTEGRATED DEVICES AND METHOD FOR FABRICATING THE SAME - The present invention may provide an integrated device, which may include a substrate having first and second regions, the first region spaced apart from the second region, a first heterojunction bipolar transistor (HBT) device formed on the first region of the substrate, the first HBT device having a first collector layer formed above the first region of the substrate, the first collector layer having a first collector thickness and a first collector doping level, and a second HBT device formed on the second region of the substrate, the second HBT device having a second collector layer formed above the second region of the substrate, the second collector layer having a second collector thickness and a second collector doping level, the second collector thickness substantially greater than the first collector thickness, the second collector doping level lower than the first collector doping level. | 2012-05-31 |
20120132961 | HETEROJUNCTION BIPOLAR TRANSISTOR MANUFACTURING METHOD AND INTEGRATED CIRCUIT COMPRISING A HETEROJUNCTION BIPOLAR TRANSISTOR - Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed. | 2012-05-31 |
20120132962 | Method of Manufacturing Semiconductor Device and Semiconductor Device - A method of manufacturing a semiconductor device, in which a second semiconductor layer of Al | 2012-05-31 |
20120132963 | STANDARD CELL FOR INTEGRATED CIRCUIT - An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact. | 2012-05-31 |
20120132964 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors. | 2012-05-31 |
20120132965 | Photoelectric Conversion Device And Electronic Device Having The Same - A plurality of transistors in which ratios of a channel length L to a channel width W, α=W/L, are different from each other is provided in parallel as output side transistors | 2012-05-31 |
20120132966 | SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE - Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged. | 2012-05-31 |
20120132967 | THROUGH SILICON VIA AND METHOD OF FABRICATING SAME - A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core. | 2012-05-31 |
20120132968 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing a semiconductor device includes forming a device isolation film defining an active region over a semiconductor substrate including a periphery region, forming a gate pattern over the active region, forming a contact plug coupled to each of the gate pattern and the active region, forming a line coupled to the contact plug and a first reservoir capacitor over the same layer as in the line, and forming a second storage capacitor coupled to the first storage capacitor. The semiconductor device sufficiently endures a high bias not only using a line electrode and a dielectric film of a periphery region but also using a MOS-type storage capacitor of an upper electrode, and couples a cylindrical storage capacitor in series to a MOS-type capacitor so that it can be used in a small region. | 2012-05-31 |
20120132969 | COMPENSATION NETWORK FOR RF TRANSISTOR - A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor. | 2012-05-31 |
20120132970 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device may include a substrate provided with a transistor, an insulating layer disposed on the substrate, the insulating layer including a contact hole exposing a portion of the transistor, a spacer disposed on an inner sidewall of the contact hole, and a contact plug disposed in the contact hole. Here, a space defined by the spacer may increase in width from a bottom side thereof to a top side thereof. | 2012-05-31 |
20120132971 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove. | 2012-05-31 |
20120132972 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device with active regions formed in the shape of a band in a substrate; a plurality of word lines arranged at equal intervals that intersect the active regions; cell contacts that includes first cell contacts in the active regions in the center portions in a longitudinal direction, and second cell contacts at both ends in the longitudinal direction; bit line contacts on the first cell contacts; bit lines that pass over the bit line contacts; storage node contacts on the second cell contacts; storage node contact pads on the storage node contacts; and storage capacitors on the storage node contact pads. The center positions of the storage node contacts are offset from the center positions of the second cell contacts. The center positions of the storage node contact pads are offset from the center positions of the storage node contacts. | 2012-05-31 |
20120132973 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 2012-05-31 |
20120132974 | INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT - Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices. | 2012-05-31 |
20120132975 | DATA RETENTION IN A SINGLE POLY EPROM CELL - An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region. | 2012-05-31 |
20120132976 | SEMICONDUCTOR DEVICES HAVING DUAL TRENCH, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM HAVING THE SAME - A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer. | 2012-05-31 |
20120132977 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes an interface, a power supply, a driver, and a switch section. The interface includes a first MOSFET and converts a terminal switch signal of input serial data into parallel data. The first MOSFET is provided on the SOI substrate and has a back gate in a floating state. The power supply includes a second MOSFET and generates an ON potential higher than a potential of a power supply to be supplied to the interface. The second MOSFET is provided on the SOI substrate and has a back gate connected to a source. The driver includes a third MOSFET and outputs a control signal for controlling the ON potential to be in a high level according to the parallel data. The third MOSFET is provided on the SOI substrate and has a back gate connected to a source. | 2012-05-31 |
20120132978 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region. | 2012-05-31 |
20120132979 | Memory Devices And Methods Of Forming Memory Devices - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures. | 2012-05-31 |
20120132980 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film. | 2012-05-31 |
20120132981 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided. | 2012-05-31 |
20120132982 | Non-Volatile Memory Devices - A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region. | 2012-05-31 |
20120132983 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a conductive member, a semiconductor pillar, and a charge storage layer. The stacked body is provided above the substrate. The stacked body includes a plurality of insulating films stacked alternately with a plurality of electrode films. A plurality of terraces are formed in a stairstep configuration along only a first direction in an end portion of the stacked body on the first-direction side. The first direction is parallel to an upper face of the substrate. The plurality of terraces are configured with upper faces of the electrode films respectively. The conductive member is electrically connected to the terrace to connect electrically the electrode film to the substrate by leading out the electrode film in a second direction parallel to the upper face of the substrate and orthogonal to the first direction. The semiconductor pillar is provided in a central portion of the stacked body and extends in a stacking direction of the insulating films and the electrode films. The charge storage layer is provided between the electrode film and the semiconductor pillar. | 2012-05-31 |
20120132984 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AS WELL AS SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A contact plug | 2012-05-31 |
20120132985 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a plurality of memory cells are provided on a semiconductor substrate. In each memory cell, a control gate electrode is provided on a charge accumulation layer with an inter-electrode insulation film interposed between the control gate electrode and the charge accumulation layer, an air gap is provided between the charge accumulation layers adjacent to each other in a word line direction, and an insulation film disposed below the inter-electrode insulation film is divided into an upper part and a lower part by the air gap. | 2012-05-31 |
20120132986 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a plurality of horizontal channel transistors formed thereon, an insulation layer structure on the substrate and covering the horizontal transistors, and a plurality of vertical channel transistors on the insulation layer structure. | 2012-05-31 |
20120132987 | Reducing Device Performance Drift Caused by Large Spacings Between Active Regions - A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting. | 2012-05-31 |
20120132988 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process. | 2012-05-31 |
20120132989 | MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION - A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure. | 2012-05-31 |
20120132990 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device. | 2012-05-31 |
20120132991 | ORGANIC THIN-FILM TRANSISTOR, AND PROCESS FOR PRODUCTION THEREOF - An organic thin-film transistor ( | 2012-05-31 |
20120132992 | SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON AN SOI SUBSTRATE - A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided. | 2012-05-31 |
20120132993 | Monolithic Integration Of Photonics And Electronics In CMOS Processes - Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. | 2012-05-31 |
20120132994 | HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICE - Embodiments of the present invention relate generally to semiconductor devices and, more particularly, to a structure for high-voltage (HV) semiconductor-on-insulator (SOI) devices and methods for their formation. In one embodiment, the invention provides a semiconductor-on-insulator (SOI) device comprising: a substrate; an insulator layer atop the substrate; a polysilicon layer atop the insulator layer; a device layer atop the polysilicon layer, the device layer comprising: a P-well; an N-well; and an undoped silicon region between the P-well and the N-well; and a trench isolation adjacent one of the P-well and the N-well and extending through the device layer and the polysilicon layer to the insulator layer. | 2012-05-31 |
20120132995 | STACKED AND TUNABLE POWER FUSE - The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided. | 2012-05-31 |
20120132996 | STRAINED SILICON STRUCTURE - A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance. | 2012-05-31 |
20120132997 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a technology capable of manufacturing a semiconductor device equipped with a HK/MG transistor having a gate insulating film comprised of a high-k material and a gate electrode comprised of a metal material and having stable operation characteristics. A film stack configuring an Nch gate stack structure is formed only in a region located in an active region surrounded with an element isolation portion and in which a gate of a core nMIS is to be formed in a later step is formed, while a film stack configuring a Pch gate stack structure is formed in a region other than the above region. This makes it possible to reduce a supply amount of oxygen atoms to be attracted from the element isolation portion to the region in which the gate of the core nMIS is to be formed. | 2012-05-31 |
20120132998 | Replacement Metal Gate Structures Providing Independent Control On Work Function and Gate Leakage Current - The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures. | 2012-05-31 |
20120132999 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR AND BIPOLAR TRANSISTOR - Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method. | 2012-05-31 |
20120133000 | FIELD EFFECT TRANSISTOR WITH CHANNEL REGION EDGE AND CENTER PORTIONS HAVING DIFFERENT BAND STRUCTURES FOR SUPPRESSED CORNER LEAKAGE - Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs. | 2012-05-31 |
20120133001 | TILEABLE SENSOR ARRAY - A method for forming a tileable detector array is presented. The method includes forming a detector module, where forming the detector module includes providing a sensor array having a first side and a second side, where the sensor array includes a first plurality of contact pads disposed on the second side of the sensor array, disposing the sensor array on an interconnect layer, where the interconnect layer includes a redistribution layer having a first side and a second side, where the redistribution layer includes a second plurality of contact pads disposed on the first side, an integrated circuit having a plurality of through vias disposed therethrough, where a first side of the integrated circuit is operationally coupled to the second side of the redistribution layer, where the sensor array is disposed on the interconnect layer such that the first plurality of contact pads on the second side of the sensor array are aligned with the second plurality of contact pads on the first side of the redistribution layer, operationally coupling the first plurality of contact pads on the second side of the sensor array to the second plurality of contact pads on the redistribution layer to form a sensor stack, coupling the sensor stack to a substrate to form the detector module, and tiling a plurality of detector modules on a second substrate to form the tileable detector array. | 2012-05-31 |
20120133002 | Method for producing MEMS structures, and MEMS structure - A method for producing microelectromechanical structures in a substrate includes: arranging at least one metal-plated layer on a main surface of the substrate in a structure pattern; leaving substrate webs open beneath a structure pattern region by introducing first trenches into the substrate perpendicular to a surface normal of the main surface in a region surrounding the structure pattern; coating the walls of the first trenches perpendicular to the surface normal of the main surface with a passivation layer; and introducing cavity structures into the substrate at the base of the first trenches in a region beneath the structure pattern region. | 2012-05-31 |
20120133003 | MICROMECHANICAL COMPONENT - A micromechanical component includes: a substrate having a multitude of trench structures which separate a first and a second mass element of the substrate from a web element of the substrate, in such a way that the first and second mass elements enclose the web element along an extension direction of the main surface of the substrate and are disposed to allow movement relative to the substrate in the direction of a surface normal of the main surface; a first electrode layer applied on the main surface of the substrate and forms a first electrode on the web element between the first and second mass elements; and a second electrode layer applied on the first and second mass elements and forming a self-supporting second electrode above the first electrode in the area of the web element, the first and second electrode forming a capacitance. | 2012-05-31 |
20120133004 | METHOD FOR PRODUCING OBLIQUE SURFACES IN A SUBSTRATE AND WAFER HAVING AN OBLIQUE SURFACE - A method for producing oblique surfaces in a substrate, comprising a formation of recesses on both surfaces of the substrate, until the recesses are so deep that the substrate is perforated by the two recesses. One recess is produced going out from a first main surface in the region of a first surface, and the other recess is produced going out from the second main surface in the region of a second surface, so that the first surface and the second surface do not coincide along a surface normal of the main surfaces of the substrate. Subsequently, flexible diaphragms are attached over the recesses on each of the main surfaces. If a vacuum pressure is then produced inside the recesses, the flexible diaphragms each curve in the direction of the recesses until their surfaces facing the substrate come into contact with one another, generally in the center of the recesses. | 2012-05-31 |
20120133005 | COLLAPSED MODE CAPACITIVE SENSOR - A capacitive sensor is configured for collapsed mode, e.g. for measuring sound or pressure, wherein the moveable element is partitioned into smaller sections. The capacitive sensor provides increased signal to noise ratio. | 2012-05-31 |
20120133006 | OXIDE MEMS BEAM - In one embodiment, a semiconductor structure includes a beam positioned within a sealed cavity, the beam including: an upper insulator layer including one or more layers; and a lower insulator layer including one or more layers, wherein a composite stress of the upper insulator layer is different than a composite stress of the lower insulator layer, such that the beam bends. | 2012-05-31 |
20120133007 | MAGNETIZATION REVERSAL DEVICE, MEMORY ELEMENT, AND MAGNETIC FIELD GENERATION DEVICE - A magnetization reversal device includes a ferromagnetic | 2012-05-31 |
20120133008 | SPIN-INJECTION ELEMENT, AND MAGNETIC FIELD SENSOR AND MAGNETIC RECORDING MEMORY EMPLOYING THE SAME - Provided are a spin-injection element having high spin-injection efficiency, and a magnetic field sensor and a magnetic recording memory employing the element. The element comprises a barrier layer, a magnetic conductive layer, and a spin accumulation portion comprised of non-magnetic conductive material. In the element, a first spin accumulation layer ( | 2012-05-31 |
20120133009 | RADIATION DETECTING ELEMENT AND RADIATION DETECTING DEVICE - There has been such a problem that radiation detecting elements using semiconductor elements have a low radiation detection efficiency, since the radiation detecting elements easily transmit radiation, even though the radiation detecting elements have merits, such as small dimensions and light weight. Disclosed are a radiation detecting element and a radiation detecting device, wherein a film formed of a metal, such as tungsten, is formed on the radiation incident surface of the radiation detecting element, and the incident energy of the radiation is attenuated. The efficiency of generating carriers by way of radiation incidence is improved by attenuating the incident energy, the thickness of the metal film is optimized, and the radiation detection efficiency is improved. | 2012-05-31 |
20120133010 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a through-hole formed in a semiconductor layer; a through-hole insulting layer formed on a sidewall of the through-hole to retract from a front surface of the semiconductor layer; a through-electrode embedded in the through-hole via the through-hole insulating layer; and a sidewall insulating film formed on a sidewall of the through-electrode to be embedded in a retracting section of the through-hole insulating layer. | 2012-05-31 |
20120133011 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME - A solid-state imaging device according to an embodiment includes: a plurality of pixels arranged on a first face of a first semiconductor layer, each of the pixels including a photoelectric conversion element converting light entering through a second face of the first semiconductor layer on the opposite side from the first face into a signal charge, the photoelectric conversion element having a pn junction formed with a first semiconductor region formed on the first face and a second semiconductor region formed on a surface of the first semiconductor region; pixel separating regions separating the pixels from one another and formed between the pixels, each of the pixel separating regions including a second semiconductor layer covering faces in contact with the photoelectric conversion elements, and an insulating film with a lower refractive index than a refractive index of the second semiconductor layer to cover the second semiconductor layer. | 2012-05-31 |
20120133012 | COMPOSITE SYSTEM FOR PHOTOVOLTAIC MODULES - The present invention relates to a composite system for photovoltaic (PV) modules. The composite system consists of a carrier foil, a metal foil applied onto the carrier foil, and an insulating layer applied onto the metal foil. Using different connecting techniques, different photovoltaic (PV) cells can be fastened to the composite system and electrically interconnected thereby. In addition, the invention relates to a method for producing the composite system for PV modules, and to the use of the composite system for the back side contacting of wafer cells that have both contacts on the same side and that are placed, with the contacts, onto conductor structures that interconnect them into a module, and to the use of the composite system for modules of internally interconnected thin-film cells. | 2012-05-31 |
20120133013 | SEMICONDUCTOR LIGHT RECEIVING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light receiving element includes a first semiconductor layer having a first conduction type, a second semiconductor layer that is provided on the first semiconductor layer and has a light receiving area, the second semiconductor layer having a second conduction type opposite to the first conduction type, an insulation film provided on the second semiconductor layer, and an electrode provided on the insulation film, the insulation film having a plurality of windows in an area in which the electrode overlaps the plurality of windows, the electrode being electrically connected to the second semiconductor layer via the plurality of windows. | 2012-05-31 |
20120133014 | Avalanche Photodiode Having Controlled Breakdown Voltage - Avalanche photodiodes and methods for forming them are disclosed. The breakdown voltage of an avalanche photodiode is controlled through the inclusion of a diffusion sink that is formed at the same time as the device region of the photodiode. The device region and diffusion sink are formed by diffusing a dopant into a semiconductor to form a p-n junction in the device region. The dopant is diffused through a first diffusion window to form the device region and a second diffusion window to form the diffusion sink. The depth of the p-n junction is based on an attribute of the second diffusion window. | 2012-05-31 |
20120133015 | PHOTOELECTRIC CONVERSION ELEMENT, PHOTOELECTRIC CONVERSION ELEMENT ASSEMBLY AND PHOTOELECTRIC CONVERSION MODULE - A photoelectric conversion element of the present invention comprises: a first semiconductor layer of a first conductivity type; a first electrode arranged on the back side of the first semiconductor layer a second semiconductor layer of a second conductivity type, the second semiconductor layer on the light-receiving side of the first semiconductor layer; a light-receiving face-side electrode provided on the light-receiving side of the second semiconductor layer; a second electrode arranged on the back side of the first semiconductor layer, and electrically separated from the first semiconductor layer, but connected to the second semiconductor layer; and a penetrating-connecting section penetrating the first semiconductor layer, and connecting the light-receiving face-side electrode with the second electrode, wherein the photoelectric conversion element is characterized in that the first electrode and the second electrode are arranged equidistantly apart from a central axis passing through a center of the photoelectric conversion element. | 2012-05-31 |
20120133016 | LATERAL POWER DIODE WITH SELF-BIASING ELECTRODE - A schottky diode includes a drift region of a first conductivity type and a lightly doped silicon region of the first conductivity type in the drift region. A conductor layer is over and in contact with the lightly doped silicon region to form a schottky contact with the lightly doped silicon region. A highly doped silicon region of the first conductivity type is in the drift region and is laterally spaced from the lightly doped silicon region such that upon biasing the schottky diode in a conducting state, a current flows laterally between the lightly doped silicon region and the highly doped silicon region through the drift region. A plurality of trenches extend into the drift region perpendicular to the current flow. Each trench has a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode. | 2012-05-31 |