22nd week of 2013 patent applcation highlights part 14 |
Patent application number | Title | Published |
20130134420 | Stress-Inducing Structures, Methods, and Materials - Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material. | 2013-05-30 |
20130134421 | SEMICONDUCTOR CHIP HAVING PLURAL PENETRATING ELECTRODES THAT PENETRATE THERETHROUGH - Disclosed herein is a semiconductor chip that includes: a semiconductor chip body including a semiconductor substrate and a circuit element layer provided on a main surface of the semiconductor substrate, the circuit element layer including a plurality of circuit elements; first to fourth penetrating electrodes penetrating the semiconductor chip body; a first conductive path electrically connected between the first penetrating electrode and the second penetrating electrode without being in contact with any one of the circuit elements; a second conductive path electrically connected between the first penetrating electrode and the third penetrating electrode without being in contact with any one of the circuit elements; and a third conductive path electrically connected between the second penetrating electrode and the fourth penetrating electrode without being in contact with any one of the circuit elements. | 2013-05-30 |
20130134422 | TRANSISTOR AND SEMICONDUCTOR DEVICE - To improve switching characteristics of a transistor in which a channel is formed in an oxide semiconductor layer. A parasitic channel is formed at an end portion of the oxide semiconductor layer because a source and a drain of the transistor are electrically connected to the end portion. That is, when at least one of the source and the drain of the transistor is not electrically connected to the end portion, the parasitic channel is not formed at the end portion. In view of this, a transistor having a structure in which at least one of a source and a drain of the transistor is not or less likely to be electrically connected to an end portion of an oxide semiconductor layer is provided. | 2013-05-30 |
20130134423 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an organic light-emitting display device is disclosed. The method includes: uniformly forming an active layer on an entire surface of a substrate on which an organic light-emitting diode, a thin film transistor (TFT), and a capacitor are to be formed; performing a first mask process on the active layer to form a pixel electrode of the organic light-emitting diode, a gate electrode of the TFT, and an upper electrode of the capacitor; performing a second mask process to form an insulating layer having openings that expose the pixel electrode, the upper electrode, and the active layer in a region of the TFT; performing a third mask process to form a source-drain electrode that contacts an exposed portion of the active layer; and performing a fourth mask process to form a pixel-defining layer (PDL) that exposes the pixel electrode and covers the TFT and the capacitor. | 2013-05-30 |
20130134424 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT EMITTING DISPLAY DEVICE COMPRISING THE SAME, AND METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR ARRAY SUBSTRATE - A thin film transistor array substrate may include a thin film transistor including an active layer, a gate electrode, source and drain electrodes, a first insulation layer arranged between the active layer and the gate electrode, and a second insulation layer arranged between the gate electrode and the source and drain electrodes, a pixel electrode arranged on the first insulation layer and comprising the same material as the gate electrode, a capacitor comprising a first electrode arranged on the same layer as the active layer and a second electrode arranged on the same layer as the gate electrode, a pad electrode arranged on the second insulation layer and comprising the same material as the source and drain electrodes, a protection layer formed on the pad electrode, and a third insulation layer formed on the protection layer and exposing the pixel electrode. | 2013-05-30 |
20130134425 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer. | 2013-05-30 |
20130134426 | COMPOSITION OF ORGANIC INSULATING LAYER AND THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE USING THE SAME - Discussed is a composition of an organic insulating layer comprising a photosensitizer, a binder, an additive and a solvent, wherein the photosensitizer includes a photoacid generator (PAG), and a thin film transistor substrate and display device using the same, wherein the composition of the present invention enables to realize a simplified process by omitting an additional entire-surface exposing process for a color change, and a baking process after an exposing process; and to minimize a problem of color-coordinates shift by realizing a good light transmittance. | 2013-05-30 |
20130134427 | TRANSISTOR, DISPLAY, AND ELECTRONIC APPARATUS - A transistor includes: a gate electrode; a semiconductor layer facing the gate electrode with an insulating layer in between; a pair of source-drain electrodes electrically connected to the semiconductor layer; and a contact layer provided in a moving path of carriers between each of the pair of source-drain electrodes and the semiconductor layer, the contact layer having end surfaces covered with the source-drain electrode. | 2013-05-30 |
20130134428 | ACTIVE DEVICE ARRAY SUBSTRATE - A repair method for repairing an active device array substrate is provided. The active device array substrate includes a substrate, scan lines, data lines, active devices, pixel electrodes, and common lines. At least one of the scan line has an open defect. The scan lines and the data lines are intersected to define sub-pixel regions. The active devices are electrically connected with the scan lines and the data lines correspondingly. Each pixel electrode is disposed in one of the sub-pixel regions and electrically connected with one of the active devices. The repair method includes cutting one of the common lines neighboring to the open defect to form a cutting block that is electrically insulated from the common lines; and welding the cutting block, the scan line having the open defect and two active devices located at two opposite sides of the open defect. | 2013-05-30 |
20130134429 | THIN-FILM TRANSISTOR AND THIN-FILM TRANSISTOR MANUFACTURING METHOD - A thin-film transistor according to the present disclosure includes: a substrate; a gate electrode above the substrate; a gate insulating layer on the gate electrode; a channel layer on the gate insulating layer which is located on the gate electrode; a source electrode above the channel layer; a drain electrode above the channel layer; and a barrier layer between the channel layer and the source electrode and between the channel layer and the drain electrode. Each of the source electrode and the drain electrode is made of a metal including copper, and the barrier layer contains nitrogen and molybdenum and has a density greater than 7.5 g/cm | 2013-05-30 |
20130134430 | Display Device - Display bright in contrast can be obtained without discrination and flicker in the display device of the direct vision type whose pixel pitches are short to 20 μm or less. A liquid crystal panel is driven through the frame inverse driving method, and the vertical frame frequency is set to 120 Hz or more. Also, each of the pixels is arranged to correspond to one of R, G and B of color filters disposed on a TFT substrate side. | 2013-05-30 |
20130134431 | THIN-FILM TRANSISTOR ARRAY MANUFACTURING METHOD, THIN-FILM TRANSISTOR ARRAY, AND DISPLAY DEVICE - Preparing a substrate; forming a plurality of gate electrodes above the substrate; forming a gate insulating layer above the gate electrodes; forming an amorphous silicon layer above the gate insulating layer; forming crystalline silicon layer regions by irradiating the amorphous silicon layer in regions above the gate electrodes with a laser beam having a wavelength from 473 nm to 561 nm so as to crystallize the amorphous silicon layer in the regions above the gate electrodes, and forming an amorphous silicon layer region in a region other than the regions above the gate electrodes; and forming source electrodes and drain electrodes above the crystalline silicon layer regions are included, and a thickness of the gate insulating layer and a thickness of the amorphous silicon layer satisfy predetermined expressions. | 2013-05-30 |
20130134432 | SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING THE SAME - A multi-layered gate electrode of a crystalline TFT is constructed as a clad structure formed by deposition of a first gate electrode, a second gate electrode and a third gate electrode, to thereby to enhance the thermal resistance of the gate electrode. Additionally, an n-channel TFT is formed by selective doping to form a low-concentration impunty region which adjoins a channel forming region, and a sub-region overlapped by the gate electrode and a sub-region not overlapped by the gate electrode, to also mitigate a high electric field near the drain of the TFT and to simultaneously prevent the OFF current of the TFT from increasing. | 2013-05-30 |
20130134433 | Metallization structure for high power microelectronic devices - A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group III nitrides. An interconnect structure is made to the semiconductor portion, and the interconnect structure includes at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The diffusion barrier layers have a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions are large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers. | 2013-05-30 |
20130134434 | NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor device includes a main surface and an indicator portion. The main surface is a plane inclined by at least 71° and at most 79° in a [1-100] direction from a (0001) plane or a plane inclined by at least 71° and at most 79° in a [−1100] direction from a (000-1) plane. The indicator portion indicates a (−1017) plane, a (10-1-7) plane, or a plane inclined by at least −4° and at most 4° in the [1-100] direction from these planes and inclined by at least −0.5° and at most 0.5° in a direction orthogonal to the [1-100] direction. | 2013-05-30 |
20130134435 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided. | 2013-05-30 |
20130134436 | METHOD FOR BONDING SEMICONDUCTOR SUBSTRATES - A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate. | 2013-05-30 |
20130134437 | METHOD FOR FORMING GALLIUM NITRIDE DEVICES WITH CONDUCTIVE REGIONS - Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. | 2013-05-30 |
20130134438 | Light Emitting, Photovoltaic Or Other Electronic Apparatus and System - The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of lenses suspended in a polymer deposited or attached over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes are substantially spherical, and have a ratio of mean diameters or lengths between about 10:1 and 2:1. The diodes may be LEDs or photovoltaic diodes, and in some embodiments, have a junction formed at least partially as a hemispherical shell or cap. | 2013-05-30 |
20130134439 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, PN JUNCTION DIODE, AND METHOD FOR MANUFACTURING AN EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT - Provided is an epitaxial substrate for use in a semiconductor element, having excellent characteristics and capable of suitably suppressing diffusion of elements from a cap layer. An epitaxial substrate for use in a semiconductor element, in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate, includes: a channel layer made of a first group-III nitride having a composition of In | 2013-05-30 |
20130134440 | High-resolution Parallel-detection Sensor Array Using Piezo-Phototronics Effect - A pressure sensor element includes a substrate, a first type of semiconductor material layer and an array of elongated light-emitting piezoelectric nanostructures extending upwardly from the first type of semiconductor material layer. A p-n junction is formed between each nanostructure and the first type semiconductor layer. An insulative resilient medium layer is infused around each of the elongated light-emitting piezoelectric nanostructures. A transparent planar electrode, disposed on the resilient medium layer, is electrically coupled to the top of each nanostructure. A voltage source is coupled to the first type of semiconductor material layer and the transparent planar electrode and applies a biasing voltage across each of the nanostructures. Each nanostructure emits light in an intensity that is proportional to an amount of compressive strain applied thereto. | 2013-05-30 |
20130134441 | GAN-BASED LEDS ON SILICON SUBSTRATES WITH MONOLITHICALLY INTEGRATED ZENER DIODES - GaN LEDs monolithically integrated with silicon-based ESD protection diodes. Hybrid MOCVD or HVPE epitaxial systems may be utilized for in-situ epitaxially growth of doped silicon containing films to form both the silicon-based ESD protection diode material stacks as well as a silicon containing transition layer prior to growth of a GaN-based LED material stack. The silicon-based ESD protection diodes may be interconnected with layers of a GaN LED material stack to form Zener diodes connected with the GaN LEDs. | 2013-05-30 |
20130134442 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A MOSFET includes: a substrate provided with a trench having a side wall surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; an oxide film; and a gate electrode. The substrate includes a source region, a body region, and a drift region formed to sandwich the body region between the source region and the drift region. The source region and the body region are formed by means of ion implantation. The body region has an internal region sandwiched between the source region and the drift region and having a thickness of 1 μm or smaller in a direction perpendicular to a main surface thereof. The body region has an impurity concentration of 3×10 | 2013-05-30 |
20130134443 | NITRIDE SEMICONDUCTOR DIODE - Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current. | 2013-05-30 |
20130134444 | STRESSED TRANSISTOR WITH IMPROVED METASTABILITY - An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material. | 2013-05-30 |
20130134445 | COMPLEX PRIMARY OPTICS AND METHODS OF FABRICATION - A light emitter package with primary optic and method of fabricating the same is disclosed that comprises a light emitter disposed on a surface. The package further comprises at least one intermediate element on the surface and at least partially surrounding the light emitter. Furthermore, an encapsulant is over the light emitter forming a primary optic. The intermediate element at least partially defines the shape of the primary optic. | 2013-05-30 |
20130134446 | COST-EFFECTIVE LED LIGHTING INSTRUMENT WITH GOOD LIGHT OUTPUT UNIFORMITY - The present disclosure involves a lighting instrument. The lighting instrument includes a board or substrate, for example, a printed circuit board. The lighting instrument also includes a plurality of light-emitting devices disposed on the substrate. The light-emitting devices may be light-emitting diode (LED) dies. The LED dies belong to a plurality of different bins. The bins are categorized based on the light output performance of the LED dies. In some embodiments, the LED dies may be binned based on the wavelength or radiant flux of the light output. The LED dies are distributed on the substrate according to a predefined pattern based on their bins. In some embodiments, the LED dies are bin-mixed in an interleaving manner. | 2013-05-30 |
20130134447 | LOW-LIGHT-EMITTING-ANGLE HIGH-LUMINANCE UV LED NAIL LAMP STRUCTURE AND LED LIGHT SOURCE MODULE THEREOF - A low-light-emitting-angle high-luminance ultraviolet (UV) light-emitting diode (LED) nail lamp structure and an LED light source module thereof are provided. The UV LED nail lamp structure includes a housing and an LED light source module. The LED light source module is provided in the housing and has a plurality of UV LEDs, wherein the light-emitting angle of each UV LED ranges between 25° and 80°. The UV LED nail lamp structure features high luminance and enhanced lighting effect. | 2013-05-30 |
20130134448 | LIGHT MODULE AND LIGHT COMPONENT THEREOF - A light component includes a printed circuit board and a plurality of lighting emitting diodes (LEDs). The printed circuit board has a metal substrate. The LEDs are disposed on the printed circuit board, wherein two opposite edges of the metal substrate protrude out and are bent towards the LEDs to form two metal clamps. | 2013-05-30 |
20130134449 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A display panel includes a substrate, a plurality of bottom electrodes, an isolation layer, a plurality of light emitting layers, a top electrode, and at least one first auxiliary electrode. The bottom electrodes and the isolation layer are disposed on the substrate. The isolation layer has a plurality of pixel region openings and at least one buffer region. Each of the pixel region openings respectively exposes the corresponding bottom electrode. The buffer region is disposed between two adjacent pixel region openings. The light emitting layers are respectively disposed on the corresponding bottom electrodes. The top electrode covers the light emitting layers, the isolation layer, and the buffer region. The first auxiliary electrode is disposed in the buffer region. | 2013-05-30 |
20130134450 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light emitting display apparatus including sub pixels, each of the sub pixels including: first and second electrodes, the second electrode extending over the first electrode; and an intermediate layer disposed between the first and second electrodes, the intermediate layer including an emission layer, wherein a first portion of the first electrode, the second electrode, and the intermediate layer extends within a weak resonance region, the weak resonance region being configured to induce a first resonance of light generated by the emission layer between the first and second electrodes, and a second portion of the first electrode, the second electrode, and the intermediate layer extends within a strong resonance region, the strong resonance region being configured to induce a second resonance of light generated by the emission layer between the first and second electrodes, the second resonance being stronger than the first resonance. | 2013-05-30 |
20130134451 | Mask Assembly and Organic Light Emitting Diode Display Manufactured Using the Same - A mask assembly includes a frame forming an opening, and a plurality of unit masks which form a plurality of deposition openings, the longitudinal ends of the unit masks being fixed to the frame. At least two adjacent ones of the plurality of unit masks have deposition recesses formed on both sides facing each other. The width of the deposition recesses along a width direction of the unit masks is equal to or greater than the width of the deposition openings along the width direction of the unit masks. | 2013-05-30 |
20130134452 | DISPLAY DEVICE - Provided is a display device including: a substrate; and multiple pixels provided on the substrate, the pixels each having an organic EL element obtained by laminating a lower electrode provided on the substrate, an organic compound layer, and an upper electrode in the stated order, and the lower electrode including an electrode independently placed for each of the pixels, in which: the lower electrode is formed of a first lower electrode layer provided on the substrate and a second lower electrode layer provided on the first lower electrode layer; the organic compound layer and the upper electrode cover the first lower electrode layer and the second lower electrode layer; and charge injection property from the second lower electrode layer into the organic compound layer is larger than charge injection property from an end portion of the first lower electrode layer into the organic compound layer. | 2013-05-30 |
20130134453 | TRANSISTOR, METHOD OF MANUFACTURING TRANSISTOR, DISPLAY UNIT, AND ELECTRONIC APPARATUS - A transistor includes: a gate electrode; a semiconductor layer facing the gate electrode, with an insulating layer interposed in between; an etching stopper layer on the semiconductor layer; a pair of contact layers provided on the semiconductor layer, at least on both sides of the etching stopper layer; and source-drain electrodes electrically connected to the semiconductor layer through the pair of contact layers, and being in contact with the insulating layer. | 2013-05-30 |
20130134454 | WATER RESISTANT LED DEVICES AND AN LED DISPLAY INCLUDING SAME - The disclosure provides an LED package including a first plastic portion having a mounting surface and a lower surface. In some embodiments, the LED package includes a second portion surrounding the first plastic portion and exposing the mounting surface and the lower surface of the first plastic portion. In other embodiments, the first plastic portion includes at least one of a hole or a protrusion and the second portion includes corresponding structure filing the hole or surrounding the protrusion of the first plastic portion. The first plastic portion and the second portion have different optical properties. | 2013-05-30 |
20130134455 | SEMICONDUCTOR LIGHT EMISSION DEVICE, IMAGE FORMATION APPARATUS AND IMAGE DISPLAY APPARATUS - A semiconductor light emission device includes a substrate, and semiconductor light emission elements mounted on the substrate and each including an anode connection pad and a cathode connection pad. At least one of the anode connection pad and the cathode connection pad has a fine shaped portion. An image formation apparatus and an image display apparatus are described using the semiconductor light emission device. | 2013-05-30 |
20130134456 | OPTICAL ARRANGEMENT FOR A SOLID-STATE LIGHTING SYTEM - An optical arrangement and a solid-state lighting system comprise an optical element having at least one lens where the lens has a faceted surface defining a plurality of facets. An LED light source comprises a plurality of LED chips and is arranged relative to the faceted surface such that the plurality of facets are disposed asymmetrically relative to the plurality of chips such that mixing of light from the plurality of LED chips occurs via the surface. | 2013-05-30 |
20130134457 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device comprising, a substrate and a first transition stack formed on the substrate comprising a first transition layer formed on the substrate having a hollow component formed inside the first transition layer, a second transition layer formed on the first transition layer, and a reflector rod formed inside the second transition layer. | 2013-05-30 |
20130134458 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR PRODUCING THE SAME - A semiconductor light-emitting element includes, a first semiconductor layer, a second semiconductor layer, a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode provided on the second semiconductor layer. A side of the second electrode facing to the second semiconductor layer is composed of at least any one of silver and silver alloy. The second electrode has a void having a width of emission wavelength or less of the light-emitting layer in a plane of the second electrode facing to the second semiconductor layer. | 2013-05-30 |
20130134459 | Micro-Bead Blasting Process for Removing a Silicone Flash Layer - Using compression molding to form lenses over LED arrays on a metal core printed circuit board leaves a flash layer of silicone covering the contact pads that are later required to connect the arrays to power. A method for removing the flash layer involves blasting particles of sodium bicarbonate at the flash layer. A nozzle is positioned within thirty millimeters of the top surface of the flash layer. The stream of air that exits from the nozzle is directed towards the top surface at an angle between five and thirty degrees away from normal to the top surface. The particles of sodium bicarbonate are added to the stream of air and then collide into the top surface of the silicone flash layer until the flash layer laterally above the contact pads is removed. The edge of silicone around the cleaned contact pad thereafter contains a trace amount of sodium bicarbonate. | 2013-05-30 |
20130134460 | COATED COLOR-CONVERTING PARTICLES AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS - Coated color-converting particles and associated devices, systems, and methods are disclosed herein. A coating of the coated color-converting particles can include, for example, a parylene, such as a fluorinated parylene. In particular embodiments, the coating can be configured to protect a color-converting material of a particle core of the coated color-converting particles from detrimental reactions. For example, the coating can prevent, slow, or otherwise inhibit detrimental reactions between the color-converting material and a matrix material or between the color-converting material and an environmental constituent that can diffuse through a matrix. In particular embodiments, the coated color-converting particles can be incorporated into a matrix to form a composite. The composite can be used, for example, with a radiation transducer. Methods associated with the coated color-converting particles can include, for example, separating coated color-converting particles having acceptable coatings from coated color-converting particles having unacceptable coatings using relative buoyancy. | 2013-05-30 |
20130134461 | DISPLAY APPARATUS - A display apparatus includes an organic electroluminescence (OEL) device and a color filter. At different correlated color temperatures (CCTs), a light emitting spectrum of the OEL device is adjusted to meet specific display requirements and improve the display quality of the display apparatus. In addition, a light filtering spectrum of the color filter is adjusted simultaneously to match the light emitting spectrum of the OEL device, so that the display apparatus has an excellent display effect. | 2013-05-30 |
20130134462 | Light emitting diode having multi-cell structure and method of manufacturing the same - Disclosed is a light emitting diode having a multi-cell structure including a number of unit cells. The light emitting diode is capable of reducing light loss of the light emitting diode surface and improving light efficiency by bonding pads to be formed for contact between mesa etching regions for forming an electrode of the existing n-type semiconductor layers and p-type semiconductor layers. The light emitting diode is also capable of controlling chip size and manufacturing chips of different sizes from each other even when going through the same chip manufacturing process as the related art. | 2013-05-30 |
20130134463 | LED PACKAGE AND LIGHT EMITTING DEVICE HAVING THE SAME - An exemplary LED package includes first and second electrodes, an LED die and an encapsulation. An inner wall of each first and second electrode includes a first oblique plane. The LED die is surrounded by and electrically connected to the first and second electrodes. The LED die includes an outputting surface. The encapsulation is filled between the first electrode ant the second electrode and covers the LED die, and includes opposite first and second outer surfaces, wherein the second outer surface acts as an outputting surface of the LED package. A reflective layer is coated on the first outer surface of the encapsulation. The first oblique plane of the electrode structure is light reflective and extends aslant from the outputting surface of the LED die towards the outputting surface of the LED package along a direction away from the LED die. | 2013-05-30 |
20130134464 | LIGHT EMITTING DIODE DEVICE AND FLIP-CHIP PACKAGED LIGHT EMITTING DIODE DEVICE - The present invention relates to a light emitting diode (LED) and a flip-chip packaged LED device. The present invention provides an LED device. The LED device is flipped on and connected electrically with a packaging substrate and thus forming the flip-chip packaged LED device. The LED device mainly has an Ohmic-contact layer and a planarized buffer layer between a second-type doping layer and a reflection layer. The Ohmic-contact layer improves the Ohmic-contact characteristics between the second-type doping layer and the reflection layer without affecting the light emitting efficiency of the LED device and the flip-chip packaged LED device. The planarized buffer layer id disposed between the Ohmic-contact layer and the reflection layer for smoothening the Ohmic-contact layer and hence enabling the reflection layer to adhere to the planarized buffer layer smoothly. Thereby, the reflection layer can have the effect of mirror reflection and the scattering phenomenon on the reflected light can be reduced as well. | 2013-05-30 |
20130134465 | VERTICAL TOPOLOGY LIGHT EMITTING DEVICE - A vertical topology light emitting device comprises a conductive adhesion structure having a first surface and a second surface; a conductive support structure on the first surface; a reflective structure on the second surface, the reflective structure also serving as a first electrode; a semiconductor structure on the reflective structure; and a second electrode on the semiconductor structure. | 2013-05-30 |
20130134466 | LED PACKAGE - An LED package is provided, which includes a base, a lighting device, and a sealing material. The lighting device is disposed on the base. The sealing material is disposed on the lighting material, and the out surface of the sealing material includes a plurality of micro-structures. The micro-structures comprise of protruded micro-structures, depressed micro-structures or any combination thereof. At least of a partial of a light from the lighting element is transmitted to an ambient through the micro-structure. | 2013-05-30 |
20130134467 | ELEMENT-CONNECTING BOARD, PRODUCING METHOD THEREOF, AND LIGHT-EMITTING DIODE DEVICE - An element-connecting board is a lead frame for allowing a light emitting diode element to be connected to one side thereof in a thickness direction. The element-connecting board includes the lead frame which is provided with a plurality of leads disposed with spaces from each other and a first insulating resin portion which is light reflective and fills the spaces. | 2013-05-30 |
20130134468 | OPTICAL SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In an optical semiconductor package, a method of manufacturing the same, and an optical semiconductor device according to the present invention, a thermosetting resin such as an unsaturated polyester resin is used for a reflector | 2013-05-30 |
20130134469 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first, a second and a third conductive layer. The stacked structural body includes first and second semiconductors and a light emitting layer provided therebetween. The second semiconductor layer is disposed between the first conductive layer and the light emitting layer. The first conductive layer is transparent. The first conductive layer has a first major surface on a side opposite to the second semiconductor layer. The second conductive layer is in contact with the first major surface. The third conductive layer is in contact with the first major surface and has a reflectance higher than a reflectance of the second conductive layer. The third conductive layer includes an extending part extending in parallel to the first major surface. At least a portion of the extending part is not covered by the second conductive layer. | 2013-05-30 |
20130134470 | LIGHT EMITTING DIODE PACKAGE MODULE - Disclosed herein is a light emitting diode package module, including: a substrate; a light emitting diode package formed on the substrate; an instrument member formed below the substrate; and a magnetic body formed on the substrate, the light emitting diode package, or the instrument member. | 2013-05-30 |
20130134471 | LED SUBSTRATE STRUCTURE, LED UNIT AND LIGHTING MODULE HAVING THE SAME - An LED substrate structure has a substrate and a conducting portion. The substrate has a bottom surface and two opposite first lateral surfaces connected with the bottom surface. The bottom surface has the conducting portion formed thereon, and the conducting portion has a first cutting segment located on a contact border defined between one of the two first lateral surfaces and the bottom surface. The conducting portion further has an expansion region connected with the first cutting segment. The length of the first cutting segment is shorter than any segment taken on the expansion region parallel thereto. | 2013-05-30 |
20130134472 | LIGHT EMITTING DIODE PACKAGE AND A METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package comprises a LED, and a lead frame electrically connected to the LED. The lead frame includes a notch which has a predetermined size and a predetermined shape configured to separate a solder paste into two regions on either side of the notch when the solder paste is disposed on the lead frame. | 2013-05-30 |
20130134473 | Radiation-Emitting Semiconductor Body, Method for Producing a Radiation-Emitting Semiconductor Body and Radiation-Emitting Semiconductor Component - A radiation-emitting semiconductor body is provided which, besides an epitaxial semiconductor layer sequence having an active zone that is suitable for generating electromagnetic radiation, has a carrier layer that is intended to mechanically stabilize the epitaxial semiconductor layer sequence. The semiconductor body furthermore has contact structures for electrical contacting of the semiconductor body, which respectively have a volume region and a surface bonding region. The surface bonding region is formed from a material which is different from the material of the volume region. | 2013-05-30 |
20130134474 | LIGHT EMITTING ELEMENT, METHOD FOR MANUFACTURING SAME, AND LIGHT EMITTING DEVICE - Organic light-emitting elements each have the following structure: a transparent anode, a functional layer including a charge injection layer and an organic light-emitting layer, and a transparent cathode are layered on a substrate in the stated order; a bank defines a formation area of the organic light-emitting layer; the charge injection layer is a metal oxide layer formed by oxidizing an upper surface portion of the anode composed of the metal layer, and a portion of the charge injection layer that is positioned under the area is depressed so as to form a recess; and the upper peripheral edge of the recess is covered with a covering portion of the bank. | 2013-05-30 |
20130134475 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device is provided and includes an n-type semiconductor layer, a p-type semiconductor layer having a structure in which first and second doping regions including p-type impurities provided in different doping concentrations are alternately disposed one or more times; and an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer, wherein the p-type semiconductor layer includes at least one interface between the first and second doping regions to prevent diffusion of p-type impurities. | 2013-05-30 |
20130134476 | SOLID-STATE DIODE - The solid-state diode comprises a semiconductor substrate having a top side and having two masking regions formed on the top side of the semiconductor substrate and made of a first masking material impermeable to ion implantation, the masking regions comprising two mutually opposite limiting edge portions. The solid-state diode comprises an n-doped cathode region formed in the semiconductor substrate and extending up into the intermediate region between the mutually opposite limiting edge portions of the masking regions, the n-doped cathode region comprising a cathode connection field. The diode comprises a p-doped anode region formed in the semiconductor substrate, extending up into the intermediate region between the mutually opposite limiting edge portions of the masking regions and bordering/overlapping on the cathode region, the p-doped anode region comprising an anode connection field. The masking regions and either the cathode or the anode connection field are substantially on the same electric potential. | 2013-05-30 |
20130134477 | BACK GATE TRIGGERED SILICON CONTROLLED RECTIFIERS - Back gate triggered silicon controlled rectifiers (SCR) and methods of manufacture are disclosed. The method includes forming a first diffusion type and a second diffusion type in a semiconductor layer of a silicon on insulator (SOI) substrate. The method further includes forming a back gate of a first diffusion type in a substrate under an insulator layer of the SOI substrate. The method further includes forming raised diffusion regions of a first dopant type and a second dopant type, adjacent to the second diffusion type and the first diffusion type, respectively. The back gate is formed to cover the second diffusion type, the first diffusion type and the second dopant type of the raised diffusion regions. | 2013-05-30 |
20130134478 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: an n | 2013-05-30 |
20130134479 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An ESD protection device including second P-type wells, first P+-type doped regions, first N+-type doped regions and a P-type substrate having a first P-type well, an N-type well and an N-type deep well is provided. The second P-type wells are disposed in the N-type deep well. The first P+-type doped regions and the first N+-type doped regions are respectively disposed in the first P-type well, the N-type well and the second P-type wells in alternation. The first P+-type doped region in the N-type well and the N-type deep well are electrically connected to the first connection terminal. The doped regions in the first P-type well and the P-type substrate are electrically connected to the second connection terminal. The second P-type wells and the first N+-type doped regions therein form a diode string connected in series between the first N+-type doped region of the N-type well and the second connection terminal. | 2013-05-30 |
20130134480 | Formation of Devices by Epitaxial Layer Overgrowth - Methods and structures are provided for formation of devices, e.g., solar cells, on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer. | 2013-05-30 |
20130134481 | Split-Channel Transistor and Methods for Forming the Same - A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel. | 2013-05-30 |
20130134482 | SUBSTRATE BREAKDOWN VOLTAGE IMPROVEMENT FOR GROUP III-NITRIDE ON A SILICON SUBSTRATE - A method of making a high-electron mobility transistor (HEMT) includes forming an unintentionally doped gallium nitride (UID GaN) layer over a silicon substrate, a donor-supply layer over the UID GaN layer, a gate, a passivation layer over the gate and portions of the donor-supply layer, an ohmic source structure and an ohmic drain structure over the donor-supply layer and portions of the passivation layer. The source structure includes a source contact portion and an overhead portion. The overhead portion overlaps the passivation layer between the source contact portion and the gate, and may overlap a portion of the gate and a portion of the passivation layer between the gate and the drain structure. | 2013-05-30 |
20130134483 | BIPOLAR TRANSISTOR WITH A RAISED COLLECTOR PEDASTAL FOR REDUCED CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR - Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased. | 2013-05-30 |
20130134484 | ABUTMENT STRUCTURE OF SEMICONDUCTOR CELL - An abutment structure comprises a power rail, a ground rail parallel to the power rail, first cells and second cells. An area is defined between the power and the ground rails. A portion of each first and second cell overlaps the power and the ground rails, and another portion thereof is within the area. The first cells are within the abutment structure with original patterns thereof. The second cells respectively has an original pattern and a base pattern being a flip pattern of the original pattern, and are within the area with alternate of the original and the base patterns. The first and the second cells are within the area alternately without overlapping. Alternatively, the first and the second cells may also be within different areas, and the second cells are within different areas respectively with the base pattern and a flip pattern of the base pattern thereof. | 2013-05-30 |
20130134485 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions. | 2013-05-30 |
20130134486 | Methods of Patterning Features in a Structure Using Multiple Sidewall Image Transfer Technique - Disclosed herein are methods of patterning features in a structure, such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate, using a multiple sidewall image transfer technique. In one example, the method includes forming a first mandrel above a structure, forming a plurality of first spacers adjacent the first mandrel, forming a plurality of second mandrels adjacent one of the first spacers, and forming a plurality of second spacers adjacent one of the second mandrels. The method also includes performing at least one etching process to selectively remove the first mandrel and the second mandrels relative to the first spacers and the second spacers and thereby define an etch mask comprised of the first spacers and the second spacer and performing at least one etching process through the etch mask on the structure to define a plurality of features in the structure. | 2013-05-30 |
20130134487 | POWER TRANSISTOR DEVICE WITH SUPER JUNCTION AND MANUFACTURING METHOD THEREOF - The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type. | 2013-05-30 |
20130134488 | Semiconductor Device and Manufacturing Method thereof - A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region. | 2013-05-30 |
20130134489 | PIXEL STRUCTURE AND FABRICATING METHOD THEREOF - A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern. | 2013-05-30 |
20130134490 | LOW RESISTANCE EMBEDDED STRAP FOR A TRENCH CAPACITOR - A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode. | 2013-05-30 |
20130134491 | POLYSILICON/METAL CONTACT RESISTANCE IN DEEP TRENCH - A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer. | 2013-05-30 |
20130134492 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Example embodiments of inventive concepts relate to semiconductor memory devices and/or methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel penetrating the plurality of gates and a data storage layer between the vertical channel and the plurality of gates. The vertical channel may include a lower channel connected to the substrate and an upper channel on the lower channel. The upper channel may include a vertical pattern penetrating some of the plurality of gates and defining an inner space filled with an insulating layer, and a horizontal pattern horizontally extending along a top surface of the lower channel. The horizontal pattern may be in contact with the top surface of the lower channel. | 2013-05-30 |
20130134493 | VERTICAL CHANNEL MEMORY DEVICES WITH NONUNIFORM GATE ELECTRODES - A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers. | 2013-05-30 |
20130134494 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese. | 2013-05-30 |
20130134495 | FLASH MEMORY AND METHOD FOR FORMING THE SAME - A flash memory cell is provided. The flash memory cell includes: a substrate with a source line thereon; a word line and a word line dielectric layer on each side of the source line; an isolating dielectric layer which isolates the source line from the word line and the word line dielectric layer on each side of the source line; a gate stack on an outer side of each word line dielectric layer, including a floating gate dielectric layer, a floating gate, a control gate dielectric layer and a control gate; a first spacer, disposed on an outer sidewall of each word line dielectric layer and on each control gate; and a source region in the substrate and in contact with the source line. The space may be saved and the costs may be reduced. | 2013-05-30 |
20130134496 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns. | 2013-05-30 |
20130134497 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is described, including a gate over a substrate, a gate dielectric between the gate and the substrate, and two charge storage layers. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein the edge of the first extension portion protrudes from the sidewall of the second extension portion. | 2013-05-30 |
20130134498 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate. | 2013-05-30 |
20130134499 | NONVOLATILE PROGRAMMABLE SWITCHES - A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases. | 2013-05-30 |
20130134500 | POWER SEMICONDUCTOR DEVICE - A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions. | 2013-05-30 |
20130134501 | METHOD OF MANUFACTURING A VERTICAL-TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A VERTICAL-TYPE SEMICONDUCTOR DEVICE - In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes. | 2013-05-30 |
20130134502 | WAFER LEVEL CHIP SCALE PACKAGE - A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads. | 2013-05-30 |
20130134503 | CROSS-POINT DIODE ARRAYS AND METHODS OF MANUFACTURING CROSS-POINT DIODE ARRAYS - Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts. | 2013-05-30 |
20130134504 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a substrate including a trench, and a gate electrode disposed at a position adjacent to the trench on the substrate, the gate electrode having a first side surface located on an opposite side of the trench, and a second side surface located on the same side as the trench. The device further includes a first sidewall insulator disposed on the first side surface, and a second sidewall insulator disposed on the second side surface and a side surface of the trench. The device further includes a source region of a first conductivity type disposed in the substrate on the same side as the first sidewall insulator with respect to the first side surface, and a drain region of a second conductivity type disposed in the substrate on the same side as the second sidewall insulator with respect to the second side surface. | 2013-05-30 |
20130134505 | SEMICONDUCTOR DEVICE FOR POWER AND METHOD OF MANUFACTURE THEREOF - According to one embodiment, a semiconductor device for power is provided with a first conductive type a first semiconductor layer, a field insulating film, a field plate electrode, a first insulating film, an electric conductor, a second insulating film, a gate insulating film, and a gate electrode. The field plate electrode is installed in a trench of the first semiconductor layer over the field insulating film. The first insulating film is formed on the field plate electrode and encloses the field plate electrode along with the field insulating film. The electric conductor is formed on the first insulating film and is insulated from the field plate electrode. The gate electrode is installed on the upper end of the field insulating film, adjacently makes contact with the electric conductor via the second insulating film, and is installed in the trench over the gate insulating film. | 2013-05-30 |
20130134506 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - A fin type semiconductor layer is formed on a substrate with a source and a drain. A dummy gate is formed crossing the fin type semiconductor layer. After depositing an insulating film on the dummy gate, the upper surface of the dummy gate is exposed. The dummy gate is then removed to form a gate trench. On the surface of the fin type semiconductor layer in the gate trench, a gate insulating film is formed. Material for a gate electrode is filled in the gate trench and etched to form the gate electrode. The height of the upper surface of the gate electrode is equal to or lower than the height of the upper surface of the fin type semiconductor layer at the source and the drain, and is equal to or higher than the height of the upper surface of the fin type semiconductor layer in the gate trench. | 2013-05-30 |
20130134507 | SEMICONDUCTOR DEVICE INCLUDING SHARED PILLAR LOWER DIFFUSION LAYER - A semiconductor device includes a high-breakdown voltage transistor in which at least first and second vertical transistor are connected in series to each other. The first vertical transistor includes a first unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The second vertical transistor includes a second unit transistor group having a plurality of unit transistors each having a semiconductor pillar. The plurality of unit transistors constituting the first and the second unit transistor groups have pillar lower diffusion layers which are shared. | 2013-05-30 |
20130134508 | SEMICONDUCTOR DEVICE WITH SIDE-JUNCTION AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench. | 2013-05-30 |
20130134509 | Semiconductor Device Arrangement Comprising a Semiconductor Device with a Drift Region and a Drift Control Region - A semiconductor device includes a source region, a drain region, a body region, and a drift region. The drift region is arranged between the body and the drain and the body is arranged between the source and the drift region in a semiconductor body. A gate electrode is adjacent the body and dielectrically insulated from the body by a gate dielectric. A drift control region is adjacent the drift region and dielectrically insulated from the drift region by a drift control region dielectric. A drain electrode adjoins the drain. The device also includes an injection control region of the same doping type as the drain, but more lowly doped. The injection control region adjoins the drift control region dielectric, extends in a first direction along the drift control region, and adjoins the drain in the first direction and an injection region in a second direction different from the first direction. | 2013-05-30 |
20130134510 | SEMICONDUCTOR DEVICE - In the interior of a semiconductor substrate having a main surface, a first p | 2013-05-30 |
20130134511 | Semiconductor Device with Self-Biased Isolation - A device includes a semiconductor substrate including a surface, a drain region in the semiconductor substrate having a first conductivity type, a well region in the semiconductor substrate on which the drain region is disposed, the well region having the first conductivity type, a buried isolation layer in the semiconductor substrate extending across the well region, the buried isolation layer having the first conductivity type, a reduced surface field (RESURF) region disposed between the well region and the buried isolation layer, the RESURF region having a second conductivity type, and a plug region in the semiconductor substrate extending from the surface of the substrate to the RESURF region, the plug region having the second conductivity type. | 2013-05-30 |
20130134512 | Power MOSFETs and Methods for Forming the Same - A power MOSFET includes a semiconductor region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor region is of a first conductivity type. A gate dielectric and a gate electrode are disposed over the semiconductor region. A drift region of a second conductivity type opposite the first conductivity type extends from the top surface of the semiconductor substrate into the semiconductor substrate. A dielectric layer has a portion over and in contact with a top surface of the drift region. A conductive field plate is over the dielectric layer. A source region and a drain region are on opposite sides of the gate electrode. The drain region is in contact with the first drift region. A bottom metal layer is over the field plate | 2013-05-30 |
20130134513 | FINFET WITH IMPROVED GATE PLANARITY - A FinFET with improved gate planarity and method of fabrication is disclosed. The gate is disposed on a pattern of fins prior to removing any unwanted fins. Lithographic techniques or etching techniques or a combination of both may be used to remove the unwanted fins. All or some of the remaining fins may be merged. | 2013-05-30 |
20130134514 | THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A thin film transistor and a fabricating method thereof are provided. The thin film transistor includes a gate, a gate insulator, an oxide semiconductor layer, a source, a drain, and a light barrier. The gate insulator covers the gate. The oxide semiconductor layer is disposed on the gate insulator and located above the gate. The source and the drain are disposed on parts of the oxide semiconductor layer. The light barrier is located above the oxide semiconductor layer and includes a first insulator, an ultraviolet shielding layer, and a second insulator. The first insulator is disposed above the oxide semiconductor layer. The ultraviolet shielding layer is disposed on the first insulator. The second insulator is disposed on the ultraviolet shielding layer. | 2013-05-30 |
20130134515 | Semiconductor Field-Effect Transistor Structure and Method for Manufacturing the Same - The present application discloses a semiconductor Field-Effect Transistor (FET) structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising an SOI structure having a body-contact hole; forming a fin on the SOI structure of the semiconductor substrate; forming a gate stack structure on top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof becomes simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated; the present invention also is favorable for suppressing short channel effects desirably, and boosts MOSFETs to develop towards a trend of downscaling size. | 2013-05-30 |
20130134516 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising a local SOI structure having a local buried isolation dielectric layer; forming a fin on the silicon substrate on top of the local buried isolation dielectric layer; forming a gate stack structure on the top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof is simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated, therefore, short channel effects are suppressed desirably, and MOSFETs are boosted to develop towards a trend of downscaling size. | 2013-05-30 |
20130134517 | BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES - After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer. | 2013-05-30 |
20130134518 | NOBLE GAS IMPLANTATION REGION IN TOP SILICON LAYER OF SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas. | 2013-05-30 |
20130134519 | SEMICONDUCTOR DEVICE - A semiconductor device includes a conductive film formed on an insulating film, and a first polysilicon film formed on the conductive film. A stacked film including the conductive film and the first polysilicon film forms a first pattern including a central region, and end regions each located at a side of the central region. A silicide film is formed on at least the central region of the stacked film. A discontinuity is formed in a central region of the conductive film. The conductive film is separated into the two portions by the discontinuity. | 2013-05-30 |