22nd week of 2015 patent applcation highlights part 62 |
Patent application number | Title | Published |
20150149713 | MEMORY INTERFACE DESIGN - An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit. | 2015-05-28 |
20150149714 | CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET - In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed. | 2015-05-28 |
20150149715 | NONVOLATILE RANDOM ACCESS MEMORY USE - For nonvolatile random access memory (NVRAM) use, a query module identifies persistent data on a NVRAM in response to waking the NVRAM. A management module makes available the persistent data for use. | 2015-05-28 |
20150149716 | WRITE AND READ COLLISION AVOIDANCE IN SINGLE PORT MEMORY DEVICES - A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time. | 2015-05-28 |
20150149717 | PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY - Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2 | 2015-05-28 |
20150149718 | A LOWER ENERGY CONSUMPTION AND HIGH SPEED COMPUTER SYSTEM AND A MARCHING MAIN MEMORY ADAPTED FOR THE COMPUTER SYSTEM, WITHOUT THE MEMORY BOTTLENECK - A computer system encompasses a processor ( | 2015-05-28 |
20150149719 | FLEXIBLE DATA STORAGE SYSTEM - Methods and systems for managing and locating available storage space in a system comprising data files stored in a plurality of storage devices and configured in accordance with various data storage schemes (mirroring, striping and parity-striping). A mapping table associated with each of the plurality of storage devices is used to determine the available locations and amount of available space in the storage devices. The data storage schemes for one or more of the stored data files are changed to a basic storage mode when the size of a new data file configured in accordance with an assigned data storage scheme exceeds the amount of available space. The configured new data file is stored in accordance with the assigned data storage scheme in one or more of the available locations and the locations of the new data file are recorded. | 2015-05-28 |
20150149720 | CONTROL METHOD, CONTROL DEVICE, AND RECORDING MEDIUM - A non-transitory computer-readable recording medium has stored therein a program that causes a computer to execute a control process. The control process includes: receiving an access request for a recording device that stores data; determining whether or not index information corresponding to the access request, which is received at the receiving, is stored in a memory that stores index information that is obtained by shortening identification information identifying data from the recording device cached in a non-volatile memory; and accessing the non-volatile memory when it is determined that the index information is stored in the memory and accessing the recording device when it is determined that the index information is not in the memory. | 2015-05-28 |
20150149721 | SELECTIVE VICTIMIZATION IN A MULTI-LEVEL CACHE HIERARCHY - Systems, methods, and apparatuses for implementing selective victimization to reduce power and utilized bandwidth in a multi-level cache hierarchy. Each set of an upper-level cache includes a counter that keeps track of the number of times the set was accessed. These counters are periodically decremented by another counter that tracks the total number of accesses to the cache. If a given set counter is below a certain threshold value, clean victims are dropped from this given set instead of being sent to a lower-level cache. Also, a separate counter is used to track the total number of outstanding requests for the cache as a proxy for bus-bandwidth in order to gauge the total amount of traffic in the system. The cache will implement selective victimization whenever there is a large amount of traffic in the system. | 2015-05-28 |
20150149722 | DELAYING CACHE DATA ARRAY UPDATES - Systems, methods, and apparatuses for reducing writes to the data array of a cache. A cache hierarchy includes one or more L1 caches and a L2 cache inclusive of the L2 cache(s). When a request from the L1 cache misses in the L2 cache, the L2 cache sends a fill request to memory. When the fill data returns from memory, the L2 cache delays writing the fill data to its data array. Instead, this cache line is written to the L1 cache and a clean-evict bit corresponding to the cache line is set in the L1 cache. When the L1 cache evicts this cache line, the L1 cache will write back the cache line to the L2 cache even if the cache line has not been modified. | 2015-05-28 |
20150149723 | HIGH-PERFORMANCE INSTRUCTION CACHE SYSTEM AND METHOD - A method is provided for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory faster than the first memory and a third memory faster than the second memory. The method includes examining instructions being filled from the second memory to the third memory, extracting instruction information containing at least branch information; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that possibly be executed by the processor core based on one or more tracks from a plurality of instruction tracks from the first memory to the second memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second memory to the third memory before the processor core executes the instructions, such that the processor core fetches the instructions from the third memory. | 2015-05-28 |
20150149724 | ARITHMETIC PROCESSING DEVICE, ARITHMETIC PROCESSING SYSTEM, AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING DEVICE - An arithmetic processing device includes: a arithmetic cores, wherein the arithmetic core comprises: an instruction controller configured to request processing corresponding to an instruction; a memory configured to store lock information indicating that a locking target address is locked, the locking target address, and priority information of the instruction; and a cache controller configured to, when storing data of a first address in a cache memory to execute a first instruction including locking of the first address from the instruction controller, suppress updating of the memory if the lock information is stored in the memory and a priority of the priority information is higher than a first priority of the first instruction. | 2015-05-28 |
20150149725 | MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS - A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address. | 2015-05-28 |
20150149726 | DATA DISTRIBUTION DEVICE AND DATA DISTRIBUTION METHOD - A data distribution device includes: a memory configured to store cache data of data to be distributed; and a processor coupled to the memory and configured to: read the cache data from the memory in accordance with a request message received from other devices to distribute the cache data to the other devices, update, when the request message is received, a counter value that gets closer to a given value with time, so as to make the counter value move away from the given value in accordance with a reference value that is a reciprocal of a threshold value of a reception rate of the request message, whether or not to store the cache data being determined based on the reception rate; and discard the cache data in the memory when the counter value becomes the given value. | 2015-05-28 |
20150149727 | WRITE AND READ COLLISION AVOIDANCE IN SINGLE PORT MEMORY DEVICES - A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time. | 2015-05-28 |
20150149728 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a received write request, and an arbiter configured to store a write address and write data associated with the write request in a write cache in response to a command from the address monitor, wherein the command generated by the address monitor is based on whether an update is made to the physical address and the write count in first address cache. | 2015-05-28 |
20150149729 | CACHE MIGRATION - Exemplary methods, apparatuses, and systems determine that a cache is to be migrated from a first storage device to a second storage device. The cache includes cache entries organized in a first list of cache entries and a second list of cache entries. Only a portion of all cache entries from the first and second lists is selected for migration to the second storage device. The selected cache entries and metadata for cache entries from the first or second list that were not selected are migrated from the first storage device to the second storage device. | 2015-05-28 |
20150149730 | CACHE MIGRATION - Exemplary methods, apparatuses, and systems determine that a cache is to be migrated from a first storage device to a second storage device. Each cache entry within the cache includes a first indicator to indicate whether or not the cache entry has long-term utility. Only a portion of all cache entries are selected to be migrated and the portion is selected from cache entries with the first indicator set to indicate long-term utility. The selected cache entries and metadata for cache entries that were not selected are migrated from the first storage device to the second storage device. | 2015-05-28 |
20150149731 | I/O CONTROLLER AND METHOD FOR OPERATING AN I/O CONTROLLER - An I/O controller, coupled to a processing unit and to a memory, includes an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator to translate received virtual addresses into real addresses by translation control entries and a cache allocated to the address translator to cache a number of the translation control entries; an I/O packet processing unit for checking the data packets received at the I/O link interface and for forwarding the checked data packets to the address translation unit; and a prefetcher to forward address translation prefetch information from a data packet received to the address translation unit; the address translator configured to fetch the translation control entry for the data packet by the address translation prefetch information from the allocated cache or, if the translation control entry is not available in the allocated cache, from the memory. | 2015-05-28 |
20150149732 | SYSTEM AND METHODS FOR CPU COPY PROTECTION OF A COMPUTING DEVICE - The present disclosure relates to techniques for system and methods for software-based management of protected data-blocks insertion into the memory cache mechanism of a computerized device. In particular the disclosure relates to preventing protected data blocks from being altered and evicted from the CPU cache coupled with buffered software execution. The technique is based upon identifying at least one conflicting data-block having a memory mapping indication to a designated memory cache-line and preventing the conflicting data-block from being cached. Functional characteristics of the software product of a vendor, such as gaming or video, may be partially encrypted to allow for protected and functional operability and avoid hacking and malicious usage of non-licensed user. | 2015-05-28 |
20150149733 | SUPPORTING SPECULATIVE MODIFICATION IN A DATA CACHE - Method and system for supporting speculative modification in a data cache are provided and described. In one embodiment, a speculative cache buffer includes a plurality of cache lines and a plurality of state indicators. At least one of the cache lines is operable to receive an evicted cache line from a cache. The at least one of the cache lines is operable to return the evicted cache line to the cache if the cache requests the evicted cache line. Further, the plurality of state indicators is operable to indicate a state of a corresponding cache line of the cache lines. | 2015-05-28 |
20150149734 | Combined Transparent/Non-Transparent Cache - In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion. | 2015-05-28 |
20150149735 | MEMORY SYSTEM - Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller. | 2015-05-28 |
20150149736 | FAST RESTART OF APPLICATIONS USING SHARED MEMORY - Technologies are described for restarting an application while maintaining data in memory (e.g., using shared memory). For example, shared memory can be associated with an application. The shared memory can also be associated with a holder process to maintain the shared memory from the time the application stops to the time the application starts again. When the application starts, the shared memory can be associated with the started application. In addition, restart of in-memory databases can be provided using shared memory. For example, in-memory data can be maintained when a database process or database management system stops and starts (e.g., during a restart). | 2015-05-28 |
20150149737 | METHOD OR SYSTEM FOR ACCESS TO SHARED RESOURCE - Methods and/or systems are provided that may be utilized to read from or write to a resource, such as a shared memory, for example. | 2015-05-28 |
20150149738 | CONTINUOUS PAGE READ FOR MEMORY - Subject matter disclosed herein relates to techniques to read memory in a continuous fashion. | 2015-05-28 |
20150149739 | METHOD OF STORING DATA IN DISTRIBUTED MANNER BASED ON TECHNIQUE OF PREDICTING DATA COMPRESSION RATIO, AND STORAGE DEVICE AND SYSTEM USING SAME - A method of storing data in a distributed manner based on data compression ratio prediction, and a mass storage device and system using the method are disclosed. The device includes a compression ratio predicting unit, a compressing unit, and a control unit. When an address and first unit sized data are received, the compression ratio predicting unit estimates the predicted compression ratio of the first unit sized data. The compressing unit generates compressed data. The control unit calculates the benefit of compression based on at least the estimated predicted compression ratio, stores the compressed data in a first storage area if the calculated benefit of compression is higher than a predetermined benefit threshold value, and stores the first unit sized data in the second storage area if the calculated benefit of compression is equal to or lower than the predetermined benefit threshold value. | 2015-05-28 |
20150149740 | DATA STORAGE DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A data processing system includes a data storage device including memory cells, which are erased to an erasure state and programmed to program states to store data, and a host device suitable for accessing the data, wherein the data storage device programs a first memory cell to a first state other than the erasure state to delete data of the first memory cell in response to a request of the host device. | 2015-05-28 |
20150149741 | Storage System and Control Method Thereof - A storage system has a plurality of physical blocks, a buffer and a controller. In response to an unmap command received from an operating machine, the controller moves a mapping between a physical block and a logical block of the storage system to a buffer to prepare a deallocation procedure. Then, the controller transmits a completion response to the operating machine. The unmap command is used to cancel the mapping, the completion response is used to notify the operating machine that execution of the unmap command has been finished, and the deallocation procedure is used to deallocate the physical block according to the mapping in the buffer. After the completion response has been transmitted to the operating machine, the controller deallocates the physical block according to workload of the storage system. | 2015-05-28 |
20150149742 | MEMORY UNIT AND METHOD - A memory unit and method are disclosed. The memory unit comprises: at least one controller interfaced with at least one corresponding persistent memory device operable to store files in accordance with a file system; and a file mapping unit operable, in response to a virtual file access request from a memory management unit of a processor, the virtual file access request having a virtual address within a virtual address space associated with one of the files identifying data to be accessed, to map the virtual address to a physical address of the data within the one of the files using pre-stored mapping information and to issue a physical access request having the physical address to access the data within the one of the files. | 2015-05-28 |
20150149743 | MANAGEMENT METHOD OF VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION SYSTEM USING PART OF BITS OF VIRTUAL ADDRESS AS INDEX - A management method of a virtual-to-physical address translation system includes the following steps: providing a first storage space, wherein the first storage space includes a plurality of buffer entries; providing a second storage space, wherein the second storage space includes a plurality of translation entries, and the translation entries correspond to a plurality of translation indices; and when receiving a write instruction to write a first virtual-to-physical address translation into a specific buffer entry of the buffer entries, storing the first virtual-to-physical address translation in a write translation entry of the translation entries according to a first part of bits of a first virtual address corresponding to the first virtual-to-physical address translation, and storing the first virtual address and a write translation index corresponding to the write translation entry in the specific buffer entry. | 2015-05-28 |
20150149744 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING VECTOR PROCESSING - A data processing apparatus and method are provided for processing execution threads, where each execution thread specifies at least one instruction. The data processing apparatus has a vector processing unit providing a plurality M of lanes of parallel processing, within each lane the vector processing unit being configured to perform a processing operation on a data element input to that lane for each of one or more input operands. A vector instruction is received that is specified by a group of the execution threads, that vector instruction identifying an associated processing operation and also providing an indication of the data elements of each input operand that are to be subjected to that associated processing operation. Vector merge circuitry then determines, based on that information, a required number of lanes of parallel processing for performing the associated processing operation. If it is determined that the required number of lanes is less than or equal to half the available number of lanes within the vector processing unit, then the vector merge circuitry allocates a plurality of the execution threads of the group to the vector processing unit such that each execution thread in that plurality is allocated different lanes amongst the available lanes of parallel processing. As a result, the vector processing unit then performs the associated processing operation in parallel for each of the plurality of execution threads, significantly increasing performance. | 2015-05-28 |
20150149745 | PARALLELIZATION WITH CONTROLLED DATA SHARING - In one general aspect, a method can include executing multiple functions calls in parallel, and receiving, by each function call, at least one data object passed as a parameter to the function call, the at least one data object associated with a data sharing mode that defines a restricted subset of allowed operations for performing by the function call on the at least one data object. The method can further include performing, by each function call, at least one operation on the at least one data object, the at least one operation included in the restricted subset of allowed operations, and performing at least one check to ensure that the at least one operation performed by the function call on the at least one data object received by the function call is included in the restricted subset of allowed operations. | 2015-05-28 |
20150149746 | ARITHMETIC PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, AND A METHOD OF CONTROLLING THE INFORMATION PROCESSING DEVICE - An arithmetic processing device promotes transmission efficiency between a processor and a memory. The arithmetic processing device has an arithmetic processing unit which issues an instruction accompanying with data which is sent to the memory, a judgment unit which judges whether or not a redundancy degree of the data which is accompanied with the instruction is more than a predetermined value, a compression unit which judges whether or not compress the data based on an waiting time and a compression time when the redundancy degree of the data is more than the predetermined value, and compress the data when judging that performs the compression, and an instruction arbitration unit which transfers the instruction accompanying with the compressed data to the memory when the compression unit performs the compression and transfers the instruction accompanying with the non-compressed data to the memory when the compression unit does not perform the compression. | 2015-05-28 |
20150149747 | METHOD OF SCHEDULING LOOPS FOR PROCESSOR HAVING A PLURALITY OF FUNCTIONAL UNITS - Provided is a loop scheduling method including scheduling a first loop using execution units, and scheduling a second loop using execution units available as a result of the scheduling of the first loop. An n-th loop (n>2) may be scheduled using a result of scheduling an (n−1)-th loop, similar to the (n−1)-th loop. The first loop may be a higher priority loop than the second loop. | 2015-05-28 |
20150149748 | COMPUTER SYSTEM - A computer system is disclosed. When a user conducts different operations on a switch module, a switch module generates different clicking indication signal, and a logic control module generates a corresponding signal according to clicking indication signals so that a management control module processes a signal generated by a logic control module. As such, a single switch may be used to trigger multiple functions, whereby achieving in the efficacy of saving a design cost of a server panel. | 2015-05-28 |
20150149749 | METHODS AND SYSTEMS OF OPERATING COMPUTING DEVICE - In one or more embodiments, a system can configure a physical mobile device via configuring a configuration for an emulator of the physical mobile device. For example, a user (e.g., a customer) can request a physical mobile device, and a system can provide the user with an emulation of the physical mobile device, where the user can configure the emulation of the physical mobile device. In one or more embodiments, the user can be provided with the configuration via at least one of a network and a physical delivery of the physical mobile device, configured with the configuration. In one example, the user can execute an emulation of the physical mobile device configured with the configuration, received via the network. In another example, the physical mobile device can be configured with the configuration, and subsequently, the physical mobile device can be physically delivered to the user. | 2015-05-28 |
20150149750 | BIOS UPDATE WITH SERVICE PROCESSOR WITHOUT SERIAL PERIPHERAL INTERFACE (SPI) ACCESS - Certain aspects direct to BIOS update with a service processor (SP) without access through a serial peripheral interface (SPI). In certain embodiments, the system includes a SP, which includes a processor, a non-volatile memory, a volatile memory and a system interface. The SP receives a BIOS image from a remote management computer, and stores the BIOS image in the volatile memory. When the SP receives, from a BIOS executed at a central processing unit (CPU) of a host computer through the system interface, a request for the BIOS image, the SP sends a copy of the BIOS image in response to the request for the BIOS image to the host computer through the system interface such that the BIOS executed at the CPU of the host computer replaces a current BIOS image stored in a BIOS chip with the copy of the BIOS image. | 2015-05-28 |
20150149751 | CPU-BASED MEASURED BOOT - A measured boot process for an electronic device includes taking a measurement of the early system start up instructions of the electronic device upon a reboot or start-up of the device. A representation of the measurement is stored in a trusted platform module of the electronic device prior to initialization of the trusted platform module. Access is granted to the representation of the measurement stored in the trusted platform module prior to initialization of the trusted platform module thereby enabling the representation of the measurement to serve as the core root of trust for measurement. | 2015-05-28 |
20150149752 | SERVER AND CONTROL METHOD THEREOF - The disclosure provides a server and a control method thereof, and the server includes a memory unit and a basic input/output system (BIOS). The memory has an address space into which a specific string is written. When the server is booted, the BIOS is started to inquire the address space and determine whether the address space has the specific string or not, to determine whether to load a BIOS default setup. When the address space has the specific string, the BIOS loads the BIOS default setup and deletes the specific string in the address space. | 2015-05-28 |
20150149753 | SERVER AND INSPECTING METHOD THEREOF - Disclosed herein are a server and a inspecting method thereof. The server comprises a baseboard management controller, a field-replaceable unit coupled with the baseboard management controller, and a basic input/output system (BIOS). After the server is powered on, the BIOS starts running, performs power-on self-test for the server to generate current hardware configuration data, and obtains preset hardware configuration data from the field-replaceable unit through the baseboard management controller. The BIOS then determines whether the current and the preset hardware configuration data agree. | 2015-05-28 |
20150149754 | SERVER AND INSPECTING METHOD THEREOF - Disclosed herein are a server and an inspecting method thereof. The server comprises a baseboard management controller (BMC), a non-volatile memory coupled with the baseboard management controller, and a basic input/output system. After the server is powered on, the basic input/output system starts running, performs power-on self-test for the server to generate current hardware configuration data. The BMC then determines whether preset hardware configuration data, stored beforehand in the non-volatile memory, and the current one agree. If the preset and the current hardware configuration data have one or more mismatches, the BMC records the mismatch or mismatches in an event log. | 2015-05-28 |
20150149755 | PROJECTOR AND BOOT UP METHOD THEREOF - A projector comprises an environment detecting module and a processing module. The environment detecting module detects a predetermined environmental information at a first time and a real-time environmental information at a second time. The processing module is coupled to the environment detecting module, receives the predetermined environmental information and the real-time environmental information and executes a boot up method. The boot up method includes the steps of: storing and defining the predetermined environmental information as a comparison reference; and comparing the predetermined environmental information with the real-time environmental information, wherein when the predetermined environmental information and the real-time environmental information are substantially the same, a boot up program is executed, and when the predetermined environmental information and the real-time environmental information are substantially different, an authorization command request is outputted. A boot up method of a projector is also disclosed. | 2015-05-28 |
20150149756 | SYSTEM AND METHOD FOR SETTING UP A BOOTABLE STORAGE DEVICE USING IMAGE - A system and method for setting up a bootable storage device using an image are disclosed, a booting image supporting the network file system service is built up in an OS installed into a temporary device, the booting image and the kernel of the OS are copied to a pre-boot execution environment (PXE) root directory of the target device, and a bootable storage device is built up on the target device with the PXE root directory of the target device after the target device is booted, afterwards, whereby solving the issue encountered in the prior art, and achieving the technical efficacy of installing software in the OS booted through the network. | 2015-05-28 |
20150149757 | System and Method for Validating Components During a Booting Process - A method and system for validating components during a booting process of a computing device are described herein. The method can include the steps of detecting a power up signal and in response to detecting the power up signal, progressively determining whether software components of the computing device are valid. If the software components are determined to be valid, the computing device may be permitted to move to an operational state. If, however, at least some of the software components are determined to be not valid, the computing device may be prevented from moving to the operational state. In one arrangement, if the computing device is prevented from moving to the operational state, corrective action can be taken in an effort to permit the computing device to move to the operational state. | 2015-05-28 |
20150149758 | METHOD, COMPUTER READABLE MEDIUM AND DEVICE FOR THE CONFIGURATION OR MAINTENANCE OF A COMPUTER SYSTEM IN A CLUSTER - The configuration and maintenance of a computer system in a cluster, where the computer system is configured to allow booting from data stored in an administration computer system is disclosed. In one aspect, after obtaining a boot disk image making it possible to boot an operating system and configuration data from the administration computer system, the operating system is booted and configured and a virtual storage disk is created. The configuration data received are analyzed in order to obtain and store in the virtual disk a program for the configuration of the computer system. The program for the configuration of the computer system is then executed. | 2015-05-28 |
20150149759 | Electronic Device Including a Memory Technology Device - The electronic device may include a RAM, a nonvolatile storage device as an MTD, and firmware that may be stored on the nonvolatile storage device. The firmware may include a kernel that is expanded onto the RAM and a root disk image as a root file system. The kernel mounts the root disk image on the nonvolatile storage device as the root file system when a boot mode of the electronic device is a normal boot mode. The kernel, when the boot mode is an update mode for updating the firmware on the nonvolatile storage device, may i) generate a RAM disk as an MTD in an area of the RAM not under management of the kernel, ii) expand the root disk image on the nonvolatile storage device into the RAM disk, and iii) mount the root disk image on the RAM disk as the root file system. | 2015-05-28 |
20150149760 | Context Agent Injection Using Virtual Machine Introspection - A computer implemented method, apparatus, and computer usable program code for executing a process within a virtual machine. A module is injected into an operating system for the virtual machine to form an injected module. The injected module is executed to load an agent process within an application space within the virtual machine. Execution of the agent process is initiated by the injected module. | 2015-05-28 |
20150149761 | Network Model for Distributed Computing Architecture - The invention sets forth a New Network Model for building and managing distributed computing networks based on a fundamental network building block referred to as a DIME; an acronym for Distributed Intelligent, Managed, Entity, and a Signaling Infrastructure. The network model enables dynamic management of the programs comprising the DIME. Five of these programs are used for implementing the functional management services commonly referred to as Fault, Configuration, Accounting, Performance and Security, or FCAPS, at the DIME level. A combination of FCAPS management and Signaling Infrastructure enables DIME based Workflows, which are groups of connected DIMEs programmed to execute in coordination with each other to produce desired results. The network model further enables basic Workflow requirements, including those of task specialization; priority based mediation; fault tolerance; reliability; and resiliency. | 2015-05-28 |
20150149762 | Method and Apparatus for Unified Encrypted Messaging - A unified encrypted messaging system transmits messages from a first computer to a second computer by dividing the encrypted message into a plurality of encrypted message fragments. A first portion of the plurality of encrypted message fragments is transmitted via a first protocol and a second portion of the plurality of encrypted message fragments is sent via a second protocol. The first portion may be sent via a first device and the second portion may be sent via a second device where the first device is different from the second device. The dividing the encrypted message may include adding a message identifier and fragment identifier to each of the plurality of encrypted message fragments to facilitate reassembly of the encrypted message upon receipt. | 2015-05-28 |
20150149763 | Server-Aided Private Set Intersection (PSI) with Data Transfer - Existing private set intersection (PSI) protocol allows two parties to find intersection of their sets, but restricts learning any other information about each other's set except for its size. In general, the server-aided private set intersection with data transfer technique described herein provides a server-aided private set intersection (PSI) protocol that supports data transfers. The technique pertains to a method for providing a server-aided private set intersection protocol which allows two parties to transfer some of the information about their elements via an untrusted third party. The protocol involves (a) parties applying a shared pseudo-random permutation to each of their sets to create labels of the elements of the set, (b) sending the labels to the third party and (c) the third party performing data transfer between the two parties along with computation of intersection of sets received using a multi-share key. | 2015-05-28 |
20150149764 | METHOD FOR NETWORK COMMUNICATION PAST ENCRYPTION DEVICES - This disclosure is directed to techniques for providing communication between devices in different networks wherein the communication must first pass through an encryption mechanism and the devices do not have the stand-alone capability to encrypt or decrypt the communication. According to these techniques, an adapter may determine certain fields in a data packet that remain unencrypted when the data packet passes through the encryption mechanism. The adapter may then process those fields in such a way that, when the data packets are received by a second adapter, the second adapter may read those fields and obtain information. | 2015-05-28 |
20150149765 | METHOD OF ANONYMIZATION - This invention is aimed at a method for the anonymisation of data that could help identify the user while a profile of said user is collected by a targeting data collection server. To implement such anonymisation, an anonymisation server is placed between a user terminal and the collections server. The profile data collected are encrypted by the terminal using a secret key shared with the data collection server. Those profile data supplemented with data that could help identify the user are then sent to the anonymisation server. The anonymisation server encrypts the data that could help identify the user with an anonymisation key of said anonymisation server before sending on the encrypted collected data and the anonymised identification data to said collection server. | 2015-05-28 |
20150149766 | SYSTEM AND METHODS FOR FACILITATING AUTHENTICATION OF AN ELECTRONIC DEVICE ACCESSING PLURALITY OF MOBILE APPLICATIONS - Systems and methods for facilitating authentication of an electronic device accessing plurality of mobile applications are disclosed. The system may receive a device public key and authentication information of the electronic device. The system may validate the authentication information to initiate a device session with the electronic device and create an authentication token signed with a server signature. The system may enable the electronic device to access a first mobile application based on the authentication information validated. Further, the system may receive the authentication token signed with a device signature. The system may authorize the authentication token by verifying the device signature and the server signature on the authentication token with a device public key and a server public key respectively. The system may then enable the electronic device to access the second mobile application using the authentication token authorized. | 2015-05-28 |
20150149767 | METHOD AND SYSTEM FOR AUTHENTICATING THE NODES OF A NETWORK - A system and a method are provided for authenticating the nodes of a communication network in order to access the services of a service provider, and includes a collective authentication of the nodes, performed in a single exchange between the nodes of the network declared in a group and an authentication server. Depending on the result of the authentication, the service provider is provided with cryptographic material in order to implement individualized controlled access to the resources or to the services offered for each node. | 2015-05-28 |
20150149768 | SYSTEM AND METHOD FOR AUTOMATED CUSTOMER VERIFICATION - Techniques are disclosed for identifying and authenticating prospective certificate authority customers of a secure socket layer (SSL) certificate prior to receiving an order from the customer. The CA generates a list of prospective customers of digital certificates (e.g., by scanning networked servers via the Internet for the presence of an installed digital certificate). The CA retrieves data for each customer on the list and determines, based on a set of approval criteria, which prospective customers to target in enrollment campaigns. For each approved customer, the CA initiates an enrollment process prior to receiving a request from the customer to provide a certificate. | 2015-05-28 |
20150149769 | SECURING A SECRET OF A USER - Methods, systems and apparatuses for securing a secret of a user are disclosed. One method includes one or more adjudicator devices providing a plurality of public keys, wherein each of the plurality of public keys has a corresponding at least one adjudicator, and a corresponding secret key, receiving, by the one or more adjudicator devices, a plurality of encrypted shares that were generated based on a secret of the user, a policy, and the plurality of public keys, and verifying that the plurality of encrypted shares can be used to reconstitute the secret upon receiving the plurality of encrypted shares, wherein the secret can be reconstructed, without access to the secret. | 2015-05-28 |
20150149770 | TIME CHECK METHOD AND BASE STATION - A time check method and a base station are provided. The base station receives an authentication interaction message sent by an authentication interaction device; extracts time information in the authentication interaction message; and uses the time information to check local time. Before an Internet Key Exchange (IKE) connection is set up between the base station and a security gateway, relatively accurate time is obtained from an external authentication interaction device and is used for aligning the local time. Therefore, the cost of installing a clock component and a battery is saved, the time on the base station is trustworthy, and the security gateway is authenticated securely. | 2015-05-28 |
20150149771 | BLOCK ENCRYPTION METHOD AND BLOCK DECRYPTION METHOD HAVING INTEGRITY VERIFICATION - An encryption method and decryption method are provided. The encryption method divides an electronic file into a plurality of message blocks, wherein the message blocks have a sequence. The encryption method sets a checking vector as the last message block. The encryption method performs the following steps on each message block according to the sequence: generating an input block, deriving an output block by encrypting the input block by an encryption key, and deriving an encrypted block by applying XOR operation to the output block and the previous message block, wherein the input block is equivalent to applying XOR operation to the message block, the output block corresponding to the previous message block, and the message block before the previous one. The encryption method generates an electronic encrypted file by concatenating the encrypted blocks. The decryption method performs a series of operations corresponding to the above operations. | 2015-05-28 |
20150149772 | SECURE ACCESS FOR ENCRYPTED DATA - Embodiments generally provide techniques for managing data security. One embodiment includes providing, at a client system, an encrypted private key that can be decrypted using a locker key. Encrypted data is received from a remote system, and embodiment determine that the received encrypted data can be decrypted using a private key recovered by decrypting the encrypted private key. A request is transmitted to the remote system for the locker key corresponding to the encrypted private key, and the requested locker key is received from the remote system. Embodiments decrypt the encrypted private key using the received locker key to recover the private key, and decrypt the encrypted data, using the private key. | 2015-05-28 |
20150149773 | AVERAGE-COMPLEXITY IDEAL-SECURITY ORDER-PRESERVING ENCRYPTION - Embodiments provide ideal security, order-preserving encryption (OPE) of data of average complexity, thereby allowing processing of the encrypted data (e.g. at a database server in response to received queries). Particular embodiments achieve high encryption efficiency by processing plaintext in the order preserved by an existing compression dictionary already available to a database. Encryption is based upon use of a binary search tree of n nodes, to construct an order-preserving encryption scheme having Ω(n) complexity and even O(n), in the average case. A probability of computationally intensive updating (which renders conventional OPE impractical for ideal security) is substantially reduced by leveraging the demonstrated tendency of a height of the binary search tree to be tightly centered around O(log n). An embodiment utilizing such an encryption scheme is described in the context of a column-store, in-memory database architecture comprising n elements. OPE according to embodiments is compatible with adjustable encryption approaches. | 2015-05-28 |
20150149774 | RIGHTS MANAGEMENT SYSTEM AND METHOD INTEGRATED WITH EMAIL TRANSMISSION OF DOCUMENTS - A rights management system and method allow users to easily associate rights management policies with documents send via email from a client (e.g. a computer or scanner). The client transmits email recipient information, including the attention type (“to,” “cc” or “bcc”) for each recipient, to a rights management server. The server stores multiple rights management policies each specifying access rights (e.g. view, edit, print) granted to specified users, and stores an attention-right rule defining a correspondence between access rights and attention types. Based on the recipient information from the client, and applying the attention-rights rule, the server selects an appropriate policy or creates a new one if an appropriate policy does not exist, and transmits the policy, a document ID and an encryption key to the client. The client encrypts the document, adds metadata to the document, and sends the email with the attached document to a mail server. | 2015-05-28 |
20150149775 | Method and System of Secure Email - A process of sending and receiving emails using uniquely associated mobile communication devices involving a sender and a recipient, both registered users in a secure email communication system. The use of uniquely associated mobile communication devices with additional user authentication in the email sending and receiving ensures the authenticity of the sender and the recipient. Furthermore, the process of sending and receiving emails through the secure email communication system includes multiple levels of encryption and decryption of emails. | 2015-05-28 |
20150149776 | APPARATUS AND METHOD FOR SECURE DELIVERY OF DATA FROM A COMMUNICATION DEVICE - A system that incorporates the subject disclosure may perform, for example, providing an upload request to a mobile communication device to cause a secure device processor of the mobile communication device to perform a modification of data according to a data protection key to generate modified data and to perform an encryption of the modified data according to an upload transport key to generate encrypted modified data where the secure device processor is separate from and in communication with a secure element of the mobile communication device, and where the secure element receives master keys from a remote management server and stores the master keys to enable the upload transport key and the data protection key to be generated by the secure element without providing the master keys to the secure device processor. Other embodiments are disclosed. | 2015-05-28 |
20150149777 | MOBILE TERMINAL, TERMINAL AND AUTHENTICATION METHOD USING SECURITY COOKIE - An authentication method including: transmitting, by a first terminal, a security cookie to a server and making an authentication request; transmitting, by the server, session information and the security cookie to a second terminal in response to the authentication request; verifying, by the second terminal, whether the security cookie has been encoded by a session key pre-stored in the second terminal; and performing, by the second terminal and the server, mutual authentication in the case in which the security cookie is encoded by the session key pre-stored in the second terminal is disclosed. | 2015-05-28 |
20150149778 | CONTENT RECEPTION APPARATUS AND METHOD, AND CONTENT TRANSMISSION APPARATUS AND METHOD - A content reception apparatus includes: a communication unit that communicates with a content transmission apparatus; an authenticating unit that performs mutual authentication with the content transmission apparatus; a content recording unit that records content; and a content reproduction output unit that reproduces the content, wherein the content is received from the content transmission apparatus and is recorded in the content recording unit after the authenticating unit performs first authentication with the content transmission apparatus, and the content recorded in the content recording unit is reproduced after the authenticating unit performs a process including second authentication with the content transmission apparatus. | 2015-05-28 |
20150149779 | Secure Transmission of a Message - The embodiments relate to methods and apparatuses for producing secure transmission of a message. The methods are based on production of a basic key that is used for producing respective transmitter keys for a plurality of transmitters. For the ascertainment of the receiver keys by respective receivers, the basic key is transmitted to the receivers, which for their part are able to ascertain a receiver key for checking the integrity of the message from a respective transmitter on the basis of the basic key and an identifier for the transmitter. The receiver ascertains a cryptographic checksum, which, in the course of the integrity check, is compared with a cryptographic checksum that has been produced by the transmitter and sent along by the respective message. The embodiments may be used within the context of automation and sensor networks. | 2015-05-28 |
20150149780 | MEDIATOR DEVICE MONITORING AND CONTROLLING ACCESS TO ELECTRONIC CONTENT - Methods, systems and apparatuses for a mediator controlling access to an electronic content, are disclosed. One method includes receiving, by a mediator device of a mediator, a second share SK | 2015-05-28 |
20150149781 | AUTHENTICATED SESSION ESTABLISHMENT - Methods, devices, and machine-readable media are provided to provide secure communications between entities. As provided in this disclosure, this may include receiving a request to begin a new communication session, determining one or more desired parameters of the session, and determining whether the desired parameters of the message match proposed parameters provided by the entity requesting the new communication session. When the one or more proposed parameters match the one or more desired parameters, a secure communication session is established between the entities. | 2015-05-28 |
20150149782 | INTEGRITY PROTECTED SMART CARD TRANSACTION - Systems, methods, and technologies for configuring a conventional smart card and client machine, and for performing a smart card authorization using the configured smart card and client. Further, the combination of methods provides for mutual authentication—authentication of the client to the user, and authentication of the user to the client. The authentication methods include presenting a specified token to the user sufficient to authenticate the client to the user and thus protect the user-provided PIN. Security is strengthened by using an integrity key based on approved client system configurations. Security is further strengthened by calculating a PIN′ value based on a user-specified PIN and a modifier and using the PIN′ value for unlocking the smart card. | 2015-05-28 |
20150149783 | Method and Apparatus for Secure Distribution of Embedded Firmware - A method and apparatus to securely distribute embedded firmware to a module in an industrial control system is disclosed. A security certificate corresponding to the firmware is generated utilizing a proprietary algorithm. The certificate includes an identifier corresponding to the module on which the firmware is to be loaded and an identifier corresponding to a removable medium on which the firmware is distributed. The removable medium is inserted into the module in the industrial control system on which the firmware is to be loaded. The module reads the security certificate and verifies that the firmware is intended for the module and verifies that the security certificate includes the identifier for the removable medium which was inserted into the module. If the firmware is intended for the module and the security certificate includes the identifier for the removable medium, the module loads the firmware from the removable medium. | 2015-05-28 |
20150149784 | Communication method utilizing fingerprint information authentication - A communication method utilizing fingerprint information authentication comprises the following steps: (a) extracting fingerprint information of first, and sending a request instruction to second user via the fingerprint information by a first user on an information exchange platform, and extracting fingerprint information of second user after receiving the request by the second user, and storing the fingerprint information in the information exchange platform and exchanging it with first user by the second user to confirm their identity; (b) inputting a message to be sent in an encrypting unit to obtain encrypted message by the first user after passing authentication, and transmitting the encrypted message to a communication application unit and sending it to second user, and receiving the encrypted message via the communication application unit by the second user; (c) decrypting the encrypted message by means of the decrypting unit by the second user after passing authentication. | 2015-05-28 |
20150149785 | GENERATING FINGERPRINTED CONTENT DATA FOR PROVISION TO RECEIVERS - A method for generating, from initial content data, output content data for provision to one or more receivers, wherein the initial content data is encoded according to a coding scheme, wherein for a quantity of data encoded according to the coding scheme, the coding scheme provides a mechanism for including in the quantity of encoded data additional data such that a decoder for the coding scheme, upon decoding the quantity of encoded data, does not use the additional data to generate decoded data, the method comprising: selecting one or more portions of the initial content data; for each selected portion, generating a data construct that comprises a plurality of data structures, each data structure comprising data, including a version of the selected portion, that is encrypted using a corresponding encryption process different from each encryption process used to encrypt data in the other data structures, wherein the data construct is arranged such that using a decryption process that corresponds to the encryption process for one data structure on the encrypted data in each data structure in the data construct produces a quantity of data encoded according to the coding scheme that uses the mechanism so that a decoder for the coding scheme would not use any data structure in the data construct other than said one data structure; and using the generated data constructs in the initial content data instead of their corresponding selected portions to form the output content data. | 2015-05-28 |
20150149786 | NETWORK STORAGE SYSTEM FOR A DOWNLOAD INTENSIVE ENVIRONMENT - A network storage system for a download intensive environment is provided. The network storage comprises at least a data storage server (DSS) that includes an interface enabling connection of the DSS to a network at a location that enables at least a view of network transactions performed by a plurality of clients; a storage unit; and a system adapted to monitor the network transactions occurring on the network and identification of the network transactions as belonging to a registered client of the DSS, and storing in the storage the transactions with an identification corresponding to the registered client. | 2015-05-28 |
20150149787 | CLIENT-BASED AUTHENTICATION - Apparatus, systems, and methods may operate to invoke multiple authentication mechanisms, by a client node, to encrypt N split-keys using credentials associated with corresponding ones of the authentication mechanisms. Further activity may include transforming the split-keys to provide N encrypted split-keys, and storing each of the encrypted split-keys with an associated local user identity and an identity of corresponding ones of the authentication mechanisms. Additional apparatus, systems, and methods are disclosed. | 2015-05-28 |
20150149788 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR OPTIMIZING DATA ENCRYPTION AND DECRYPTION BY IMPLEMENTING ASYMMETRIC AES-CBC CHANNELS - A system, method, and computer program product are provided for implementing asymmetric AES-CBC (Advanced Encryption Standard-Cipher Block Chaining) channels usage between encryption and decryption of data. In operation, data to be written to memory is identified. In addition, the data is encrypted utilizing a first AES-CBC channel. Additionally, at least one of a plurality of AES-CBC channels is utilized to decrypt the data to achieve a determined performance target. | 2015-05-28 |
20150149789 | MEMORY SYSTEM, HOST SYSTEM, AND METHOD OF PERFORMING WRITE OPERATION IN MEMORY SYSTEM - A write operation is performed in a memory system by encoding, in the memory system, original data transmitted from a host system, according to a first type of host command, to produce an encoding result, transmitting information about the encoding result to the host system after the encoding, and writing the encoding result or the original data into a nonvolatile memory device, according to a second host command, wherein the second host command is transmitted from the host system based on the information about the encoding result. | 2015-05-28 |
20150149790 | NONVOLATILE MEMORY AND ELECTRONIC DEVICE - The embodiments of the present invention disclose a nonvolatile memory and an electronic device, where each time the nonvolatile memory is powered on, an exchanger is used to implement a random exchange of at least one address subsignal and its inverted signal in a bank decoder and/or a row decoder in a bank and/or a column decoder in a bank, which causes that data stored before the nonvolatile memory is powered off is interrupted when the nonvolatile memory is powered off and then powered on and that data stored in the nonvolatile memory cannot be read sequentially from original storage addresses to achieve an encrypting effect and increase security of the data stored in the nonvolatile memory. | 2015-05-28 |
20150149791 | ELECTRONIC APPARATUS - An electronic apparatus includes a chip, a memory and a switch unit. The chip works in a boot state. The memory coupled to the chip stores firmware and has a write-protection control end connected to the chip through a write-protection control path. In a standby state, when receiving an electric potential signal through the write-protection control end, the memory disables a write-protection function, so as to update the firmware. The switch unit is located on the write-protection control path and is controlled by a power-on signal related to the boot state. In the standby state, the switch unit is turned-off and the delivery of the electric potential signal to the chip through the write-protection control path is disabled. In the boot state, the switch unit is turned-on and the write-protection control way is conducted by the power-on signal so that the chip controls the write-protection function. | 2015-05-28 |
20150149792 | SERVER SYSTEM AND CONTROLLING METHOD FOR OPERATION TIMING AFTER BEING POWERED UP - A server system and controlling method for an operation timing after being powered up are disclosed. The sever system controls a reset signal to have a voltage lower than a first voltage value by introducing a voltage monitoring module when a work power lower than a voltage threshold. On the other hand, when the work power voltage increases to higher than the voltage threshold of the voltage monitoring module, the voltage monitoring module controls the reset signal voltage to be higher than a second voltage value, whereby achieving in a technical efficacy of stable initialization and reset of the server. | 2015-05-28 |
20150149793 | VARIOUS PSUS ADAPTIVE SERVER AND METHOD - A various PSUs adaptive server and method used therefor, in which the management module sends a detection command to the bus address corresponding to the model corresponding to each of the PSUs, identifies the model according to the bus address in the response information and controls the one of the PSUs corresponding to the identified model by using the control protocol corresponding thereto, whereby reducing a number of the versions of a base plate management controller and reducing a test burden therefor. | 2015-05-28 |
20150149794 | METHODS AND SYSTEMS TO CONTROL POWER GATES DURING AN ACTIVE STATE OF A GATED DOMAIN BASED ON LOAD CONDITIONS OF THE GATED DOMAIN - Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die. | 2015-05-28 |
20150149795 | Semiconductor Device and Electronic Device - To reduce a variation in the electrical characteristics of a transistor. A potential generated by a voltage converter circuit is applied to a back gate of a transistor included in a voltage conversion block. Since the back gate of the transistor is not in a floating state, a current flowing through the back channel can be controlled so as to reduce a variation in the electrical characteristics of the transistor. Further, a transistor with low off-state current is used as the transistor included in the voltage conversion block, whereby storage of the output potential is controlled. | 2015-05-28 |
20150149796 | VOLTAGE REGULATOR TRAINING - Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system. Specifically, the system may include a processor chip which may include an on-die voltage regulator (VR) configured to supply a voltage to a component of the processor chip. The processor chip may be coupled with a dynamic random access memory (DRAM). The system may further include an external VR coupled with the DRAM. A BIOS may be configured to regulate the voltage output of one or both of the on-die VR and/or the external VR. Other embodiments may be described or claimed. | 2015-05-28 |
20150149797 | HIERARCHICAL WEARABLE PROCESSING UNIT - A hierarchical wearable processing unit (HWPU) ( | 2015-05-28 |
20150149798 | INFORMATION PROCESSING DEVICE - In an information processing device | 2015-05-28 |
20150149799 | POWER COORDINATION SYSTEM FOR HYBRID ENERGY STORAGE SYSTEM - A method of controlling power in a hybrid energy storage system that may include controlling power through the at least one battery storage element and the capacitor storage element using a multi-level power management system. In some embodiments, the multi-level power management system includes at least a long term battery management layer and a real time power management layer. The long term battery management layer can be for estimating and managing a life cycle for the battery. The real time power management layer can be for managing power sharing between the at least one battery storage element and the at least one capacitor storage element at each time instant dependent upon adjustments to battery performance based upon the long term battery management layer. | 2015-05-28 |
20150149800 | PERFORMING AN OPERATING FREQUENCY CHANGE USING A DYNAMIC CLOCK CONTROL TECHNIQUE - In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation circuit to receive and distribute a first clock signal at a first operating frequency provided from a phase lock loop of the processor to a plurality of units of the core. The clock generation circuit may include a dynamic clock logic to receive a dynamic clock frequency command and to cause the clock generation circuit to distribute the first clock signal to at least one of the units at a second operating frequency. Other embodiments are described and claimed. | 2015-05-28 |
20150149801 | COMPLEX WAKEUP GESTURE FRAMEWORK - A processing system for sensing includes a sensor module including sensor circuitry coupled to sensor electrodes, the sensor module configured to generate sensing signals received with the sensor electrodes. The processing system further includes a determination module that is configured to determine, from the sensing signals, a positional information for a gesture while a host device is in low power mode, determine, based on the positional information and while the host device is in the low power mode, that the gesture is deliberate input, send, in response to determining that the gesture is deliberate input, a wake signal to the host device to switch the host device out of the low power mode, and send the positional information to the host device after the host device receives the wake signal. | 2015-05-28 |
20150149802 | POWER-SAVE MODE IN ELECTRONIC APPARATUS - This document discloses a solution for employing a power-save mode in an electronic device providing, in a display unit, a plurality of home screens and a mechanism to switch from one home screen to another home screen in response to a user input received through user input means of the electronic device. At least one of the home screens is a home screen for a power-save mode of the electronic apparatus and, upon detecting a user input causing a switch to the home screen for the power-save mode, the electronic device switches on at least some of the power-save features of the electronic device. | 2015-05-28 |
20150149803 | ELECTRONIC DEVICE, CONTROL METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - In an embodiment, an electronic device includes a power supply module, a processor, a mode setting module and a clock module. The processor is configured to operate with power from the power supply module, and to be able to enter a power-saving operation state. The mode setting module turns on or off a mode in which the processor is inhibited from exiting the power-saving operation state due to an interrupt. The clock module is configured to generate the interrupt, if the mode is off, when predetermined time is reached while the processor is in the power-saving operation state, and not to generate the interrupt, if the mode is on, even when the time is reached while the processor is in the power-saving operation state. | 2015-05-28 |
20150149804 | RESPONDING DEVICE AND RESPONDING METHOD - A responding device has operating modes including a first mode and a second mode. The responding device includes a first responding unit and a second responding unit. The first responding unit operates during the first mode and outputs, when receiving a request, a response including information in accordance with the type of the request. The second responding unit outputs the response in place of the first responding unit during the second mode. The second responding unit includes a storage section, an information accumulation section, and a mode transition control section. The information accumulation section stores in the storage section the information included in the response output from the first responding unit during the first mode. The mode transition control section causes the responding device to transition to the second mode when a first condition and a second condition in terms of the information stored in the storage section are satisfied. | 2015-05-28 |
20150149805 | Managing Graphics Power Consumption and Performance - The graphics pipeline produces real time utilization data for each of a plurality of functional units making up an overall graphics processor or graphics system on a chip. This information may be used for fine grain management of power consumption and performance at the functional unit level as opposed the overall device level. As a result, the graphics functional units may be managed dynamically based on real time hardware metrics to improve performance and reduce power consumption. The technique may be implemented in a software module in one embodiment. | 2015-05-28 |
20150149806 | Hard Power Fail Architecture - The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, the method includes determining whether a power supply voltage provided to the storage device is higher than an over-voltage threshold. The method further includes, in accordance with a determination that the power supply voltage is higher than the over-voltage threshold, performing a power fail operation, the power fail operation including: (1) signaling a power fail condition to a plurality of controllers on the storage device, (2) transferring data held in volatile memory to non-volatile memory, and (3) removing power from the plurality of controllers on the storage device. | 2015-05-28 |
20150149807 | Computer Device - A computer device is disclosed. The computer device includes a central processing unit (CPU), a chipset, an input/output (I/O) chip, a general purpose I/O (GPIO) interface, and a smart battery. The chipset is electrically connected to the CPU. The I/O chip is electrically connected to the chipset. The GPIO interface is electrically connected to the CPU. The smart battery is electrically connected to the GPIO interface and the I/O chip. The CPU reads information of two bytes saved in the smart battery through the GPIO interface and determines a relative processing according to information of two bytes when a status of the smart battery is changed. | 2015-05-28 |
20150149808 | FREQUENCY CALIBRATION METHOD APPLICABLE IN UNIVERSAL SERIAL BUS DEVICE AND RELATED UNIVERSAL SERIAL BUS DEVICE - A frequency calibration method applied to a Universal Serial Bus (USB) device includes: coupling the USB device to a USB host, wherein the USB device at least comprises a programmable oscillator; utilizing the USB device to extract a low frequency periodic signal from the USB host; and calibrating the programmable oscillator of the USB device according to the low frequency periodic signal, to make the programmable oscillator generate an oscillating signal having a predetermined frequency. | 2015-05-28 |
20150149809 | SYNCHRONOUS BRIDGE CIRCUITRY AND A METHOD OF TRANSFERRING DATA USING ASYNCHRONOUS BRIDGE CIRCUITRY - Asynchronous bridge circuitry provides data communication between source circuitry | 2015-05-28 |
20150149810 | APPARATUS, SYSTEM AND METHOD FOR AUTONOMOUS RECOVERY FROM FAILURES DURING SYSTEM CHARACTERIZATION ON AN ENVIRONMENT WITH RESTRICTED RESOURCES - A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions. | 2015-05-28 |
20150149811 | METHOD FOR MAINTAINING THE FUNCTIONAL ABILITY OF A FIELD DEVICE - A method for maintaining the functional ability of a field device of automation technology, wherein the method comprises the following steps: monitoring the field device for at least one achieved parameter change (Δn | 2015-05-28 |
20150149812 | Self-Debugging Router Platform - Exemplary methods for network debugging include a control plane of a first network device generating and injecting debug traffic into a data plane of the first network device such that the debug traffic appears to the data plane as if it originated from an external network device. The methods include the data plane transmitting the debug traffic to a network. In one embodiment, the control plane collects debug information of the debug traffic as it is processed by the data plane and the network. In one embodiment, the first network device is configured to exchange debug information of the debug traffic with a second network device, and to provide the debug information to an operator. | 2015-05-28 |