21st week of 2021 patent applcation highlights part 60 |
Patent application number | Title | Published |
20210159335 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a drift region disposed on a principal surface of the substrate; a first well region extending from a second principal surface of the drift region in a direction perpendicular to the second principal surface and having a bottom portion; a second well region being in contact with the bottom portion and disposed at a portion inside the substrate located below the bottom portion; and a source region extending in a perpendicular direction from a region of the second principal surface provided with the first well region, and reaching the second well region. In a direction parallel to the second principal surface and oriented from a source electrode to a drain electrode, a distance of the second well region in contact with a gate insulating film is shorter than a distance of the first well region in contact with the gate insulating film. | 2021-05-27 |
20210159336 | VERTICAL FIELD EFFECT TRANSISTOR (FET) - The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions. | 2021-05-27 |
20210159337 | THREE DIMENSIONAL VERTICALLY STRUCTURED ELECTRONIC DEVICES - In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure. | 2021-05-27 |
20210159338 | SILICON METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR (Si MOSFET) WITH A WIDE-BANDGAP III-V COMPOUND SEMICONDUCTOR GROUP DRAIN AND METHOD FOR FABRICATING THE SAME - A silicon metal-oxide-semiconductor field effect transistor with a wide-bandgap III-V compound semiconductor drain and a method for fabricating the same are disclosed. The method fabricates a hundred nanometer-scale hole in a (100) silicon substrate to expose the (111) facet of the silicon substrate, which favors to use selective area growth to form lattice matched III-V materials with high quality. | 2021-05-27 |
20210159339 | SEMICONDUCTOR DEVICE HAVING DOPED EPITAXIAL REGION AND ITS METHODS OF FABRICATION - Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance. | 2021-05-27 |
20210159340 | FERROELECTRIC SEMICONDUCTOR DEVICE INCLUDING A FERROELECTRIC AND MANUFACTURING METHOD THEREOF - A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer. | 2021-05-27 |
20210159341 | SEMICONDUCTOR DEVICE WITH AN OXIDIZED INTERVENTION AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a memory unit including a memory unit conductive layer positioned above the substrate and a lateral oxidized intervention layer positioned below the memory unit conductive layer, and a control unit positioned in the substrate and below the lateral oxidized intervention layer. The lateral oxidized intervention layer includes a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion. | 2021-05-27 |
20210159342 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device capable of miniaturization or high integration and manufacture of a semiconductor device are provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator and first and second conductors over the oxide; a third conductor over the second insulator; a fourth conductor over the first conductor; a fifth conductor over the second conductor; a third insulator over the first insulator and the first and second conductors; a fourth insulator over the second and third insulators and the third conductor; and a fifth insulator over the fourth insulator. The first and second conductors are provided to face each other with the second insulator therebetween. The second insulator is provided along an inner wall of an opening provided in the third insulator, facing side surfaces of the first and second conductors, and a top surface of the oxide. The level of a top surface of the third conductor is higher than the levels of top surfaces of the second and third insulators. The fourth insulator is provided along the top surfaces of the second and third insulators and the top surface and a side surface of the third conductor. | 2021-05-27 |
20210159343 | THIN FILM TRANSISTOR, ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - A thin film transistor, an array substrate, a display panel and a display device are provided, which is related to the field of display technologies. A thin film transistor comprises: a substrate; at least two active layers on the substrate, each active layer comprising a first terminal and a second terminal opposite to each other; a source and a drain above the substrate. The first terminal of each of the at least two active layers is electrically connected to the source, and the second terminal of each of the at least two active layers is electrically connected to the drain, and the at least two active layers are arranged on an upper surface of the substrate and separated from one another. | 2021-05-27 |
20210159344 | THIN FILM TRANSISTOR, IMAGE DISPLAY PANEL, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A thin film transistor according to one embodiment comprises a gate electrode; a semiconductor layer being formed using amorphous silicon and comprising a region overlapping with the gate electrode; a gate insulating layer; and a source electrode and a drain electrode facing each other with a predetermined interval therebetween. The gate electrode comprises a first layer having a first work function; and a second layer having a second work function and being interposed between the first layer and the gate insulating layer. The semiconductor layer comprises an intrinsic region being formed with non-doped amorphous silicon; and a low concentration impurities region. The second work function is less than the first work function when n-type impurities are contained in the low concentration impurities region, while the second work function is greater than the first work function when p-type impurities are contained in the low concentration impurities region. | 2021-05-27 |
20210159345 | OXIDE SEMICONDUCTOR FILM AND SEMICONDUCTOR DEVICE - An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm | 2021-05-27 |
20210159346 | SILICON-OXIDE-NITRIDE-OXIDE-SILICON MULTI-LEVEL NON-VOLATILE MEMORY DEVICE AND METHODS OF FABRICATION THEREOF - A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially. | 2021-05-27 |
20210159347 | OPTOELECTRONIC PACKAGE ASSEMBLIES INCLUDING SOLDER REFLOW COMPATIBLE FIBER ARRAY UNITS AND METHODS FOR ASSEMBLING THE SAME - A method for assembling an optoelectronic package assembly includes engaging a connector holder with a substrate, the connector holder defining an engagement feature and the substrate including optical waveguides, engaging a connector of a fiber array unit with the engagement feature the connector holder where the engagement feature retains the connector and where the fiber array unit includes the connector and optical fibers coupled to the connector, optically coupling the optical fibers to the optical waveguides of the substrate, heating the connector holder, the fiber array unit, the substrate, and a solder positioned between the substrate and a base substrate, where the heating is sufficient to melt the solder, and cooling the solder to couple the substrate to the base substrate. | 2021-05-27 |
20210159348 | OPTICALLY TRANSPARENT ELECTROMAGNETICALLY SHIELDING ELEMENT COMPRISING A PLURALITY OF ZONES - A shielding element comprises a rigid substrate and at least one electrically conductive two-dimensional structure which is placed on one of the faces of the substrate. The substrate and the electrically conductive two-dimensional structure are such that the shielding element has optical-transmission and shielding-efficiency values at least one of which varies between two zones of the shielding element. Such a shielding element enables easier assembly of a detection system comprising multiple optical sensors. | 2021-05-27 |
20210159349 | STACKED MULTI-JUNCTION SOLAR CELL - A stacked multi-junction solar cell with a front side contacted through the rear side and having a solar cell stack having a Ge substrate layer, a Ge subcell, and at least two III-V subcells, with a through contact opening, a front terminal contact, a rear terminal contact, an antireflection layer formed on a part of the front side of the multi-junction solar cell, a dielectric insulating layer, and a contact layer. The dielectric insulating layer covers the antireflection layer, an edge region of a top of the front terminal contact, a lateral surface of the through contact opening, and a region of the rear side of the solar cell stack adjacent to the through contact opening. The contact layer from a region of the top of the front terminal contact that is not covered by the dielectric insulating layer through the through contact opening to the rear side. | 2021-05-27 |
20210159350 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip. | 2021-05-27 |
20210159351 | BACKSIDE ILLUMINATED SEMICONDUCTOR PHOTODETECTION ELEMENT - A semiconductor substrate includes first and second main surfaces opposing each other. The semiconductor substrate includes second semiconductor regions in a side of the second main surface. Each of the second semiconductor regions includes a first region including a textured surface, and a second region where a bump electrode is disposed. The second semiconductor regions are two-dimensionally distributed in a first direction and a second direction orthogonal to each other when viewed in a direction orthogonal to the semiconductor substrate. The first region and the second region are adjacent to each other in a direction crossing the first direction and the second direction. The textured surface of the first region is located toward the first main surface in comparison to the surface of the second region in a thickness direction of the semiconductor substrate. The first main surface is a light incident surface of the semiconductor substrate. | 2021-05-27 |
20210159352 | PHOTOVOLTAIC MODULES AND METHOD OF MANUFACTURE THEREOF - Photovoltaic module comprising:
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20210159353 | PHOTOVOLTAIC MODULES AND METHOD OF MANUFACTURE THEREOF - Photovoltaic module comprising:
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20210159354 | SPACER FOR PHOTOVOLTAIC APPLICATIONS - A spacer for a multi-pane insulating glazing unit includes a spacer body made from a first material with first and second hollow desiccant chambers extending in a longitudinal direction and a longitudinal groove between the first and second chambers open to a first side of the spacer for holding an intermediate pane of the glazing unit, the groove being delimited in a width direction by first and second side walls and having a bottom wall, and the spacer body having a gas barrier on a second side opposite the first side. The first side wall and/or the second side wall and/or the bottom wall of the groove include at least two electrically conductive portions electrically isolated from each other and configured to make electrical contact with at least one electrical contact of the intermediate pane. | 2021-05-27 |
20210159355 | SOLAR CELL, AND METHOD FOR MANUFACTURING SOLAR CELL - A solar cell ( | 2021-05-27 |
20210159356 | INTEGRATED TANDEM SOLAR CELL AND MANUFACTURING METHOD THEREOF - Disclosed herein are a recombination layer containing nanoparticles and an integrated tandem solar cell manufactured using the same. The integrated tandem solar cell includes a first solar cell having a form in which a rear electrode, a light absorption layer, and a buffer layer are stacked, a recombination layer formed on the buffer layer and including a triple layer structure which has first and second transparent conductive layers with a transparent conductive nanoparticle layer disposed therebetween, and a second solar cell disposed on and bonded to the recombination layer and including a perovskite layer. | 2021-05-27 |
20210159357 | METHOD AND APPARATUS FOR ENHANCED PHOTOCONDUCTIVITY OF SEMICONDUCTOR - A photoconductor assembly includes a substrate formed of an undoped and single-crystal semiconductor material that is configured to absorb electromagnetic energy, a plurality of electrodes arranged normal to the substrate, and a power supply that applies a voltage to the electrodes for modulating the electromagnetic energy through the substrate. | 2021-05-27 |
20210159358 | OPTICAL DETECTION DEVICE - An optical detection device includes an optical semiconductor element having a plurality of light receiving portions and a light transmitting substrate bonded to the optical semiconductor element directly or via only a light transmitting adhesive layer. A surface of the light transmitting substrate on a side opposite to the optical semiconductor element is provided with a first refractive index changing layer having a projecting and recessed structure in which a refractive index continuously changes from a refractive index of air to a refractive index of the light transmitting substrate toward the light transmitting substrate. When a distance between the optical semiconductor element and the first refractive index changing layer is A, a distance between adjacent light receiving portions of the plurality of light receiving portions is B, and a refractive index of the light transmitting substrate to a refractive index of the air is n, A>B/[2 tan{sin | 2021-05-27 |
20210159359 | METHOD FOR FORMING A COMMON ELECTRODE OF A PLURALITY OF OPTOELECTRONIC DEVICES - A method for forming a common electrode is provided, including: a) providing a support substrate on which rest optoelectronic devices separated by trenches; b) forming a dielectric layer on front faces, flanks, and a bottom of the trenches, of a thickness E | 2021-05-27 |
20210159360 | ULTRA-DENSE ARRAY OF LEDS WITH HALF CAVITIES AND REFLECTIVE SIDEWALLS - In one approach, an LED array uses a combination of a half cavity and straight reflective sidewalls to improve the power distribution so that more light falls within the collection angle of the projection optics. From the bottom upwards, the LEDs in the array include a reflector, a thinner p-layer and a thicker n-layer. An active region (such as quantum wells) between the p-layer and the p-layer generates light. Without additional structures, the generated light would have an isotropic distribution and not much of the light would fall within the collection angle of the projection optics. However, the bottom reflector and p-layer form a half cavity for the light emitted from the active region. This alters the angular power distribution. Straight reflective sidewalls extending from the active region upwards into the n-layer further reflect light from the altered power distribution into the collection angle of the projection optics. | 2021-05-27 |
20210159361 | LED DEVICE, METHOD OF MANUFACTURING THE LED DEVICE, AND DISPLAY APPARATUS INCLUDING THE LED DEVICE - Provided are a light-emitting diode (LED) device, a method of manufacturing the LED device, and a display apparatus including the LED device. The LED device includes a light-emitting layer having a core-shell structure, a passivation layer provided to cover a portion of a top surface of the first semiconductor layer, a first electrode provided on the light-emitting layer, and a second electrode provided under the light-emitting layer. The light-emitting layer includes a first semiconductor layer, an active layer, and a second semiconductor layer. The first electrode is provided to contact the first semiconductor layer, and the second electrode is provided to contact the second semiconductor layer. | 2021-05-27 |
20210159362 | LIGHT EMITTING DEVICE - A light emitting device according to an embodiment of the present disclosure includes: a first layer including Al | 2021-05-27 |
20210159363 | DRIVE BACKBOARD, MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE - A drive backboard, a manufacturing method thereof, a display panel and a display device are provided. The drive backboard includes a plurality of pixel units and a plurality of spare electrode groups. Each pixel unit includes m subpixel units, and m is a positive integer greater than or equal to 2. Each spare electrode group includes two first spare electrodes and one second spare electrode; two adjacent i | 2021-05-27 |
20210159364 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - Disclosed are an array substrate, a display panel and a display device. The array substrate includes: a base substrate provided with a bonding region for packaging a chip on film, and a first electrode structure, an interlayer dielectric layer, a second electrode structure and a third electrode structure sequentially arranged on the base substrate, the orthographic projections of the first electrode structure, the interlayer dielectric layer, the second electrode structure and the third electrode structure on the base substrate being located in the bonding region. The array substrate further includes protection layers located between the first portion of the second electrode structure and a third electrode and between the second portion of the second electrode structure and the third electrode respectively; and the protection layers cover the side end face of the first portion and the side end face of the second end surface. | 2021-05-27 |
20210159365 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Semiconductor light emitting devices and methods of fabricating the same are provided. The semiconductor light emitting device includes a light emitting structure, a first electrode, a first dielectric layer, a second electrode, and a vertical conductive pattern. The light emitting structure includes a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked, and includes a first opening that penetrates the second semiconductor layer and the active layer, the first opening exposing the first semiconductor layer. The first electrode fills at least a portion of the first opening. The first dielectric layer is on the first electrode. The second electrode is on the light emitting structure and covers the first dielectric layer, the second electrode being electrically connected to the second semiconductor layer. The vertical conductive pattern surrounds outer lateral surfaces of the light emitting structure and is electrically connected to the first electrode. | 2021-05-27 |
20210159366 | LIGHT-EMITTING DEVICE WITH REFLECTIVE LAYER - A light-emitting device includes a semiconductor structure including a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer includes a first edge; a reflective structure located on the second semiconductor layer and including an outer edge; a first electrode pad located on the reflective structure, wherein the first electrode pad including an outer side wall adjacent to the outer edge, wherein the outer edge extends beyond the outer side wall and does not exceed the first edge in a cross-sectional view of the light-emitting device. | 2021-05-27 |
20210159367 | PACKAGE STRUCTURE - A package structure is provided. The package structure includes a substrate, an electrode layer, a lighting unit, a wall, and a package compound. The substrate and the wall that is disposed on the substrate jointly define an accommodating space. The lighting unit in the accommodating space and is electrically connected to the electrode layer disposed on the substrate. The package compound covers the electrode layer, and the lighting unit. The package compound includes an attaching portion disposed on a top surface of the lighting unit and a surrounding portion that is arranged around the attaching portion. The surrounding portion has an annular slot arranged on a top surface thereof. A bottom end of the annular slot is located at a position aligning with 25%˜90% of a thickness of the lighting diode along a height direction. | 2021-05-27 |
20210159368 | SUBMOUNT STRUCTURES FOR LIGHT EMITTING DIODE PACKAGES - Submount structures for light-emitting diode (LED) packages are provided. Submounts may include a base material that is configured to provide high thermal conductivity and a ceramic layer on the base material that is configured to provide high reflectivity for one or more LED chips that are mounted thereon. In certain aspects, the base material may include a ceramic base having a ceramic material that is different than a material of the ceramic layer. In certain aspects, submounts may also include additional ceramic layers configured to provide high reflectivity. In certain aspects, LED packages include electrical traces that are arranged either on one or more ceramic layers or at least partially embedded within one or more ceramic layers. The arrangement of such ceramic layers may provide increased reflectivity in areas where it may be difficult for other reflective materials to be present, such as gaps formed between tightly spaced electrical traces. | 2021-05-27 |
20210159369 | LIGHT EMITTING DEVICE - A light emitting device includes a wavelength conversion layer, at least one light emitting unit and a reflective protecting element. The wavelength conversion layer has an upper surface and a lower surface opposite to each other. The light emitting unit has two electrode pads located on the same side of the light emitting unit. The light emitting unit is disposed on the upper surface of the wavelength conversion layer and exposes the two electrode pads. The reflective protecting element encapsulates at least a portion of the light emitting unit and a portion of the wavelength conversion layer, and exposes the two electrode pads of the light emitting unit. | 2021-05-27 |
20210159370 | MICRO LIGHT-EMITTING DEVICE AND DISPLAY - A micro light-emitting device includes a micro light-emitting diode and a light-emitting structure. The micro light-emitting diode includes a semiconductor light-emitting unit that emits an excitation light having a first wavelength. The light-emitting structure is disposed on the micro light-emitting diode, and is configured to be excited by the excitation light to emit an excited light having a second wavelength. The light-emitting structure is a multiple quantum well structure. A display including the micro light-emitting device is also disclosed. | 2021-05-27 |
20210159371 | LIGHT EMITTING DEVICE INCLUDING RGB LIGHT EMITTING DIODES AND PHOSPHOR - A light emitting device including a plurality light emitting diodes configured to produce a primary light; a wavelength conversion means configured to at least partially convert the primary light into secondary light having peak emission wavelength ranges between 450 nm and 520 nm, between 500 nm and 570 nm, and between 570 nm and 680 nm; and a molded part to enclose the light emitting diodes and the wavelength conversion means. | 2021-05-27 |
20210159372 | ELECTRONIC DEVICE - The present disclosure provides an electronic device including a substrate and at least one light emitting unit. The light emitting unit includes a light emitting diode, a protective layer, and a light conversion layer. The protective layer includes a portion having a ripped section and not overlapped with the light emitting diode in a top view direction of the electronic device. The electronic device of the present disclosure may provide an electronic device that may reduce the influence from the outside or a subsequent process on the light emitting diode and improve luminance performance and reliability. | 2021-05-27 |
20210159373 | LIGHT EXTRACTION FOR MICRO-LEDS - Techniques disclosed herein relate to light extraction structures for micro-LED arrays. According to certain embodiments, a device includes an array of micro-LEDs characterized by a first pitch, and an array of micro-lenses on the array of micro-LEDs and characterized by a second pitch different from the first pitch. Each micro-lens in the array of micro-lenses corresponds to a respective micro-LED in the array of micro-LEDs. In some embodiments, the first pitch is greater than the second pitch such that a chief ray of light from each micro-LED in the array of micro-LEDs after passing through the corresponding micro-lens tilts in a respective direction towards a middle line of the device. | 2021-05-27 |
20210159374 | OPTICAL SEMICONDUCTOR ELEMENT MOUNTING PACKAGE AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - An optical semiconductor element mounting package as well as an optical semiconductor device using the package are provided. The optical semiconductor element mounting package has a recessed part that serves as an optical semiconductor element mounting region. The package includes a resin molding and at least a pair of positive and negative lead electrodes. The resin molding is composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part. The lead electrodes are disposed opposite to each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes. | 2021-05-27 |
20210159375 | SUBSTRATE FOR MOUNTING A LIGHT-EMITTING ELEMENT AND CIRCUIT BOARD FOR MOUNTING A LIGHT-EMITTING ELEMENT THAT INCLUDES IT, AND LIGHT-EMITTING ELEMENT MODULE - A substrate for mounting a light-emitting element according to the present disclosure contains a crystal particle of aluminum oxide and is composed of an alumina-based ceramic that contains 97% by mass or more of Al as a value of an Al | 2021-05-27 |
20210159376 | LED ARRAY HAVING TRANSPARENT SUBSTRATE WITH CONDUCTIVE LAYER FOR ENHANCED CURRENT SPREAD - In a flip-chip LED assembly having an array of LEDs formed on the same substrate, different LEDs of the array have different distances to the n-contacts of the assembly. This may cause current crowding as current has to spread from the n-contacts through the substrate to each the farthest LEDs of the LED array, requiring LEDs that are farther away to be driven with a higher voltage in order to receive a desired amount of current. To spread current more evenly through the LED assembly and reduce a voltage difference between the closest and farthest LEDs of the array, a current spreading layer having a conductive material (e.g., a conductive oxide) is formed on a surface of the substrate of the LED assembly. The current spreading layer may be a bulk layer or be patterned to increase light extraction from the LEDs of the array. | 2021-05-27 |
20210159377 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package is provided. The LED package includes a package body having a concave portion; an LED chip disposed on the concave portion; a phosphor sheet disposed on the LED chip; a barrier wall disposed on the concave portion and spaced apart from the LED chip by a first distance, the barrier wall being disposed in parallel with at least one side surface of the LED chip, an upper surface of the barrier wall being higher than an upper surface of the LED chip with respect to the lower surface of the concave portion and disposed at a level that is 50 μm or less from an upper surface of the phosphor sheet; and an encapsulation portion disposed on the LED chip, a side surface of the phosphor sheet and a side surface of the barrier wall. | 2021-05-27 |
20210159378 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor light-emitting device includes a plurality of light-emitting device structures separated from each other, each of the plurality of light-emitting device structures including a first conductivity type semiconductor layer, an active layer on the first conductivity type semiconductor layer, a second conductivity type semiconductor layer on the active layer, a first electrode connected to the first conductivity type semiconductor layer, and a second electrode connected to the second conductivity type semiconductor layer, and a partition wall structure between two adjacent light-emitting device structures of the plurality of light-emitting device structures, the partition wall structure defining a pixel space. | 2021-05-27 |
20210159379 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure discloses a method of manufacturing a light-emitting device includes steps of providing a first substrate with a plurality of first light-emitting elements and adhesive units arranged thereon, providing a second substrate with a first group of second light-emitting elements and a second group of second light-emitting elements arranged thereon, and connecting the a second group of second light-emitting elements and the adhesive units. The first light-emitting elements and the first group of second light-emitting elements are partially or wholly overlapped with each other during connecting the second group of second light-emitting elements and the adhesive units. | 2021-05-27 |
20210159380 | LIGHT-EMITTING DEVICE - A light-emitting device includes: a resin package; and a first light-emitting element and a second light-emitting element. The resin package includes: a resin portion; a first lead having an upper surface and an end surface; a second lead having an upper surface and an end surface; and a recess having lateral surfaces and a bottom surface that includes a portion of the upper surface of the first lead and a portion of the upper surface of the second lead that are exposed from the resin portion. The first light-emitting element and the second light-emitting element are disposed in the recess. The first lead and the second lead are arranged in a first direction. The first light-emitting element and the second light-emitting element are arranged in a second direction perpendicular to the first direction. | 2021-05-27 |
20210159381 | Thermoelectric Micro-Module With High Leg Density For Energy Harvesting And Cooling Applications - Micro-scale thermoelectric devices having high thermal resistance and efficiency for use in cooling and energy harvesting applications and relating fabricating methods are disclosed. The thermoelectric devices include first substrates substantially parallel with second substrates. Scaffold members are deposited between the first and second substrate. The scaffold members include a plurality of cavities having sidewalls. The scaffold members may be formed from the second substrate. The sidewalls are substantially vertical with respect to the second substrate. The sidewalls may be substantially parallel. Thermoelectric materials are deposited on the sidewalls. | 2021-05-27 |
20210159382 | PERMANENT WAFER HANDLERS WITH THROUGH SILICON VIAS FOR THERMALIZATION AND QUBIT MODIFICATION - A quantum device includes a qubit chip having a plurality of qubits and an interposer attached to and electrically connected to the qubit chip. The device also includes a substrate handler attached to one side of the qubit chip or to one side of the interposer, or both so as to be thermally in contact with the qubit chip or the interposer, or both. The substrate handler includes a plurality of vias, at least a portion of plurality of vias being filled with a non-superconducting material, the non-superconducting material being selected to dissipate heat generated in the qubit chip, the interposer or both. | 2021-05-27 |
20210159383 | HTS MAGNET SECTIONS - A segment of a field coil, a toroidal field coil, and a method of manufacturing is provided. The segment of a field coil is for use in a superconducting electromagnet. The segment includes an assembly for carrying electrical current in a coil of a magnet. The assembly includes a pre-formed housing comprising a channel configured to retain high temperature superconductor (HTS) tape, the channel including at least one pre-formed curved section. The assembly further includes a plurality of layers of HTS tape fixed within the channel. Wherein the pre-formed curved section has a radius of curvature which is less than a total thickness of the layers of HTS tape in that section divided by twice a maximum permitted strain of the HTS tape. | 2021-05-27 |
20210159384 | SUPERCONDUCTING QUBIT AND RESONATOR SYSTEM BASED ON THE JOSEPHSON RING MODULATOR - A superconducting quantum mechanical device includes first, second, third and fourth Josephson junctions connected in a bridge circuit having first, second and third resonance eigenmodes. The device also includes first and second capacitor pads. The first and second capacitor pads and the bridge circuit form a superconducting qubit having a resonance frequency corresponding to the first resonance eigenmode. The device further includes first and second resonator sections. The first and second resonator sections and the bridge circuit form a resonator having a resonance frequency corresponding to the second resonance eigenmode. The device also includes a source of magnetic flux arranged proximate the bridge circuit. The source of magnetic flux is configured to provide, during operation, a magnetic flux through the bridge circuit to cause coupling between the first, second and third resonance eigenmodes when the third resonance eigenmode is excited. | 2021-05-27 |
20210159385 | VIBRATION DEVICE - A vibration device includes a substrate having a first surface and a second surface at an opposite side to the first surface, a vibration element disposed on the first surface, a first through electrode which penetrates the substrate, and is configured to electrically couple the power supply interconnection disposed on the second surface and the first circuit block disposed on the first surface, and a second through electrode which penetrates the substrate, and is configured to electrically couple the power supply interconnection and the second circuit block including an analog circuit disposed on the first circuit, wherein R | 2021-05-27 |
20210159386 | MATCHING CONTROL METHOD FOR MECHANICAL IMPEDANCE OF MAGNETOSTRICTIVE PRECISION TRANSDUCER - A matching control method for mechanical impedance of a magnetostrictive precision transducer includes developing a three-layer neural network model corresponding to a Young's modulus of a Terfenol-D material; acquiring sample data to form a training sample set and a testing sample set; training the model using a Bayesian regularization training algorithm, and optimizing connection weights and thresholds among layers of the tested model, so as to obtain a final three-layer neural network model; based on the final model, building an inverse model of mechanical impedance of the magnetostrictive precision transducer; using a current level of impedance of a load as an input of the inverse model to obtain a bias magnetic field, and changing a level of the bias magnetic field by changing a bias current in an excitation coil of the transducer, thereby achieving adaptive matching between the mechanical impedance of the transducer and the impedance of the load. | 2021-05-27 |
20210159387 | MEMS STRUCTURES AND METHODS OF FORMING MEMS STRUCTURES - A MEMS structure may include a substrate, a first metal layer arranged over the substrate, an aluminum nitride layer at least partially arranged over the first metal layer and a second metal layer including one or more patterns arranged over the aluminum nitride layer. The first metal layer may include an electrode area configured for external electrical connection and one or more isolated areas configured to be electrically isolated from the electrode area and further configured to be electrically isolated from external electrical connection. Each pattern of the second metal layer may be arranged to at least partially overlap with one of the isolated area(s) of the first metal layer. | 2021-05-27 |
20210159388 | HUMAN JOINT ENERGY HARVESTING APPARATUS AND WEARABLE ELECTRONIC DEVICE COMPRISING THE SAME - The present application provides a human joint energy harvesting apparatus for capturing the biomechanical energy of a joint to generate electrical energy. The generated electrical energy may provide a real-time power supply to the wearable electronics. The apparatus employs a linear slide rail mechanism and cooperates with the user's first limb and second limb to form a slider-crank mechanism, which converts the rotating motion of the joint into a linear motion of the linear slide rail mechanism. The bending beam converts the linear motion of the linear slide rail mechanism into a bending motion. A piezoelectric film may be bonded to the upper and lower surfaces of the bending beam. During walking, the bending beam is deformed, causing the piezoelectric film to be stretched or compressed to generate electrical energy. To harvest more energy, the bending beam used in the apparatus is designed to be subjected to forced motion and free vibration, and a proof mass is attached to it. The present application also provides a wearable electronic device equipped with the human joint energy harvesting apparatus. | 2021-05-27 |
20210159389 | DOUBLE MAGNETIC TUNNEL JUNCTION DEVICE, FORMED BY UVH WAFER BONDING - A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack. The first magnetic tunnel junction stack includes a first reference layer. The method also includes forming a second magnetic tunnel junction stack, where the second magnetic tunnel junction stack includes a second reference layer. The method also includes bonding the first magnetic tunnel junction stack to the second magnetic tunnel junction stack with ultra-high vacuum bonding to form the double magnetic tunnel junction device. | 2021-05-27 |
20210159390 | SPIN-ORBIT-TORQUE MAGNETO-RESISTIVE RANDOM ACCESS MEMORY WITH STEPPED BOTTOM ELECTRODE - A memory structure, and a method for forming the same, includes a spin-orbit-torque electrode within a dielectric layer located above a substrate. The spin-orbit-torque electrode including a first conductive material, and a spin-orbit torque via is directly above the spin-orbit-torque electrode that includes a second conductive material. A magnetic tunnel junction pillar is directly above the spin-orbit torque via, and the spin-orbit-torque via contacting a center of a bottom surface of the magnetic-tunnel-junction pillar. A third conductive material is positioned directly below the bottom surface of the magnetic tunnel junction pillar on opposite sides of the spin-orbit torque via and directly above the spin-orbit-torque electrode. The third conductive material, the spin-orbit torque electrode and the spin-orbit torque via form a bottom spin-orbit torque electrode of the magnetic tunnel junction pillar. | 2021-05-27 |
20210159391 | MAGNETORESISTIVE MEMORY DEVICE INCLUDING A HIGH DIELECTRIC CONSTANT CAPPING LAYER AND METHODS OF MAKING THE SAME - Magnetoelectric or magnetoresistive memory cells include at least one of a high dielectric constant dielectric capping layer and/or a nonmagnetic metal dust layer located between the free layer and the dielectric capping layer. | 2021-05-27 |
20210159392 | MAGNETORESISTIVE MEMORY DEVICE INCLUDING A HIGH DIELECTRIC CONSTANT CAPPING LAYER AND METHODS OF MAKING THE SAME - Magnetoelectric or magnetoresistive memory cells include at least one of a high dielectric constant dielectric capping layer and/or a nonmagnetic metal dust layer located between the free layer and the dielectric capping layer. | 2021-05-27 |
20210159393 | MAGNETIC TUNNEL JUNCTION DEVICES AND METHODS OF FORMING THEREOF - In a non-limiting embodiment, a semiconductor device may include a magnetic tunnel junction (MTJ) stack. The MTJ stack may include a reference layer comprising a magnetic layer, a first tunneling barrier layer arranged over the reference layer, a free layer comprising a magnetic layer arranged over the first tunneling barrier layer, and a capping layer arranged over the reference layer, the first tunneling barrier layer and the free layer. The capping layer may be a non-magnetic layer. According to various non-limiting embodiments, the capping layer may include a rare earth element. According to various non-limiting embodiments, the MTJ stack may further include a second tunneling barrier layer arranged between the free layer and the capping layer. The capping layer may contact the second tunneling barrier layer. | 2021-05-27 |
20210159394 | PILLAR-BASED MEMORY HARDMASK SMOOTHING AND STRESS REDUCTION - A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack. | 2021-05-27 |
20210159395 | MAGNETIC MEMORY USING SPIN-ORBIT TORQUE - Spin-orbit-torque (SOT) segments are provided along the sides of free layers in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT segments injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction in order to improve the efficiency of the switching current applied to the magnetoresistive device. | 2021-05-27 |
20210159396 | MAGNETORESISTANCE EFFECT ELEMENT AND METHOD FOR MANUFACTURING THE SAME - This magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer which is interposed between the first and second ferromagnetic layers, wherein the tunnel barrier layer has a spinel structure represented by a compositional formula X | 2021-05-27 |
20210159397 | MAGNETIC MEMORY - A magnetic memory including a plurality of magnetoresistance effect elements that hold information, each including a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer with a varying magnetization direction, and a non-magnetic layer sandwiched between the first and second ferromagnetic metal layers; a plurality of first control elements that control reading of the information, wherein each of the plurality of first ferromagnetic metal layers is connected to a first control element; a plurality of spin-orbit torque wiring lines that extend in a second direction intersecting with a first direction which is a stacking direction of the magnetoresistance effect elements, wherein each of the second ferromagnetic metal layers is joined to one spin-orbit torque wiring line; a plurality of second control elements that control electric current flowing through the spin-orbit torque wiring lines. | 2021-05-27 |
20210159398 | NANOMETER SCALE NONVOLATILE MEMORY DEVICE AND METHOD FOR STORING BINARY AND QUANTUM MEMORY STATES - Example implementations include an electronic memory device with a metallic layer having a first planar crystalline structure, a first encapsulating layer including an encapsulating material having a second planar crystalline structure, and disposed adjacent to a first planar surface of the metallic layer, and a second encapsulating layer including the encapsulating material, and disposed adjacent to a second planar surface of the metallic layer. Example implementations also include a method of depositing graphite crystals onto a substrate to form a gate bottom layer, depositing BN crystals onto the graphite bottom layer to form a BN bottom layer, depositing tungsten ditelluride (WTe | 2021-05-27 |
20210159399 | Magnetic Memory Element Incorporating Dual Perpendicular Enhancement Layers - The present invention is directed to a magnetic memory element including a magnetic free layer structure incorporating three magnetic free layers separated by two perpendicular enhancement layers (PELs) and having a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a third perpendicular enhancement layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer has a second invariable magnetization direction substantially opposite to the first invariable magnetization direction. | 2021-05-27 |
20210159400 | MATERIAL, SYSTEM AND METHOD MAKING USE OF PLASMON RESONANCE - A plasmonic nanostructure material having semiconductor nanocrystals or metal-oxide nanocrystals configured with point defects to provide localized surface plasmon resonance as a parameter for tuning the electronic structure of the nanocrystals. A method of preparing a plasmonic nanostructure material including: colloidal synthesis of nanocrystals to provide point defects resulting in localized surface plasmon resonance as a parameter for tuning the electronic structure of the nanocrystals; and depositing nanocrystals as a thin film, growing nanocrystals on a desired substrate, or drawing nanocrystals into a nanowire. | 2021-05-27 |
20210159401 | MAGNETORESISTIVE ELEMENT HAVING A PERPENDICULAR AFM STRUCTURE - A magnetoresistive element comprises a perpendicular coupling layer between a novel perpendicular AFM layer and ferromagnetic recording layer. The perpendicular coupling layer introduces giant magnetic anisotropy energies (P-MAE) on the recording layer interface and the P-AFM layer interface which further introduce RKKY coupling between the magnetic moment of the recording layer and the P-MAE induced magnetic moment at the P-AFM layer interface, yielding a giant perpendicular magnetic anisotropy of the recording layer. | 2021-05-27 |
20210159402 | OXIDE INTERLAYERS CONTAINING GLASS-FORMING AGENTS - A magnetic junction usable in a magnetic device is described. The magnetic junction includes a free layer and an oxide interlayer on the free layer. The oxide interlayer includes at least one glass-forming agent. In some aspects, the magnetic junction includes a reference layer and a nonmagnetic spacer layer being between the reference layer and the free layer. The free layer is between the nonmagnetic spacer layer and the oxide interlayer. | 2021-05-27 |
20210159403 | HALL-EFFECT SENSOR PACKAGE WITH ADDED CURRENT PATH - A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head. | 2021-05-27 |
20210159404 | THERMAL DISPERSION LAYER IN PROGRAMMABLE METALLIZATION CELL - Some embodiments relate to a method for manufacturing a memory device. The method includes forming a bottom electrode over a substrate. A heat dispersion layer is formed over the bottom electrode. A dielectric layer is formed over the heat dispersion layer. A top electrode is formed over the dielectric layer. The heat dispersion layer comprises a first dielectric material. | 2021-05-27 |
20210159405 | PHASE CHANGE MEMORY CELL WITH A METAL LAYER - A method may include filling a via opening with a spacer, the via opening formed in a dielectric layer, forming a trench within the spacer, filling the trench with a metal layer, recessing the spacer to form an opening and expose an upper portion of the metal layer, wherein the exposed portion of the metal layer is formed into a cone shaped tip, conformally depositing a liner along a bottom and a sidewall of the opening and the exposed portion of the metal layer, depositing a second dielectric layer along the bottom of the opening on top of the liner, recessing the liner to form a channel and partially exposing a sidewall of the second dielectric layer and a sidewall of the metal layer, depositing a third dielectric layer in the channel, and depositing a phase change memory layer within the opening. | 2021-05-27 |
20210159406 | RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformity formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar. | 2021-05-27 |
20210159407 | RRAM STRUCTURE - In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device. | 2021-05-27 |
20210159408 | MIEC AND TUNNEL-BASED SELECTORS WITH IMPROVED RECTIFICATION CHARACTERISTICS AND TUNABILITY - A selector device for a memory cell in a memory array includes a first electrode, a second electrode, and a separator between the first electrode and the second electrode. The separator includes a mixed ionic-electronic conduction material with first ions having a first charge such that the first ions respond to a voltage applied between the first electrode and the second electrode by moving away from the first electrode. The separator is doped near the second electrode with second ions having a second charge that opposes the first charge. | 2021-05-27 |
20210159409 | 3D ReRAM FORMED BY METAL-ASSISTED CHEMICAL ETCHING WITH REPLACEMENT WORDLINE AND WORDLINE SEPARATION - Metal-assisted chemical etching is employed to form a three-dimensional (3D) resistive random access memory (ReRAM) in which the etching aspect ratio limit is extended and the top trench and bottom trench CD uniformity is improved. The 3D ReRAM includes a metal catalyst located between a bitline electrode and a selector device. Further, the 3D ReRAM includes vertically stacked and spaced apart replacement wordline electrodes that are located adjacent to the bitline electrode. | 2021-05-27 |
20210159410 | Organic Compound, Light-Emitting Element, Light-Emitting Device, Electronic Device, Display Device, and Lighting Device - An object of one embodiment of the present invention is to provide a novel organic compound. The organic compound is a triarylamine derivative. The triarylamine derivative has an aryl group including a skeleton in which a naphthyl group is bonded to a naphthylene group. The other two aryl groups are each independently a phenyl group, a biphenyl group, or a terphenyl group. These groups may each have a substituent. As the substituent, an alkyl group having 1 to 6 carbon atoms or a cycloalkyl group having 3 to 6 carbon atoms can be selected. | 2021-05-27 |
20210159411 | CONDENSED CYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME - A condensed cyclic compound and an organic light-emitting device including the same are provided. The condensed cyclic compound is represented by Formula 1: | 2021-05-27 |
20210159412 | HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME - An organic light-emitting device includes a heterocyclic compound represented by Formula 1, wherein A | 2021-05-27 |
20210159413 | SYSTEM AND METHOD FOR ORGANIC ELECTRONIC DEVICE PATTERNING - A method for fabricating an organic electronic device comprises providing a plurality of photoresist structures on a substrate, the substrate having a first electrode layer, the photoresist structures having a bottom surface attached to the substrate and a top surface opposite the bottom surface, the top surface having a dimension greater than a dimension of the bottom surface, positioning a mask over the structures, the mask having a plurality of openings, and depositing an emissive material over the substrate through at least one of the plurality of openings to form at least one emissive element. An organic electronic device and a method of fabricating an organic electronic component are also described. | 2021-05-27 |
20210159414 | METHOD FOR PRODUCING VAPOR DEPOSITION MASK, VAPOR DEPOSITION MASK PRODUCING APPARATUS, LASER MASK AND METHOD FOR PRODUCING ORGANIC SEMICONDUCTOR ELEMENT - A step of preparing a resin plate-equipped metal mask including a metal mask in which a slit is provided and a resin plate, and a step of laser irradiation from the metal mask side to form an opening corresponding to a pattern to be produced by vapor deposition in the resin plate are included, wherein in the step of forming the opening, by using a laser mask in which an opening region corresponding to the opening and an attenuating region that is positioned in a periphery of the opening region and attenuates energy of the laser, the opening corresponding to the pattern to be produced by vapor deposition is formed with respect to the resin plate with the laser that passes through the opening region, and a thin part is formed in a periphery of the opening of the resin plate with the laser that passes through the attenuating region. | 2021-05-27 |
20210159415 | MICROSTRUCTURES ARRAY AND METHOD OF MANUFACTURING THE SAME AND MICRO LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE - Disclosed are a method of manufacturing a microstructure array that includes preparing a mold having a concave micro pattern array in which a plurality of concave micro patterns are arranged, preparing a perovskite precursor solution including a perovskite precursor and a hydrophilic polymer, coating the perovskite precursor solution on a substrate, disposing the mold on the perovskite precursor solution to confine the perovskite precursor solution in the plurality of concave micro patterns, obtaining a composite of perovskite nanocrystals and the hydrophilic polymer from the perovskite precursor solution in the plurality of concave micro patterns, and, and removing the mold to form a microstructure array in which a plurality of microstructures including a composite of the perovskite nanocrystals and the hydrophilic polymer are arranged, a microstructure array, a micro light emitting diode including the same, and a manufacturing method thereof, and a display device. | 2021-05-27 |
20210159416 | LIGHT EMITTING DEVICE - A light emitting device having excellent external quantum efficiency contains an anode, a cathode, and two organic layers disposed therebetween. One layer contains a phosphorescent transition metal complex and a low molecular weight compound containing no transition metal, and the second layer contains a crosslinked body of a polymer compound (having an energy level of the lowest triplet excited state of 2.30 eV or more) containing a constitutional unit having a crosslinking group. The low molecular weight compound has formula (T-1) and the absolute value of the difference between the energy levels of the lowest triplet excited state and the lowest singlet excited state is less than 0.25 eV. | 2021-05-27 |
20210159417 | Fullerene Derivative Blends, Methods of Making and Uses Thereof - Fullerene derivative blends are described herein. The blends are useful in electronic applications such as, e.g., organic photovoltaic devices. | 2021-05-27 |
20210159418 | ORGANIC LIGHT EMITTING DIODE - An organic light emitting diode includes a first electrode, a hole transport region disposed on the first electrode, an emission layer disposed on the hole transport region, an electron transport region disposed on the emission layer, and a second electrode disposed on the electron transport region. The hole transport region includes a first hole transport layer which is directly disposed on the lower portion of the emission layer and has a first refractive index, and a second hole transport layer which is disposed on the lower portion of the first hole transport layer and has a second refractive index, thereby exhibiting an improved luminous efficiency characteristic. | 2021-05-27 |
20210159419 | NON-FULLERENE ACCEPTORS (NFAS) AS INTERFACIAL LAYERS IN PEROVSKITE SEMICONDUCTOR DEVICES - A method for producing an organic non-fullerene electron transport compound includes mixing naphthalene-1,4,5,8-tetracarboxylic dianhydride and an amine compound in dimethylformamide. The method also includes heating the mixture to a temperature greater than or equal to 70° and less than or equal to 160° C. for an amount of time greater than or equal to 1 hour and less than or equal to 24 hours. The method further includes isolating an organic non-fullerene electron transport compound reaction product. | 2021-05-27 |
20210159420 | ORGANIC ELECTROLUMINESCENCE DEVICE AND AMINE COMPOUND FOR ORGANIC ELECTROLUMINESCENCE DEVICE - An organic electroluminescence device of an embodiment of the present disclosure includes a first electrode, a second electrode facing the first electrode, and a plurality of organic layers disposed between the first electrode and the second electrode, wherein at least one organic layer of the plurality of organic layers includes an amine compound containing a fluorene group; an aryl group having 6 to 60 ring-forming carbon atoms, which is substituted to the fluorene group; a heteroaryl group having 2 to 60 ring-forming carbon atoms, which is substituted to the fluorene group; and at least one amine group, which is substituted to the fluorene group; wherein all the carbons of the aryl group are substituted with deuterium, and the organic electroluminescence device exhibits high efficiency and a long service life. | 2021-05-27 |
20210159421 | COMPOSITION FOR FORMING CHARGE-TRANSPORTING THIN FILM - This composition for forming a charge-transporting thin film, which contains an organic solvent and a charge-transporting substance precursor that has a 9-t-butoxycarbonyl carbazole structure in the molecule, yields a thin film that exhibits excellent charge transport properties even when firing is performed at a low temperature. As pertains to the charge-transporting substance precursor, the composition can be prepared using a low-polarity solvent that causes less damage to a substrate or a member comprising an organic compound than is the case with a high-polarity amide-based solvent, etc. | 2021-05-27 |
20210159422 | Organic Compound, Light-Emitting Element, Light-Emitting Device, Electronic Device, and Lighting Device - A novel organic compound is provided. A novel organic compound having a hole-transport property is provided. A novel hole-transport material is provided. A novel light-emitting element is provided. A light-emitting element with a favorable lifetime is provided. A light-emitting element with favorable emission efficiency is provided. An organic compound having a substituted or unsubstituted benzonaphthofuran skeleton, a substituted or unsubstituted carbazole skeleton, and a substituted or unsubstituted amine skeleton is provided. Alternatively, a light-emitting element that uses the hole-transport material is provided. | 2021-05-27 |
20210159423 | NEAR-INFRARED ABSORBERS, NEAR-INFRARED ABSORBING/BLOCKING FILMS, PHOTOELECTRIC DEVICES, ORGANIC SENSORS, AND ELECTRONIC DEVICES - A near-infrared absorber includes a compound represented by Chemical Formula 1. A near-infrared absorbing/blocking film, a photoelectric device, an organic sensor, and an electronic device may include the near-infrared absorber. | 2021-05-27 |
20210159424 | HOLE TRANSPORTING MATERIAL USING SPIROBIACRIDINE AS CORE AND ORGANIC LIGHT EMITTING DIODE - A hole transporting material using spirobiacridine as a core is provided, having a following structural formula (I) and suitable migration rates under highest occupied molecular orbital (HOMO) energy levels and lowest unoccupied molecular orbital (LUMO) energy levels. Moreover, an organic light emitting diode is disclosed, including an anode, a cathode, and a light emitting structure located between the anode and the cathode, wherein the light emitting structure includes the hole transporting material using spirobiacridine as the core which is represented by the following structural formula (I) | 2021-05-27 |
20210159425 | THERMALLY ACTIVATED DELAYED FLUORESCENCE MATERIAL AND ORGANIC LIGHT-EMITTING DIODE PREPARED USING SAME - The present disclosure provides a thermally activated delayed fluorescence material having a structure of formula (I) and having a low single-triplet energy gap, a high reverse intersystem crossover constant, and a high photoluminescence quantum yield. | 2021-05-27 |
20210159426 | PEROVSKITE COMPOSITIONS COMPRISING MIXED SOLVENT SYSTEMS - Described herein is an ink solution, comprising a composition of formula (I): ABX | 2021-05-27 |
20210159427 | LOW REFRACTIVE INDEX COMPOUND AND ELECTRONIC APPARATUS INCLUDING THE SAME - A metallic compound for use in an electronic apparatus having an organic light emitting element, the metallic compound having a refractive index: n | 2021-05-27 |
20210159428 | ORGANOMETALLIC COMPOUND AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE SAME - An organometallic compound and an organic light-emitting device including the same are provided. The organometallic compound is represented by Formula 1: | 2021-05-27 |
20210159429 | LIGHT-EMITTING LAYER, ORGANIC LIGHT EMITTING DIODE DEVICE AND DISPLAY APPARATUS - The present disclosure provides a light-emitting layer, an organic light emitting diode (OLED) device, and a display apparatus. The light-emitting layer has a host material containing a first photocrosslinker group. A guest material containing a second photocrosslinker group is prepared. The host material and the guest material are mixed in a solvent to form a mixture. The mixture is coated, annealed, and LV-irradiated on a substrate to form the light-emitting layer. As such, the disclosed light-emitting layer is prepared by the polymerization after being on the substrate. The light-emitting layer has a mesh structure. The mesh structure improves energy transfer between the host material and guest material and increases the lifespan of the resultant OLED device and OLED display apparatus. | 2021-05-27 |
20210159430 | ORGANIC ELECTROLUMINESCENCE DEVICE AND ORGANOMETALLIC COMPOUND FOR ORGANIC ELECTROLUMINESCENCE DEVICE - An organic electroluminescence device of an embodiment includes a first electrode, a second electrode, and an emission layer between the first electrode and the second electrode, wherein the emission layer includes an organometallic compound represented by Formula 1, and the emission layer may show high emission efficiency properties. | 2021-05-27 |
20210159431 | ORGANOMETALLIC COMPOUND, ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME, AND DIAGNOSTIC COMPOSITION INCLUDING THE ORGANOMETALLIC COMPOUND - An organometallic compound represented by Formula 1A: | 2021-05-27 |
20210159432 | TETRA-NUCLEAR NEUTRAL COPPER (I) COMPLEXES - The invention relates to tetra-nuclear neutral copper (I) complexes of Formula (A) that have a cubane-like structure, wherein said complexes comprise phosphine ligands which bear one or more aldehyde or ester groups. Furthermore, the present invention refers to methods for generating such copper (I) complexes of Formula (A) and to uses thereof. Each L is independently from each other a ligand that has a structure of Formula (A1): P(Ar) | 2021-05-27 |
20210159433 | FLEXIBLE DISPLAY PANEL, FLEXIBLE DISPLAY DEVICE, AND MANUFACTURING METHOD OF FLEXIBLE DISPLAY PANEL - The present invention provides a flexible display panel, a flexible display device, and a manufacturing method of the flexible display panel. The flexible display panel is used as a protective cover of the flexible display device. The flexible display panel includes a flexible substrate, organic pixel units, a first inorganic layer, a spacer, an organic layer, and a second inorganic layer. The organic pixel units are disposed in an array on a side of the flexible substrate. The first inorganic layer covers a side of the organic pixel units away from the flexible substrate. The spacer is disposed on a side of the first inorganic layer away from the flexible substrate, wherein the spacer is provided with a plurality of through holes. The flexible display panel of the present invention not only has high flexibility and bendability but also has strong water and oxygen barrier capabilities. | 2021-05-27 |
20210159434 | LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE - A highly portable and highly browsable light-emitting device is provided. A light-emitting device that is less likely to be broken is provided. The light-emitting device has a strip-like region having high flexibility and a strip-like region having low flexibility that are arranged alternately. In the region having high flexibility, a light-emitting panel and a plurality of spacers overlap with each other. In the region having low flexibility, the light-emitting panel and a support overlap with each other. When the region having high flexibility is bent, the angle between normals of facing planes of the two adjacent spacers changes according to the bending of the light-emitting panel; thus, a neutral plane can be formed in the light-emitting panel or in the vicinity of the light-emitting panel. | 2021-05-27 |