21st week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100127328 | SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICES USING VOID SPACES - An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining. | 2010-05-27 |
20100127329 | Thin Film Transistor Substrate And Method Of Manufacturing The Same - A thin film transistor substrate with good process efficiency and a method of manufacturing the same are provided. The thin film transistor substrate includes a first conductive type MOS transistor and a second conductive type MOS transistor. The first conductive type MOS transistor includes a first semiconductor layer formed on a blocking layer and having first conductive type low-concentration doping regions adjacent to both sides of a channel region, first conductive type source/drain regions adjacent to the first conductive type low-concentration doping regions, a first gate insulating layer formed on the first semiconductor layer, a second gate insulating layer formed on the first gate insulating layer and overlapping with the channel region and the low-concentration doping regions of the first semiconductor layer, and a first gate electrode formed on the second gate insulating layer. The second conductive type MOS transistor includes a second semiconductor layer formed on the blocking layer and having second conductive type source/drain regions adjacent to both sides of a channel region, the first gate insulating layer formed on the second semiconductor layer, a third gate insulating layer formed on the first gate insulating layer and overlapping with the second semiconductor layer, and a second gate electrode formed on the third gate insulating layer. | 2010-05-27 |
20100127330 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises an insulated gate field effect transistor and a protection diode. The insulated gate field effect transistor has a gate electrode formed on a gate insulating film, a source and a drain. The source and the drain are formed in a first area of a semiconductor substrate. A first silicon oxide film is formed on a second area of the semiconductor substrate adjacent to the first area. The first silicon oxide film is thicker than the gate insulating film and contains larger amount of impurities than the gate insulating film. A poly-silicon layer is formed on the first silicon oxide film. The protection diode has a plurality of PN-junctions formed in the poly-silicon layer. The protection diode is connected between the gate electrode and the source so as to prevent breakdown of the gate insulating film. | 2010-05-27 |
20100127331 | ASYMMETRIC METAL-OXIDE-SEMICONDUCTOR TRANSISTORS - Mixed gate metal-oxide-semiconductor transistors are provided. The transistors may have an asymmetric configuration that exhibits increased output resistance. Each transistor may be formed from a gate insulating layer formed on a semiconductor. The gate insulating layer may be a high-K material. Source and drain regions in the semiconductor may define a transistor gate length. The gate length may be larger than the minimum specified by semiconductor fabrication design rules. The transistor gate may be formed from first and second gate conductors with different work functions. The relative sizes of the first and gate conductors in a given transistor control the threshold voltage for the transistor. A computer-aided design tool may be used to receive a circuit design from a user. The tool may generate fabrication masks for the given design that include mixed gate transistors with threshold voltages optimized to meet circuit design criteria. | 2010-05-27 |
20100127332 | INTEGRATED CIRCUIT TRANSISTORS - Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor. | 2010-05-27 |
20100127333 | NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT - The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate. | 2010-05-27 |
20100127334 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a semiconductor integrated circuit device capable of realizing an analog circuit required to have a high-precision relative ratio between adjacent transistors, which is reduced in size and cost. A single MOS transistor is provided within each of well regions. A plurality of the MOS transistors is combined to serve as an analog circuit block. Since distances between the well regions and channel regions may be made equal to one another, a high-precision semiconductor integrated circuit device can be obtained. | 2010-05-27 |
20100127335 | Methods to Enhance Effective Work Function of Mid-Gap Metal by Incorporating Oxygen and Hydrogen at a Low Thermal Budget - A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed. | 2010-05-27 |
20100127336 | STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER - A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed. | 2010-05-27 |
20100127337 | INVERTER STRUCTURE AND METHOD FOR FABRICATING THE SAME - An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact. | 2010-05-27 |
20100127338 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device may include a semiconductor substrate, a salicide, a gate electrode, and an insulating layer. The semiconductor substrate has a lightly doped drain (LDD) region formed therein. The salicide is formed on the LDD region. The gate electrode is formed on the semiconductor substrate. The gate electrode has a stacked structure of a gate oxide and a metal layer. The insulating layer is formed on the semiconductor substrate and at a side of the gate electrode. | 2010-05-27 |
20100127339 | MICROMECHANICAL COMPONENT HAVING AN ANTI-ADHESIVE LAYER - A micromechanical component, having a substrate and a functional element, the functional element having a functional surface which has an anti-adhesion layer, that has been applied at least in regions, for reducing the surface adhesion forces, and in which the anti-adhesion layer is stable to a temperature of more than 800° C. | 2010-05-27 |
20100127340 | MEMS PACKAGE AND METHOD OF MANUFACTURING THE MEMS PACKAGE - An MEMS chip is mounted face-down on a semiconductor wafer such that a movable section is opposed to the semiconductor wafer. A resin layer is formed on the semiconductor wafer around the MEMS chip to reduce a step between the MEMS chip and the semiconductor wafer. After the semiconductor substrate is removed, the land electrode is formed on the resin layer. | 2010-05-27 |
20100127341 | Imaging Device Manufacturing Method, Imaging Device and Portable Terminal - Provided are a method for manufacturing a low cost imaging device, the low cost imaging device manufactured by such method and a portable terminal using the imaging device. A silicon wafer | 2010-05-27 |
20100127342 | BACK-ILLUMINATED TYPE SOLID-STATE IMAGING DEVICE - A back-illuminated type solid-state imaging device is provided in which an electric field to collect a signal charge (an electron, a hole and the like, for example) is reliably generated to reduce a crosstalk. | 2010-05-27 |
20100127343 | Glass-Ceramic-Based Semiconductor-On-Insulator Structures and Method For Making The Same - Methods and apparatus for forming a semiconductor on glass-ceramic structure provide for: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a precursor glass substrate using electrolysis; separating the exfoliation layer from the donor semiconductor wafer to thereby form an intermediate semiconductor on precursor glass structure; sandwiching the intermediate semiconductor on precursor glass structure between first and second support structures; applying pressure to one or both of the first and second support structures; and subjecting the intermediate semiconductor on precursor glass structure to heat-treatment step to crystallize the precursor glass resulting in the formation of a semiconductor on glass-ceramic structure. | 2010-05-27 |
20100127344 | CONTACT OVER ISOLATOR - An apparatus and method for providing a reliable connection to an internal node from the backside of an integrated circuit using focused ion beam (“FIB”) milling are disclosed herein. In accordance with at least some embodiments, an integrated circuit includes an isolation region, an active region, a first contact, and a metal layer. The isolation region separates adjacent integrated circuit devices. The first contact is disposed between the isolation region and the metal layer. The first contact is electrically connected to the active region. A dummy structure is disposed between the isolation region and the first contact. A FIB via is milled through the isolation region and the dummy structure to the first contact to establish an electrical connection with active region through the via. | 2010-05-27 |
20100127345 | 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES | 2010-05-27 |
20100127346 | POWER DISTRIBUTION FOR CMOS CIRCUITS USING IN-SUBSTRATE DECOUPLING CAPACITORS AND BACK SIDE METAL LAYERS - A semiconductor device and method for fabricating the same is provided. The semiconductor device includes a substrate, at least one capacitor, an active circuit and a power plane. The substrate has a first cavity formed through a first surface to a first depth and a second cavity formed through a second surface to a second depth. The first and second cavities forming a via hole through the substrate. The at least one capacitor includes a first conductive material layer deposited in the via hole, a first isolation material layer deposited over the first conductive material layer, and a second conductive material layer deposited over the first isolation material layer. The active circuit adjacent the first surface and electrically coupled to the at least one capacitor, and the power plane adjacent the second surface and electrically coupled to the at least one capacitor to provide power conditioning to the active circuit. | 2010-05-27 |
20100127347 | SHIELDING FOR INTEGRATED CAPACITORS - A capacitor in an integrated circuit (“IC”) includes a core capacitor portion having first conductive elements electrically connected to and forming a part of a first node of the capacitor formed in a first layer and second conductive elements electrically connected to and forming a part of a second node of the capacitor formed in the first layer. The first and second conductive elements alternate in the first conductive layer. Third conductive elements electrically connected to and forming a part of the first node are formed in a second layer adjacent to the first layer. The capacitor also includes a shield capacitor portion having fourth conductive elements formed in at least first, second, third, and fourth layers. The shield capacitor portion is electrically connected to and forms a part of the second node of the capacitor and surrounds the first and third conductive elements. | 2010-05-27 |
20100127348 | INTEGRATED CAPICITOR WITH CABLED PLATES - A capacitor in an integrated circuit (“IC”) has a distribution grid formed in a first patterned metal layer of the integrated circuit and a first vertical conductive filament connected to and extending away from the distribution grid along a first direction. A second vertical conductive filament is connected to the distribution grid and extends in the opposite direction. First and second grid plates are formed in the metal layers above and below the first patterned metal layer. The grid plates surround the first and second vertical conductive filaments. The distribution grid, first vertical conductive filament and second vertical conductive filament are connected to and form a portion of a first node of the capacitor and the first grid plate and the second grid plate are connected to and form a portion of a second node of the capacitor. | 2010-05-27 |
20100127349 | INTEGRATED CAPACITOR WITH ARRAY OF CROSSES - A capacitor in an integrated circuit (“IC”) has a first plurality of conductive crosses formed in a layer of the IC electrically connected to and forming a portion of a first node of the capacitor and a second plurality of conductive crosses formed in the metal layer of the IC. The conductive crosses in the second plurality of conductive crosses are electrically connected to and form a portion of a second node of the capacitor and capacitively couple to the first node. | 2010-05-27 |
20100127350 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a lower electrode on a semiconductor substrate, applying a photoresist on the lower electrode, forming an opening in the photoresist spaced from the periphery of the lower electrode, forming a high-dielectric constant film of a high-k material having a dielectric constant of 10 or more, performing liftoff so that the high-dielectric-constant film remains on the lower electrode, and forming an upper electrode on the high-dielectric-constant film remaining after the liftoff. | 2010-05-27 |
20100127351 | INTEGRATED CAPACITOR WITH INTERLINKED LATERAL FINS - A capacitor in an integrated circuit (“IC”) has a first node conductor formed in a first metal layer of the IC with a first spine extending along a first direction, a first vertical element extending from the first spine along a second direction perpendicular to the first direction. A first capital element extends along the first direction, and a first serif element extends from the capital element. The capacitor also has a second node conductor having a second spine, a second vertical element extending from the second spine toward the first spine, a second capital element, and a second serif element extending from the second capital between the first vertical element and the first serif element. | 2010-05-27 |
20100127352 | SELF-ALIGNED BIPOLAR TRANSISTOR STRUCTURE - A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region. | 2010-05-27 |
20100127353 | STRAIN ENGINEERED COMPOSITE SEMICONDUCTOR SUBSTRATES AND METHODS OF FORMING SAME - Composite substrates are produced that include a strained III-nitride material seed layer on a support substrate. Methods of producing the composite substrate include developing a desired lattice strain in the III-nitride material to produce a lattice parameter substantially matching a lattice parameter of a device structure to be formed on the composite substrate. The III-nitride material may be formed with a Ga polarity or a N polarity. The desired lattice strain may be developed by forming a buffer layer between the III-nitride material and a growth substrate, implanting a dopant in the III-nitride material to modify its lattice parameter, or forming the III-nitride material with a coefficient of thermal expansion (CTE) on a growth substrate with a different CTE. | 2010-05-27 |
20100127354 | SILICON SINGLE CRYSTAL AND METHOD FOR GROWING THEREOF, AND SILICON WAFER AND METHOD FOR MANUFACTURING THEREOF - A method for growing a silicon single crystal having a hydrogen defect density of equal to or less than 0.003 pieces/cm | 2010-05-27 |
20100127355 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and method. One embodiment provides a semiconductor substrate having a plurality of cut regions. A metal layer is located within a cut region. The metal layer includes a recess, the recess having a slit-like shape. | 2010-05-27 |
20100127356 | STRUCTURES AND METHODS FOR REDUCING JUNCTION LEAKAGE IN SEMICONDUCTOR DEVICES - Structures and method for reducing junction leakage in semiconductor devices. The die can include a substrate having a cut edge, a first region of first conductivity type within the substrate and a region of a second conductivity type within the substrate and in contact with the first region forming a junction. At least one semiconductor device is on the substrate. A second region of the first conductivity type is between the plurality of semiconductor devices and the cut edge within the region of the second conductivity type, and extending to the junction. The second region of the first conductivity type can isolate the at least one semiconductor device from leakage pathways created by saw damage at the junction along the cut edge. | 2010-05-27 |
20100127357 | SEMICONDUCTOR DEVICE - A semiconductor device includes a seal ring formed on an outer circumference of an element forming region when seen from the top in a multilayer interconnect structure formed on a silicon layer, and dummy metal structures formed on a further outer circumference of the seal ring. The more inner circumference side the dummy interconnect is formed on, the more upper layer the dummy interconnect is arranged on. | 2010-05-27 |
20100127358 | Integration of damascene type diodes and conductive wires for memory device - A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element. | 2010-05-27 |
20100127359 | Die-To-Die Power Consumption Optimization - Power consumption of electronic components is reduced, particularly in a multi-chip package. Embodiments reduce parasitic capacitance of a semiconductor chip by reducing ESD protection circuitry that is not needed during operation of the package. ESD protection circuitry would be operational during production and/or testing of the chip, but some circuitry would be disabled or removed prior to normal operation of the multi-chip package. | 2010-05-27 |
20100127360 | Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die - A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections. | 2010-05-27 |
20100127361 | ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR - A method of manufacturing a semiconductor package system including: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer. | 2010-05-27 |
20100127362 | SEMICONDUCTOR PACKAGE HAVING ISOLATED INNER LEAD - A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip. A jumping wire electrically connecting the isolated inner lead and the external lead is adjacent to the second side to achieve the redistribution of pin assignments without affecting wire-bonding. Especially, this package can be applied for multi-chip stacking. | 2010-05-27 |
20100127363 | Very extremely thin semiconductor package - A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. | 2010-05-27 |
20100127364 | SEMICONDUCTOR DEVICE AND HEAT RADIATION MEMBER - A semiconductor device includes a semiconductor element mounted on a substrate; at least one electronic part arranged around the semiconductor element; and a heat radiation member bonded to a backside of the semiconductor element by a bonding material. The heat radiation member has an isolation part extending between an outer circumference of the semiconductor element and the electronic part. | 2010-05-27 |
20100127365 | LEADFRAME-BASED CHIP SCALE SEMICONDUCTOR PACKAGES - Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages comprise a leadframe supporting a die that contains a discrete device. The chip scale semiconductor device also contains and an interconnect structure that also serves as a land for the package. The leadframe contains a topset feature adjacent a die attach pad supporting the die, a configuration which provides a connection to the interconnect structure as well as the backside of the die. This leadframe configuration provides a maximum die size to be used in the chip scale semiconductor packages while allowing them to be used in low power and ultra-portable electronic devices. Other embodiments are described. | 2010-05-27 |
20100127366 | Integrated Leadframe And Bezel Structure And Device Formed From Same - An integrated leadframe and bezel structure includes a planar carrier frame, a plurality of bonding leads, a die pad region, and a bezel structure. The bezel structure includes a bending portion shaped and disposed to facilitate a portion of said bezel structure being bent out of the plane of said carrier frame. A sensor IC may be secured to the die pad region, and wire bonds made to permit external connection to the sensor IC. The bezel structure includes portions which are bent such that their upper extent is in or above a sensing surface. The assembly is encapsulated, exposing on the top surface part of the bezel portions and the upper surface of the sensor IC, and on the bottom surface the contact pads. Two or more bezel portions may be provided, one or more on each side of the sensor IC. | 2010-05-27 |
20100127367 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including a circuit substrate, a chip, a B-staged adhesive layer, a leadframe, a number of first bonding wires, a number of second bonding wires, and a number of third bonding wires. The chip is disposed on the circuit substrate. The B-staged adhesive layer is disposed on the circuit substrate. The leadframe is disposed on the circuit substrate and includes a number of leads. Portions of the leads are embedded in the B-staged adhesive layer, and an end of each of the leads is exposed by the B-staged adhesive layer. The first bonding wires are electrically connected between the chip and the circuit substrate. The second bonding wires are electrically connected between the chip and the leads. The third bonding wires are electrically connected between the leads and the circuit substrate. In addition, a manufacturing method of a chip package is also provided. | 2010-05-27 |
20100127368 | LEAD FRAME - A lead frame includes a plurality of units arranged in a matrix manner. Each unit has an external frame defining an accommodation area, a die mount pad disposed in the accommodation area of the external frame, a plurality of leads connected with the external frame and arranged around the die mount pad, a short bar having two ends respectively electrically connected with the die mount pad and one of the leads, and a plurality of support bars each having a straight section connected with the external frame, and a continuous curved section connected with the die mount pad. By means of the continuous curved sections of the support bars, thermal deformation and/or displacement of the lead frame can be prevented. | 2010-05-27 |
20100127369 | LEAD FRAME, METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE - A lead frame includes a lead frame body | 2010-05-27 |
20100127370 | WIRING BOARD, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR ELEMENT - On a semiconductor element loading face, wiring patterns are drawn out from those formed in the vicinity of the edge of the semiconductor element of the loading pads formed to correspond to the electrode terminals of the semiconductor element, and connected to via pads formed in the vicinity of the edge of the semiconductor element loading face; area pads constructed of the loading pads corresponding to the electrode terminals formed in the central region of the semiconductor element and its vicinity are electrically connected to external connecting terminal pads formed in the central region on the other side of the wiring board and its vicinity, through the nearest area pad vias encircled by the external connecting terminal pads and passing through the wiring board and the wiring patterns; and a plurality of the loading pads constituting the area pads commonly use one of the area pad vias. | 2010-05-27 |
20100127371 | POWER SEMICONDUCTOR MODULE WITH SEGMENTED BASE PLATE - A power semiconductor module with segmented base plate. One embodiment provides a semiconductor module including a base plate and at least two circuit carriers. The base plate includes at least two base plate segments spaced distant from one another. Each of the circuit carriers includes a ceramic substrate provided with at least a first metallization layer. Each of the circuit carriers is arranged on exactly one of the base plate segments. At least two of the circuit carriers are spaced distant from one another. | 2010-05-27 |
20100127372 | SEMICONDUCTOR PACKAGES - A semiconductor package comprising a first semiconductor sub-package ( | 2010-05-27 |
20100127373 | Package structure - A package structure includes a first semiconductor package with at least one mount portion recessed from a first surface of the first semiconductor package toward a second surface of the first semiconductor package, the first and second surfaces facing each other. The first semiconductor package at least partially surrounds a second semiconductor package and is spaced apart therefrom via a material layer. | 2010-05-27 |
20100127374 | Multi-stack semiconductor package, semiconductor module and electronic signal processing system including thereof - Multi-stack semiconductor packages and application technologies are provided. The multi-stack semiconductor package may include stacked semiconductor packages which may include a topmost semiconductor package and a bottommost semiconductor package. Each of the unit semiconductor packages may include a substrate, a semiconductor chip formed on the substrate, a molding material filled around the semiconductor chip on the substrate, and an adhesive layer formed on the semiconductor chip and the molding material. The semiconductor chip and the substrate of a semiconductor package may each include conductive vias providing an electrical connection between the semiconductor packages. The substrate of the upper semiconductor package stacked in an upper portion may be directly adhered onto the adhesive layer of the lower semiconductor package stacked in a lower portion. | 2010-05-27 |
20100127375 | WAFER LEVEL CHIP SCALE SEMICONDUCTOR PACKAGES - Wafer-level chip scale (WLCSP) semiconductor packages and methods for making and using the same are described. The WLCSP semiconductor packages contain a grid array of land pads rather than solder balls or solder bumps. The land pads can be provided directly on a semiconductor wafer by using a leadframe interconnect structure that has been formed from a leadframe. The land pads can be used to mount the WLCSP to a circuit board. Such a configuration allows the formation of a thinner chip scale semiconductor package using a simpler manufacturing process, thereby reducing costs and improving performance. Other embodiments are described. | 2010-05-27 |
20100127376 | SYSTEM AND METHOD TO PROVIDE RF SHIELDING FOR A MEMS MICROPHONE PACKAGE - A semiconductor package has a substrate. An opening is formed through the substrate. A first RF shield is formed around a perimeter of the opening. A first die is attached to the first surface of the substrate and positioned over the opening. | 2010-05-27 |
20100127377 | Method for Producing a MEMS Package - A carrier substrate has a mounting location with a number of electrical connection pads on a top side and external contacts connected thereto on an underside. A metal frame encloses the connection pads of the mounting location. A MEMS chip has electrical contacts on an underside. The MEMS chip is placed on the mounting location of the carrier substrate in such a way that the MEMS chip is seated with an edge region of its underside on the metal frame. Using a flip-chip process, the electrical contacts of the MEMS chip are connected to the connection pads of the carrier substrate by means of bumps the metal frame is connected to the MEMS chip such that a closed cavity is formed between MEMS chip and carrier substrate. | 2010-05-27 |
20100127378 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - There is provided a semiconductor device including: plural bit cells each including the same circuit; plural electrodes supplied with power from outside, wherein each of the respective plural electrodes is mounted above the same circuit within the plural bit cells. Further, there is provided a semiconductor package including: the semiconductor device; a substrate mounted with the semiconductor device; an external input terminal formed on the substrate; an external output terminal formed on the substrate; an input wiring pattern connecting the semiconductor device mounted above the substrate and the external input terminal; an output wiring pattern connecting the semiconductor device mounted above the substrate and the external output terminal; and plural power supply lines, arranged without contact with each other on the same face of the substrate, and connecting the plural electrodes mounted to the semiconductor device to the corresponding electrode from the plural external power input electrodes. | 2010-05-27 |
20100127379 | Power Semiconductor Module with Control Functionality and Integrated Transformer - A power semiconductor module comprising: a substrate, a plurality of conductor tracks arranged thereon, the conductor tracks being electrically insulated from one another, and including power semiconductor components arranged thereon; a connecting device, composed of an alternating layer sequence of at least two electrically conductive layers and at least one electrically insulating layer disposed therebetween, for the circuit-conforming connection of the power semiconductor components, the conductor tracks and/or external contact devices. The electrically conductive layers form connecting tracks and at least one transformer is formed integrally with, and thus from the constituent parts of, the connecting device. The transformer is composed of at least one transmitter coil and at least one receiver coil, which are in each case arranged coaxially with respect to one another and are formed with spiral windings. | 2010-05-27 |
20100127380 | LEADFRAME FREE LEADLESS ARRAY SEMICONDUCTOR PACKAGES - Leadframe-free semiconductor packages and methods for making and using the same are described. The semiconductor packages contain an interconnect structure comprising an array of land pads. The interconnect structure is formed from and routed using a printable or wirebondable conductive material and is not formed using any etching procedure. A solderable mask covers the interconnect structure except for the land pads. A die containing an integrated circuit device is connected to the interconnect structure by either a wirebonding process or by a flipchip process. The land pad arrays can contain a solder connector, such as a solder ball or bump, that can be used to connect the semiconductor package to a printed circuit board. Other embodiments are described. | 2010-05-27 |
20100127381 | Integrated Circuit Devices Having Printed Circuit Boards Therein With Staggered Bond Fingers That Support Improved Electrical Isolation - An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangement of first and second electrically conductive bond fingers. These first and second bond fingers are elevated at first and second different heights, respectively, relative to the plurality of electrically conductive pads. The printed circuit board also includes a first plurality of electrically insulating pedestals supporting respective ones of the first electrically conductive bond fingers at elevated heights relative to the second electrically conductive bond fingers. First and second pluralities of electrical interconnects (e.g., wires, beam leads) are also provided. The first plurality of electrical interconnects operate to electrically connect first ones of the plurality of electrically conductive pads to respective ones of the first electrically conductive bond fingers. The second plurality of electrical interconnects electrically connect second ones of the plurality of electrically conductive pads to respective ones of the second electrically conductive bond fingers. | 2010-05-27 |
20100127382 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor carrier with a top surface on which a plurality of electrodes are disposed; and a semiconductor element electrically connected through a plurality of bump electrodes to the plurality of associated electrodes. The plurality of electrodes are substantially uniformly spaced. | 2010-05-27 |
20100127383 | POWER SEMICONDUCTOR MODULE - In the power semiconductor module, a wiring metal plate electrically connects between power semiconductor elements joined to the circuit pattern, and between the power semiconductor elements and the circuit pattern. Cylindrical main terminals are joined, substantially perpendicularly, to the wiring metal plate and the circuit pattern, respectively. A cylindrical control terminal is joined, substantially perpendicularly, to one of the power semiconductor elements. | 2010-05-27 |
20100127384 | Semiconductor device and connection checking method for semiconductor device - Provided is a semiconductor device in which a connection between connection terminals and land of the semiconductor device can be checked with the semiconductor device kept in a sound condition, the connection not being allowed to be checked with a semiconductor chip. The semiconductor device of the present invention includes: a package substrate; a semiconductor chip mounted on the package substrate; a first land formed in a first principal surface of the package substrate; a second land formed in a second principal surface of the package substrate; first connection terminals connected to the second land and having the connection thereto not allowed to be checked with the semiconductor chip; a connection interconnection for connecting the first land and the second land; a second connection terminal formed in the second principal surface of the package substrate; and a branch interconnection for connecting the connection interconnection and the second connection terminal. | 2010-05-27 |
20100127385 | METHOD FOR MANUFACTURING AN ELEMENT HAVING ELECTRICALLY CONDUCTIVE MEMBERS FOR APPLICATION IN A MICROELECTRONIC PACKAGE - A microelectronic package ( | 2010-05-27 |
20100127386 | DEVICE INCLUDING A SEMICONDUCTOR CHIP - A device including a semiconductor chip. One embodiment provides a device, including a metal layer having a first layer face. A semiconductor chip includes a first chip face. The semiconductor chip is electrically coupled to and placed over the metal layer with the first chip face facing the first layer face. An encapsulation material covers the first layer face and the semiconductor chip. At least one through-hole extends from the first layer face through the encapsulation material. The at least one through-hole is accessible from outside the device. | 2010-05-27 |
20100127387 | POWER SEMICONDUCTOR MODULE | 2010-05-27 |
20100127388 | METAL INJECTION MOLDED HEAT DISSIPATION DEVICE - A heat dissipation device is provided. The heat dissipation device includes an integrated heat spreader and a base plate coupled to the integrated heat spreader, wherein tile base plate comprises a plurality of metal pellets to dissipate heat from the integrated heat spreader. | 2010-05-27 |
20100127389 | POWER SEMICONDUCTOR MODULE - The power semiconductor module includes: a circuit substrate; power semiconductor elements joined to element mounting portions of the wiring pattern on the circuit substrate; the cylindrical external terminal communication section joined to the wiring pattern; circuit forming means for connecting between portions that require electrical connection therebetween; and transfer molding resin for sealing these components. The cylindrical external terminal communication section is a metal cylinder, and the cylindrical external terminal communication section has a hole filled with gel. | 2010-05-27 |
20100127390 | Cooling Structures and Methods - Cooling structures and methods, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a cooling structure for a semiconductor device includes at least one channel defined between a first workpiece and a second workpiece. The second workpiece is bonded to the first workpiece. The at least one channel is adapted to retain a fluid. | 2010-05-27 |
20100127391 | FIXTURE FOR SEMICONDUCTOR DEVICE AND ASSEMBLY OF SEMICONDUCTOR DEVICE - A pressing portion of a fixture is put on a lid of a semiconductor package, and anchor portions on the opposite sides of the pressing portion are opposed to a baseplate. Two screw members are passed individually through opening parts formed spanning the pressing portion and anchor portions and threadedly engage with a heat sink through the baseplate. If the screw members are tightened in this state, the anchor portions are pressed by the baseplate, and the pressing portion presses the lid of the semiconductor package, whereby the baseplate is fixed to the heat sink in pressure contact with it. | 2010-05-27 |
20100127392 | Semiconductor die - A semiconductor die includes a semiconductor substrate, electrodes provided on the semiconductor substrate, an isolating layer provided on the electrodes, an upper protective layer provided on the electrodes and the isolating layer, pads provided on the upper protective layer and connectors inserted through the upper protective layer and used to connect the electrodes to the pads. The area of the pads is larger than that of the electrodes. | 2010-05-27 |
20100127393 | Electronic device and semiconductor device - An electronic device includes: a wiring board having first and second regions; a plurality of first lands in the first region; a plurality of second lands in the second region; and an insulator covering the wiring board. More heat is applied to the first region than the second region. The second land is smaller in volume than the first land. The insulator has a plurality of openings being adjacent to the plurality of first lands and the plurality of second lands. Each of the plurality of openings has substantially the same area. | 2010-05-27 |
20100127394 | THROUGH SUBSTRATE VIAS FOR BACK-SIDE INTERCONNECTIONS ON VERY THIN SEMICONDUCTOR WAFERS - Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming ( | 2010-05-27 |
20100127395 | METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY - Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer. | 2010-05-27 |
20100127396 | INTEGRATED CIRCUIT MODULE AND METHOD OF PACKAGING SAME - An integrated circuit (IC) module ( | 2010-05-27 |
20100127397 | Optoelectronic semiconductor device - An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer. | 2010-05-27 |
20100127398 | Wiring structure of a semiconductor device - In a wiring structure of a semiconductor device and a method of manufacturing the same, a wiring structure includes a contact pad, a contact plug, a spacer and an insulation interlayer pattern. The contact pad is electrically connected to a contact region of a substrate. The contact plug is provided on the contact pad and is electrically connected to the contact pad. The spacer faces an upper side surface of the contact pad and sidewalls of the contact plug. The insulation interlayer pattern has an opening, the contact plug and the spacer being provided in the opening. The spacer of the wiring structure may prevent the contact pad from being damaged by a cleaning solution while forming a contact plug to be connected to a capacitor. | 2010-05-27 |
20100127399 | WIRING STRUCTURE BETWEEN STEPS AND WIRING METHOD THEREOF - In a wiring structure between steps in which a step portion is covered by an insulating slope formed by providing and drying droplets of an insulating ink in which an insulating material is dispersed in a dispersion medium and a wiring line formed by drying and firing provided droplets of a conductive ink in which a conductive material is dispersed in a dispersion medium is laid out between the steps and passes on a top surface of the insulating slope, the structure includes a liquid repellent layer formed of a liquid repellent material repelling the dispersion medium in the insulating ink, and a plurality of dot lines including a plurality of dots that is formed by hardening arranged droplets of a resin ink including a resin material. In the structure, the liquid repellent layer covers a surface including the step portion where the wiring line to be laid out. The droplets for forming the dot lines are arranged on a surface of the liquid repellent layer so as not to contact with each other in a region partitioned by a side serving as a start point and a side serving as an end point in a direction in which the wiring line is laid out. The insulating slope is formed by drying the droplets of the insulating ink provided to the step portion so as to connect the plurality of dot lines. | 2010-05-27 |
20100127400 | SEMICONDUCTOR MODULE AND PROCESS FOR ITS FABRICATION - A semiconductor module is disclosed, including a substrate and at least one semiconductor component in bottom contact with the substrate. The semiconductor component including a main current branch sandwiched between the bottom and top of the semiconductor component. The side edges of a barrier layer zone coincide with the side edge portions of the semiconductor component between the top and the bottom. The space above the substrate and to the side of the semiconductor component is packed with an insulating compound at least up to the level of the top of the semiconductor component. Topping the semiconductor component and parallel thereto is a patterned or unpatterned metallization connected to a contact pad on the top of the semiconductor component. | 2010-05-27 |
20100127401 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device. The semiconductor device includes a circuit part, a pad metal aligned over the circuit part to electrically connect the circuit part, and a metal layer interposed between the pad metal and the circuit part to electrically connect the pad metal to the circuit part. A buffer layer including an insulating layer with metal patterns having a slit shape formed therein is formed within the metal layer. | 2010-05-27 |
20100127402 | Interconnect System without Through-Holes - Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations. | 2010-05-27 |
20100127403 | SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND SEMICONDUCTOR APPARATUS - There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning. | 2010-05-27 |
20100127404 | SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor device, insulation resistance of the porous film is stabilized, and leakage current between adjacent interconnects provides an improved reliability in signal propagation therethrough. The method includes: sequentially forming over a semiconductor substrate a porous film and a patterned resist film; forming a concave exposed surface of the substrate; forming a non-porous film covering the interior wall of the concave portion and the porous film; selectively removing the non-porous film from the bottom of the concave portion and the non-porous film by anisotropic etch; forming a barrier metal film covering the porous film and the interior wall; and forming a metallic film on the barrier metal film to fill the concave portion. The anisotropic etch process uses an etching gas with mixing ratio MR, 45≦MR≦100, where MR=((gaseous “nitrogen” containing compound)+(inert gas))/(gaseous “fluorine” containing compound). | 2010-05-27 |
20100127405 | WIRING BOAD, SEMICONDUCTOR DEVICE IN WHICH WIRING BOARD IS USED, AND METHOD FOR MANUFATURING THE SAME - A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer. | 2010-05-27 |
20100127406 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: plural first output pads formed along one edge of an outer periphery of a substrate; plural second output pads formed along at least one of an edge at an opposite side of the substrate from the one edge, and an edge adjoining the one edge; plural internal circuits, each of which is provided with an output terminal connected with an output pad of one of the first output pads and the second output pads; plural first lines, each of which connects one of the output terminals of the internal circuits with one of the plurality of first output pads; and plural second lines, each of which connects one of the output terminals of the internal circuits with one of the plural second output pads, resistance values per unit of wiring length being lower in the second lines than in the first lines. | 2010-05-27 |
20100127407 | Two-sided substrateless multichip module and method of manufacturing same - A two-sided substrateless multichip module including at least one die layer having at least one die. At least one bottomside interconnect layer is coupled to a bottom surface of the at least one die. At least one topside interconnect layer is coupled to a top surface of the at least one die. One or more embedded electrical connections is configured to provide an electrical interconnection between the at least one bottomside interconnect layer and the at least one die and/or the at least bottomside interconnect layer and the at least one topside interconnect layer and/or the at least one topside interconnect layer and the at least one die, wherein the at least one bottomside interconnect layer includes one or more electrical contacts on a bottom surface of the multichip module and the at least topside interconnect layer includes one or more electrical contacts on a top surface of the multichip module. | 2010-05-27 |
20100127408 | BONDING PAD STRUCTURE FOR BACK ILLUMINATED OPTOELECTRONIC DEVICE AND FABRICATING METHOD THEREOF - A bonding pad structure for an optoelectronic device. The bonding pad structure comprises a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same. | 2010-05-27 |
20100127409 | MICROELECTRONIC DEVICE WAFERS INCLUDING AN IN-SITU MOLDED ADHESIVE, MOLDS FOR IN-SITU MOLDING ADHESIVES ON MICROELECTRONIC DEVICE WAFERS, AND METHODS OF MOLDING ADHESIVES ON MICROELECTRONIC DEVICE WAFERS - A microelectronic device wafer includes an adhesive molded in-situ on the wafer. Adhesives and wafers are positioned in molds and a method that includes drawing in the molds at least a partial vacuum and partially curing the adhesive provides an in-situ molded adhesive that is positioned on the wafer. The adhesives can be in liquid, solid, or other forms prior to molding. During molding, the adhesive can be partially cured by heating or irradiating. | 2010-05-27 |
20100127410 | METHOD AND DEVICE FOR THE METERED RELEASE OF IRRITANTS - The invention relates to a method and a device for the metered release of irritants by means of a propellant and/or solvent gas in anti-people defense rooms. The invention describes a method and a device for a metering controller for releasing irritants by means of a propellant and/or solvent gas in anti-people defense rooms while complying with health limits. After a first dose (T | 2010-05-27 |
20100127411 | METHOD OF MANUFACTURING OPTICAL MEMBER, METHOD OF MANUFACTURING PLASTIC LENS, GASKET FOR MOLDING PLASTIC LENS, AND JIG FOR CASTING MONOMER - A method of manufacturing an optical member by mixing isocyanate terminal prepolymer component (A) and aromatic diamine component (B), and immediately after mixing, casting a mixture into a casting mold to obtain a molded article. A method of manufacturing a plastic lens by mixing said components (A) and (B), immediately after mixing, casting a mixture into a casting mold and polymerizing it to obtain a molded article. A gasket for molding plastic lenses comprised of a cylindrical member. A casting mold for molding plastic lenses using this gasket and a monomer casting jig. | 2010-05-27 |
20100127412 | METHOD AND APPARATUS FOR FABRICATING LENS MASTERS - A method and apparatus used for forming a lens master for forming lenses on a wafer. The method includes using an inverted lens pin mold in conjunction with a dispense method to create both concave and convex lens masters for making lens stamps containing lens-shaped cavities. The lens-shaped cavities are used to imprint a plurality of lenses into a curable material. | 2010-05-27 |
20100127413 | Method for Manufacturing Plastic Lens - A method for manufacturing a plastic lens includes: disposing a pair of plastic lens molding dies in such a way that the dies face each other and are spaced apart from each other by a predetermined distance; forming a frame between the pair of dies; injecting a polymerizable composition into the space surrounded by the frame and the pair of dies; and polymerizing the polymerizable composition in the space to form a plastic lens. | 2010-05-27 |
20100127414 | Nanoparticles for Delivery of Therapeutic Agents Using Ultrasound and Associated Methods - The present invention relates to lipid based nanoparticles or liposomes that are sensitive to ultrasonic energy, compositions containing these particles, methods for delivering one or more active agents using the particles, and methods for preparing the particles. The nanoparticles and liposomes encapsulate active agents such as chemotoxins, genes, virus vectors, proteins, peptides, antisense oligonucleotides, carbohydrates, and stem cells. The particles contain an aqueous core, at least one active agent located within the aqueous core, and a lipid bilayer or membrane that encapsulates the active agent within the aqueous core. The lipid bilayer may comprise a primary phospholipid and a lysolipid that preferably have different acyl chain lengths, making the lipid bilayer sensitive to ultrasound. Ultrasound may be used to track the particles as they move throughout the body. When the ultrasonic energy reaches a certain pressure, the lipid bilayer will break apart, releasing the active agent. | 2010-05-27 |
20100127415 | METHOD FOR PREPARING POLYUREA MICROCAPSULE CONTAINING SATURATED ALCOHOL DISPERSION MEDIUM, AND MICROCAPSULE PREPARED USING THE METHOD - Provided are a method for forming polyurea microcapsules containing a saturated alcohol as a dispersion medium, and microcapsules prepared using the method. According to the method, suspensions, in which microcapsules are dispersed in a saturated alcohol dispersion medium as a core material, may be used to prepare microcapsules. Diverse and fine color expression may be obtained from various response characteristics in the display applications. In addition to superior processibility, excellent thermal stability, solvent resistance, and chemical stability may be achieved by using polyurea in microcapsules as a wall material according to one embodiment of the present invention. | 2010-05-27 |
20100127416 | MANUFACTURING APPARATUS AND MANUFACTURING METHOD FOR SOLID PARTICLE - The apparatus for manufacturing solid particles at a nano level includes a chamber for isolation from an external space, a monoaxial rotary disk disposed in the chamber, a receiving surface at one end of the rotary disk, a material supply mechanism for supplying the material to the receiving surface, a rotary mechanism for applying a centrifugal force to the rotary disk so that the raw material supplied to the receiving surface is produced into a thin film and atomized and scattered from the outer peripheral edge, and a control mechanism for the temperature in the chamber that controls the temperature at least at the outer peripheral edge of the receiving surface and on the side nearer to the center of rotation to a temperature lower than a volatilization temperature of a volatile solvent and the temperature at the outer side therefrom to the volatilization temperature of the volatile solvent or higher. | 2010-05-27 |
20100127417 | Venting device - A venting device for venting a cavity of an injection mold via a venting opening of the injection mold which cavity can be filled with an injection molding material is provided. The venting device comprising a housing which has a through-opening and is designed and intended for an arrangement on an injection mold in such a way that air which is present in the cavity and which escapes from a venting opening of the injection mold when injection molding material is introduced into the cavity can exhaust through the through-opening of the housing into an exterior space surrounding the injection mold. A valve pin extending longitudinally along a direction of extent and being mounted in the housing movably along its direction of extent. The valve pin is designed for being moved from a venting position, in the direction of the cavity into a first cleaning position. | 2010-05-27 |
20100127418 | Methods For Continuous Firing Of Shaped Bodies And Roller Hearth Furnaces Therefor - The present disclosure relates to methods and apparatuses for continuous firing of shaped bodies in one cycle, in particular a continuous method for heat treatment and/or control oxidation of shaped bodies by passing them through a roller hearth furnace on furnace trays. | 2010-05-27 |
20100127419 | CERAMIC HONEYCOMB EXTRUSION METHOD AND APPARATUS - Honeycomb shapes are extruded from plasticized ceramic powder mixtures by methods that include reducing the core temperature of the charge of the plasticized mixture during transit through the extruder, such methods being carried out utilizing apparatus comprising twin-screw extruders incorporating actively cooled screw elements, whereby temperature-conditioned charges of plasticized material that exhibit reduced core-to-periphery temperature differentials are delivered for extrusion. | 2010-05-27 |
20100127420 | METHOD OF FORMING A SHAPED ARTICLE FROM A SHEET OF MATERIAL - An apparatus for forming a shaped article having a first surface with a first surface profile and a second surface with a second surface profile is provided. The apparatus includes a first end mold having a cavity formed therein, where the cavity is defined by a surface having at least a portion of the first surface profile. The apparatus includes an intermediate mold having a hole formed therein. The intermediate mold is distinct from the first end mold and is configured for stacking against the first end mold such that the hole is aligned with the cavity. The apparatus includes a second end mold having a protuberance formed on a surface thereof. The protuberance is defined by a surface having at least a portion of the second surface profile and is sized for insertion into the hole and cavity. | 2010-05-27 |
20100127421 | BI-DIRECTIONAL FLOW FOR PROCESSING SHAPED BODIES - Disclosed herein are methods of making shaped bodies, such as carbon-based, inorganic cement, or ceramic bodies. Methods disclosed herein may comprise applying a bidirectional gas flow to at least one heat treatment and/or controlled oxidation step. Also disclosed herein are methods of making shaped bodies comprising a single-step controlled oxidation firing process. Further disclosed herein are shaped bodies made by a process comprising applying a bi-directional gas flow to at least one heat treatment and/or controlled oxidation step, and shaped bodies made by a single-step controlled oxidation firing process. Further disclosed herein is a bidirectional gas flow furnace for the heat treatment and/or the controlled oxidation of a shaped body. | 2010-05-27 |
20100127422 | METHOD FOR THE DIRECT AND CONTINUOUS MANUFACTURE OF POLYESTER MOULDED BODIES WITH LOW ACETALDEHYDE CONTENT - The invention relates to a continuous method for the direct production of multilayer mold bodies from a highly condensed polyester melt. | 2010-05-27 |
20100127423 | FERRITE POWDER AND ITS PRODUCTION METHOD - On producing a ferrite sintered body, there is used a ferrite powder having a median diameter D | 2010-05-27 |
20100127424 | Fabrication of metal meshes/carbon nanotubes/polymer composite bipolar plates for fuel cell - A reinforced mesh structure containing bipolar plate for a polymer electrolyte membrane fuel cell (PEMFC) is prepared as follows: a) compounding vinyl ester and graphite powder to form bulk molding compound (BMC) material, the graphite powder content ranging from 60 wt % to 95 wt % based on the total weight of the graphite powder and vinyl ester, wherein 0.05-10 wt % reactive carbon nanotubes modified by acyl chlorination-amidization reaction, based on the weight of the vinyl ester resin, are added during the compounding; b) molding the BMC material from step a) with a metallic net being embedded in the molded BMC material to form a bipolar plates having a desired shaped at 80-200° C. and 500-4000 psi. | 2010-05-27 |
20100127425 | Process of and Apparatus for Making a Shingle, and Shingle Made Thereby - A process and apparatus for making a shingle, together with the shingle made thereby, is provided, in which one or more thermoplastic materials are extruded or co-extruded to form an extrudate, with the extrudate being cut into a preliminary shingle shape, which is allowed to dissipate heat, and then is delivered to a compression mold, wherein the preliminary shingle shape is compression molded to substantially its final dimensions and is then discharged from the mold and allowed to cool. | 2010-05-27 |
20100127426 | FLUOROTELOMER/SILANE COMPOSITIONS - A composition and its use as a mold release composition are disclosed. The composition comprises a fluorotelomer, which comprises repeat units derived from a fluoroalkene, and optionally a comonomer, and has an endgroup derived from an alcohol, an alcohol derivative, or a combination thereof, and said fluorotelomer has or comprises a structure depicted as H(CX | 2010-05-27 |
20100127427 | PREFORMS AND METHODS OF MAKING THE SAME - A method for making a preform includes creating a pressure differential between an inside and an outside of a perforated shape memory polymer mandrel in its temporary shape. The pressure differential is such that pressure outside the perforated shape memory polymer mandrel is greater than pressure inside the perforated shape memory polymer mandrel. The perforated shape memory polymer mandrel has i) a predetermined preform shape as the temporary shape and ii) a shrunken shape as its permanent shape, wherein the shrunken shape is configured such that it is removable from the predetermined preform shape. The method further includes depositing, as the pressure differential is maintained, at least one material onto a surface of the perforated shape memory polymer mandrel. The at least one material is set in the predetermined preform shape, thereby forming the preform. | 2010-05-27 |