21st week of 2022 patent applcation highlights part 59 |
Patent application number | Title | Published |
20220165703 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. | 2022-05-26 |
20220165704 | DEVICE MANUFACTURING METHOD AND LIGHT EMITTING DEVICE - A device manufacturing method includes: applying a bonding material in a predetermined position on a mounting face of a base by dispensing the bonding material through a nozzle of a bonding machine, in which an outline of a leading end face of the nozzle defines an area of at least 75% of a bonding face of a component to be mounted, so that the bonding material applied onto the mounting face has an outline that at least partially extends beyond a shape of the bonding face; and bonding the bonding face in the predetermined position on the mounting face by placing and pressing the component onto the base via the bonding material so that at least a portion of the bonding material interposed between the mounting face of the base and the bonding face of the component flows out beyond the bonding face of the component. | 2022-05-26 |
20220165705 | MICROELECTRONICS PACKAGE WITH ENHANCED THERMAL DISSIPATION - A semiconductor package system is disclosed. The system includes a first interposer and a first integrated circuit die electrically coupled and thermally coupled to a first side of the first interposer. The system further includes a second integrated circuit die electrically coupled and thermally coupled to a second side of the first interposer. The system further includes a ring carrier electrically coupled and thermally coupled to the first interposer. The ring carrier is configured to transmit an input to the first interposer. In some embodiments, the system further includes at least one thermal spreader thermally coupled to the ring carrier and at least one of the first integrated circuit, the second integrated circuit, or the first interposer. | 2022-05-26 |
20220165706 | SEMICONDUCTOR STRUCTURE OF CELL ARRAY - Semiconductor structures are provided. A semiconductor structure includes a cell array. The cell array includes a plurality of first cells arranged in a first column, a plurality of second cells arranged in a second column abutting the first column and a third cell arranged in the first column. Each first cell has a first cell height and is configured to perform a first function. Each second cell has a second cell height and is configured to perform a second function. The third cell has a third cell height and is configured to perform a third function. Each second cell is coupled to and in contact with a respective first cell. The second cell height is greater than the first cell height, and the number of first cells is equal to the number of second cells. The third cell height is proportional to the first cell height. | 2022-05-26 |
20220165707 | INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING FRONT SIDE BACK-END-OF-LINE (FS-BEOL) TO BACK SIDE BACK-END-OF-LINE (BS-BEOL) STACKING FOR THREE-DIMENSIONAL (3D) DIE STACKING, AND RELATED FABRICATION METHODS - Integrated circuit (IC) packages employing front side back-end-of-line (FS-BEOL) to back side back-end-of-line (BS-BEOL) stacking for three-dimensional (3D) die stacking. To facilitate providing additional electrical routing paths for die-to-die interconnections between stacked IC dice in the IC package, a BS-BEOL metallization structure of a first die of the stacked dice of the IC package is stacked adjacent to a FS-BEOL metallization structure of a second die of the stacked IC dice. Electrical routing paths for die-to-die interconnections between the stacked IC dice are provided from the BS-BEOL metallization structure of the first die to the FS-BEOL metallization structure of the second die. It may be more feasible to form shorter electrical routing paths in the thinner BS-BEOL metallization structure than in a FS-BEM metallization structure for lower-resistance and/or lower-capacitance die-to-die interconnections for faster and/or compatible performance of semiconductor devices in the IC dice. | 2022-05-26 |
20220165708 | SEMICONDUCTOR ASSEMBLIES WITH HYBRID FANOUTS AND ASSOCIATED METHODS AND SYSTEMS - Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board. | 2022-05-26 |
20220165709 | STACKED SEMICONDUCTOR PACKAGE AND PACKAGING METHOD THEREOF - A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package. | 2022-05-26 |
20220165710 | IMAGE SENSING DEVICE - An image sensing device includes a first pixel array and a second pixel array. The first pixel array includes a plurality of first unit pixels consecutively arranged to generate a first pixel signal through a photoelectric conversion of incident light. The second pixel array is disposed below the first pixel array, and includes a plurality of second unit pixels consecutively arranged to generate a second pixel signal through a photoelectric conversion of the incident light. The first unit pixels are arranged to have a uniform spacing between adjacent first unit pixels in the first pixel array. The second unit pixels are arranged so that spacing between adjacent second unit pixels are not the same in the second pixel array. | 2022-05-26 |
20220165711 | METHOD OF MANUFACTURING DIE STACK STRUCTURE - A method of manufacturing a die stack structure includes the following steps. A first bonding structure is formed over a front side of a first die. The method of forming the first bonding structure includes the following steps. A first bonding dielectric material is formed on a first test pad of the first die. A first blocking layer is formed over the first bonding dielectric material. A second bonding dielectric material and a first dummy metal layer are formed over the first blocking layer. The first dummy metal layer and the first test pad are electrically isolated from each other by the first blocking layer. Thereafter, a second bonding structure is formed over a front side of a second die. The first die and the second die are bonded through the first bonding structure and the second bonding structure. | 2022-05-26 |
20220165712 | POWER MODULE - A power module includes three switching elements including a third switching element, a second switching element, and a third switching element. Each of the switching elements includes two positive electrode terminals including a third positive electrode terminal and a second positive electrode terminal, which are connected to a drain electrode. Each of the switching elements includes one negative electrode terminal including a negative electrode terminal connected to a source electrode. In the power module, a total number of the positive electrode terminals and the negative electrode terminals is three. | 2022-05-26 |
20220165713 | STACKED LIGHT EMITTING DIODE (LED) DISPLAY - Embodiments of the present disclosure include apparatuses and method for a stacked light emitting diode (LED) display. A stacked LED display can include a first array of LEDs that are configured to emit red light, a second array of LEDs that are configured to emit green light, and a third array of LEDs that are configured to emit blue light. The stacked LED hologram display can include a number of actuators configured to adjust a position of a first array of LEDs in a first direction and a second direction orthogonal to the first direction, adjust a position of a second array of LEDs in the first direction and the second direction, and adjust a position of a third array of LEDs in the first direction and the second direction to control the packing scheme of the LEDs. | 2022-05-26 |
20220165714 | STACKED LIGHT EMITTING DIODE (LED) HOLOGRAM DISPLAY - Embodiments of the present disclosure include apparatuses and method for a stacked light emitting diode (LED) hologram display. A stacked LED hologram display can include a first array of LEDs that are configured to emit red light received by a meta-optics panel configured to display a first portion of a holographic image, a second array of LEDs that are configured to emit green light received by a meta-optics panel configured to display a second portion of a holographic image, and a third array of LEDs that are configured to emit blue light received by a meta-optics panel configured to display a third portion of a holographic image. The stacked LED hologram display can include a number of actuators configured to adjust a position of a first array of LEDs in first direction and a second direction, adjust a position of a second array of LEDs in the first direction and the second direction, and adjust a position of a third array of LEDs in the first direction and the second direction. | 2022-05-26 |
20220165715 | LIGHT-EMITTING COMPONENT AND DISPLAY DEVICE COMPRISING THE SAME - The invention relates to a light-emitting component comprising a light-emitting semiconductor chip, a transparent conductive layer, and at least two electrical connection points, wherein the transparent conductive layer covers the light-emitting semiconductor chip at least in places, and the electrical connection points are arranged on a side of the light-emitting semiconductor chip facing away from the transparent conductive layer. | 2022-05-26 |
20220165716 | DISPLAY DEVICE - According to an aspect of the present disclosure, the display device includes: a stretchable lower substrate and a plurality of first substrates disposed on the lower substrate. The display device also includes a plurality of second substrates coupling first substrates adjacent to each other among the plurality of first substrates. The display device further includes a plurality of pixels disposed on the plurality of first substrates. The display device also includes a plurality of connection lines disposed on the plurality of second substrates and coupling the plurality of pixels. The display device further includes a protection layer disposed on each of the plurality of pixels. | 2022-05-26 |
20220165717 | TILED DISPLAY FOR OPTOELECTRONIC SYSTEM - The present invention discloses structures and methods for making tiled displays for optoelectronic systems. | 2022-05-26 |
20220165718 | LIGHT EMITTING DIODE FOR DISPLAY AND DISPLAY APPARATUS HAVING THE SAME - A light emitting diode stack for a display including a first LED stack, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, and a conductive growth substrate coupled to at least one of the second LED stack and the third LED stack, in which light generated from the first LED stack is configured to be emitted to the outside of the light emitting diode stack through the second LED stack, the third LED stack, and the conductive growth substrate, and light generated from the second LED stack is configured to be emitted to the outside of the light emitting diode stack through the third LED stack and the conductive growth substrate. | 2022-05-26 |
20220165719 | SEMICONDUCTOR DEVICE - A semiconductor device includes a support member, a first switching element, a second switching element, a first passive element, a second passive element, and an electrical conductor. The support member includes a plurality of wiring parts, and the plurality of wiring parts include a first wiring section and a second wiring section spaced apart from each other in a first direction perpendicular to the thickness direction of the support member. The first switching element is electrically connected to the first wiring section. The second switching element is electrically connected to the first switching element and the second wiring section. The first passive element has a first electrode and a second electrode, and the first electrode is bonded to the first wiring section. The second passive element has a third electrode and a fourth electrode, and the fourth electrode is bonded to the second wiring section. The electrical conductor connects the second electrode and the third electrode to each other. At least one of the first passive element and the second passive element is a capacitor. | 2022-05-26 |
20220165720 | STRETCHABLE DISPLAY DEVICE - According to an aspect of the present disclosure, the display device includes a stretchable lower substrate and a plurality of first substrates disposed on the lower substrate and in which pixels are disposed. The display device also includes a plurality of second substrates connecting first substrates adjacent to each other among the plurality of first substrates. The display device further includes a plurality of connection lines disposed on the plurality of second substrates and connecting the pixels. | 2022-05-26 |
20220165721 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network. | 2022-05-26 |
20220165722 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body. | 2022-05-26 |
20220165723 | LAYOUT STRUCTURE - Provided is a layout structure adapted for a signal format converter. The layout structure includes a first and a second capacitor array. The first capacitor array is disposed on one side of a reference axis, and includes multiple first capacitor units that form multiple first capacitors. The first capacitors respectively have multiple first capacitances. The second capacitor array is disposed on the other side of the reference axis, and includes multiple second capacitor units that form multiple second capacitors. The second capacitors respectively have multiple second capacitances. The first capacitors respectively correspond to the second capacitors. Each first capacitor and each corresponding second capacitor are symmetrical with respect to the reference axis, or each first capacitor and each corresponding second capacitor are separated from each other by the same distance. Each first capacitor and each corresponding second capacitor have the same capacitance. | 2022-05-26 |
20220165724 | SEMICONDUCTOR DEVICE HAVING WELL CONTACT DIFFUSION REGION SUPPLYING WELL POTENTIAL - Disclosed herein is an apparatus that includes: a first diffusion region extending in a first direction; second diffusion regions arranged in the first direction; a first metallic line overlapping with the first diffusion region; second metallic lines each overlapping with an associated one of the second diffusion regions; a third metallic line overlapping with the first and second metallic lines; first contact plugs connecting the first metallic line to the first diffusion region; second contact plugs each electrically connecting an associated one of the second metallic lines to an associated one of the second diffusion regions; and third contact plugs each electrically connecting the third metallic line to an associated one of the second metallic lines. | 2022-05-26 |
20220165725 | High Voltage ESD Protection Apparatus - A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well. | 2022-05-26 |
20220165726 | ELECTRONIC DEVICE - The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a variable capacitor. The transistor is disposed on the substrate. The variable capacitor is disposed on the substrate and adjacent to the transistor. A material of the transistor and a material of the variable capacitor both a include a III-V semiconductor material. The electronic device of an embodiment of the disclosure may simplify manufacturing process, reduce costs, or reduce dimensions. | 2022-05-26 |
20220165727 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A built-in resistor electrically connecting a trench gate electrode and a gate pad is formed of a conductive film formed on a semiconductor substrate via an insulating film. Here, a film thickness of the insulating film is larger than a film thickness of an insulating film in a trench and is smaller than an insulating film which is a field oxide film. | 2022-05-26 |
20220165728 | GATE STRUCTURE, FIN FIELD-EFFECT TRANSISTOR, AND METHOD OF MANUFACTURING FIN-FIELD EFFECT TRANSISTOR - A gate structure includes a gate dielectric layer, a work function layer, a metal layer, and a barrier layer. The work function layer is surrounded by the gate dielectric layer. The metal layer is disposed over the work function layer. The barrier layer is surrounded by the work function layer and surrounds the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. | 2022-05-26 |
20220165729 | INTEGRATED CIRCUIT DEVICES HAVING HIGHLY INTEGRATED NMOS AND PMOS TRANSISTORS THEREIN AND METHODS OF FABRICATING THE SAME - A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate. | 2022-05-26 |
20220165730 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material. | 2022-05-26 |
20220165731 | SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF - A semiconductor device structure is provided. The device includes first semiconductor layers and second semiconductor layers disposed below and aligned with the first semiconductor layers. Each first semiconductor layer is surrounded by a first and fourth intermixed layers. The first intermixed layer is disposed between the first semiconductor layer and the fourth intermixed layer and includes a first and second materials. The fourth intermixed layer includes a third and fourth materials. Each second semiconductor layer is surrounded by a second and third intermixed layers. The second intermixed layer is disposed between the second semiconductor layer and the third intermixed layer and includes the first and a fifth material. The third intermixed layer includes the third and a sixth material. The second and fourth material are a dipole material having a first polarity, and the fifth and sixth material are a dipole material having a second polarity opposite the first polarity. | 2022-05-26 |
20220165732 | SEMICONDUCTOR DEVICES INCLUDING TWO-DIMENSIONAL MATERIAL AND METHODS OF FABRICATION THEREOF - According to embodiments of the present disclosure, two-dimensional (2D) materials may be used as nanosheet channels for multi-channel transistors. Nanosheet channels made two-dimensional (2D) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. Embodiments of the present disclosure also provide a solution of P-type and N-type balancing in a device without increasing footprint of the device. | 2022-05-26 |
20220165733 | SEMICONDUCTOR DEVICES WITH BACKSIDE CONTACTS AND ISOLATION - A method includes forming a fin structure over a substrate, wherein the fin structure includes a base layer, an isolating layer over the base layer, and a stack of channel layers and first sacrificial layers alternately stacked over the isolating layer. The method further includes forming an isolation structure adjacent to sidewalls of the fin structure, wherein a top surface of the isolation structure is above a bottom surface of the isolating layer and below a top surface of the isolating layer. The method further includes depositing a second sacrificial layer over the isolation structure and over the sidewalls of the fin structure; etching the second sacrificial layer and the fin structure to form two source/drain trenches, wherein the source/drain trenches expose the base layer; partially removing the first and the second sacrificial layers through the source/drain trenches to form gaps; and depositing a dielectric spacer in the gaps. | 2022-05-26 |
20220165734 | SEMICONDUCTOR DEVICE WITHOUT A BREAK REGION - A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region. | 2022-05-26 |
20220165735 | COMPUTE NEAR MEMORY WITH BACKEND MEMORY - Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein. | 2022-05-26 |
20220165736 | SEMICONDUCTOR DEVICES - A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a spacer structure on a sidewall of the bit line structure, a contact plug structure contacting the spacer structure, an insulating interlayer structure partially penetrating through upper portions of the contact plug structure, the spacer structure and the bit line structure, and a capacitor on the contact plug structure. The spacer structure includes an air spacer including air. The insulating interlayer structure includes first and second insulating interlayers. The second insulating interlayer may include an insulation material different from that of the first insulating interlayer. A lower surface of the second insulating interlayer covers a top of the air spacer, and a lowermost surface of the first insulating interlayer is covered by the second insulating interlayer. | 2022-05-26 |
20220165737 | VERTICAL 1T-1C DRAM ARRAY - A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element. | 2022-05-26 |
20220165738 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a semiconductor base, a bit line and a word line. The semiconductor base includes a substrate and an isolation structure. The isolation structure is arranged above the substrate and configured to isolate a plurality of active regions from each other. The bit line is arranged in the substrate and connected to the plurality of active regions. The word line is arranged in the isolation structure, intersects with the plurality of active regions and surrounds the plurality of active regions. The substrate is a Silicon-On-Insulator (SOI) substrate. | 2022-05-26 |
20220165739 | NONVOLATILE MEMORY DEVICE WITH A METAL-INSULATOR-METAL (MIM) CAPACITOR IN A SUBSTRATE AND INTEGRATION SCHEMES - A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate. | 2022-05-26 |
20220165740 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a cell stack structure including first cell stack layers and stack conductive layers, which are alternately stacked; a cell plug penetrating the cell stack structure; and a cell chip guard surrounding the cell stack structure and the cell plug. The cell chip guard includes a guard semiconductor layer and a guard insulating layer covering a sidewall of the guard semiconductor layer. | 2022-05-26 |
20220165741 | THREE-DIMENSIONAL MEMORY AND CONTROL METHOD THEREOF - The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage. The first pass voltage is applied to first non-selected memory cells in the first portion, and the second pass voltage is applied to second non-selected memory cells in the second portion. | 2022-05-26 |
20220165742 | Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells - A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions, Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally therealong in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed. | 2022-05-26 |
20220165743 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An insulating film is formed on a semiconductor substrate, and a silicon film is formed on the insulating film. The silicon film and the insulating film in a transistor forming region are removed, and the silicon film and the insulating film in a transistor forming region are left. An insulating film is formed on the semiconductor substrate in the transistor forming region. A Hf-containing film is formed on the insulating film and the silicon film, and a silicon film is formed on the Hf-containing film. Then, a gate electrode is formed by patterning the silicon film, and a gate electrode is formed by patterning the silicon film. A gate insulating film under the gate electrode is formed by the insulating film, and a gate insulating film under the gate electrode is formed by the insulating film and the Hf-containing film. | 2022-05-26 |
20220165744 | SEMICONDUCTOR MEMORY DEVICE HAVING CELL UNITS AND VIA REGIONS WITH A DIFFERENT WIDTH - A semiconductor memory device includes a memory cell array disposed over a substrate extending in a first direction and a second direction intersecting with the first direction in a first semiconductor layer, and including a plurality of cell units and at least two via regions that are arranged in the second direction, wherein a width of each of the at least two via regions in the second direction is a multiple of a width of each of the plurality of cell units in the second direction. | 2022-05-26 |
20220165745 | THREE-DIMENSIONAL MEMORY AND METHOD FOR MANUFACTURING THE SAME - The present disclosure relates to a three-dimensional memory and a method for manufacturing the same. The three-dimensional memory includes a gate stack structure including a core area and a step area which are disposed in juxtaposition and in direct contact in a first direction; a dummy separation structure penetrating through the step area in the first direction; and a gate separation structure penetrating through the core area in the first direction, the gate separation structure having a first end in contact with the dummy separation structure in the first direction, the dummy separation structure having a second end in contact with the gate separation structure in the first direction, and the first end being located within the second end. | 2022-05-26 |
20220165746 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes conductive layers and insulating layers alternately stacked. The memory strings penetrate the stack along a first direction. Each of the memory strings includes a first conductive pillar, a second conductive pillar, a channel layer and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction, respectively, and electrically isolated to each other. The channel layer extends along the first direction. The channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer. | 2022-05-26 |
20220165747 | THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three-dimensional memory device and a method of manufacturing a three-dimensional memory device are provided. The method includes providing a precursor structure including a substrate, a multi-layered stack, a plurality of vertical channel pillars and a barrier structure. A first slit and a second slit are then formed in the multi-layered stack and the substrate along a first direction, in which the first slit and the second slit have a pitch between thereof, and the second slit cuts the barrier structure. A portion of the second insulating layers is then replaced with a plurality of conductive layers. A first slit structure and a second slit structure are then formed in the first slit and the second slit, in which the first slit structure and the second slit structure separate the vertical channel pillars in a second direction that is different from the first direction. | 2022-05-26 |
20220165748 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a cell stack structure including first cell stack layers and stack conductive layers, which are alternately stacked. The semiconductor device also includes a dummy stack structure including first dummy stack layers and second dummy stack layers, which are alternately stacked. The semiconductor device further includes a cell plug penetrating the cell stack structure and a cell chip guard penetrating the dummy stack structure, wherein the cell chip guard surrounds the cell stack structure and the cell plug. A level of a bottom surface of a cell chip guard is substantially equal to that of a bottom surface of the cell plug. | 2022-05-26 |
20220165749 | SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS OF THE SAME - A semiconductor device includes a vertical stack of gate electrodes. The gate electrodes extend in different lengths to provide contact regions. The gate electrodes have a conductive region and an insulating region. Contact plugs fills contact holes that pass through the stack of gate electrodes in the contact regions. The contact plugs are connected to the gate electrodes. The contact plugs pass through a conductive region of one gate electrode and are electrically connected to the one gate electrode and pass through the insulating region of other gate electrodes in the contact region. The insulating region is disposed outside of the contact holes in a region in which the gate electrodes intersect the contact plugs. | 2022-05-26 |
20220165750 | SEMICONDUCTOR DEVICE - A semiconductor device including a lower structure, an upper pattern, a stacked structure, a separation structure passing through the stacked structure, a vertical structure comprising a channel layer, wherein the stacked structure comprises a plurality of interlayer insulating layers and a plurality of gate layers, the lower structure comprises a first lower pattern and a second lower pattern of a material different from a material of the first lower pattern, the first lower pattern comprises a first portion between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and the substrate structure, and the first lower pattern does not extend toward a side surface of the upper pattern. | 2022-05-26 |
20220165751 | METHODS FOR FORMING MULTI-LAYER VERTICAL NOR-TYPE MEMORY STRING ARRAYS - A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks. | 2022-05-26 |
20220165752 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate; a lower structure including a sealing layer on the substrate and a support layer on the sealing layer, the sealing layer and the support layer both including a semiconductor material; a mold structure on the lower structure and having an interlayer insulating film and a conductive film alternately stacked therein; a channel hole penetrating the mold structure; a channel structure extending along sidewalls of the channel hole; an isolation trench penetrating the mold structure and extending into the lower structure; and a poly liner extending along sidewalls of the isolation trench, the poly liner being connected to the lower structure and including the semiconductor material. | 2022-05-26 |
20220165753 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes. | 2022-05-26 |
20220165754 | METHOD FOR FABRICATING MEMORY DEVICE - A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks. | 2022-05-26 |
20220165755 | PIXEL ARRAY SUBSTRATE - A pixel array substrate, including a substrate, multiple conductors, a pixel driving circuit, a first pad, and a second pad, is provided. The substrate has a first surface, a second surface, and multiple through holes. The through holes extend from the first surface to the second surface. The conductors are respectively disposed in the through holes. The pixel driving circuit is disposed on the first surface of the substrate. The first pad and the second pad are disposed on the second surface of the substrate. The conductors include a first conductor, a second conductor, and a first dummy conductor. The first conductor is electrically connected to the pixel driving circuit and the first pad. The second conductor is electrically connected to the pixel driving circuit and the second pad. The first dummy conductor is overlapped with and electrically isolated from the pixel driving circuit. | 2022-05-26 |
20220165756 | DISPLAY APPARATUS USING SEMICONDUCTOR LIGHT-EMITTING DEVICES - Discussed is a display device including: a substrate; a power wiring and a ground wiring disposed on the substrate and spaced apart from each other; a driving thin film transistor (TFT) disposed on the substrate and having a source terminal electrically connected to the ground wiring; at least one insulating. layer disposed on the substrate; and a pair of assembly electrodes spaced apart from each other between the at least one insulating layer and the substrate, wherein the pair of assembly electrodes is configured to generate an electric field as a voltage is applied to any one of the pair of assembly electrodes. | 2022-05-26 |
20220165757 | DISPLAY DEVICE, METHOD OF MANUFACTURING THE SAME, AND TILED DISPLAY DEVICE INCLUDING THE SAME - A display device includes: a first substrate; a second substrate on the first substrate and exposing a first edge portion of the first substrate, the second substrate protruding beyond a second edge portion of the first substrate; a connection line on the first edge portion of the first substrate, the connection line having a first end portion protruding beyond a first side of the second substrate and a second end portion covered by the second substrate; and a thin-film transistor layer on the second substrate and connected to the connection line. The thin-film transistor layer includes signal lines extending from the first side to a second side of the second substrate. The signal lines extend into contact openings in the thin-film transistor layer and are exposed at a lower part of the second substrate on the second side of the second substrate. | 2022-05-26 |
20220165758 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined. | 2022-05-26 |
20220165759 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device and a method of manufacturing a display device are provided. The display device includes a first conductive layer on a substrate, a passivation layer disposed on the first conductive layer and exposing at least a part of the first conductive layer, a second conductive layer disposed on the passivation layer and covering an upper surface of the passivation layer, a via layer on the second conductive layer, a third conductive layer including a first electrode, a second electrode, and a connection pattern, and spaced apart from each other on the via layer, and a light emitting element having ends that are disposed on the first electrode and the second electrode, respectively. The connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer. | 2022-05-26 |
20220165760 | IMAGE SENSING DEVICE - An image sensing device includes a substrate including a front side and a back side that are opposite to each other, wherein the image sensing device is structured to operate by receiving incident light through the back side of the substrate; a depletion region disposed in the substrate to be in contact with the back side of the substrate; an epitaxial layer disposed in the substrate to be in contact with or near the front side of the substrate; and a plurality of detection structures disposed in the epitaxial layer, each configured to capture photocharge generated by incident light and move by a current flowing in the epitaxial layer. | 2022-05-26 |
20220165761 | IMAGE SENSOR - An image sensor includes a substrate having a first surface and a second surface facing each other. A deep trench extends from the first surface to the second surface of the substrate and defines a pixel region within the substrate. A photoelectric conversion region is disposed. within the pixel region. A shallow trench extends from the first surface of the substrate into the substrate and at least partially defines a pattern within the pixel region. In a plan view, the pattern has a first corner, a second corner facing the first corner in a first diagonal direction, a third corner, and a fourth corner facing the third corner in a second diagonal direction that crosses the first diagonal direction. In the plan view, a radius of curvature of the third corner is less than a radius of curvature of the first corner. | 2022-05-26 |
20220165762 | PIXEL WITH BURIED OPTICAL ISOLATION - The invention provides an image sensor comprising a light receiving side (Fa) and, in a substrate ( | 2022-05-26 |
20220165763 | IMAGE SENSOR - An image sensor includes a first pixel; a second pixel disposed adjacent to the first pixel; a pixel isolation structure disposed between the first pixel and the second pixel; a rear side anti-reflective layer disposed on the first pixel, the second pixel, and the pixel isolation structure; and a fence disposed on the rear side anti-reflective layer aligning with the pixel isolation structure and including a buried air gap. | 2022-05-26 |
20220165764 | X-RAY FLAT PANEL DETECTOR, METHOD FOR MANUFACTURING X-RAY FLAT PANEL DETECTOR, DETECTION DEVICE AND IMAGING SYSTEM - An X-ray flat panel detector, a method for manufacturing the X-ray flat panel detector, a detection device and an imaging system are provided. The X-ray flat panel detector includes: a substrate; a back plate layer arranged on the substrate and including a plurality of thin film transistors, each thin film transistor including a source/drain electrode layer; a wiring layer arranged at a side of the back plate layer distal to the substrate and including a plurality of connection lines; and a photosensitive element layer arranged at a side of the wiring layer distal to the substrate and including first electrodes. Each first electrode is electrically connected to the source/drain electrode layer of a corresponding thin film transistor through a corresponding connection line, and an orthogonal projection of the first electrode onto the substrate does not overlap an orthogonal projection of the corresponding thin film transistor onto the substrate. | 2022-05-26 |
20220165765 | IMAGE SENSOR AND IMAGE SENSING SYSTEM - An image sensor includes a first element separation film inside a substrate and having a mesh shape, pixel regions on the substrate defined by the first element separation film and including at least first and second pixel regions, and a second element separation film inside the substrate and partitioning the first pixel region into sub-pixel regions, the second element separation film not being in the second pixel region, wherein the first pixel region includes first photoelectric conversion elements, and a first color filter on the first photoelectric conversion elements, the first color filter being one of white, green, and blue color filters, and wherein the second pixel region includes second photoelectric conversion elements, and a second color filter on the second photoelectric conversion elements, the second color filter being different from the first color filter and one of red and white color filters. | 2022-05-26 |
20220165766 | IMAGE SENSOR AND MANUFACTURING PROCESS THEREOF - An image sensor includes: a substrate including a plurality of first and second pixels; a light blocking pattern providing a plurality of first spaces respectively disposed on the first pixels and at least one second space disposed on the plurality of second pixels; a plurality of color filters respectively disposed in the plurality of first spaces; and a microlens layer including a plurality of first microlenses respectively disposed on the plurality of color filters, at least one filling portion disposed in the at least one second space, and at least one second microlens disposed on the at least one filling portion, wherein the microlenses are disposed at the same height as each other, and wherein the at least one filling portion and the at least one second microlens comprise an integrated structure without an interface between the at least one filling portion and the at least one second microlens. | 2022-05-26 |
20220165767 | IMAGING DEVICE - An imaging device according to an embodiment of the present disclosure includes: a first substrate including, in a first semiconductor substrate, a sensor pixel that performs photoelectric conversion; a second substrate including, in a second semiconductor substrate, a readout circuit that outputs a pixel signal based on electric charges outputted from the sensor pixel, the second substrate being stacked on the first substrate; a first insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; and a second insulating layer provided between the first semiconductor substrate and the second semiconductor substrate, and having lower film density than the first insulating layer. | 2022-05-26 |
20220165768 | SEMICONDUCTOR DEVICES AND IMAGE SENSORS INCLUDING THE SAME - Semiconductor devices may include an active fin extending on a substrate in a first direction and including a recess opening both sides located in the first direction, a source region and a drain region respectively adjacent opposing ends of the active fin, a gate electrode traversing the active fin in the second direction, perpendicular to the first direction, on an upper surface of the recess of the active fin, and extending to a side region, adjacent to the recess, and a gate insulating layer between the active fin and the gate electrode. In some embodiments, the first recess may extend through the first active fin in a width direction thereof. | 2022-05-26 |
20220165769 | WAFER LEVEL IMAGE SENSOR PACKAGE - A method for forming an image sensor package is provided. An image sensor chip is formed over a package substrate. A protection layer is formed overlying the image sensor chip. The protection layer has a planar top surface and a bottom surface lining and contacting structures under the protection layer. An opening is formed into the protection layer and spaced around a periphery of the image sensor chip. A light shielding material is filled in the opening to form an on-wafer shield structure having a sidewall directly contact the protection layer. | 2022-05-26 |
20220165770 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE - A solid-state imaging device according to the present disclosure includes a semiconductor layer, a plurality of on-chip lenses, a first separation region, and a second separation region. The semiconductor layer is provided with a plurality of photoelectric conversion units. The plurality of on-chip lenses causes light (L) to be incident on the corresponding photoelectric conversion units. The first separation region separates the plurality of photoelectric conversion units on which the light (L) is incident through the same on-chip lens. The second separation region separates the plurality of photoelectric conversion units on which light is incident through the different on-chip lenses. In addition, the first separation region has a higher refractive index than the second separation region. | 2022-05-26 |
20220165771 | PIXEL ARRAY AND METHOD FOR MANUFACTURING THE SAME - A pixel array may include a plurality of pixel regions including a first pixel region and a second pixel region. The pixel array may include a metal grid structure over the plurality of pixel regions. The pixel array may include a light blocking layer. A first portion of the light blocking layer may be over the first pixel region and under the metal grid structure. The first portion may have a first thickness. A second portion of the light blocking layer may be over the second pixel region and under the metal grid structure. The second portion may have a second thickness that is different from the first thickness. | 2022-05-26 |
20220165772 | FINGERPRINT ACQUISITION APPARATUS, DISPLAY PANEL AND ELECTRONIC DEVICE - A fingerprint acquisition apparatus includes a plurality of photoelectric conversion units and a first shading pattern. The first shading pattern includes at least one first shading block including a first opening, and an orthographic projection of the first opening in the first shading block on the base substrate is within an orthographic projection of a target photoelectric conversion unit corresponding to the first shading block on the base substrate. | 2022-05-26 |
20220165773 | LIGHT RECEIVING ELEMENT, LIGHT DETECTION DEVICE, AND LIGHT DETECTION METHOD - A light receiving element capable of detecting predetermined light among incident light beams with high sensitivity by a simple structure is provided. A light receiving element | 2022-05-26 |
20220165774 | IMAGE SENSOR INCLUDING A PIXEL SEPERATION STRUCTURE - An image sensor includes: a semiconductor substrate that has a first surface and a second surface opposite to each other. The semiconductor substrate includes: a first trench that vertically extends from the first surface of the semiconductor substrate and provides a pixel region, and a second trench that vertically extends from the first surface of the semiconductor substrate and is disposed on the pixel region. The image sensor further includes: a pixel separation structure that vertically extends from the second surface of the semiconductor substrate and overlaps the first trench; and a gap-fill dielectric layer disposed on the first surface of the semiconductor substrate, wherein the gap-fill dielectric layer includes a pixel separation part and a scattering pattern part, wherein the pixel separation part is disposed in the first trench, and the scattering pattern part is disposed in the second trench. | 2022-05-26 |
20220165775 | DEPTH PIXEL HAVING MULTIPLE PHOTODIODES AND TIME-OF-FLIGHT SENSOR INCLUDING THE SAME - A depth pixel includes a first photodiode, a second photodiode and a common microlens. First and second taps are disposed at both sides of the first photodiode in a first horizontal direction to sample a photo charge stored in the first photodiode. The second photodiode is disposed at a side of the first photodiode in a second horizontal direction perpendicular to the first horizontal direction. Third and fourth taps are disposed at both sides of the second photodiode in the first horizontal direction to sample a photo charge stored in the second photodiode. The common microlens is disposed above or below the semiconductor substrate. The common microlens covers both of the first photodiode and the second photodiode to focus an incident light to the first photodiode and the second photodiode. | 2022-05-26 |
20220165776 | PIXEL ARRAY INCLUDING AIR GAP REFLECTION STRUCTURES - A pixel array may include air gap reflection structures under a photodiode of a pixel sensor to reflect photons that would otherwise partially refract or scatter through a bottom surface of a photodiode. The air gap reflection structures may reflect photons upward toward the photodiode so that the photons may be absorbed by the photodiode. This may increase the quantity of photons absorbed by the photodiode, which may increase the quantum efficiency of the pixel sensor and the pixel array. | 2022-05-26 |
20220165777 | CIRCUIT BOARD, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - The present technology relates to a circuit board, a semiconductor device, and an electronic device for enabling effective suppression of generation of noise in a signal. A circuit board includes a first conductor periodically arranged with a first periodic width in a first region, a second conductor periodically arranged with a second periodic width in the first region, a third conductor periodically arranged with a third periodic width in a second region different from the first region, and a fourth conductor periodically arranged with a fourth periodic width in the second region, in which the first periodic width and the second periodic width are in a rational number relationship, the third periodic width and the fourth periodic width are in a rational number relationship, the first periodic width and the fourth periodic width are same or substantially same, the first region and the second region have a conductor structure mirror-symmetrical or substantially mirror-symmetrical in a first direction, and a first power supply connected to the first conductor and the third conductor and a second power supply connected to the second conductor and the fourth conductor are power supplies having different voltage values. The present technology can be applied to, for example, a solid-state imaging device. | 2022-05-26 |
20220165778 | IMAGE SENSOR PACKAGE INCLUDING GLASS SUBSTRATE - An image sensor package includes a glass substrate configured to focus incident light, a first redistribution layer and a second redistribution layer both disposed under the glass substrate while being horizontally spaced apart from each other by a first distance, an image sensor disposed such that an upper surface thereof is vertically spaced apart from both a lower surface of the first redistribution layer and a lower surface of the second redistribution layer by a second distance, and a first connector that connects both the first redistribution layer and the second redistribution layer to the image sensor. The thickness of the glass substrate is 0.6 to 0.8 mm. The first distance is smaller than the horizontal length of the image sensor by 50 μm to 1 mm. The second distance is equal to or less than 0.1 mm. | 2022-05-26 |
20220165779 | PIXEL ARRAY INCLUDING OCTAGON PIXEL SENSORS - A pixel array includes octagon-shaped pixel sensors and square-shaped pixel sensors. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. Moreover, the pixel array may include a combination of red, green, and blue pixel sensors to obtain color information from incident light; yellow pixel sensors for blue and green color enhancement and correction for the pixel array; near infrared (NIR) pixel sensors to increase contour sharpness and low light performance for the pixel array; and/or white pixel sensors to increase light sensitivity and brightness for the pixel array. The capability to configure different sizes and types of pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters. | 2022-05-26 |
20220165780 | Fingerprint Identification Substrate and Manufacturing Method Therefor, Identification Method and Display Apparatus - Provided a fingerprint identification substrate and a manufacturing method therefor, a identification method, and a display apparatus. The fingerprint identification substrate includes a substrate and at least two kinds of identification pixels disposed on the substrate, a first identification pixel includes a first photodiode and a second identification pixel includes a second photodiode. The first photodiode includes a first electrode, a first photoelectric conversion layer and a second electrode, the second photodiode includes the first electrode, a second photoelectric conversion layer and the second electrode, and the first photoelectric conversion layer and the second photoelectric conversion layer have different spectral response characteristics to red light or infrared light. | 2022-05-26 |
20220165781 | SOLID-STATE IMAGE SENSOR AND ELECTRONIC APPARATUS - The present disclosure relates to a solid-state image sensor and an electronic apparatus that suppress a decrease in light collection efficiency and degradation in oblique light resistance and enable a reduction in the height of a solid-state image sensor. A solid-state image sensor according to a first aspect of the present disclosure is a solid-state image sensor of a vertical spectral diffraction type in which a plurality of photoelectric conversion units are stacked in a region of each pixel, the solid-state image sensor including: a first photoelectric conversion module that includes a first photoelectric conversion unit configured to perform photoelectric conversion on light in a first wavelength range of incident light, a first upper electrode and a first lower electrode formed with the first photoelectric conversion unit placed between the first upper electrode and the first lower electrode, and a first spectral correction unit formed between the first upper electrode and the first lower electrode to be stacked on the first photoelectric conversion unit; and a second photoelectric conversion unit configured to perform photoelectric conversion on light in a second wavelength range of light that has passed through the first photoelectric conversion module, the second wavelength range being different from the first wavelength range. The present disclosure can be applied to, for example, a CMOS image sensor. | 2022-05-26 |
20220165782 | SYSTEMS, METHODS, AND DEVICES FOR REDUCING OPTICAL AND ELECTRICAL CROSSTALK IN PHOTODIODES - Devices, systems, and methods are provided for reducing electrical and optical crosstalk in photodiodes. A photodiode may include a first layer with passive material, the passive material having no electric field. The photodiode may include a second layer with an absorbing material, the second layer above the first layer. The photodiode may include a diffused region with a buried p-n junction. The photodiode may include an active region with the buried p-n junction and having an electric field greater than zero. The photodiode may include a plateau structure based on etching through the second layer to the first layer, the etching performed at a distance of fifteen microns or less from the buried p-n junction. | 2022-05-26 |
20220165783 | Method For Fabrication Of NIR CMOS Image Sensor - A method of fabricating CMOS image sensors is disclosed. In contrast to traditional fabrication processes, the present sequence implants dopants into the epitaxial layer from both the first surface and the second surface. Because dopant is introduced through both sides, the maximum implant energy to perform the implant may be reduced by as much as 50%. In certain embodiments, the second implant is performed prior to the application of the electrical contacts. In another embodiments, the second implant is performed after the application of the electrical contacts. This method may allow deeper photodiodes to be fabricated using currently available semiconductor processing equipment than would otherwise be possible. | 2022-05-26 |
20220165784 | SOLID STATE TRANSDUCER DEVICES, INCLUDING DEVICES HAVING INTEGRATED ELECTROSTATIC DISCHARGE PROTECTION, AND ASSOCIATED SYSTEMS AND METHODS - Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate. | 2022-05-26 |
20220165785 | MICRO LED TRANSPARENT DISPLAY - A micro LED transparent display has a first display surface and a second display surface, which are opposite to each other. The micro LED transparent display includes a substrate, pixels and at least one grating layer. The first display surface and the second display surface are located on two opposite sides of the substrate, respectively. The pixels are arranged in arrays on the substrate, each of the pixels includes micro LEDs, and the micro LEDs are electrically connected to the substrate. The grating layer is disposed on the substrate, and the micro LEDs are located between the grating layer and the substrate. Lights generated from the micro LEDs of the pixels can be controlled by the grating layer, and the lights partially penetrate through the first display surface and are partially reflected and penetrate through the second display surface. | 2022-05-26 |
20220165786 | METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING DISPLAY DEVICE - A method of manufacturing a light emitting element includes: forming a plurality of light emitting patterns on a stack substrate; forming a polysilazane layer on the plurality of light emitting patterns; forming a first insulating film by curing the polysilazane layer; and forming a second insulating film on the first insulating film. The forming of the first insulating film includes photocuring the polysilazane layer by irradiating ultraviolet rays onto the polysilazane layer. The forming of the plurality of light emitting patterns includes: forming a light emitting stack structure on the stack substrate; and etching the light emitting stack structure. | 2022-05-26 |
20220165787 | DISPLAY DEVICE - A display device capable of improving a light emission efficiency includes a plurality of insulating films disposed on a substrate, a trench exposing side surfaces of the plurality of insulating films, a first alignment electrode disposed on the side surfaces of the plurality of insulating films exposed by the trench, a second alignment electrode disposed so as to be surrounded by the first alignment electrode, and a light-emitting device connected to the first and second alignment electrodes and disposed between the first and second alignment electrodes within the trench, thereby improving a light emission efficiency. | 2022-05-26 |
20220165788 | NANOROD LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Disclosed is a technology of preferentially forming an ohmic contact layer and a conductor layer before separating a nanorod light emitting diode (LED) from a substrate, thereby being capable of omitting a heat treatment process performed at high temperature after aligning the nanorod LED, and, accordingly, preventing electrical short while maximizing the quantum efficiency of the nanorod LED and increasing a selection range of a material constituting a light emitting diode (LED) display. More particularly, the nanorod LED includes a first semiconductor layer; a multi-quantum well structure layer; a second semiconductor layer; and a conductor layer formed on at least one semiconductor layer of the first semiconductor layer and the second semiconductor layer, wherein a length and shape of the conductor layer are controlled such that the multi-quantum well structure layer is disposed between two electrodes of the electrode pattern on which the conductor layer is to be aligned. | 2022-05-26 |
20220165789 | METHODS FOR TRANSFER OF MICRO-DEVICES - An apparatus for positioning micro-devices on a substrate includes one or more supports to hold a donor substrate and a destination substrate, an adhesive dispenser to deliver adhesive on micro-devices on the donor substrate, a transfer device including a transfer surface to transfer the micro-devices from the donor substrate to the destination substrate, and a controller. The controller is configured to operate the adhesive dispenser to selectively dispense the adhesive onto selected micro-devices on the donor substrate based on a desired spacing of the selected micro-devices on the destination substrate. The controller is configured to operate the transfer device such that the transfer surface engages the adhesive on the donor substrate to cause the selected micro-devices to adhere to the transfer surface and the transfer surface then transfers the selected micro-devices from the donor substrate to the destination substrate | 2022-05-26 |
20220165790 | INTEGRATED NON VOLATILE MEMORY ELECTRODE THIN FILM RESISTOR CAP AND ETCH STOP - A non-volatile memory cell includes a thin film resistor (TFR) in series and between a top state influencing electrode and a top wire. The TFR limits or generally reduces the electrical current at the top state influencing electrode from the top wire. As such, non-volatile memory cell endurance may be improved and adverse impacts to component(s) that neighbor the non-volatile memory cell may be limited. The TFR is additionally utilized as an etch stop when forming a top wire trench associated with the fabrication of the top wire. In some non-volatile memory cells where cell symmetry is desired, an additional TFR may be formed between a bottom wire and a bottom state influencing electrode. | 2022-05-26 |
20220165791 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. Each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. At least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall. | 2022-05-26 |
20220165792 | METHOD FOR MANUFACTURING A MICROELECTRONIC DEVICE COMPRISING A PLURALITY OF RESISTIVE MEMORY POINTS CONFIGURED TO FORM A PHYSICAL UNCLONABLE FUNCTION AND SAID DEVICE - A method for manufacturing a microelectronic device including resistive memory points, a first portion of the memory points forming a physical unclonable function, the memory points of the first portion forming a PUF zone, a second portion of the memory points providing a memory function, the memory points of the second forming a memory zone, the method including providing a support including a first electrode layer and an active oxide resistive memory layer; etching the active oxide resistive memory layer in the PUF zone; etching the active oxide resistive memory layer in the memory zone, the etching in the memory zone producing a dispersion of roughness of the oxide layer less than the dispersion of roughness produced by the etching in the PUF zone; depositing a second electrode layer; etching the second electrode layer, the active oxide layer and the first electrode layer to define the memory points. | 2022-05-26 |
20220165793 | VIA FORMATION FOR A MEMORY DEVICE - Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack. | 2022-05-26 |
20220165794 | High-Density Three-Dimensional Vertical Memory - High-density three-dimensional (3-D) vertical memory (3D-M | 2022-05-26 |
20220165795 | ACCESS LINE FORMATION FOR A MEMORY ARRAY - Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps. | 2022-05-26 |
20220165796 | DISPLAY DEVICE, DISPLAY PANEL AND METHOD OF MANUFACTURING DISPLAY PANEL - The present disclosure relates to a display device, a display panel and a method of manufacturing the same, and relates to display technology. The display panel of the present disclosure includes a driving backplane, a first planarization layer, a second planarization layer, light-emitting devices and photoelectric sensing devices. The first planarization layer is provided on one side of the driving backplane. The second planarization layer is provided on a surface of the first planarization layer distal to the driving backplane, and the second planarization layer is provided with sensing holes. The light-emitting devices are provided on a surface of the second planarization layer distal to the driving backplane and are located outside the sensing holes. The photoelectric sensing devices are provided on a surface of the second planarization layer distal to the driving backplane, and each of the photoelectric sensing devices is at least partially located inside the sensing hole. | 2022-05-26 |
20220165797 | OPTOELECTRONIC DEVICE - An optoelectronic device includes a substrate with a light emitter and a photodetector supported by the substrate. The light emitter and photodetector are stacked one on top of the other. At least one of the light emitter and photodetector is formed by a stack including the following order of layers: a first electrode layer, a hole transport layer, a quantum nano-structure layer (for example, a semiconductor nanoparticle layer, a quantum dot layer, a quantum rod layer or quantum well layer), an electron transport layer and a second electrode layer. An insulating layer is positioned between the light emitter and photodetector in the stack. | 2022-05-26 |
20220165798 | HYBRID MULTISPECTRAL DEVICE - The invention concerns a hybrid multispectral device comprising a substrate having a first surface and a second surface, at least one first functional element having a first functional layer operable to detect or emit light of a first wavelength range, and at least one second functional element having a second functional layer operable to detect or emit light of a second wavelength range different from the first wavelength range. The first functional element is arranged on the first surface of the substrate, while the second functional element is arranged on the second surface of the substrate. The first functional element is arranged in a first lateral region of the multispectral device, and the second functional element is arranged in a second lateral region of the multispectral device. The first lateral region and the second lateral region are arranged laterally offset from each other such that the light of the second wavelength region reaches the second functional element or the light of the second wavelength region emitted from the second functional element exits the multispectral device on the first surface of the substrate without having passed through the first functional layer. | 2022-05-26 |
20220165799 | SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS - A solid-state imaging device and an imaging apparatus capable of realizing further miniaturization of an imaging apparatus and further improvement of light use efficiency are to be provided. The present technology provides a solid-state imaging device that includes a plurality of pixels arranged one- or two-dimensionally, in which each pixel includes at least a light receiving unit, and the light receiving unit included in at least some of the plurality of pixels have circularly polarized dichroism. The present technology also provides an imaging apparatus that includes at least: the solid-state imaging device; and a signal processing unit that generates an image capturing only specific circularly polarized light, on the basis of a signal obtained from at least one of the pixels of the solid-state imaging device. | 2022-05-26 |
20220165800 | PHOTOELECTRIC CONVERSION ELEMENT AND SOLID-STATE IMAGING DEVICE - A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode; a second electrode disposed to be opposed to the first electrode; and an organic photoelectric conversion layer provided between the first electrode and the second electrode. The organic photoelectric conversion layer has a domain of one organic semiconductor material therein. The domain of the one organic semiconductor material has a percolation structure in which the domain vertically extends in the organic photoelectric conversion layer in a film-thickness direction, and has a smaller domain length in a plane direction of the organic photoelectric conversion layer than a domain length in the film-thickness direction of the organic photoelectric conversion layer. | 2022-05-26 |
20220165801 | COLOR CONVERSION PANEL, METHOD OF MEASURING VOLUME OF INK LAYER THEREOF, AND DISPLAY DEVICE INCLUDING THE COLOR CONVERSION PANEL - A color conversion panel includes an active area corresponding to a display area and including an active pixel portion at which light is emitted, a dummy area adjacent to the active area and including a first dummy pixel portion and a second dummy pixel portion, and a color conversion layer including a bank layer in both the active area and the dummy area. The bank layer defines each of an active opening corresponding to the active pixel portion and defining an active opening planar area, a first dummy opening corresponding to the first dummy pixel portion and defining a first planar area, and a second dummy opening corresponding to the second dummy pixel portion and defining a second planar area. The first planar area of the first dummy opening is different from the second planar area of the second dummy opening. | 2022-05-26 |
20220165802 | DISPLAY APPARATUS - A display apparatus includes a first pixel, a second pixel, and a third pixel that emit light of different colors, a first quantum conversion layer arranged corresponding to an emission area of the first pixel and including first quantum dots and first metal nanoparticles, and a second quantum conversion layer arranged corresponding to an emission area of the second pixel and including second quantum dots and second metal nanoparticles, where the plurality of first quantum dots has an average size different from an average size of the second quantum dots, and the first metal nanoparticles have an average size identical to an average size of the plurality of second metal nanoparticles, and outer shapes of the first metal nanoparticles and the second metal nanoparticles have sharper corners than virtual outer spherical shapes. | 2022-05-26 |