21st week of 2011 patent applcation highlights part 17 |
Patent application number | Title | Published |
20110121402 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - In a BiCMOS device, a device isolation film separating the bipolar transistor region from the MOS region is taller than the substrate at least where it contacts the bipolar transistor region, and is preferably taller than the same layer where it contacts the MOS transistor region. This makes it possible to maintain the processing accuracy of a MOS transistor while stabilizing the diode current characteristics of the bipolar transistor. | 2011-05-26 |
20110121403 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure. | 2011-05-26 |
20110121404 | ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION - An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 | 2011-05-26 |
20110121405 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING TRANSISTORS AND SEMICONDUCTOR DEVICE HAVING TRANSISTORS - A method of manufacturing a semiconductor device has forming a first mask pattern exposing a region for forming a first transistor and a region for forming a second transistor, performing a first ion implantation using the first mask pattern, performing a second ion implantation using the first mask pattern, removing the first mask pattern and forming a second mask pattern in which the first transistor forming region is covered and the second transistor forming region is opened, and performing a third ion implantation using the second mask pattern. | 2011-05-26 |
20110121406 | FinFETs with Different Fin Heights - An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height. | 2011-05-26 |
20110121407 | BIDIRECTIONAL POWER SWITCH CONTROLLABLE TO BE TURNED ON AND OFF - A bidirectional power transistor formed horizontally in a semiconductor layer disposed on a heavily-doped semiconductor wafer with an interposed insulating layer, the wafer being capable of being biased to a reference voltage, the product of the average dopant concentration and of the thickness of the semiconductor layer ranging between 5·10 | 2011-05-26 |
20110121408 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME - A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, and LDD regions are formed in the semiconductor layer. A main gate is formed on the gate insulating film. A sub-gate is formed on the main gate and the gate insulating film so as to cover a part of the main gate and either the LDD regions adjacent to the source region or the drain region. An interlayer insulating film containing hydrogen is formed on the sub-gate, main gate, and gate insulating film. Subsequently, a heat treatment for hydrogenation is performed to terminate a crystal defect of the semiconductor layer with hydrogen. | 2011-05-26 |
20110121409 | Field effect transistors, methods of fabricating a carbon-insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor - Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10 | 2011-05-26 |
20110121410 | Semiconductor Contact Barrier - System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer. | 2011-05-26 |
20110121411 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING AND OPERATING THE SAME - The invention provides a semiconductor cell comprising a gate, a dielectric layer, a channel layer, a source region, a drain region and an oxide region. The dielectric layer is adjacent to the gate. The channel layer is adjacent to the dielectric layer and is formed above a source region, a drain region, and an oxide region. | 2011-05-26 |
20110121412 | PLANAR MICROSHELLS FOR VACUUM ENCAPSULATED DEVICES AND DAMASCENE METHOD OF MANUFACTURE - Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell. | 2011-05-26 |
20110121413 | MICROELECTROMECHANICAL SYSTEMS MICROPHONE PACKAGING SYSTEMS - This document discusses, among other things, a conductive frame, a silicon die coupled to the conductive frame, the silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a silicon die port extending through the silicon die to the vibratory diaphragm, with a silicon die terminal in electrical communication with the conductive frame and an insulator affixed to the conductive frame and the silicon die, with the insulator extending through interstices in the conductive frame to a conductive frame bottom of the conductive frame, and around an exterior of the silicon die to the silicon die top, with the insulator physically affixed to the silicon die and to the conductive frame, with the silicon die port exposed and with a conductive frame terminal disposed at the conductive frame bottom in electrical communication with the silicon die terminal. | 2011-05-26 |
20110121414 | Encapsulation, MEMS and Method of Selective Encapsulation - The invention relates to an encapsulation ( | 2011-05-26 |
20110121415 | PLANAR MICROSHELLS FOR VACUUM ENCAPSULATED DEVICES AND DAMASCENE METHOD OF MANUFACTURE - Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell. | 2011-05-26 |
20110121416 | PLANAR MICROSHELLS FOR VACUUM ENCAPSULATED DEVICES AND DAMASCENE METHOD OF MANUFACTURE - Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell. | 2011-05-26 |
20110121417 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction structure above a bottom electrode. The method also includes forming a diffusion barrier layer above and adjacent to the magnetic tunnel junction structure. The method further includes etching back the diffusion barrier layer, removing the diffusion barrier layer above the magnetic tunnel junction structure. The method also includes connecting a top of the magnetic tunnel junction structure to a conductive layer. | 2011-05-26 |
20110121418 | MRAM Cells Including Coupled Free Ferromagnetic Layers for Stabilization - A free ferromagnetic data storage layer of an MRAM cell is coupled to a free ferromagnetic stabilization layer, which stabilization layer is directly electrically coupled to a contact electrode, on one side, and is separated from the free ferromagnetic data storage layer, on an opposite side, by a spacer layer. The spacer layer provides for the coupling between the two free layers, which coupling is one of: a ferromagnetic coupling and an antiferromagnetic coupling. | 2011-05-26 |
20110121419 | METHOD FOR MANUFACTURING A MAGNETIC MEMORY DEVICE AND MAGNETIC MEMORY DEVICE - A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer. | 2011-05-26 |
20110121420 | REVERSE IMAGE SENSOR MODULE AND METHOD FOR MANUFACTURING THE SAME - A reverse image sensor module includes first and second semiconductor chips, and first and second insulation layers. The first semiconductor chip includes a first semiconductor chip body having a first surface and a second surface facing away from the first surface, photodiodes disposed on the first surface, and a wiring layer disposed on the second surface and having wiring lines electrically connected to the photodiodes and bonding pads electrically connected to the wiring lines. The second semiconductor chip includes a second semiconductor chip body having a third surface facing the wiring layer, and through-electrodes electrically connected to the bonding pads and passing through the second semiconductor chip body. The first insulation layer is disposed on the wiring layer, and the second insulation layer is disposed on the third surface of the second semiconductor chip body facing the first insulation layer and is joined to the first insulation layer. | 2011-05-26 |
20110121421 | IMAGE SENSOR HAVING NONLINEAR RESPONSE - In previously known imaging devices as in still and motion cameras, for example, image sensor signal response typically is linear as a function of intensity of incident light. Desirably, however, akin to the response of the human eye, response is sought to be nonlinear and, more particularly, essentially logarithmic. Preferred nonlinearity is realized in image sensor devices of the invention upon severely limiting the number of pixel states, combined with clustering of pixels into what may be termed as super-pixels. | 2011-05-26 |
20110121422 | SOLID-STATE IMAGE SENSOR - A solid-state image sensor having a configuration which reduces increases in light-collection loss and light mixing due to an increase in the angle of light entering into a waveguide path during oblique incidence and which is effective for sensitivity improvement includes: an Si substrate; unit-pixels arranged on the Si substrate; a wiring layer formed on the unit-pixels; optical waveguide regions each formed on a photoelectric conversion region included in a corresponding one of the unit-pixels, and penetrating the wiring layer; and light-collecting elements each formed above a corresponding one of the optical waveguide regions, wherein each of the light-collecting elements is a gradient index microlens having an effective refractive index distribution. | 2011-05-26 |
20110121423 | Concentric Ring Mask for Controlling The Shape of a Planar PN Junction - A mask for use in making a planar PN junction in a semiconductor device includes a central mask opening and a plurality of spaced apart concentric mask openings surrounding the central mask opening. The concentric mask openings each have a width less than a maximum dimension of the central mask opening. The central mask opening can be circular and the concentric mask openings can have a ring-shape. The mask can be used to form openings in a wafer layer for introducing an impurity to dope that wafer layer. | 2011-05-26 |
20110121424 | LOW OXYGEN CONTENT SEMICONDUCTOR MATERIAL FOR SURFACE ENHANCED PHOTONIC DEVICES AND ASSOCIATED METHODS - Radiation-absorbing semiconductor devices and associated methods of making and using are provided. In one aspect, for example, a method for making a radiation-absorbing semiconductor device having enhanced photoresponse can include forming an active region on a surface of a low oxygen content semiconductor, and annealing the low oxygen content semiconductor to a temperature of from about 300° C. to about 1100° C., wherein the forming of the active region and the annealing of the low oxygen content semiconductor are performed in a substantially oxygen-depleted environment. | 2011-05-26 |
20110121425 | SEMICONDUCTOR DEVICE WITH IMPROVED ESD PROTECTION - The present invention relates to a semiconductor device, comprising a semiconductor substrate ( | 2011-05-26 |
20110121426 | ELECTRONIC DEVICE WITH FUSE STRUCTURE AND METHOD FOR REPAIRING THE SAME - According to an embodiment of the invention, an electronic device with a fuse structure is provided. The electronic device includes a substrate, at least a conducting layer formed in or on the substrate and having a fuse area, and at least a lens disposed overlying the fuse area of the conducting layer, wherein the lens is substantially aligned with the fuse area and there is no optical device disposed between the lens and the fuse area. | 2011-05-26 |
20110121427 | THROUGH-SUBSTRATE VIAS WITH POLYMER FILL AND METHOD OF FABRICATING SAME - An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole, and depositing a polymer material over the conductive material such that any continuous top-to-bottom openings present in the via holes are filled by the polymer material. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias. | 2011-05-26 |
20110121428 | HIGH GAIN TUNABLE BIPOLAR TRANSISTOR - An improved bipolar transistor ( | 2011-05-26 |
20110121429 | LOW-VOLTAGE BIDIRECTIONAL PROTECTION DIODE - A vertical bidirectional protection diode including, on a heavily-doped substrate of a first conductivity type, first, second, and third regions of the first, second, and first conductivity types, these regions all having a doping level greater than from 2 to 5×10 | 2011-05-26 |
20110121430 | METHOD FOR FORMING A SILICON DIOXIDE/METAL OXIDE-NANOLAMINATE WITH A DESIRED WET ETCH RATE - An atomic layer deposition-deposited silicon dioxide/metal oxide-nanolaminate, comprising at least one layer of silicon dioxide and at least one layer of a metal oxide, and having a wet etch rate in an etchant, said wet etch rate being either greater or smaller than both a wet etch rate of a film of silicon dioxide and a wet etch rate of a film of said metal oxide in said etchant. Also provided is a method for manufacturing the same. | 2011-05-26 |
20110121431 | Substrate Comprising a Nanometer-scale Projection Array - A method for forming a substrate comprising nanometer-scale pillars or cones that project from the surface of the substrate is disclosed. The method enables control over physical characteristics of the projections including diameter, sidewall angle, and tip shape. The method further enables control over the arrangement of the projections including characteristics such as center-to-center spacing and separation distance. | 2011-05-26 |
20110121432 | Semiconductor Device and Method of Forming Holes In Substrate to Interconnect Top Shield and Ground Shield - A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die. | 2011-05-26 |
20110121433 | SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip and a stacked semiconductor package are presented. The semiconductor chip includes a semiconductor substrate, circuit patterns, first input/output pads and second input/output pads. The semiconductor substrate is divided into cell and peripheral regions and has first and second surfaces which oppose each other. The circuit patterns are formed on the first surface of the semiconductor substrate and are connected with the cell region and the peripheral region. The first input/output pads are formed in the cell region and are connected to the circuit patterns. The second input/output pads are formed in the peripheral region and connected with the circuit patterns. | 2011-05-26 |
20110121434 | METHOD OF FABRICATING A PLANAR SEMICONDUCTOR NANOWIRE - A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semi-conductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane. | 2011-05-26 |
20110121435 | PHOTOSENSITIVE ADHESIVE COMPOSITION, FILMY ADHESIVE, ADHESIVE SHEET, ADHESIVE PATTERN, SEMICONDUCTOR WAFER WITH ADHESIVE LAYER, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - A photosensitive adhesive composition that comprises (A) a resin with a carboxyl and/or hydroxyl group, (B) a thermosetting resin, (C) a radiation-polymerizable compound and (D) a photoinitiator, wherein the 3% weight reduction temperature of the entire photoinitiator mixture in the composition is 200° C. or greater. | 2011-05-26 |
20110121436 | METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF - Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N | 2011-05-26 |
20110121437 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone. | 2011-05-26 |
20110121438 | EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE - An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. | 2011-05-26 |
20110121439 | SEMICONDUCTOR DEVICE WITH PROTRUDING COMPONENT PORTION AND METHOD OF PACKAGING - A semiconductor package device having a protruding component portion and a method of packaging the semiconductor device is disclosed. The semiconductor device has a component, such as a leadframe, and a packaging mold body. The packaging mold body is formed around a portion of the component and a recess is formed in the packaging mold body adjacent the protruding portion of the component to prevent the protruding portion of the component from damaging other adjacent and abutting semiconductor devices. | 2011-05-26 |
20110121440 | SEMICONDUCTOR DEVICE AND LEAD FRAME THEREOF - A semiconductor device includes a semiconductor element and a lead frame. The lead frame includes a first lead, a second lead, a third lead, a fourth lead, and a fifth lead placed parallel to one another. The first and second leads are placed adjoining to each other and constitute a first lead group, and the third and fourth leads are placed adjoining to each other and constitute a second lead group. The spacing between the first lead group and the fifth lead, the spacing between the second lead group and the fifth lead, and the spacing between the first lead group and the second lead group are larger than the spacing between the first lead and the second lead and the spacing between the third lead and the fourth lead. | 2011-05-26 |
20110121441 | DIODE LEADFRAME FOR SOLAR MODULE ASSEMBLY - A leadframe design for a diode or other semiconductor device that reduces stress on the device and provides increased heat dissipation is provided. According to various embodiments, the leadframe has a contoured profile including a recessed area and a raised surface within the recessed area. The surface supports the device such that the edges of the device extend past the surface. Also provided are device assemblies including the novel leadframes. In certain embodiments, the assemblies include one or more leadframes attached via a solder joint to a device. According to various embodiments, the leadframes are attached to the front side of the device, back side of the device or both. In particular embodiments, the device is a bypass diode for one or more solar cells in a solar module. | 2011-05-26 |
20110121442 | PACKAGE STRUCTURE AND PACKAGE PROCESS - A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias. | 2011-05-26 |
20110121443 | SEMICONDUCTOR DEVICE - A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other. | 2011-05-26 |
20110121444 | EMBEDDED CHIP PACKAGES - Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed. | 2011-05-26 |
20110121445 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a plural number of interconnects and a plural number of vias are stacked. A semiconductor element is enclosed in an insulation layer. At least one of the vias provided in insulation layers and/or at least one of interconnects provided in the interconnect layers are of cross-sectional shapes different from those of the vias formed in another one of the insulation layers and/or interconnects provided in another one of the interconnect layers. | 2011-05-26 |
20110121446 | Fabrication of Atomic Scale Devices - This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves. | 2011-05-26 |
20110121447 | ADHESIVE FOR CONNECTION OF CIRCUIT MEMBER AND SEMICONDUCTOR DEVICE USING THE SAME - An adhesive for connecting circuit members, which is interposed between a semiconductor chip having protruding connecting terminals and a board having wiring patterns formed thereon for electrically connecting the connecting terminals and the wiring patterns facing each other and bonding the semiconductor chip and the board by applying pressure/heat, containing a resin composition containing a thermoplastic resin, a crosslinkable resin and a hardening agent for forming a crosslink structure of the crosslinkable resin; and composite oxide particles dispersed in the resin composition. | 2011-05-26 |
20110121448 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - The semiconductor device comprises a support plate; a semiconductor element; and conductor posts consisting of a conductor having a first end at one end and a second end at the other end, the second end being connected to the semiconductor element and the conductor posts being connected to the support plate at a position on the side of the second end that is closer to the first end, wherein the conductor posts have a heat conductivity of approximately 200 W/m·K or higher and a Vickers hardness of approximately 70 or lower. | 2011-05-26 |
20110121449 | Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP - A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer. | 2011-05-26 |
20110121450 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A semiconductor device includes a support plate having a hole formed therein and a conductor formed on a wall surface of the hole, a semiconductor element; and a conductive post formed by a conductor having a first end portion at one end, and a second end portion at an other end. The second end portion of the conductive post is connected to the semiconductor element, and a side surface of the conductive post is fixed to the conductor on the wall surface of the hole deformed by pressing force of the conductive post on a side closer to the first end portion than the second end portion. | 2011-05-26 |
20110121451 | ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion. | 2011-05-26 |
20110121452 | Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers - A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer. | 2011-05-26 |
20110121453 | SEMICONDUCTOR SYSTEM-IN-PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described. | 2011-05-26 |
20110121454 | STACK SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members. | 2011-05-26 |
20110121455 | Semiconductor Devices Having Interconnection Structures - An interconnection structure for a semiconductor device may include lower interconnection patterns disposed in a checker board shape and upper interconnection patterns disposed in a checker board shape and connecting two adjacent lower interconnection patterns to each other. | 2011-05-26 |
20110121456 | Techniques for Modular Chip Fabrication - Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform. | 2011-05-26 |
20110121457 | Process for Reversing Tone of Patterns on Integrated Circuit and Structural Process for Nanoscale Production - A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric. | 2011-05-26 |
20110121458 | Bonding Connection Between a Bonding Wire and a Power Semiconductor Chip - A bonding connection between a bonding wire and a power semiconductor chip is disclosed. The power semiconductor chip has a semiconductor body arranged in which is an active cell region with a multiplicity of cells arranged one following the other in a lateral direction and connected electrically in parallel. The semiconductor body has a surface portion arranged above the active cell region in a vertical direction perpendicular to the lateral direction. Applied to the surface portion is a metallization layer onto which a bonding wire is bonded. The bonding wire comprises an alloy containing at least 99% by weight aluminium and at least one further alloying constituent. The aluminum has a grain structure with a mean grain size which is less than 2 μm. | 2011-05-26 |
20110121459 | SEMICONDUCTOR INTERCONNECTION - Provided is a semiconductor interconnection wherein a barrier layer different from a TiO | 2011-05-26 |
20110121460 | SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE - A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second conductor pattern at a second region further away from, or closer to the third conductor pattern with regard to the first region via a second via-plug of a diameter smaller than the first via-plug, the extension part of the third conductor pattern, the first via-plug and the second via-plug form, together with the second interlayer insulation film, a dual damascene structure. | 2011-05-26 |
20110121461 | SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING A SEMICONDUCTOR DEVICE WITH A CLIP - A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip. | 2011-05-26 |
20110121462 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor chip includes a semiconductor chip body, a through-silicon via and a silicon pattern. The semiconductor chip body has a first surface and a second surface facing away from the first surface. The through-silicon via is formed to pass through the semiconductor chip body and has a metal layer and an insulation layer which protrude from the second surface. The silicon pattern is formed on a sidewall of the protruding through-silicon via. | 2011-05-26 |
20110121463 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE AND METHODS OF THE SAME - According to one embodiment, a semiconductor package is disclosed. The semiconductor package can include an insulative substrate having a first surface and a second surface opposed to the first surface, a first through hole formed in the insulative substrate from the first surface to the second surface, and a second through hole formed near the first through hole in the insulative substrate from the first surface to the second surface, a conductive body formed in the vicinity of the second through hole and penetrating into the insulative substrate, a first outer electrode formed on the first surface and connected to an one end of the conductive body, and a second outer electrode formed on the second surface and connected to the other end of the conductive body. | 2011-05-26 |
20110121464 | Semiconductor Device and Method of Forming Electrical Interconnect with Stress Relief Void - A semiconductor device has a semiconductor die with a plurality of tapered bumps formed over a surface of the semiconductor die. The tapered bumps can have a non-collapsible portion and collapsible portion. A plurality of conductive traces is formed over a substrate with interconnect sites. A masking layer is formed over the substrate with openings over the conductive traces. The tapered bumps are bonded to the interconnect sites so that the tapered bumps contact the mask layer and conductive traces to form a void within the opening of the mask layer over the substrate. The substrate can be non-wettable to aid with forming the void in the opening of the masking layer. The void provides thermally induced stress relief. Alternatively, the masking layer is sufficiently thin to avoid the tapered interconnect structures contacting the mask layer. An encapsulant or underfill material is deposited between the semiconductor die and substrate. | 2011-05-26 |
20110121465 | PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer. | 2011-05-26 |
20110121466 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP - An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer. | 2011-05-26 |
20110121467 | SEMICONDUCTOR DEVICE METAL PROGRAMMABLE POOLING AND DIES - A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication. | 2011-05-26 |
20110121468 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING SAME - An improved semiconductor package includes thermal tape placed over a top side of a die that is attached to a substrate with an underfill material. The tape extends to the substrate. The tape deforms with heat and entraps the die and underfill material. Air bubbles are trapped between the tape and the die and underfill material. The tape can be weighted and lined with an adhesive material. The tape aids in preventing the die from cracking due to mishandling. | 2011-05-26 |
20110121469 | PASSIVATION LAYER SURFACE TOPOGRAPHY MODIFICATIONS FOR IMPROVED INTEGRITY IN PACKAGED ASSEMBLIES - A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material. | 2011-05-26 |
20110121470 | FOAMING METHOD AND APPARATUS THEREFOR - A gas mixing/supplying device and a method includes of introducing a gas into a high-viscosity material. The method the steps of effecting a first suction stroke in which the piston ( | 2011-05-26 |
20110121471 | Carburetor - To enable a carburetor having a manual choke valve to be provided with a gas mixture of adequate concentration in accordance with the atmospheric temperature when an engine starts up and when the engine runs continuously right after starting up, there is provided an open-close valve | 2011-05-26 |
20110121472 | AERATION DEVICE FOR THE INTRODUCTION OF GAS BUBBLES INTO A LIQUID MEDIUM - An aeration device adapted for the introduction of gas into a liquid medium is provided, including an elongated primary distribution member with a proximal end adapted to be connected to a gas source and a distal end adapted to be immersed into the medium. Additionally, at least one aeration member is connected to the primary distribution member at a location on the distribution member spaced from the proximal end thereof and being in fluid communication with the distribution member, adapted for bringing the gas into a state entrappable within the liquid medium. Also, a flotation member is provided, mounted onto the primary distribution member and adapted to assume various positions along the distribution member according to the level of the liquid medium. An aeration system is also provided, the system including an array of aeration devices as described above. | 2011-05-26 |
20110121473 | Method for Fabricating Sintered Annular Nuclear Fuel Pellet Through Rod-Inserted Sintering - A method for fabricating a sintered annular nuclear fuel pellet includes: molding nuclear fuel powder or granules to fabricate an annular nuclear fuel green body; inserting a rod-like shaped structure into the annular nuclear fuel green body; sintering the rod-like shaped structure-inserted annular nuclear fuel green body in a reductive gas atmosphere; and separating the sintered annular nuclear fuel pellet from the rod-like shaped structure. | 2011-05-26 |
20110121474 | METHOD OF DRAWING MICROSTRUCTURED GLASS OPTICAL FIBERS FROM A PREFORM, AND A PREFORM COMBINED WITH A CONNECTOR - A method of manufacturing a microstructured fibre, includes: providing a preform having a plurality of elongate holes; mating at least one, but not all, of the holes with a connector to connect the hole(s) to an external pressure-controller; drawing the preform into the fibre whilst controlling gas pressure in the hole(s) connected to the pressure-controller. | 2011-05-26 |
20110121475 | Casting Method For Matrix Drill Bits And Reamers - An apparatus and method for manufacturing a down hole tool that reduces manufacturing costs and enhances the tool's performance. A belted mold assembly includes a casting assembly, a belt assembly, and a mid-belt. The belted mold assembly is used to fabricate a casting that allows for a larger diameter blank to be used which displaces the more expensive casting material and for using a smaller outer diameter thin-walled mold. The casting assembly is disposed within the belt assembly and the mid-belt is loaded in the volume created between the casting assembly's outer surface and the belt assembly's inner surface. The mid-belt provides a bracing for the casting assembly during the casting process. Optionally, a cap can be disposed on top of the blank for preventing metallurgical bonds from forming between the binder material and the upper portion of the blank. This allows for the excess binder material to remain high in purity so that it can be reprocessed. The cap can be used with the belted mold assembly or with a casting assembly known in the prior art. | 2011-05-26 |
20110121476 | ENCODED CONSUMABLE MATERIALS AND SENSOR ASSEMBLIES FOR USE IN ADDITIVE MANUFACTURING SYSTEMS - A consumable material and sensor assembly for use in an additive manufacturing system, the consumable material comprising an exterior surface having encoded markings that are configured to be read by the sensor assembly, where the consumable material is configured to be consumed in the additive manufacturing system to build at least a portion of a three-dimensional model. | 2011-05-26 |
20110121477 | Methods Of Operating An Extrusion Apparatus - Methods of operating an extrusion apparatus are provided for extruding ceramic or ceramic-forming material. The extrusion apparatus includes an extrusion die mounted with respect to a barrel. At least one screw is rotatably mounted within the barrel, and a feeder is configured to introduce a batch material to the screw. Example methods can adjust at least one of a rotational rate of the screw to an initial rotational rate or a feed rate of the feeder to an initial feed rate when based on a changed operating condition and/or when the batch material reaches the extrusion die. At least one of the rotational rate of the screw or the feed rate of the feeder can then be increased during a transient state until a steady state is reached. | 2011-05-26 |
20110121478 | Methods for Manufacturing Low Back Pressure Porous Cordierite Ceramic Honeycomb Articles - Disclosed are porous ceramic honeycomb articles, such as filters, which are composed predominately of a cordierite composition. The ceramic honeycomb articles possess a porous microstructure characterized by a unique combination of relatively high porosity (>45%), and moderately narrow pore size distribution wherein greater than 15% and less than 38% of the total porosity exhibits a pore diameter less than 10 μm, and low CTE wherein CTE≦6.0×10 | 2011-05-26 |
20110121479 | Forming Device for Manufacturing Profiled Semifinished Products, System with such a Forming Device and Method for Manufacturing Profiled Semifinished Products - Disclosed is a method for producing a profiled semifinished fiber composite (FC) product from a semifinished product ( | 2011-05-26 |
20110121480 | METHOD FOR MELT SPINNING, STRETCHING, AND WINDING A MULTIFILAMENT THREAD AS WELL AS A DEVICE FOR PERFORMING THE METHOD - A method for melt spinning, stretching, and winding a multifilament thread to form an FDY-yarn as well as a device for performing the method are presented. Hereby, a plurality of filaments are first extruded from thermoplastic melt, cooled to a temperature below the glass transition temperature of the thermoplastic material, and gathered to form a filament bundle without adding a preparation fluid. The filament bundle is then drawn-off at a speed above 1,500 m/min., heated to have a temperature above the glass transition temperature of the thermoplastic material, and stretched at a drawing speed above 4,000 m/min. Preparation of the filament bundle with a preparation fluid and winding the thread to form a spool is then performed. The device has the preparation device arranged in a zone of the thread course between the drawing device and the winding device, in which the thread has a thread-running speed above 4,000 m/min. | 2011-05-26 |
20110121481 | Fabric Comprising Shaped Conductive Monofilament Used in the Production of Non-Woven Fabrics - In an apparatus for the production of a non-woven web, structure, or article using a spun-bonding process in combination with a forming fabric which is woven having flat CMD yarns, flat MD yarns or both with some or all of such yarns being conductive so as to dissipate static electricity. | 2011-05-26 |
20110121482 | Methods of forming low static non-woven chopped strand mats - A method of forming a chopped strand mat formed of bonding materials and wet use chopped strand glass fibers (WUCS) which demonstrate a reduced occurrence of static electricity is provided. In one exemplary embodiment, the occurrence of static electricity on the glass fibers is reduced or eliminated by increasing the total solids content on the glass fibers, such as by applying an increased or excess amount of size composition to the glass fibers. Alternatively, an anti-static agent may be added directly to the sizing composition and applied to the glass filaments by any suitable application device. The antistatic agent may be applied to the wet chopped strand glass prior to chopping the strands or as the wet chopped strands are packaged. The static free wet use chopped strand glass fibers may be used in dry-laid processes to form chopped strand mats having a reduced tendency to accumulate static electricity. | 2011-05-26 |
20110121483 | CONTINUOUS CASTING DEVICE FOR PRODUCING PELLETS FROM PLASTIC MATERIAL AND METHOD FOR OPERATING THE SAME - The invention relates to a device for producing pellets from plastic material or from material to be pelletized. Said device comprises a continuous casting device ( | 2011-05-26 |
20110121484 | Method of producing a color enhanced surface seeded exposed aggregate concrete - An improved method is provided for producing a color enhanced surface seeded exposed aggregate concrete. The method includes preparing a subgrade or framework for receipt of a concrete mixture. Fill sand and/or rebar may be utilized for structural strength. A concrete mixture is poured over the subgrade. The surface of the concrete is floated or screeded to an appropriate slope. A color hardener is applied to the concrete surface to create a colorized concrete surface. The color hardener is troweled to provide uniformity of color. An aggregate is broadcast into the colorized concrete surface and than troweled to fully embed the aggregate in place. The aggregate is then exposed utilizing a chemical retardant or mechanical apparatus. Thereafter, preferably the color enhanced surface seeded exposed aggregate surface is washed and sealed. | 2011-05-26 |
20110121485 | METHOD AND APPARATUS FOR THE MANUFACTURE OF A FIBER - A method for the extrusion of a silk fibre from a water-soluble material which comprises providing the water-soluble material ( | 2011-05-26 |
20110121486 | METHOD OF MANUFACTURING SOLID SOLUTION PEFORATOR PATCHES AND USES THEREOF - Methods for fabricating and manufacturing solid solution perforators (SSPs) using sharp metal or glass needles and/or subsequent molding and use are described. The methods entail making microneedles by various precision machining techniques and micromold structures from curable materials. Various designs of patch, cartridge and applicator are described. Also described are methods for adjusting the microneedle mechanical strength using formulation and/or post-drying processes. | 2011-05-26 |
20110121487 | METHOD OF MANUFACTURING A COMPOSITE ELEMENT - A method of manufacturing a composite element. A stack of plies is assembled on a lay-up table, each ply comprising a plurality of reinforcement elements such as dry-fibres. A first part of the stack of plies is bound to form a partially bound stack of plies, a second part of the stack of plies remaining unbound. The partially bound stack of plies is press-formed in a mould cavity between a pair of mould tools to form a shaped pre-form, plies in the second part of the stack sliding against each other during the press-forming. A liquid matrix material is injected into the shaped pre-form in the mould cavity and subsequently cured. | 2011-05-26 |
20110121488 | Apparatus and method for producing structures with multiple undercut stems - A method is disclosed for producing structures having a plurality of stems extending away from a fenestrated base to undercut islands projecting over fenestrations in the base. Such structures include slidingly-engaging fastener portions, self-engaging fasteners, uni-directional stepped fasteners, fastening segments integral with larger product components, and other structures with similar aspects. The method includes providing a set of partially bypassing dies to define a fenestrated common cavity contiguous with pluralities of undercut stem chambers and a terminal chamber, filling the cavity with a ductile moldable material, engaging the dies, and releasing the resultant product. | 2011-05-26 |
20110121489 | COMPRESSION MOLDING APPARATUS, AND SYNTHETIC RESIN CONTAINER MANUFACTURING METHOD - In supplying a predetermined amount of a molten resin D between an upper mold | 2011-05-26 |
20110121490 | Mold Apparatus - A mold apparatus includes a core having a mold cavity for molding an article and a gate for allowing molten plastics to flow into the mold cavity therefrom. An ejector pin is arranged with a distal end thereof facing and adjacent to the gate. The ejector pin is movable with respect to the gate for making the distal end thereof close the gate or depart from the gate. The mold apparatus is capable of automatically separating redundant parts from an article without burrs. | 2011-05-26 |
20110121491 | Method For Manufacturing Three-Dimensional Objects and Machine Employing Said Method - Method for manufacturing three-dimensional objects (W) consisting of superimposed layers (L) of a base material (M), liquid at ambient temperature and capable of solidifying permanently following a stimulating action, comprising the following operations: spreading a layer (L | 2011-05-26 |
20110121492 | METHOD FOR MANUFACTURING A THREE-DIMENSIONAL OBJECT - Method of manufacturing a three-dimensional object according to which the object is built layer-wise by solidification of a building material, wherein a test specimen is built which is excited to oscillate after being built and wherein natural frequencies of the oscillations are determined. | 2011-05-26 |
20110121493 | METHOD FOR MANUFACTURING CERAMIC FIRED BODY AND METHOD FOR MANUFACTURING HONEYCOMB STRUCTURED BODY - A method for manufacturing a ceramic fired body includes molding and degreasing a ceramic raw material to manufacture a ceramic degreased body. The ceramic degreased body is fired in a continuous firing furnace. The firing step includes preheating the ceramic degreased body up to a preheating temperature of at least about 1500° C. and at most about 2000° C. by resistance heating with a resistance heating mechanism. High-temperature firing includes heating the ceramic degreased body from the preheating temperature to a firing temperature of at least about 2000° C. and at most about 2300° C. by both the resistance heating with the resistance heating mechanism and direct energizing heating in which the ceramic degreased body is energized and heated. The temperature of the ceramic degreased body is held at the firing temperature. | 2011-05-26 |
20110121494 | Method for the Production of an Electrically Insulating Cast Body and Base for a Lamp - A method for the production of an electrically insulating cast body having one or more electronic components that are arranged in a plastic casting chamber ( | 2011-05-26 |
20110121495 | CARBON NANOTUBE (CNT) EXTRUSION METHODS AND CNT WIRE AND COMPOSITES - A carbon nanotube (CNT) extrusion system includes a carbon source, an extrusion die having a baseplate having a plurality of die sets, each die set has a plurality of through-holes in fluid communication with the carbon source and a corresponding plurality of template tubes connected at one end to the baseplate and coaxial with the through-holes, each template tube includes a catalyst for forming a CNT structure in combination with the carbon source. An oscillating mechanism operatively associated with the free end of each template tube axially oscillates the template tubes to alternately form and release the CNT structure within each template tube in a continuous manner. The oscillating mechanism can be an alternating electric field or magnetic field applied to the template tubes, the frequency of the electric or magnetic field being synchronized with a formation rate of the CNT within the template tubes. | 2011-05-26 |
20110121496 | SHAPE MANIPULATION OF NANOSTRUCTURES - A method for reshaping a nanostructure. The method includes applying a vector force to the nanostructure to obtain a desired shape and passing current through the nanostructure thereby reshaping the nanostructure to a reshaped geometry different from the initial shape. The nanostructure may additionally be cleaned. | 2011-05-26 |
20110121497 | PLANT FOR BLOW-MOULDING PLASTIC CONTAINERS, PARTICULARLY BOTTLES - A plant for blow-moulding plastic containers ( | 2011-05-26 |
20110121498 | METHOD FOR PRODUCING RARE EARTH SINTERED MAGNET - The present invention relates to a method for producing a rare earth sintered magnet including the steps of: molding a mixture of magnetic powder containing a rare earth compound and oil-extended rubber containing oil and rubber to produce a molded body; removing the oil-extended rubber from the molded body; and calcining the molded body from which the oil-extended rubber is removed to produce a rare earth sintered magnet | 2011-05-26 |
20110121499 | CUSHION MECHANISM - A cushion mechanism includes a four-bar linkage and at least one hinge assembly. The four-bar linkage includes a first link member, a second link member, a third link member, and a fourth link member forming a quadrangle. The at least one hinge assembly connects two joined link members. The at least one hinge assembly includes a shaft extending through the two joined link members, a fixing member, a rotating member, and an elastic member. The fixing member, the rotating member, and the elastic member are sleeved on the shaft. One of the fixing member and the rotating member forms a protrusion, and the other defines a slot receiving the protrusion. | 2011-05-26 |
20110121500 | VIBRATION ABSORBER FOR A VEHICLE SUSPENSION SPRING - A dynamic vibration absorber for a vehicle suspension system includes a spring elastically supporting a vehicle body on a vehicle frame, the spring including multiple coils, an isolator secured to at least one of the coils, at least a portion of the isolator being elastically displaceable in response to movement of said one of the coils, and a mass formed as unit with the isolator portion, and supported on the isolator for elastic movement. | 2011-05-26 |
20110121501 | Methods, Systems, and Products for Welding Grounding Rods - Methods, systems, apparatuses, and products are disclosed for welding ground wires to a grounding rod. A jig retains the ground wires to the grounding rod. The jig has a first horseshoe oriented to a second horseshoe to form a crucifix. Each horseshoe has a pair of legs supporting the jig from earth and providing electrical ground to the earth. A central passage bisects each horseshoe through which the grounding rod inserts. Means are included for clamping a ground wire to at least one of the legs, such that the ground wire is retained for welding to the grounding rod. | 2011-05-26 |