21st week of 2014 patent applcation highlights part 29 |
Patent application number | Title | Published |
20140140106 | ADAPTIVE DEAD TIME CONTROL SCHEME FOR SWITCH MODE POWER CONVERTER WITH SYNCHRONOUS RECTIFIERS TOPOLOGY - An adaptive dead time (ADT) control scheme for use with a switch mode power converter having a full bridge with synchronous rectifiers topology. A controller which implements the control scheme includes an input circuit arranged to receive a signal representative of the converter's output voltage, and an output circuit arranged to operate the converter's switching elements and synchronous rectifiers to produce a desired output voltage. The controller is further arranged such that the converter's “dead time” is adaptively varied in an inverse relationship to the magnitude of the load current. In a preferred embodiment, the signals used to operate the synchronous rectifiers are PWM signals, and the controller adaptively varies the dead time in a linear inverse relationship to the magnitude of the load current by modulating the rising and falling edges of the signals used to operate the synchronous rectifiers. | 2014-05-22 |
20140140107 | ISOLATED POWER CONVERTER, INVERTING TYPE SHUNT REGULATOR, AND OPERATING METHOD THEREOF - An isolated power converter, an inverting type shunt regulator, and an operating method thereof are disclosed. The isolated power converter includes a transformer, an inverting type shunt regulator, a controller, and an optocoupler. The inverting type shunt regulator is located on the secondary side of the transformer. The inverting type shunt regulator includes an error amplifier and a MOSFET. The controller is located on the primary side of the transformer. The controller includes an inverting unit cooperated with the MOSFET. The controller receives a feedback voltage. The optocoupler is coupled to the inverting type shunt regulator and the controller to provide an opto-coupling current to the controller. | 2014-05-22 |
20140140108 | CONTROLLER FOR GENERATING JITTERS IN A CONSTANT CURRENT MODE OF A POWER CONVERTER AND METHOD THEREOF - A controller for generating jitters in a constant current mode of a power converter includes a current pin, an auxiliary pin, a constant current control unit, and a control signal generation unit. The current pin is used for receiving a primary side voltage determined according to a resistor and a primary side current flowing through the power converter. The auxiliary pin is used for receiving a voltage corresponding to an auxiliary winding of the power converter. The constant current control unit is used for generating an adjustment signal according to the primary side voltage, a discharge time corresponding to the voltage, and a reference voltage. The reference voltage has a predetermined range jitter voltage. The control signal generation unit is used for adjusting a period of a gate control signal according to the adjustment signal. | 2014-05-22 |
20140140109 | FLYBACK POWER SUPPLY REGULATION APPARATUS AND METHODS - Apparatus and methods disclosed herein are associated with a primary side voltage and/or current regulator (PSR) in a flyback power converter. Apparatus and methods sense characteristics of a waveform generated in an auxiliary primary winding of a flyback transformer at a single terminal of the PSR. The waveform is analyzed, and error signals derived therefrom are used to maintain constant voltage and/or constant current regulation and to generate a peak current stabilization signal that is independent of line input voltage. | 2014-05-22 |
20140140110 | Switch Mode Power Supply and Method for Operating the Switch Mode Power Supply - A switch mode power supply and method for operating the power supply and to the use of the same, wherein the switch mode power supply comprises a control for controlling a control element and is connected to a DC link of the converter, the switch mode power supply comprises a startup-delay such that control of the switch element is blocked until a predetermined start delay duration (T) has lapsed, where the start delay duration (T) is longer than the time span between DC link charging. | 2014-05-22 |
20140140111 | REACTOR, CONVERTER AND POWER CONVERSION DEVICE - A reactor includes a coil formed by winding a wire, and a magnetic core in which a closed magnetic path is formed by both an inner core portion inserted in the coil and an outer core portion covering outer peripheral surfaces of the inner core portion and the coil. The outer core portion is formed of a mixture containing a magnetic material and resin. One of the coil and the inner core portion has an exposed portion where a part of the outer peripheral surface is not covered with the outer core portion, and at least a part of the exposed portion is in contact with a heat dissipation layer provided in a heat dissipation plate. | 2014-05-22 |
20140140112 | POWER CONVERSION APPARATUS WITH LOW COMMON MODE NOISE AND APPLICATION SYSTEMS THEREOF - A power conversion apparatus, comprising: a power conversion circuit comprising an AC source; a power conversion unit with DC terminals and AC terminals; a filter inductor unit including first and second terminals, the first terminals of the filter inductor unit being connected to the AC source, the second terminals of the filter inductor unit being connected to the AC terminals of the power conversion unit; a common mode noise suppression circuit comprising a capacitive impedance network including first and second terminals; an impedance balancing network including first and second terminals; the second terminals of the capacitive impedance network are connected to the first terminals of the impedance balancing network, the first terminals of the capacitive impedance network are connected to the first terminals of the filter inductor unit, and the second terminals of the impedance balancing network are connected to the DC terminals of the power conversion unit. | 2014-05-22 |
20140140113 | AC-DC RESONANT CONVERTER THAT PROVIDES HIGH EFFICIENCY AND HIGH POWER DENSITY - The disclosed embodiments provide an AC/DC power converter that converts an AC input voltage into a DC output voltage. This AC/DC power converter includes an input rectifier stage which rectifies an AC input voltage into a first rectified voltage of a first constant polarity and a first amplitude. The AC/DC power converter also includes a switching resonant stage which is directly coupled to the output of the input rectifier stage. This switching resonant stage converts the rectified voltage into a second rectified voltage of a second constant polarity and a second amplitude. The AC/DC power converter additionally includes an output rectifier stage coupled to the output of the switching resonant stage, wherein the output rectifier stage rectifies the second rectified voltage into a DC voltage output. | 2014-05-22 |
20140140114 | FULL-BRIDGE POWER CONVERTER - A full-bridge power converter is provided. A control unit | 2014-05-22 |
20140140115 | Monolithic AC/DC Converter for Generating DC Supply Voltage - An integrated circuit (IC) comprises a rectifier/regulator circuit coupled to receive an ac source voltage and output a regulated dc voltage. The rectifier/regulator circuit includes first and second switching elements that provide charging current when enabled. The first and second switching elements do not provide charging current when disabled. A sensor circuit is coupled to sense the regulated dc voltage and generate a feedback control signal coupled to the rectifier/regulator circuit that enables the first and second switching elements when the regulated do voltage is above a target voltage, and disables the first and second switching elements when the regulated do voltage is below the target voltage. | 2014-05-22 |
20140140116 | SWITCHING CONVERTER AND METHOD FOR CONTROLLING THE SWITCHING CONVERTER - A switching converter and method for controlling a switching converter in a quasi resonant mode of operation, wherein a sense voltage is predefined for a PWM controller to determine a switch off time of a switching element, a switch-on time of the switching element also falls in a valley of an oscillating voltage that is being applied to the switched-off switching element, and where the sense voltage is reduced in each valley occurring after a switch-off operation such that a stable operating point is thus reached under any load. | 2014-05-22 |
20140140117 | ELECTRIC POWER CONVERTER - The passage from a cooling medium inlet to a cooling medium outlet of a cooler includes: an upstream cooling portion and a downstream cooling portion for cooling heat generating bodies; an upstream distribution portion located on the cooling medium inlet side; a downstream distribution portion located on the cooling medium outlet side; a connecting portion for connecting the upstream cooling portion and the downstream cooling portion; and a partition portion for partitioning the upstream cooling portion and the downstream cooling portion, and the upstream distribution portion and the downstream distribution portion. The passage is connected so that the cooling medium flows in order of the upstream distribution portion, the upstream cooling portion, the connecting portion, the downstream cooling portion, and the downstream distribution portion. | 2014-05-22 |
20140140118 | CONNECTION STRUCTURE AND INVERTER - Two opening through which a refrigerant runs are connected by a first connecting pipe and a second connecting pipe. One end of the first connecting pipe is connected to a first opening by a planar seal. Another end of the first connecting pipe is connected to one end of a second connecting pipe by a shaft seal. Another end of the second connecting pipe is connected to a second opening by a planar seal. An axial direction of a shaft seal is perpendicular to a plane that includes the first opening. | 2014-05-22 |
20140140119 | Power Inverter - A power inverter includes a plurality of power modules; a first casing housing the power modules and a cooling path in which a coolant flows is formed; a plurality of AC busbars connected to AC terminals of the power modules; a holding member, in which a positioning pin protruding to an upper side in a direction opposite to the first casing is formed, that maintains the AC busbars and is fixed to the first casing; a current sensor module including a plurality of current sensors detecting the AC currents of the AC busbars; a frame body for maintaining the current sensors, and a lead terminal protruding from the frame body to the upper side; and a driver circuit board, in which a through-hole used for the lead terminal and a board positioning through-hole are formed, arranged on the upper side of the frame body arranged on the holding member. | 2014-05-22 |
20140140120 | MEMORY CELL AND MEMORY CELL ARRAY USING THE SAME - A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided. | 2014-05-22 |
20140140121 | High-Performance Scalable Read-Only-Memory Cell - A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing. | 2014-05-22 |
20140140122 | ARRAY VOLTAGE REGULATING TECHNIQUE TO ENABLE DATA OPERATIONS ON LARGE CROSS-POINT MEMORY ARRAYS WITH RESISTIVE MEMORY ELEMENTS - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal. | 2014-05-22 |
20140140123 | PRESERVATION CIRCUIT AND METHODS TO MAINTAIN VALUES REPRESENTING DATA IN ONE OR MORE LAYERS OF MEMORY - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 2014-05-22 |
20140140124 | RESISTIVE MEMORY DEVICE HAVING SELECTIVE SENSING OPERATION AND ACCESS CONTROL METHOD THEREOF - A method of controlling a read operation of a resistive memory device is provided which includes activating at least one of a plurality of word lines in response to a first command; after receiving a second command, sensing data of a memory cell, corresponding to a selected page, from among all memory cells connected with the activated word line through a corresponding bit line sense amplifier; and outputting the sensed data as read data according to a sensing output control signal. | 2014-05-22 |
20140140125 | SEMICONDUCTOR DEVICE AND CONTROL METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device is provided with the variable resistance element, and a control circuit that controls a resistance state of the variable resistance element by controlling current between a first end and a second end of the variable resistance element. The control circuit causes the variable resistance element to change from a first resistance state to a second resistance state by having a first current flow from the first end to the second end of the variable resistance element. In addition, after a second current smaller than the first current is made to flow from the first end to the second end of the variable resistance element, the control circuit causes the variable resistance element to change from the second resistance state to the first resistance state by having a third current flow from the second end to the first end thereof. | 2014-05-22 |
20140140126 | MAGNETIC STORAGE ELEMENT, MAGNETIC STORAGE DEVICE, MAGNETIC MEMORY, AND DRIVING METHOD - A magnetic storage element includes a magnetic nanowire. A cross-section of the magnetic nanowire has first and second visible outlines, the first visible outline has a first minimal point at which a distance from a virtual straight line becomes minimal, a second minimal point at which the distance from the virtual straight line becomes minimal, and a first maximal point at which the distance from the virtual straight line becomes longest between the first minimal point and the second minimal point, and an angle between a first straight line connecting the first minimal point and the second minimal point, and one of a second straight line connecting the first minimal point and the first maximal point and a third straight line connecting the second minimal point and the first maximal point is not smaller than four degrees and not larger than 30 degrees. | 2014-05-22 |
20140140127 | MAGNETIC RANDOM ACCESS MEMORY APPARATUS, METHODS FOR PROGRAMMING AND VERIFYING REFERENCE CELLS THEREFOR - A magnetic random access memory apparatus includes a memory cell array including a plurality of magnetic memory cells; a reference cell array including a pair of reference magnetic memory cells; a write driver configured to program data in the memory cell array and the reference cell array; and a first switching unit configured to form a current path which extends from a bit line connected to the write driver via the reference cell array including the pair of reference magnetic memory cells to a source line connected to the write driver or a current path which extends from a source line connected to the write driver via the reference cell array including the pair of reference magnetic memory cells to a bit line connected to the write driver. | 2014-05-22 |
20140140128 | Processors and Systems with Divided-Down Phase Change Memory Read Voltages - Methods and systems for fast, low power PCM memory using a bitline precharge scheme in which unselected bitlines are driven to predetermined voltages and a selected bitline is set to ground, such that when selected and unselected bitlines are shorted together, the selected bitline is charged to a PCM sense voltage. Inventive methods and systems do not require a precharge voltage regulator to drive selected bitlines to a sense voltage. | 2014-05-22 |
20140140129 | PROGRAMMING METHOD FOR NAND FLASH MEMORY DEVICE TO REDUCE ELECTRONS IN CHANNELS - In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described. | 2014-05-22 |
20140140130 | SEMICONDUCTOR MEMORY DEVICE FOR AND METHOD OF APPLYING TEMPERATURE-COMPENSATED WORD LINE VOLTAGE DURING READ OPERATION - A semiconductor memory device configured to apply a temperature-compensated word line voltage to a word line during a data read operation includes a memory cell array including a plurality of word lines, a plurality of non-volatile memory cells connected to the word lines, and a word line voltage application unit configured to apply a temperature-compensated read voltage to a selected word line and to apply a temperature-compensated pass voltage to at least one unselected word line during a read operation. | 2014-05-22 |
20140140131 | THREE DIMENSIONAL GATE STRUCTURES WITH HORIZONTAL EXTENSIONS - A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure. | 2014-05-22 |
20140140132 | FLASH MEMORY CIRCUIT - A memory circuit is provided, including: a plurality of sectors, where each sector includes at least two parallel rows of memory units; a first control line, a second control line and a word line corresponding to each row of memory units, where at least two of the first control lines which are in the same sector and neighboring with each other are connected, and at least two of the second control lines which are in the same sector and neighboring with each other are connected; and a plurality of bit lines perpendicular with the word lines. The number of the first and second control lines may be reduced, so decoding units which control the control lines may occupy less chip areas, thereby reducing chip areas occupied by the memory circuit. | 2014-05-22 |
20140140133 | SEMICONDUCTOR DEVICE - To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device. | 2014-05-22 |
20140140134 | APPARATUS AND METHODS INCLUDING A BIPOLAR JUNCTION TRANSISTOR COUPLED TO A STRING OF MEMORY CELLS - Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described. | 2014-05-22 |
20140140135 | STORAGE DEVICE, RECOVERY METHOD, AND RECORDING MEDIUM FOR RECOVERY PROGRAM - A storage device includes a control device that controls an access to storage, a volatile memory that stores data that is used for operation control of the control device, and a non-volatile memory is a backup destination of the data. Furthermore a storage device includes a detection unit that detects a failure occurred in the control device, a determination unit that determines whether or not backup data that is stored in the non-volatile memory is valid when the detection unit detects the failure occurred in the control device, and a control unit that causes the control device to execute a first processing of restoring the backup data of the non-volatile memory in the volatile memory after restart-up without backup of the data of the volatile memory, when the determination unit determines that the backup data of the non-volatile memory is valid. | 2014-05-22 |
20140140136 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor device includes storing LSB data in a LSB page included in plural pages of corresponding word line group of a first memory block, generating a data combination signal by combining plural sets of LSB data after the step of storing LSB data, storing the data combination signal in a second memory block, and storing MSB data in a MSB page included in the plural pages. | 2014-05-22 |
20140140137 | NAND-TYPE NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a NAND-type non-volatile semiconductor storage includes a memory cell array and a control circuit. The memory cell array has a memory string in which more than one of memory cells are connected in series, a word line connected to more than one of memory cells, and a bit line connected to one end of the memory string. The control circuit performs a program operation, a verify operation, and a step-up operation in a program operation loop. The control circuit performs the program operation to apply a program voltage to the word line. The control circuit performs the verify operation after the program operation. The control circuit performs the step-up operation to program a memory cell judged to be insufficiently programmed at the verify-read operation using a step-up voltage. The control circuit sets the step-up voltage increasing, each time the step-up operation is performed. | 2014-05-22 |
20140140138 | Three-Dimensional Flash Memory System - A three-dimensional flash memory system is disclosed. | 2014-05-22 |
20140140139 | INTERCONNECTION MATRIX USING SEMICONDUCTOR NON-VOLATILE MEMORY - An interconnection matrix consists of a plurality of semiconductor Non-Volatile Memory (NVM) forming an M×N array. Semiconductor NVM devices in the array are either programmed to a high threshold voltage state or erased to a low threshold voltage state according to a specific interconnection configuration. Applied with a gate voltage bias higher than the low threshold voltage and lower than the high threshold voltage to the control gates of the entire semiconductor NVM devices in the array, the configured interconnection network is formed. The disclosed interconnection matrix can be applied to configuring circuit routing in Integrated Circuit (IC). | 2014-05-22 |
20140140140 | Vertical Nonvolatile Memory Devices and Methods of Operating Same - Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST). | 2014-05-22 |
20140140141 | READ MARGIN MEASUREMENT IN A READ-ONLY MEMORY - Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit. | 2014-05-22 |
20140140142 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROGRAMMING DATA THEREOF - A method for programming data is provided for a memory storage device having a rewritable non-volatile memory module and a buffer memory. The method includes receiving a plurality of data including a first-type data and at least one second-type data, and a size of the first-type data is smaller than a data size threshold. The method includes temporarily storing the plurality of data into the buffer memory, and programming the first-type data and at least one part of the at least one second-type data stored in the buffer memory into a physical program unit set if it is determined that the plurality of data are complied with a predetermined condition. The method includes obtaining writing statuses of the first-type data and the at least one part of the at least one second-type data at the same time. | 2014-05-22 |
20140140143 | MEMORY CIRCUIT AND METHOD OF OPERATING THE MEMORY CIRCUIT - A memory circuit includes a memory cell, a data line coupled to the memory cell, a sense amplifier having an input terminal, a precharge circuit coupled to the input terminal of the sense amplifier, a first transistor of a first type, and a second transistor of the first type. The first transistor is coupled between the input terminal of the sense amplifier and the data line, and the second transistor is coupled between to the input terminal of the sense amplifier and the data line. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage lower than the first threshold voltage. | 2014-05-22 |
20140140144 | SENSE AMPLIFIER CIRCUIT - A sense amplifier circuit includes first and second signal lines and first and second inverters. Each inverter includes an input terminal, an output terminal, and a power source terminal. A second signal line potential is supplied to the first inverter input terminal. The second inverter input terminal is connected to the first inverter output terminal, and the second inverter output terminal is connected to the first inverter input terminal. A first signal line potential is supplied to the second inverter input terminal. A first switch transistor is connected to the first inverter power source terminal and has a gate connected to the second signal line. A switch second transistor is connected to the second inverter power source terminal and has a gate connected to the first signal line. | 2014-05-22 |
20140140145 | SEMICONDUCTOR DEVICE - A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing. | 2014-05-22 |
20140140146 | POWER-EFFICIENT, SINGLE-ENDED TERMINATION USING ON-DIE VOLTAGE SUPPLY - Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal. | 2014-05-22 |
20140140147 | STATIC RANDOM ACCESS MEMORY CIRCUIT WITH STEP REGULATOR - Implementations of the present disclosure involve a circuit and/or method for providing a static random access memory (SRAM) component of a very large scale integration (VLSI) design, such as a microprocessor design. In particular, the present disclosure provides for an SRAM circuit that includes a step voltage regulator coupled to the SRAM circuit and designed to maintain a fixed-value voltage drop across the regulator rather than a fixed voltage across the load of the SRAM circuit. The fixed-value drop across the regulator allows the SRAM circuit to be operated at a low retention voltage to reduce leakage of the SRAM circuit while maintaining the parasitic decoupling capacitance across the power supply from the SRAM circuit to reduce power signal fluctuations. In addition, the regulator circuit coupled to the SRAM circuit may include a switch circuit to control the various states of the SRAM circuit. | 2014-05-22 |
20140140148 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes performing a pre-read and a first main read to selected memory cells in response to a read request, and performing a second main read to the selected memory cells in response to a re-read request. | 2014-05-22 |
20140140149 | Strobe Acquisition and Tracking - A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value. | 2014-05-22 |
20140140150 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a bank; a temperature sensor configured to generate a temperature voltage of which voltage level is changed according to a temperature variation of the bank; and a timing control block configured to control a timing of a signal to be inputted to the bank, according to the voltage level of the temperature voltage. | 2014-05-22 |
20140140151 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a data alignment control signal generation unit configured to output a data alignment control signal by generating a pulse when a tuning mode signal is enabled, and generate the data alignment control signal as a count pulse is inputted after the data alignment control signal generated by the tuning mode signal is outputted; a timing control block configured to determine a delay amount according to delay codes, generate a delay control signal by delaying the data alignment control signal, and output a timing control signal by latching the delay control signal at an enable timing of a data output control signal; a delay time control block configured to generate the delay codes; and a data alignment unit configured to convert parallel data into serial data, and change a data sequence of the serial data in response to the timing control signal. | 2014-05-22 |
20140140152 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal. | 2014-05-22 |
20140140153 | REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not. | 2014-05-22 |
20140140154 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH LEVERAGING DRIVING METHOD THEREOF - A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address. | 2014-05-22 |
20140140155 | SEMICONDUCTOR DEVICE AND METHOD INCLUDING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE - A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command. | 2014-05-22 |
20140140156 | MEMORY OPERATIONS USING SYSTEM THERMAL SENSOR DATA - Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack. | 2014-05-22 |
20140140157 | Complementary Metal-Oxide-Semiconductor (CMOS) Min/Max Voltage Circuit for Switching Between Multiple Voltages - A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption and electro-migration effects. The voltage selection mechanism comprises cross-coupled circuitry, which comprises a first positive-channel field effect transistor (PFET) and a second PFET. The voltage selection mechanism further comprises diode circuitry, which comprises a third PFET and a fourth PFET. | 2014-05-22 |
20140140158 | PRE-CHARGING A DATA LINE - A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver. | 2014-05-22 |
20140140159 | SHORT ASYNCHRONOUS GLITCH - A circuit receives a parameter signal at a set or reset input, a clock signal at a clock input and a constant digital value at a data input. A synchronous signal is output from the circuit: wherein when the parameter signal is in a first state, then the output synchronous signal has the digital value; wherein when the parameter signal transitions to a second state, then the output synchronous signal transitions to an inverse of the digital value at substantially the same time; and wherein when the parameter signal transitions back to the first state, then the output synchronous signal transitions to the digital value on a next clock edge. | 2014-05-22 |
20140140160 | Semiconductor Device - A semiconductor device has an antifuse element and a measurement unit. The antifuse element stores information according to whether the antifuse element is in the broken or unbroken state. The measurement unit determines a resistance value related to the resistance value of the broken antifuse element | 2014-05-22 |
20140140161 | NON-VOLATILE MEMORY ROBUST START-UP USING ANALOG-TO-DIGITAL CONVERTER - In accordance with at least one embodiment, an onboard analog-to-digital converter (ADC) on a system-on-a-chip (SOC) is utilized to determine whether a charge pump output for a non-volatile memory (NVM) is correct or not. The SOC is directed to wait until the output is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the SOC such that the application can react to it. | 2014-05-22 |
20140140162 | MEMORY CELL ARRAY WITH RESERVED SECTOR FOR STORING CONFIGURATION INFORMATION - A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device. | 2014-05-22 |
20140140163 | AGITATION DEVICE - The present invention provides an agitation device ( | 2014-05-22 |
20140140164 | Homogeneity Sensor For Product Blender/Mixer - A method and apparatus for monitoring the degree of blending of the constituents of a mixture being churned in a blender involves placement of a dielectric properties sensor in a wall of the blender. In that such sensors respond to moisture content, density and temperature of the ingredients, when the sensor output reaches a steady-state, it is indicative of arrival of a homogenous mix. | 2014-05-22 |
20140140165 | STIRRING BLADE AND SUPPORT PLATE FOR USE IN A MIXING VAT HAVING A BOTTOM SURFACE - The present disclosure relates to a stirring blade for attachment to a support plate, and to a combination of a stirring blade and of a support plate, for use in a mixing vat of a mixing apparatus. The support plate is attached to a driving element of the mixing apparatus. The stirring blade has an elongate section for mixing a content of the vat. The stirring blade also defines an aperture for attachment of the stirring blade to the support plate. The aperture is configured so that raising the stirring blade away from the bottom surface of the vat causes an upper surface of the stirring blade to abut on a stop of the support plate, and raising the driving element and the support plate away from the bottom of the vat allows the stirring blade to pivot downward about the support plate for easy removal of the stirring blade. | 2014-05-22 |
20140140166 | Dual Component Mixing Bag - A container has elastomeric sheets defining a periphery with four sides. A seal extends about the periphery defining a closed chamber. A separator extends across the closed chamber dividing the closed chamber into a first compartment and a second compartment. The separator includes a rod for wrapping the sheets around the rod to define a dividing portion. A retainer clip presents an inner wall clamped about the dividing portion providing an impermeable closure between the sheets. The sheets define at least two aligned and spaced pockets separated by a gap whereby removing the rod from the retainer clip and inserting the rod into the pockets extending across the gap and clamping the retainer clip over the rod to define a handle. The present invention also includes a method for mixing a first component and a second component in the container and releasing the components. | 2014-05-22 |
20140140167 | Non Destructive Testing Apparatus and Method Using Ultrasound Imaging - Improved imaging is provided for structures under test that have propagation direction dependent ultrasound propagation speed or position dependent ultrasound propagation speed due to fibrous, coarse grain or single crystalline material. A set reflection points is selected in the structure under test and ultrasound propagation time delays between the reflection point or points on one hand and the plurality of positions on the other hand that fit an observed time delay of the detected reflections are computed. This may be done by means of an iterative method. In the iterative method a synthetically focused ultrasound beam is realized by summing measurements after compensation for propagation time delay from different transmitting transducers to the reflection points. Time delays to receiving transducers are measured from the arrival time of reflections of this synthetically focused ultrasound beam, and the propagation time delay from different transmitting transducers is iteratively adapted until it matches time delays corresponding to the measured arrival times. Time delays to other points in the structure under test are interpolated between the selected reflection points and used in the computation of an image of reflections within the structure under test. | 2014-05-22 |
20140140168 | SEISMIC SURVEY METHOD - Method of performing a 3-D seismic survey using a plurality of vibroseis sources, and an array of seismic sensors arranged within a survey area. Each vibroseis source emits a distinctive acoustic signal and each seismic sensor of the array is in a continuous state of readiness to detect reflected acoustic signals. The method includes assigning vibroseis points (VPs) to each vibroseis source, moving each vibroseis source to assigned VPs where the vibroseis source emits an acoustic signal, recording the emission time of the acoustic signal by each vibroseis source at its assigned VPs together with the geographic position of the assigned VPs, continuously listening for reflected acoustic signals using the seismic sensors and recording a time domain record of the reflected acoustic signals received by each seismic sensor. Reflected acoustic signals associated with emission of an acoustic signal by a vibroseis source at an assigned VP are then determined. | 2014-05-22 |
20140140169 | STEERABLE TOWED SIGNAL SOURCE - Techniques are disclosed relating to steering a signal source towed behind a survey vessel. In one embodiment, a method includes towing a signal source and a streamer in a body of water. The signal source includes a steering mechanism. The method further includes determining a current heading of the streamer and, based on the determined heading, using the steering mechanism to adjust a heading of the signal source. In some embodiments, the method also includes determining a current heading of the signal source based on location information received from one or more location buoys coupled to the signal source, and, based on the determined heading of the signal source, using the steering mechanism to adjust the heading of the signal source. In one embodiment, the steering mechanism is used to align the heading of the signal source with the heading of the streamer. | 2014-05-22 |
20140140170 | JET-PUMP-BASED AUTONOMOUS UNDERWATER VEHICLE AND METHOD FOR COUPLING TO OCEAN BOTTOM DURING MARINE SEISMIC SURVEY - An autonomous underwater vehicle (AUV) is configured to record seismic signals during a marine seismic survey. The AUV includes a body having a base (B) and first and second sides (A, C), the body having a head part and a tail part; a propulsion system for guiding the AUV to a final target on the ocean bottom; jet pumps connected to corresponding nozzles on the first and second sides (A, C); a control device connected to the jet pumps; and a seismic sensor configured to record seismic signals. The jet pumps are actuated by the control device in a given sequence so that the base (B) penetrates into the ocean bottom. | 2014-05-22 |
20140140171 | METHODS AND SYSTEMS FOR EXTRAPOLATING WAVEFIELDS - Methods and Systems for extrapolating wavefields while avoiding disruptions due to spatial aliasing are disclosed. Pressure wavefields measured with pressure sensors and vertical and horizontal velocity wavefields measured with three-axial motions sensors may be spatially aliased in at least one horizontal direction. The pressure wavefield and/or the vertical velocity wavefield are decomposed into one of an up-going wavefield and a down-going wavefield. The up-going or down-going wavefield is extrapolated using an extrapolator that depends on components of a slowness vector. In order to avoid disruptions in the extrapolated wavefield due to spatial aliasing, the components of the slowness vector are calculated from the measured pressure wavefield and the two horizontal velocity wavefields. | 2014-05-22 |
20140140172 | DEGHOSTING MEASURED SURVEY DATA - Propagation of wavefields are simulated along paths in a survey environment, where the simulated propagation includes an influence of a reflection at an interface that causes ghost data in measured survey data. Deghosting of the measured survey data is performed using the simulated wavefields. | 2014-05-22 |
20140140173 | Land Seismic Devices, Systems and Methods - Devices, systems and methods for land seismic. The devices include an above-ground storage tank in which an acoustic energy source is immersed in liquid. The above-ground storage tank may be portable, reusable, self-supporting and may lay flat when empty of liquid and rise on its own when being filled with liquid. The systems include the seismic source-storage tank device, one or more sensors for recording signals that are generated when the source is activated, and a processor for analyzing the recorded signals for geophysical information. The methods involve methods of inducing seismic waves using the seismic source-storage tank devices, and methods of conducting seismic surveys using the seismic source-storage tank devices. | 2014-05-22 |
20140140174 | REDUCING RUN TIME IN SEISMIC IMAGING COMPUTING - A system, method and computer program product for seismic imaging implements a seismic imaging algorithm utilizing Reverse Time Migration technique requiring large communication bandwidth and low latency to convert a parallel problem into one solved using massive domain partitioning. Since in RTM, both the forward and reverse wave propagation is iteratively calculated on time step increments, the method implements methods that includes partitioning memory between computation and intermediate results to optimize an RTM computation. The methods make maximum use of the memory to either eliminate storing the snapshot wavefield data to disk, or hide all or a significant portion of the disk I/O time. Furthermore, the schemes can provide the flexibility to vary a number of iterations (step size) for each snapshot to be kept in the memory. If any of the given conditions changes during the process, maximum usage of the available memory is ensured. | 2014-05-22 |
20140140175 | TRACKBALL MODULE, ULTRASONIC IMAGE PROCESSING APPARATUS USING TRACKBALL MODULE AND METHOD OF CONTROLLING ULTRASONIC IMAGE PROCESSING APPARATUS USING TRACKBALL MODULE - An ultrasonic image processing apparatus includes a trackball module configured to receive a control command from a user, and a controller configured to generate a control command for the trackball module and transfers the generated control signal to the trackball module. The trackball module includes a trackball configured to receive a control command from a user, and a lighting device. The lighting device includes a light source, an optical passage bent at least once to provide an optical path through which light emitted from the light source passes while being reflected at least once, and a light exit opening defined at one end of the optical passage from which light passing through the optical passage is emitted to an outside of the lighting device. The light exit opening is defined around the trackball. | 2014-05-22 |
20140140176 | LOCAL POSITIONING SYSTEM FOR REFRACTORY LINING MEASURING - A method and system for measuring wear in the lining of a vessel in which undirected radiation signals are transmitted by at least two transmitters at known positions to a receiver at the device for measuring wear. The distances between the transmitters and receiver are determined based on the time of flight of the radiation between the transmitters and receiver. The location of the receiver at the measuring device is determined to be at a point on an arc of points at the distance calculated based on the time of flight of the signal from each of the transmitters to the receiver. The receiver is determined to be at the intersection of the two arcs of points at the distance calculated based on the time of flight of the signal from the each of the transmitters. Also, the orientation of the measuring device relative to the known positions of the transmitters can be determined if a second receiver is present at or near the measuring device and receives signals from the transmitters based on the positions of the receivers relative to each other at the measuring device. | 2014-05-22 |
20140140177 | USER-INTERFACE TARGET MOTION ANALYSIS METHOD USING TWO-DIMENSIONAL PARAMETER CONTROL AND SPEED ZOOM - Disclosed is a user-interface target motion analysis (TMA) method using two-dimensional parameter control and speed zoom, and the method includes a first step of displaying a user-interface target motion analysis screen capable of selecting an input method; a second step of receiving the input method of a user; a third step of simultaneously calculating a speed and a course by speed zoom or simultaneously calculating a course and an initial range; a fourth step of calculating an initial range or a speed by speed zoom that is not calculated in the third step; and a step of generating a result of the target motion analysis using the parameters inputted through the first to fourth steps. | 2014-05-22 |
20140140178 | Ultrasonic Sensor for Capturing Value Documents and Method for Manufacturing the Same - An ultrasonic sensor and method for using the same are arranged for capturing a value document transported through a capture region of the ultrasonic sensor. The ultrasonic sensor has an ultrasound transmitter arranged for emitting ultrasound into the capture region and an ultrasound receiver arranged for receiving ultrasound from the ultrasound transmitter from the capture region. A control and evaluation circuit is arranged for controlling the ultrasound transmitter and for capturing and evaluating the signals of the ultrasound receiver. A circuit carrier carries the control and evaluation circuit, the ultrasound transmitter, the ultrasound receiver, and conducting paths electrically connecting the control and evaluation circuit to the first and second ultrasonic transducers. The circuit carrier has a U-shaped configuration and two interconnected arm portions, and the ultrasound transmitter is held on one of the two arm portions and the ultrasound receiver on the other of the two arm portions. | 2014-05-22 |
20140140179 | INFRASOUND GENERATING DEVICE BASED ON A DISPLACEMENT-FEEDBACK TYPE VIBRATION EXCITER - The infrasound generating device based on a displacement-feedback type vibration exciter comprises a displacement-feedback type vibration exciter system, an infrasound generating chamber ( | 2014-05-22 |
20140140180 | PROTECTIVE OVERCOAT LAYER OF CARBON AND A SELECTED TRANSITION METAL - Apparatus for recording data and method for making the same. In accordance with some embodiments, a magnetic recording layer is adapted to store data along perpendicular magnetic domains. A protective overcoat layer is formed on the magnetic recording layer to substantially protect the magnetic recording layer from environmental effects. The protective overcoat layer is made of carbon intermixed with at least one transition metal, such as but not limited to chromium. | 2014-05-22 |
20140140181 | SYSTEMS AND METHODS FOR CONTENT PLAYBACK AND RECORDING - A method for content playback and recording may include using a computer to obtain media content from a recorded medium. Concurrently with obtaining the media content, the method may include reencrypting the encrypted media content using a secondary encryption key and storing the reencrypted media content in a storage device. | 2014-05-22 |
20140140182 | Harmonic Ratio Based Defect Classifier - The disclosure is directed to a system and method for detecting and classifying at least one media defect. A periodic pattern is written to a medium to yield at least one waveform. The magnitude of the waveform is compared against a defect threshold to detect the presence or absence of media defects in the medium. When at least one defect is detected, a magnitude for each of at least two harmonics of the waveform is determined in the defect range. The defect is classified by comparing a ratio of the magnitudes of the at least two harmonics against a classification threshold. | 2014-05-22 |
20140140183 | INFORMATION RECORDING/REPRODUCTION DEVICE, CLEANING TAPE, AND OPTICAL PICKUP CLEANING METHOD - An information recording and reproduction device comprises an optical pickup that has an objective lens and records information to a tape-form medium or reproduces information from a tape-form medium using laser light; a tape threading component that allows the tape-form medium to be arranged opposite the objective lens; a controller that detects that the tape-form medium is a cleaning tape; a movement mechanism that operates so as to bring the tape-form medium and the objective lens into contact with each other, in response to the detection by the control unit; and a first drive mechanism that plays out the tape-form medium in a state in which the tape-form medium and the objective lens are in contact with each other. The information recording and reproduction device is capable of cleaning the optical pickup even with a tape-form medium. | 2014-05-22 |
20140140184 | OPTICAL TAPE PICK UP UNIT WITH HOLOGRAPHIC OPTICAL ELEMENT - An optical tape pick up unit includes a holographic optical element and an aspheric objective lens. The holographic optical element splits a laser beam into first order beams and introduces pre-compensating wavefront error into the first order beams. The aspheric objective lens focuses the first order beams onto optical tape and introduces wavefront error into the first order beams having a magnitude similar to and polarity opposite that of the pre-compensating wavefront error. | 2014-05-22 |
20140140185 | PLAYBACK DEVICE AND PLAYBACK METHOD - There is provided a playback device including a light source, an objective lens that radiates light emitted onto an optical recording medium, and onto which is incident reflected light obtained from a recording surface of the optical recording medium, a condenser lens that condenses the reflected light, a photodetecting section configured to, provided that a confocal position is a focal position of the condenser lens, λ is a wavelength of light radiated onto the optical recording medium, and NA is a numerical aperture of the objective lens, extract and detect light within a range of a diameter less than 1.5λ/NA centered on an optical axis at the confocal position, and a phase difference imparting section that imparts a designated phase difference between a reflected light component from a readout track and a reflected light component from a track neighboring the readout track. | 2014-05-22 |
20140140186 | CIRCUIT BOARD WITH LOW SIGNAL FAR END CROSSTALK - A circuit board includes at least four signal lines. The at least four signal lines are substantially parallel to each other and includes two first adjacent signal lines and two second adjacent signal lines adjacent to the first adjacent signal lines. A polarity of signals transmitted by the two first adjacent signal lines is opposite to a polarity of signals transmitted by two second adjacent signal lines. | 2014-05-22 |
20140140187 | METHOD, APPARATUS AND SYSTEM FOR SUPPORTING NON-VECTOR LINE - Embodiments of the present invention provide a method, an apparatus, and a system for supporting a non-vector line. The method includes: selecting n non-vector lines T | 2014-05-22 |
20140140188 | Cooperative Subspace Multiplexing in Communication Networks - A source node selects a plurality of transmitting nodes to cooperatively encode a set of original packets to transfer to a destination node. Encoding produces a plurality of coded packets and a corresponding code matrix of coefficients. The coded packets and the corresponding code matrix comprise a set of independent equations of independent variables in a system of linear equations, wherein the independent variables comprise the original packets. A destination node may select a set of receiving nodes to cooperatively receive the transmissions. The destination node collects the coded packets and code matrix from the receiving nodes, which provide a sufficient number of independent equations for decoding the original packets. Decoding comprises calculating a solution for the system of linear equations. | 2014-05-22 |
20140140189 | Cooperative Subspace Demultiplexing in Communication Networks - A source node selects a plurality of transmitting nodes to cooperatively encode a set of original packets to transfer to a destination node. Encoding produces a plurality of coded packets and a corresponding code matrix of coefficients. The coded packets and the corresponding code matrix comprise a set of independent equations of independent variables in a system of linear equations, wherein the independent variables comprise the original packets. A destination node may select a set of receiving nodes to cooperatively receive the transmissions. The destination node collects the coded packets and code matrix from the receiving nodes, which provide a sufficient number of independent equations for decoding the original packets. Decoding comprises calculating a solution for the system of linear equations. | 2014-05-22 |
20140140190 | Wireless Terminal Apparatus and Wireless Base Station Apparatus - Both a wireless terminal apparatus and wireless base station apparatus are provided that can, in an operation of encoding the control signals of the upstream link transmitted from the multiple terminal stations while encoding with regard to each of the terminal stations, increase a number of the terminal stations to which different codes are respectively assigned. A wireless terminal apparatus includes: an encoding information receiving portion receiving encoding information which is used at the wireless terminal apparatus from the base station; a phase-shifting unit which conducts a phase-shifting operation on a predetermined first code based on the encoding information; a code selection unit which, based on the received encoding information, selects a second code from multiple codes orthogonally crossing each other; and a control signal encoding portion which conducts an encoding operation on the control signal that is going to be transmitted to the base station by using both the first code on which the phase-shifting operation has been conducted and the second code. | 2014-05-22 |
20140140191 | Wireless Terminal Apparatus and Wireless Base Station Apparatus - Both a wireless terminal apparatus and wireless base station apparatus are provided that can, in an operation of encoding the control signals of the upstream link transmitted from the multiple terminal stations while encoding with regard to each of the terminal stations, increase a number of the terminal stations to which different codes are respectively assigned. A wireless terminal apparatus includes: an encoding information receiving portion receiving encoding information which is used at the wireless terminal apparatus from the base station; a phase-shifting unit which conducts a phase-shifting operation on a predetermined first code based on the encoding information; a code selection unit which, based on the received encoding information, selects a second code from multiple codes orthogonally crossing each other; and a control signal encoding portion which conducts an encoding operation on the control signal that is going to be transmitted to the base station by using both the first code on which the phase-shifting operation has been conducted and the second code. | 2014-05-22 |
20140140192 | Wireless Terminal Apparatus and Wireless Base Station Apparatus - Both a wireless terminal apparatus and wireless base station apparatus are provided that can, in an operation of encoding the control signals of the upstream link transmitted from the multiple terminal stations while encoding with regard to each of the terminal stations, increase a number of the terminal stations to which different codes are respectively assigned. A wireless terminal apparatus includes: an encoding information receiving portion receiving encoding information which is used at the wireless terminal apparatus from the base station; a phase-shifting unit which conducts a phase-shifting operation on a predetermined first code based on the encoding information; a code selection unit which, based on the received encoding information, selects a second code from multiple codes orthogonally crossing each other; and a control signal encoding portion which conducts an encoding operation on the control signal that is going to be transmitted to the base station by using both the first code on which the phase-shifting operation has been conducted and the second code. | 2014-05-22 |
20140140193 | Wireless Terminal Apparatus and Wireless Base Station Apparatus - Both a wireless terminal apparatus and wireless base station apparatus are provided that can, in an operation of encoding the control signals of the upstream link transmitted from the multiple terminal stations while encoding with regard to each of the terminal stations, increase a number of the terminal stations to which different codes are respectively assigned. A wireless terminal apparatus includes: an encoding information receiving portion receiving encoding information which is used at the wireless terminal apparatus from the base station; a phase-shifting unit which conducts a phase-shifting operation on a predetermined first code based on the encoding information; a code selection unit which, based on the received encoding information, selects a second code from multiple codes orthogonally crossing each other; and a control signal encoding portion which conducts an encoding operation on the control signal that is going to be transmitted to the base station by using both the first code on which the phase-shifting operation has been conducted and the second code. | 2014-05-22 |
20140140194 | METHOD FOR GENERATING AN OFDM DATA SIGNAL - An OFDM signal generator includes a time domain data signal generator configured to generate a time domain data signal, a partial signal generator configured to generate a plurality of partial signals based on a tail section of the time domain data signal, and a circuit element configured to form a difference between or a sum of the time domain data signal and the plurality of partial signals. | 2014-05-22 |
20140140195 | COMMUNICATION METHOD AND TRANSMISSION APPARATUS - An electronic device that performs an inverse fast Fourier transform (IFFT) on N (N is an integer equal to or larger than 2) orthogonal frequency-division multiplexed (OFDM) transmission signals; performs a fast Fourier transform (FFT) on the N transmission signals which have been subjected to the IFFT; detects phases of the N transmission signals which have been subjected to the FFT; detects relative delay amounts of the N transmission signals based on the detected phases of the N transmission signals; and adjusts a timing at which at least one of the N transmission signals is subjected to the inverse fast Fourier transform based on the detected relative delay amounts. | 2014-05-22 |
20140140196 | METHOD AND SYSTEMS FOR BIDIRECTIONAL OUTAGE BYPASS FOR A VOICE OVER INTERNET PRIVATE BRANCH EXCHANGE - A system and method is disclosed herein for providing a bidirectional outage bypass for a hosted voice-over Internet protocol (VoIP) private branch exchange (PBX) system. An outage monitoring system is in communication with both the bidirectional bypass system and one or more bypass enablers that act at the direction of the bidirectional bypass system. The outage monitoring system detects outages and overloads, as well as, network failures between the VoIP PBX and the public switched telephone network (PSTN). The bidirectional bypass system, in response to detection of an outage, determines error-handling procedures for the bidirectional bypass based on bypass configuration data. The bypass enablers forward outgoing communications between a client device and the PSTN, in accordance the error-handling procedures, by bypassing components that are currently experiencing failures or overloads. The bypass enablers forward incoming communications for the VoIP PBX to an alternative destination in accordance with the error-handling procedures. | 2014-05-22 |
20140140197 | APPARATUS, SYSTEM AND METHOD OF CONTROLLING DATA FLOW OVER A COMMUNICATION NETWORK - Some demonstrative embodiments include apparatuses, systems and/or methods of controlling data flow over a communication network. For example, an apparatus may include a communication unit to communicate between first and second devices a transfer response, the transfer response in response to a transfer request, the transfer response including a transfer pending status indicating data is pending to be received at the second device, the communication unit is to communicate the transfer response regardless of whether a retry indicator of the transfer request represents a first request for transfer or a retried request. | 2014-05-22 |
20140140198 | Fault Routing Of An Emergency Communication - Aspects of the disclosure relate to routing of an emergency communication under fault conditions. Routing can be implemented in a packet-switching (PS) network that provides voice service. For a network node of the PS network, availability to route the emergency communication through a specific emergency service routing number (ESRN) can be determined and, in response to the network node being unavailable, administrative data associated with the ESRN can be accessed. In addition, an identifier associated with the administrative data can be updated (e.g., created or modified) with data indicative of the device that originated the emergency communication. The administrative data and the resulting identifier can be delivered to a second network node that can route the emergency communication to an emergency service network. | 2014-05-22 |
20140140199 | VIRTUAL LINK AGGREGATIONS ACROSS MULTIPLE FABRIC SWITCHES - One embodiment of the present invention provides a switch. The switch is configurable to be a member of a first fabric switch. The switch includes a link aggregation module. During operation, the link aggregation module marks an ingress-switch field of a frame with a virtual switch identifier. This virtual switch identifier is associated with the switch and a second switch, which is a member of a second fabric switch, and is from a range of identifier associated with the first fabric switch and the second fabric switch. Each of the first fabric switch and the second fabric switch is operable to accommodate a plurality of switches and operate as a single switch. | 2014-05-22 |
20140140200 | METHOD AND SYSTEMS FOR AN OUTGOING UNIDIRECTIONAL OUTAGE BYPASS FOR A VOICE OVER INTERNET PROTOCOL PRIVATE BRANCH EXCHANGE SYSTEM - A system and method is disclosed herein for providing a unidirectional outage bypass for outgoing communications from a session initiation protocol (SIP) device in a hosted Voice-over Internet Protocol (VoIP) private branch exchange (PBX) system. An outage monitoring system is in communication with both a bypass configuration system and one or more bypass enablers that act at the direction of the bypass configuration system. The outage monitoring system detects outages and overloads, as well as, network failures between network components, the VoIP PBX, Client Devices and the public switched telephone network (PSTN). The bypass configuration system, in response to a detection of an outage, determines error-handling procedures for the unidirectional outage bypass system based on bypass configuration data. The bypass enablers forward outgoing communications between a client device and the PSTN, in accordance the error-handling procedures, by bypassing components that are currently experiencing failures or overloads. | 2014-05-22 |
20140140201 | SEA FAILOVER MECHANISM WITH MINIMIZED PACKET LOSSES - Provided are techniques for active SEA learning about a client LPAR MAC addresses via address resolution protocol (ARP) packets received on a virtual interface (of the active SEA). Any new client MAC addresses learned on the active SEA are sent to the inactive SEA via a control channel. When SEA failover happens, as the previously inactive SEA is about to become active, it will first send out RARP (reverse ARP) packets with the client MAC addresses as the source MAC addresses respectively. This effectively informs the switch connected to the previously inactive SEA that these client MAC addresses are to be routed through this switch port; the client MAC addresses saved on the switch connected to the previously active SEA are cleared as a result. | 2014-05-22 |
20140140202 | METHOD AND SYSTEMS FOR AN INCOMING UNIDIRECTIONAL OUTAGE BYPASS FOR A VOICE OVER INTERNET PROTOCOL PRIVATE BRANCH EXCHANGE SYSTEM - A system and method are disclosed herein for providing a unidirectional outage bypass for incoming communications via a hosted Voice-over Internet Protocol (VoIP) private branch exchange (PBX) system to a session initiation protocol (SIP) device. An outage monitoring system is in communication with both the unidirectional bypass system and one or more bypass enablers that act at the direction of the unidirectional bypass system. The outage monitoring system detects outages and overloads, as well as, network failures between network components, the VoIP PBX, Client Devices and the public switched telephone network (PSTN). The unidirectional bypass system, in response to detection of an outage, determines error-handling procedures for the unidirectional bypass based on bypass configuration data. The bypass enablers forward incoming communications between the PSTN and a bypass destination following a bypass route in accordance the error-handling procedures, by bypassing components that are currently experiencing failures or overloads. | 2014-05-22 |
20140140203 | RESILIENT ROUTING BASED ON A MULTI-CHANNEL MODEL FOR EMERGENCY MANAGEMENT - There is provided a system and method for resilient routing based on a multi-channel model for emergency management. The system includes a packet delivery anomaly detector for determining an existence of an anomaly in a mandated routing infrastructure for a packet that renders the packet incapable of reaching a destination node designated for the packet through the mandated routing infrastructure. The system further includes a dynamic alternate route identifier for dynamically identifying alternate routes for the packet responsive to a determination of the existence of the anomaly. The alternate routes are outside the mandated routing infrastructure, are provided using one or more mobile devices external to and not part of the mandated routing infrastructure, and are dynamically identified responsive to at least geographic location information. The system also includes a wireless transmitter for wirelessly routing the packet using at least one of the alternate routes. | 2014-05-22 |
20140140204 | RESILIENT ROUTING BASED ON A MULTI-CHANNEL MODEL FOR EMERGENCY MANAGEMENT - There is provided a system and method for resilient routing based on a multi-channel model for emergency management. The system includes a packet delivery anomaly detector for determining an existence of an anomaly in a mandated routing infrastructure for a packet that renders the packet incapable of reaching a destination node designated for the packet through the mandated routing infrastructure. The system further includes a dynamic alternate route identifier for dynamically identifying alternate routes for the packet responsive to a determination of the existence of the anomaly. The alternate routes are outside the mandated routing infrastructure, are provided using one or more mobile devices external to and not part of the mandated routing infrastructure, and are dynamically identified responsive to at least geographic location information. The system also includes a wireless transmitter for wirelessly routing the packet using at least one of the alternate routes. | 2014-05-22 |
20140140205 | POST-SILICON REPAIR OF ON-DIE NETWORKS - A method and apparatus for post-silicon repair of on-die networks is disclosed. In one embodiment, an integrated circuit includes a first network node of an on-chip network configured to couple each of a plurality of functional units to at least one other one of the plurality of functional units. The first network node includes a plurality of ports. Each of the plurality of ports includes a plurality of multiplexers configured to substitute a spare channel of the network node into the network responsive to a test determining that another one of a plurality of channels is defective. | 2014-05-22 |