21st week of 2009 patent applcation highlights part 68 |
Patent application number | Title | Published |
20090132778 | SYSTEM, METHOD AND A COMPUTER PROGRAM PRODUCT FOR WRITING DATA TO DIFFERENT STORAGE DEVICES BASED ON WRITE FREQUENCY - A system, method, and computer program product are provided for writing data to different storage devices based on write frequency. In operation, a frequency in which data is written is identified. Additionally, a plurality of storage devices of different types is selected from to write the data, based on the frequency. | 2009-05-21 |
20090132779 | STORAGE SYSTEM AND REMOTE COPY CONTROL METHOD - A plurality of second groups respectively including one or more second volumes are configured in correspondence with each of the first groups of a remote copy source in a remote copy destination, journals are acquired from the first storage apparatus periodically and in the order the journals were created for each of the configured second groups, and the acquired journals are reflected in the corresponding second volume in the corresponding second group. In addition, the latest time stamp of each of the second groups containing the journals retained in the second volume in an unreflected state is compared, the time difference of the latest and oldest time stamps is detected, and prescribed control processing is executed for acquiring the journals regarding the second group with the oldest time stamp in preference to the journals regarding other second groups when the time difference exceeds a preset threshold value. | 2009-05-21 |
20090132780 | CACHE LINE RESERVATIONS - Illustrative embodiments provide a computer implemented method, an apparatus in the form of a data processing system and a computer program product for cache line reservations. In one embodiment, the computer implemented method comprises, dividing a memory into an unreserved section and a set of reserved sections. The method performs selected allocations of the memory only from the set of reserved sections, and performing un-selected allocations of the memory from the unreserved section. The method further mapping a specified selected allocation of the memory to a same corresponding line of cache memory each time the mapping for the specified selected allocation of the memory occurs, thereby maintaining locality. | 2009-05-21 |
20090132781 | MEMORY HUB WITH INTEGRATED NON-VOLATILE MEMORY - A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for receiving memory access requests, a non-volatile memory having memory configuration information stored therein, and a memory controller coupled to the high-speed interface and the non-volatile memory. The memory controller includes registers into which the memory configuration information is loaded and is operable to output memory requests in response to receiving memory access requests from the high-speed interface and in accordance with the memory configuration information loaded in the registers. A method for initializing a memory sub-system is also provided. The method includes loading configuration registers of a plurality of memory hubs with the configuration information provided by a respective one of a plurality of embedded non-volatile memories integrated in the respective memory hub. | 2009-05-21 |
20090132782 | Compressing And Decompressing Image Data Without Introducing Artifacts - An apparatus may include a memory to store a first frame, a buffer to store at least one portion of a second frame previously stored in the memory, and first and second units to, respectfully, store and fetch data. The first unit may copy a datum of the second frame stored at a particular location in the memory to the buffer. The first unit may then store a datum of a first frame at the particular location. The second unit may fetch a datum of a second frame from a selected location. If a write-segment pointer and a read-segment pointer identify the same memory segment, and the read-data pointer is greater than the write-data pointer, the memory may be selected. If the write-segment pointer and the read-segment pointer identify the same memory segment, and the write-data pointer is greater than the read-data pointer, the buffer may be selected. In addition, if the write-segment pointer and the read-segment pointer identify different memory segments, either the memory or the buffer may be selected depending on additional criteria. | 2009-05-21 |
20090132783 | System and Method of Determining an Address of an Element Within a Table - In a particular embodiment, a method is disclosed that includes executing a single instruction to identify a location within a table stored at a memory. The single instruction is executable by a processor to extract bit field data from a first register and insert the bit field data into an index portion of a second register. The second register includes a table address portion and an index portion. The table address portion includes a table address identifying a memory location associated with a table. The table address and the bit field data combine to form an indexed address to an element within the table. | 2009-05-21 |
20090132784 | CACHE MEMORY AND METHOD OF OPERATING THE SAME - Provided are a cache memory using a linear hash function and a method of operating the same. The cache memory includes: a first hash function module for converting a main memory address received from a central processing unit (CPU) into a first index value using a first hash function; a second hash function module for converting the main memory address into a second index value using a second hash function; a first comparator for comparing a tag value of a data block located at the first index value in the first bank with a tag value of the main memory address; and a second comparator for comparing a tag value of a data block located at the second index value in the second bank with the tag value of the main memory address. In a pair of linear hash functions according to the present invention, each constructed with a 2m×m binary matrix, even if m is an odd number, each of the linear hash functions has the highest degree of interbank dispersion and avoids conflicts in row, column, diagonal, anti-diagonal, and rectangular patterns, so that a 2-way skewed associative cache can be constructed in relatively wide ranges. | 2009-05-21 |
20090132785 | SIMD processor executing min/max instructions - A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays. | 2009-05-21 |
20090132786 | METHOD AND SYSTEM FOR LOCAL MEMORY ADDRESSING IN SINGLE INSTRUCTION, MULTIPLE DATA COMPUTER SYSTEM - A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight columns in a respective SRAM device. Each PE includes a local column address register that can be loaded through a data bus of the respective PE. A local column address stored in the local column address register is applied to an AND gate, which selects either the local column address or a column address applied to the AND gate by the central control unit. As a result, the central control unit can globally access the SRAM device, or a specific one of the eight columns that can be accessed by each PE can be selected locally by the PE. | 2009-05-21 |
20090132787 | Runtime Instruction Decoding Modification in a Multi-Processing Array - A method and system for decoding and modifying processor instructions in runtime according to certain rules in order to separately control processing elements embedded within a multi-processor array using a single instruction. The present invention allows multiple processing elements and/or execution units in a multi-processor array to perform different operations, based upon a variable or variables such as their location in the multi-processor array, while accepting a single instruction as an input. | 2009-05-21 |
20090132788 | CONTROL SYSTEM WITH MULTIPLE PROCESSORS AND CONTROL METHOD THEREOF - A control system comprises a master processor, a main memory and multiple slave processors. The main memory stores programs, and a signal-program table for storing relationships between the programs and input signals. The multiple slave processors are configured for sending input signals in response to external stimuli to the master processor, and executing programs corresponding to the input signals sent back by the master processor. The master processor is configured for interrogating the signal-program table to determine the corresponding programs according to one of the input signals, searching the main memory for acquiring the corresponding programs, determining which one or more of the multiple slave processors should execute the corresponding programs, and transmitting each of the corresponding programs to the one or more of the multiple slave processors. A related control method is also provided. | 2009-05-21 |
20090132789 | APPARATUS AND METHOD FOR CHANNEL-SPECIFIC CONFIGURATION IN A READOUT ASIC - An application-specific integrated circuit (ASIC) comprising a plurality of channels, each channel having circuitry for time and energy discrimination, a plurality of programmable registers, each programmable register configured to output at least one configuration parameter for the circuitry, and a channel-select register configured to identify a channel of the plurality of channels to be configured. The ASIC further includes a configuration-select register configured to identify the programmable register to be used for channel configuration, and a communications interface configured to transmit instructions received from a controller to one of the channel-select register, the configuration-select register, and the plurality of programmable registers. | 2009-05-21 |
20090132790 | SYSTEM AND METHOD FOR PROCESSOR WITH PREDICTIVE MEMORY RETRIEVAL ASSIST - A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance. | 2009-05-21 |
20090132791 | System and Method for Recovering From A Hang Condition In A Data Processing System - A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition. | 2009-05-21 |
20090132792 | Method of generating internode timing diagrams for a multiprocessor array - The apparatus used includes a multi core computer processor | 2009-05-21 |
20090132793 | System and Method of Selectively Accessing a Register File - In a particular embodiment, a method is disclosed that includes identifying a first block of bits within a result to be written to a destination register by an execution unit. The result includes a plurality of bits having the first block of bits and a second block of bits. The first block of bits has a value of zero. The method further includes providing an encoded bit value representing the first block of bits to a control register and selectively writing the second block of bits, but not the first block of bits, to the destination register. The destination register is sized to receive the first and second blocks of bits. | 2009-05-21 |
20090132794 | Method and apparatus for performing complex calculations in a multiprocessor array - A method and apparatus for performing complex mathematical calculations. The apparatus includes a multicore processor | 2009-05-21 |
20090132795 | Processor with excludable instructions and registers and changeable instruction coding for antivirus protection - Digital processor architecture is characterized by processor's instruction set and registers. If architecture is fixed and known to software developers the viruses may be created to harm computers. Invented processor architecture protects against viruses by modifying of association between instruction set coding and processor's functions. Additionally, invented architecture allows to exclude processor's parts associated with unused by program instructions and exclude registers. Exclusion of processor's parts unused by program makes processor smaller and faster in comparison with processor containing all blocks. Developed architecture also allows to exclude unused portions of instructions from instruction's format resulting in smaller memory size required for the same program. | 2009-05-21 |
20090132796 | POLLING USING RESERVATION MECHANISM - A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread. | 2009-05-21 |
20090132797 | Methods, Media and Apparatus for Booting Diskless Systems - The disclosure provides a system, method, and computer readable medium for booting a diskless client in an information handling system (IHS). Cached boot data is stored in a non-volatile memory of the diskless client. The diskless client sends a boot request with an identifier and receives a boot reply containing an image signature associated with the identifier. The diskless client determines whether there is a match between a cached image signature and the received image signature. If there is a match, the diskless client boots with the cached boot data. If there is not a match, the cached boot data is invalidated and new boot data is requested and received from a server. The diskless client stores the new boot data in the non-volatile memory and boots with the new boot data. The cached boot data may be update when network traffic is below a predetermined level and/or an administrator change to boot data affects a plurality of diskless clients. The diskless client request and receives updated boot data stores the updated boot data in the non-volatile memory. | 2009-05-21 |
20090132798 | ELECTRONIC DEVICE AND METHOD FOR RESUMING FROM SUSPEND-TO-MEMORY STATE THEREOF - An electronic device and a method for resuming from a suspend-to-memory (S3) state thereof are provided. The electronic device comprises a detecting circuit, a storage unit and a booting module. The detecting circuit outputs a state change value when detecting a state variation of any non-hot plug device. The storage unit is used for storing the state change value output from the detecting circuit. When the electronic device is resumed from the S3 state to the working state, a normal booting procedure is performed on the electronic device if the state change value is detected by the booting module. | 2009-05-21 |
20090132799 | Systems and Methods for Configuring Out-of-Band Bios Settings - A method may for updating system configuration data is provided. A configuration change request may be received from a remote user at a local baseboard management controller (BMC) via a network while a processor associated with the BMC is offline. The configuration change request may be stored in a request log. After the processor comes online, the configuration data may be updated based on the configuration change request stored in the request log. A copy of the updated configuration data from the chipset may be stored in a storage device coupled to the BMC such that the copy of the updated configuration data is accessible when the processor is offline. The copy of the updated system configuration may be provided to a subsequent remote user for a subsequent system configuration update. | 2009-05-21 |
20090132800 | METHOD FOR ADJUSTING SETUP DEFAULT VALUE OF BIOS AND MAIN BOARD THEREOF - A method for adjusting setup default value of a basic input output system (BIOS) and a main board are provided. The main board offers a BIOS memory which includes a boot block and a main block. The boot block includes an adjusting table, and the main block includes an original setup default value and a dynamic table. The adjusting table is used to read the dynamic table, and the original setup default value is adjusted to be a customized setup default value according to the adjusting table and the dynamic table. Afterwards, the customized setup default value is stored in a setup value memory. | 2009-05-21 |
20090132801 | CONFIGURATION MANAGEMENT FOR REAL-TIME SERVER - A Realtime Event Server comprising a component to operate on data from data streams; and a configuration system adapted to supply configuration for the realtime event server, the configuration including dynamic configuration, the dynamic configuration being changeable without restarting the component. | 2009-05-21 |
20090132802 | Encryption Data Integrity Check With Dual Parallel Encryption Engines - An encryption method encrypts a clear text twice using a first encryption engine to produce a first cipher text and a second encryption engine to produce a second cipher text. The method compares the first cipher text with the second cipher text, or compares a checksum of the first cipher text with a checksum of the second cipher text. If the comparison succeeds, the method transmits the data. In some embodiments, the method uses a first instance of an encryption key to produce the first cipher text and a second instance of the encryption key to produce the second cipher text. | 2009-05-21 |
20090132803 | Secure Delivery System - Aspects of the present invention provide systems and methods relating to storing and forwarding electronic files securely throughout the lifecycle of the file. One aspect of the invention relates to providing encrypted copies of electronic files that can only be unencrypted by the intended recipient. | 2009-05-21 |
20090132804 | SECURED LIVE SOFTWARE MIGRATION - A novel approach is introduced for secured live migration of a software component currently running on one hosting device to another hosting device. One or more pages of the software component are encrypted before migration of the software component, and are later decrypted after the migration is complete. The software component is kept operational during the encryption, migration, and decryption of the software component. The one or more pages to be encrypted and decrypted can be selected based on data sensitivity and/or other criteria. | 2009-05-21 |
20090132805 | Systems and methods for secure transaction management and electronic rights protection - The present invention provides systems and methods for secure transaction management and electronic rights protection. Electronic appliances such as computers equipped in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information. Such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Distributed and other operating systems, environments and architectures, such as, for example, those using tamper-resistant hardware-based processors, may establish security at each node. These techniques may be used to support an all-electronic information distribution, for example, utilizing the “electronic highway.” | 2009-05-21 |
20090132806 | Method for agreeing between at least one first and one second communication subscriber to security key for securing communication link - The use of suitable measures in a method for agreeing on a security key between at least one first and one second communication station to secure a communication link is improved so that the security level for the communication is increased and the improved method can be combined with already available methods. A first parameter is determined from an authentication and key derivation protocol. In addition, an additional parameter is sent securely from the second to the first communications station. A security key is then determined from the first parameter and the additional parameter. | 2009-05-21 |
20090132807 | Renegotiating SSL/TLS connections with client certificates on post requests - A method and apparatus for providing securing a connection with a (Secure Sockets Layer) SSL/TLS-enabled server. In one embodiment, a web client establishes a new connection by initiating a communication with the SSL/TLS-enabled server. The communication includes a non-POST request. After the client negotiates the secured connection with the server in response to the non-POST request, the client submits a POST request to the SSL/TLS-enabled server via the secured connection. | 2009-05-21 |
20090132808 | SYSTEM AND METHOD OF PERFORMING ELECTRONIC TRANSACTIONS - A system and method of performing electronic transactions between a server computer and a client computer. The method implements a communication protocol with encrypted data transmission and mutual authentication between a server and a hardware device via a network, performs a decryption of encrypted server responses, forwards the decrypted server responses from the hardware device to the client computer, displays the decrypted server responses on a client display, receives requests to be sent from the client computer to the server, parses the client requests for predefined transaction information by the hardware device, encrypts and forwards client requests, displays the predefined transaction information upon detection, forwards and encrypts the client request containing the predefined transaction information to the server if a user confirmation is received, and cancels the transaction if no user confirmation is received. | 2009-05-21 |
20090132809 | Method and Apparatus for the Provision of Unified Systems and Network Management of Aggregates of Separate Systems - A method and apparatus for the provision of unified systems and network management of aggregates of separate systems is described herein. | 2009-05-21 |
20090132810 | Distributed digital certificate validation method and system - A distributed digital certificate validation method of a client connectable in communication with a host is provided. The method comprises making a first connection with the host to establish data communication with the host, sending to the host a request for a certificate validation result, importing from the host a file containing at least the requested certificate validation result, and storing the imported file locally for later retrieval of at least the requested certificate validation result. | 2009-05-21 |
20090132811 | ACCESS TO AUTHORIZED DOMAINS - In a domain comprising a plurality of devices, the devices in the domain sharing a common domain key, a method of enabling a entity that is not a member of the domain to create an object that can be authenticated and/or decrypted using the common domain key, the method comprising providing to the entity that is not a member of the domain a diversified key that is derived using a one-way function from at least the common domain key for creating authentication data related to said object and/or for encrypting said object, the devices in the domain being configured to authenticate and/or decrypt said object using the diversified key. | 2009-05-21 |
20090132812 | METHOD AND APPARATUS FOR VERIFYING REVOCATION STATUS OF A DIGITAL CERTIFICATE - Verifying revocation status of a digital certificate is provided in part by a receiver verifying a security certificate for a sender. In an embodiment, an approach comprises receiving a first security certificate associated with the sender and storing the security certificate in a location accessible to the receiver; updating the first security certificate in the location accessible to the receiver if the first security certificate is changed or revoked; receiving a second security certificate from the sender when identity of the sender needs to be verified; comparing the second security certificate to the first security certificate; and confirming the sender's identity only if the second security certificate matches the first security certificate for the sender. | 2009-05-21 |
20090132813 | Apparatus and Methods for Providing Scalable, Dynamic, Individualized Credential Services Using Mobile Telephones - Apparatus and methods perform transactions in a secure environment between an individual and another party, such as a merchant, in various embodiments. The individual possesses a mobile electronic device, such as a smartphone, that can encrypt data according to a public key infrastructure. The individual authenticates the individual's identity to the device, thereby unlocking credentials that may be used in a secure transaction. The individual causes the device to communicate the credentials, in a secure fashion, to an electronic system of a relying party, in order to obtain the relying party's authorization to enter the transaction. The relying party system determines whether to grant the authorization, and communicates the grant and the outcome of the transaction to the device using encryption according to the public key infrastructure. | 2009-05-21 |
20090132814 | PROGRAM, METHOD AND APPARATUS FOR MANAGING ELECTRONIC DOCUMENTS - An electronic document management program, an electronic document management method and an electronic document management apparatus acquire a plurality of pieces of part identification information respectively identifiably expressing a plurality of parts of document information and a digital signature corresponding to the document information, acquire the preparation type, the preparer's name and the time and date of preparation of the document information as tracing information of the document information, manage the part identification information, the digital signature and the tracing information in association with each other and present information relating to the tracing information to the user in response to a request from the user. Additionally, they acquire new document information and tracing information according to a directive from the user. | 2009-05-21 |
20090132815 | Systems and methods for secure transaction management and electronic rights protection - The present invention provides systems and methods for secure transaction management and electronic rights protection. Electronic appliances such as computers equipped in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information. Such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Distributed and other operating systems, environments and architectures, such as, for example, those using tamper-resistant hardware-based processors, may establish security at each node. These techniques may be used to support an all-electronic information distribution, for example, utilizing the “electronic highway.” | 2009-05-21 |
20090132816 | PC on USB drive or cell phone - Disclosed are virtual, personal computers implemented on USB drive, cell phone platforms, or other small portable computing platform. Exemplary personal computers include a nanokernel or minikernel configured to boot when connected to a host computer. A memory is provide for storing the nanokernel or minikernel, along with encrypted data, secure keys and certificates, and one or more software applications. The nanokernel or minikernel is configured to allow selected stored software applications to run on the host computer and execute on the user data stored in the memory when the computing apparatus is connected to the host computer and booted. The nanokernel or minikernel is also configured to prevent any other application from executing on user data stored in the memory. The TPM provides the mechanism to seal and authenticate the compute environment of the host computer its components and/or the USB drive et al itself. The contents of the virtual, personal computer are meant to execute on the host computer, but have persistent, encrypted storage on the USB drive, cell phone platforms, or other small portable computing platform which may have additional biometric identification. | 2009-05-21 |
20090132817 | METHOD, SYSTEM AND DEVICE FOR DETERMINING A MOBILE IP KEY, NOTIFYING A MOBILE IP TYPE - The present invention relates to a wireless communication technology field. A method for determining a mobile IP key of a mobile terminal is provided, which includes: receiving a mobile IP registration request message of a mobile terminal, in which the mobile IP registration request message includes a key material field; and reporting material information for determining a key according to the key material field. A method for determining a mobile IP key of a mobile terminal, a mobile IP agent device, a system for obtaining a mobile IP type, and a mobile terminal are also provided. With the technical solutions provided in the present invention, the mobile IP keys and/or the mobile IP type of the mobile terminal can be correctly determined, thus achieving a fast and correct access of the mobile terminal. | 2009-05-21 |
20090132818 | CONTENT SERVER APPARATUS, ON-VEHICLE PLAYER APPARATUS, SYSTEM, METHOD, AND PROGRAM - A content server apparatus ( | 2009-05-21 |
20090132819 | SYSTEM FOR SELF-SERVICE RECHARGING AND METHOD FOR THE SAME - The present invention discloses a method for self-service recharging and a system for the same, relating to the security communications of online banking. The system comprises a client and a server. The method mainly comprises the steps of: 1) establishing a data security channel between the client and the server; 2) inputting an identifier by a user to a secure transaction device; 3) determining whether the identifier is legitimate; and if legitimate allowing the user to input a recharging operation message; 4) connecting to the server and transmitting a recharging operation request packet after receiving the recharging operation message; 5) verifying whether the secure transaction device is legitimate by the server according to information in a database stored natively, and if legitimate, deducting a recharging amount from a user account, recording an operation log, and transmitting a recharging permission command packet to the secure transaction device; and 6) conducting a recharging operation by the secure transaction device and recording an operation log. The present invention provides a way to conveniently and rapidly recharge. | 2009-05-21 |
20090132820 | Content data management system and method - Embodiments of the present invention provide a simplified authentication transaction for reconnecting a storage device to a host apparatus that has completed authentication in the past. According to one embodiment, an authentication log is recorded in the host. Plural units of this log information are recorded in the storage device. At the time of transferring a content decryption key and usage rules between the host and the storage device, the decryption key and usage rules are recorded into the host as a log for the transfer. The used authentication log is recorded into the storage device as RAPDI. If RAPDI indicates the authentication log in the simplified authentication transaction, recovery transaction is permitted. The host device deletes/invalidates or holds the log for the transfer in accordance with non-permission/permission. In the case of permission, the key and usage rules are recovered by using a log for the transfer prior to the simplified authentication transaction. | 2009-05-21 |
20090132821 | INFORMATION SECURITY DEVICE - The present invention provides an apparatus for securely acquire a circuit configuration information set corresponding to a new cryptosystem without increasing the number of reconfigurable circuits. A content playback apparatus | 2009-05-21 |
20090132822 | METHOD AND DEVICE FOR SECURELY DISTRIBUTING DATA IN GROUP COMMUNICATION - In a method for securely distributing data in group communication, the group has a plurality of members, and the method includes the following steps: (A) under a data recording mode, assigning one member of the group as a recording member; (B) enabling the recording member to generate and send a security key to other members of the group, to record communication contents of all the members during a group communication session, and to create an entry of recorded data therefor; and (C) enabling the other members of the group to receive and store the security key, the security key enabling the other members of the group to retrieve the recorded data from the recording member under a data retrieval mode. | 2009-05-21 |
20090132823 | MULTIMEDIA DATA PROTECTION - The invention provides a method of transmitting a media work such as a movie to a client comprising the steps of (a) encrypting the work using a sequence of different keys corresponding to respective temporally spaced segments of the document, (b) transmitting software code containing an algorithm from a security server to the client, the algorithm having a result that is a function of the state of the client, (c) executing the code at the client and returning the result to the security server, (d) determining whether the result is indicative of an unmodified client, and further comprising the steps of: (e) transmitting a segment from a server to the client, (f) securely streaming a key corresponding to the transmitted segment from a secure remote server to the client, (g) decrypting the segment using the obtained media key, (h) if step (d) indicates a modified client, preventing further keys from being transmitted, otherwise repeating steps (e) to (g) and repeating steps (b) to (d). | 2009-05-21 |
20090132824 | Original, data circulation method, system, apparatus, and computer readable medium - An original data circulation system for storing or circulating original data which is digital information is provided. The original data circulation system includes an issuer apparatus, a user apparatus and a collector apparatus. The issuer apparatus generates originality information including first information corresponding to the issuer apparatus and second information corresponding to data and sends the originality information. The user apparatus verifies the validity of the source apparatus of the originality information and stores the originality information when the validity is verified. The collector apparatus verifies the validity of the source apparatus of the originality information and processes data corresponding to the second information when the validity is verified. | 2009-05-21 |
20090132825 | APPARATUS AND METHOD FOR TRANSMITTING SECURE AND/OR COPYRIGHTED DIGITAL VIDEO BROADCASTING DATA OVER INTERNET PROTOCOL NETWORK - A content distribution method for video copyright authentication and security comprising the steps of invisibly watermarking digital video data input from a video data source to create watermarked data; encrypting the watermarked digital video data using an encryption key to create encrypted video data; sending the encrypted watermarked digital data and a decryption key to a distribution network; decrypting the encrypted watermarked digital data to generate video data and adding visible watermarking data to the video data to generate visibly encrypted watermarked data compressing the visibly encrypted watermarked data to create compressed data; sending said compressed data and to an end user receiver; decompressing the compressed data at the receiver to generate decompressed data; and displaying the decompressed data to an end user. | 2009-05-21 |
20090132826 | HYBRID ENCODING OF DATA TRANSMISSIONS IN A SECURITY SYSTEM - A security system in which wireless transmitting security devices use a hybrid or dual encoding methodology, wherein a first part of a data message is encoded in a return-to-zero (RZ) format and a second part of the data message is encoded in a non-return-to-zero (NRZ) format, thereby increasing error detection and correction. In a first aspect of the invention, status information is included in the first part of the message and redundant status information is included in the second part of the message. In a second aspect of the invention, message sequence information is included in the second part of the message to avoid processing of stale or out-of-sequence messages. | 2009-05-21 |
20090132827 | DEBUGGING PORT SECURITY INTERFACE - The present invention provides a secure JTAG interface to an application-specific integrated circuit (ASIC). In the preferred embodiment the invention operates through the combined efforts of a Security Module (SM) comprising a state machine that controls the security modes for the ASIC, and a Test Control Module (TCM) which contains the JTAG interface. The TCM operates in either a restricted mode or an unrestricted mode, depending on the state of the SM state machine. In a restricted mode, only limited access to memory content is permitted. In an unrestricted mode, full access to memory content is permitted. | 2009-05-21 |
20090132828 | CRYPTOGRAPHIC BINDING OF AUTHENTICATION SCHEMES - Methods and apparatus cryptographically bind authentication schemes to verify that a secure authentication sequence was executed for access to sensitive applications/resources. Users execute two login sequences with a strong authentication framework. Upon completion of the first, the framework generates an unencrypted token from underlying data, later hashed into an authentication token. With a private key corresponding to the first sequence, the authentication token is encrypted and passed to the second sequence where it is encrypted again with a private key corresponding to the second sequence. Upon access attempts to the sensitive applications/resources, verification of execution of the two login sequences includes recovering the authentication token from its twice encrypted form and comparing it to a comparison token independently generated by the application/resource via the underlying data. An audit log associated with the application/resource stores the data, the recovered authentication token, etc., for purposes of later non-repudiation. | 2009-05-21 |
20090132829 | INFORMATION PROCESSOR, METHOD FOR VERIFYING AUTHENTICITY OF COMPUTER PROGRAM, AND COMPUTER PROGRAM PRODUCT - A disc stores therein a computer program and encrypted information. A BIOS is executed at the time of start-up and starts the computer program. A TPM is connected to the BIOS by a low-speed bus. The TPM includes a register for storing data. A blob stores therein true hash values of the computer program and the BIOS in advance. The BIOS includes a hash value calculating unit that calculates hash values of the computer program and the BIOS and stores those hash values in the register. The TPM compares the hash values stored in the register with the hash values stored in the blob and decrypts information in the blob if the hash values agree with each other. | 2009-05-21 |
20090132830 | SECURE PROCESSING DEVICE, SECURE PROCESSING METHOD, ENCRYPTED CONFIDENTIAL INFORMATION EMBEDDING METHOD, PROGRAM, STORAGE MEDIUM, AND INTEGRATED CIRCUIT - When performing secure processing using confidential information that needs to be confidential, the secure processing device according to the present invention prevents the confidential information from being exposed by an unauthorized analysis such as a memory dump. A signature generation device | 2009-05-21 |
20090132831 | CIRCUIT ARRANGEMENT WITH NON-VOLATILE MEMORY MODULE AND METHOD FOR EN-/DECRYPTING DATA IN THE NON-VOLATILE MEMORY MODULE - An apparatus and method is provided for protecting data in a non-volatile memory by using an encryption and decryption that encrypts and decrypts the address and the data stored in the non-volatile memory using a code read only memory that stores encryption and decryption keys that are addressed by a related central processing unit at the same time data is being written or read from the non-volatile memory by the central processing unit. | 2009-05-21 |
20090132832 | ELECTRONIC MUSICAL APPARATUS FOR RECORDING AND REPRODUCING MUSIC CONTENT - In an electronic musical apparatus, a media ID (MD | 2009-05-21 |
20090132833 | STORAGE DEVICE, TERMINAL DEVICE USING THE STORAGE DEVICE, AND METHOD THEREOF - A method of using a storage device in a terminal device connected to the storage device includes reading an identification key stored in the storage device, if the storage device is connected, recovering, based on the identification key, one or more characteristic parameters regarding at least one of the storage device and a file stored in the storage device, and authenticating the storage device using the one or more recovered characteristic parameters. If the authentication is successful, the file is decrypted using the identification key and used. As a result, increased security is provided for the file stored in the storage device. | 2009-05-21 |
20090132834 | Distributing Integrated Circuit Net Power Accurately in Power and Thermal Analysis - A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet. | 2009-05-21 |
20090132835 | METHOD AND SYSTEM FOR POWER-STATE TRANSITION CONTROLLERS - Power-state transitioning arrangements are implemented using a variety of methods. Using one such method, a power-state transitioning circuit arrangement is implemented having a processing circuit that does not include an arithmetic logic unit. A power-state transition script including instructions from an instruction set is stored in a memory circuit. The processing circuit implements the power-state transition script to facilitate a change in a power-state of another processor circuit. | 2009-05-21 |
20090132836 | POWER-SAVING CONTROL APPARATUS AND METHOD - A power-saving control apparatus includes a memory storing first to Nth different authentication codes, determines, every time a signal including an authentication code is received, whether the authentication code in the received signal is a valid code which matches one of the authentication codes in the memory, outputs an operation signal to a main apparatus when the authentication code in the received signal is determined to be the valid code, and generates a new authentication code, when (a) the number of times the authentication code in each received signal matches a first authentication code of the authentication codes in the memory is equal to a predetermined value or (b) the authentication code in the received signal matches a second or subsequent authentication code of the authentication codes in the memory, to delete one of the authentication codes in the memory, and to store the new authentication code in the memory. | 2009-05-21 |
20090132837 | System and Method for Dynamically Selecting Clock Frequency - A system and method for dynamically changing the clock frequency of a system clock is disclosed. The invention includes selecting a peripheral interface clock signal from a plurality of currently active peripheral interface clock signals, each operating at a particular frequency. The selected peripheral interface clock signal operates at the highest frequency of the plurality of currently active peripheral interfaces clock signals. Once selected, the frequency of the system clock is set equal to the frequency of the selected peripheral interface clock signal. | 2009-05-21 |
20090132838 | System and Method for Power Management of A Storage Enclosure - A system and method for power management of storage enclosures are disclosed. A system may include a storage enclosure and a host communicatively coupled to the storage enclosure. The storage enclosure may include at least one storage resource and a management module. The host may be configured to: (a) communicate data to the at least one storage resource via a particular transmission protocol; (b) communicate a power down command via the particular transmission protocol to the storage enclosure, the power down command operable to transition the storage enclosure from a high-power state to a low-power state; and (c) communicate a power up command via the particular transmission protocol to the storage enclosure, the power up command operable to transition the storage enclosure from the low-power state to the high-power state. | 2009-05-21 |
20090132839 | Method and device to handle denial of service attacks on wake events - A method and device may selectively resume a computing device from a low power state according to a security policy. The security policy may be embedded in the hardware of the computing device and may be enforced even when the device is in a low power state. Such a policy may provide protection from hacker and virus based denial of service attacks using a flood of packets formatted to provide a wake event request. Other embodiments are described and claimed. | 2009-05-21 |
20090132840 | CROSS-LAYER POWER MANAGEMENT IN A MULTI-LAYER SYSTEM - A method for cross-layer power management in a multi-layer system includes determining whether there is a service level violation for an application running on a hardware platform. Power consumption of the hardware platform is controlled in response to the service level violation. | 2009-05-21 |
20090132841 | Processor Accessing A Scratch Pad On-Demand To Reduce Power Consumption - The present invention provides processing systems, apparatuses, and methods that access a scratch pad on-demand to reduce power consumption. In an embodiment, an instruction fetch unit initiates an instruction fetch. When a scratch pad is enabled, an instruction is retrieved from the scratch pad in parallel with a translation of a virtual address to a physical address. If the physical address is associated with the scratch pad, the retrieved instruction is provided to an execution unit. Otherwise, the scratch pad is disabled to reduce power consumption and the instruction fetch is re-initiated. When the scratch pad is disabled, an instruction is retrieved from another instruction source, such as an instruction cache, in parallel with the translation of the virtual address to the physical address. If the physical address is associated with the scratch pad, the scratch pad is enabled and the instruction fetch is re-initiated. | 2009-05-21 |
20090132842 | Managing Computer Power Consumption In A Computer Equipment Rack - Methods, systems, and computer program products are provided for managing power consumption of computing devices in a computer equipment rack. Embodiments include monitoring aggregate power consumption of a plurality of computing devices in the computer equipment rack; determining whether the aggregate power consumption exceeds a predetermined maximum threshold; if the aggregate power consumption exceeds the predetermined maximum threshold, selecting a number of computing devices for throttling in dependence upon priority; and throttling-down the selected computing devices computing devices, reducing the aggregate power consumption to a level below the predetermined maximum threshold. Some embodiments may also include determining whether the aggregate power consumption is below a predetermined minimum threshold; if the aggregate power consumption is below the predetermined minimum threshold, selecting a number of computing devices computing devices computing devices for throttling in dependence upon priority; and throttling-up the selected computing devices, increasing the aggregate power consumption to a level above the predetermined minimum threshold. | 2009-05-21 |
20090132843 | CURRENT MODE BUS INTERFACE SYSTEM, METHOD OF PERFORMING A MODE TRANSITION AND MODE CONTROL SIGNAL GENERATOR FOR THE SAME - A current mode bus interface system includes a host interface device configured to transmit a reference current and a clock current, and to transmit a data current during a first transfer mode, and to receive a reverse direction data current and compare the reverse direction data current with the reference current to generate a reverse direction data voltage during a second transfer mode; and a client interface device configured to receive the reference current and the clock current and compare the reference current with the clock current to generate a clock voltage, to receive the data current and compare the data current with the reference current to generate a data voltage during the first transfer mode, and to transmit the reverse direction data current through a conducting wire over which the data current is received during the second transfer mode. | 2009-05-21 |
20090132844 | Method, Apparatus, and System for optimizing Frequency and Performance in a Multi-Die Microprocessor - With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status. | 2009-05-21 |
20090132845 | Power supply monitoring system and power supply apparatus through using software instruction - A power supply monitoring system with power supply apparatus is operated by a software instruction. The power supply monitoring system includes a computer motherboard, a power supply, and a microprocessor. The microprocessor built in the power supply and coupled to an electro-thermal adjusting unit of the power supply; a transmission line, for connecting the microprocessor to a transmission interface of the computer motherboard; and a power supply status monitor program, for displaying operating status information of the power supply and providing a software instruction to control the electro-thermal adjusting unit of the power supply. | 2009-05-21 |
20090132846 | VIRTUAL MACHINE MONITOR, VIRTUAL MACHINE SYSTEM AND CLOCK DISTRIBUTION METHOD THEREOF - A virtual machine monitor, a virtual machine system and a clock distribution method thereof. The clock distribution method includes: distributing real clock resource to a Guest Operation System (GOS), and saving correspondence between said GOS and said real clock resource; intercepting an access operation of said GOS to a virtual clock resource; sending said access operation to the corresponding real clock resource according to said correspondence, and then performing a write operation, or injecting an interrupt of said real clock resource into a local Advanced Programmable Interrupt Controllers (APIC) of a virtual CPU of the corresponding GOS of said GOSs. | 2009-05-21 |
20090132847 | Information processing apparatus having memory clock setting function and memory clock setting method - A memory clock setting function acquires the band of a memory bus, and acquires the total band of a CPU bus and the I/O buses. When the band of the memory bus is greater than the total band of the CPU bus and I/O buses, the clock rate less than or equal to the current operation clock of a memory is selected so that the band of the memory bus may not be less than the total band of the CPU bus and the I/O buses, and the selected clock rate is set as the operation clock of the memory to a memory controller. | 2009-05-21 |
20090132848 | PARALLEL PROGRAMMING ERROR CONSTRUCTS - A system receives a program, allocates the program to a first software unit of execution (UE) and a second software UE, executes a first portion of the program with the first and second software UEs in parallel, and determines whether an error is detected during execution of the first portion of the program by the first and second software UEs. The system also sends a signal, between the first and second software UEs, to execute a second portion of the program when the error is detected in the first portion of the program, executes the second portion of the program with the first and second software UEs when the error is detected, and provides for display information associated with execution of the first portion and the second portion of the program by the first and second software UEs. | 2009-05-21 |
20090132849 | Method and Computer Program for Selecting Circuit Repairs Using Redundant Elements with Consideration of Aging Effects - A method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects provides a mechanism for raising short-term and long-term performance of memory arrays beyond present levels/yields. Available redundant elements are used as replacements for selected elements in the array. The elements for replacement are selected by BOL (beginning-of-life) testing at a selected operating point that maximizes the end-of-life (EOL) yield distribution as among a set of operating points at which post-repair yield requirements are met at beginning-of-life (BOL). The selected operating point is therefore the “best” operating point to improve yield at EOL for a desired range of operating points or maximize the EOL operating range. For a given BOL repair operating point, the yield at EOL is computed. The operating point having the best yield at EOL is selected and testing is performed at that operating point to select repairs. | 2009-05-21 |
20090132850 | ERROR HANDLING SCHEME FOR TIME-CRITICAL PROCESSING ENVIRONMENTS - As a result of detecting an error, command routing logic for device driver logic is reconfigured so that command processing logic of the device driver is not invoked and to return from commands in a manner indicative of successful completion of command processing. | 2009-05-21 |
20090132851 | PARALLEL REED-SOLOMON RAID (RS-RAID) ARCHITECTURE, DEVICE, AND METHOD - The parallel RS-RAID data storage architecture can aggregate that data and checksums within each cluster into intermediate or partial sums that are transferred or distributed to other clusters. The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture. | 2009-05-21 |
20090132852 | PORTABLE ELECTRONIC DEVICE AND CONTROL METHOD THEREOF - A portable electronic device includes a storage unit in which information indicating correct process contents is stored. A reception unit of the portable electronic device receives a command for requesting a process from an external device, and the portable electronic device determines whether or not process contents to be executed according to the received command are matched with process contents stored in the storage unit. When it is determined that process contents according to the received command are matched with process contents stored in the storage unit, the portable electronic device executes a process according to the command received by the reception unit. | 2009-05-21 |
20090132853 | Hardware-error tolerant computing - Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion. | 2009-05-21 |
20090132854 | METHOD AND APPARATUS TO LAUNCH WRITE QUEUE READ DATA IN A MICROPROCESSOR RECOVERY UNIT - A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction completion signal. The capture latch can directly drive the checkpoint register circuitry in the recovery unit of the microprocessor. If the queue is empty, a pair of multiplexers connected to the input of the register queue array are used to pass the input data value. The instruction completion signal may indicate whether all instructions in an instruction group have successfully completed. | 2009-05-21 |
20090132855 | AUTOMATED KERNEL EXTRACTION - A method and system for automatically developing a fault classification system from time series data. The sensors need not have been intended for diagnostic purposes (e.g., control sensors). These methods and systems are functionally independent of knowledge related to a particular equipment system, thereby allowing seamless application to multiple systems, regardless of the suite of sensors in each system. Because this algorithm is totally automated, substantial savings in time and development cost can be achieved. The algorithm results in a classification system and a set of features that might be used to develop alternative classification systems without human intervention. | 2009-05-21 |
20090132856 | SYSTEM AND METHOD FOR DISTRIBUTED MONITORING OF A SOAP SERVICE - A computer implemented method, apparatus, and computer usable program code for the distributed monitoring of a SOAP service is provided. A test configuration file specifying a test input is distributed from a central reporting location to at least one remote data processing system that has access to a SOAP service to be tested. The test configuration file is created without accessing the SOAP service to be tested. Furthermore, the user that created the test configuration file is not allowed access to the SOAP service to be tested. | 2009-05-21 |
20090132857 | SYSTEM AND METHOD FOR TESTING AN EMBEDDED SYSTEM - A testing system for an embedded system is provided. The testing system includes a plurality of devices and one or more host computers. Each device, which includes the embedded system to be tested, is connected to the host computer via a network based on the network file system protocol. The host computers are further connected with a control server, and each of the host computers comprises a root file system. The control server is configured for providing an interface for a user to set test parameters, controlling each of the host computers to invoke a test program, thereby testing the embedded system according to the test parameters, and receiving test results of the embedded system from the host computer. A related testing method is also provided. | 2009-05-21 |
20090132858 | ANALYZER, ANALYZING SYSTEM, AND COMPUTER PROGRAM PRODUCT - An analyzer for accepting an operation input of a user and analyzing an object includes a measuring section for measuring the object; and a controller, wherein the controller includes a memory under control of a processor, the memory storing instructions enabling the processor to carry out operations, comprising: (a) storing information related to a position stored with information related to an operation history of the user; (b) storing information related to a position stored with information related to failure; (c) storing the information related to the operation history of the user; and (d) storing the information related to the failure of the analyzer. A sample analyzing system and computer program product are also disclosed. | 2009-05-21 |
20090132859 | SERVICE DIAGNOSTIC ENGINE AND METHOD AND SERVICE MANAGEMENT SYSTEM EMPLOYING THE SAME - A service management system and a method of performing service diagnostics. In one embodiment, the service management system includes: (1) a service description repository configured to contain service descriptions that define services in terms of end points that assume roles based on at least one of the capabilities and attributes thereof, (2) a diagnostic rule definition repository configured to contain diagnostic rules pertaining to problem areas regarding the services and (3) a diagnostic engine coupled to the service description repository and the diagnostic rule definition repository and configured to retrieve at least one diagnostic rule based on a subscriber, a service and a problem area, evaluate at least one diagnostic rule to produce at least one solution, retrieve data regarding end points associated with the service and return a possible solution. | 2009-05-21 |
20090132860 | SYSTEM AND METHOD FOR RAPIDLY DIAGNOSING BUGS OF SYSTEM SOFTWARE - A system and a method for rapidly diagnosing bugs of system software are apply for rapidly localizing a system program fault that causes a system error and then feeding back to a subscriber. First, according to the subscriber's requirement, a program of system fault analysis standard is preset and written into the system. Next, a plurality of fault insertion points is added into a program module of the system according to the subscriber's requirement for the precision of the fault analysis result. Then, fault management information is generated at the fault insertion points during the running process of the system program, and the management information is monitored for collecting relevant system fault data. After that, the collected system fault data is analyzed in real time through the program of system fault analysis standard, so as to obtain the minimum fault set for causing the system error. | 2009-05-21 |
20090132861 | Privacy Enhanced Error Reports - Methods and apparatus for generating error reports with enhanced privacy are described. In an embodiment the error is triggered by an input to a software program. An error report is generated by identifying conditions on an input to the program which ensure that, for any input which satisfies the conditions, the software program will follow the same execution path such that the error can be reproduced. The error report may include these conditions or may include a new input generated using the conditions. | 2009-05-21 |
20090132862 | METHOD AND APPARATUS FOR NETWORK FAULT ISOLATION - A computer implemented method, apparatus, and computer usable program code for network fault isolation. A plurality of real-time path traces is performed between the sender and the receiver to form a plurality of trace paths in response to receiving a request for the network fault isolation between a sender and a receiver. A determination is made as to whether an asymmetry is present between the sender and the receiver from the plurality of trace paths. A set of routers is identified with each trace path in the plurality of trace paths to form a plurality of identified routers. Each event stored is identified for the plurality of identified routers to form a set of identified events. | 2009-05-21 |
20090132863 | Packing trace protocols within trace streams - A data processing apparatus is provided with packing circuitry | 2009-05-21 |
20090132864 | CLUSTERING PROCESS FOR SOFTWARE SERVER FAILURE PREDICTION - Embodiments of the present invention allow the prevention and/or mitigation of damage caused by server failure by predicting future failures based on historic failures. Statistical data for server parameters may be collected for a period of time immediately preceding a historic server failure. The data may be clustered to identify cluster profiles indicating strong pre-fault clustering patterns. Real time statistics collected during normal operation of the server may be applied to the cluster profiles to determine whether real time statistics show pre-fault clustering. If such a pattern is detected, measures to prevent or mitigate server failure may be initiated. | 2009-05-21 |
20090132865 | Systems and Methods for Automatic Profiling of Network Event Sequences - Systems and methods are disclosed that profile event sequences by creating a mixture model from the event sequences; estimating parameters for the mixture model; and applying the mixture model to profile the event sequences. | 2009-05-21 |
20090132866 | STORAGE APPARATUS - According to an aspect of an embodiment, a storage apparatus comprising; a pair of control devices for controlling storage devices, each control device being connected with another control device; storage devices for storing data; switches being connected with the plurality of storage devices, the switches being connected between the control devices in series; wherein the control device for controlling the plurality of switches according to a process comprising the steps of: detecting a fault in the connection of the switches, and; controlling the control devices to access the storage devices via the switches such that one of the control devices accesses a part of the storage devices via a part of the switches located between said one of the control devices and the fault, and the other of the control devices accesses remainder of the storage devices via remainder of the switches, respectively. | 2009-05-21 |
20090132867 | MEDIA FOR USING PARALLEL PROCESSING CONSTRUCTS - One or more computer-readable media store executable instructions that, when executed by processing logic, perform parallel processing. The media store one or more instructions for receiving one or more portions of an inner context of a program created for a technical computing environment, allocating one or more portions of the inner context of the program to two or more labs for parallel execution, receiving one or more results associated with the parallel execution of the one or more portions from the two or more labs, and providing the one or more results to an outer context of the program. | 2009-05-21 |
20090132868 | MESSAGE STATE MAINTENANCE AT A MESSAGE LOG - The present invention extends to methods, systems, and computer program products for maintaining message state at a message log. Messages are accumulated at a message log in accordance with a message retention policy. Any of a variety of message capture assurances can be used when capturing a message from a message producer within a message log. A message becomes visible to message consumers after the outcome of writing the message is known (either failure or success). Messages are requested using (e.g., monotonically increasing) sequence numbers. Messages are also dropped from the message log in accordance with the message retention policy. | 2009-05-21 |
20090132869 | TIMEOUT REQUEST SCHEDULING USING GROUPING AND NONSYNCHRONIZED PROCESSING TO ENHANCE PERFORMANCE - An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling timeout requests to determine whether the expiration time has been reached for execution of an input/output (I/O) request, thereby requiring action to cancel the I/O operation if it has not yet been completed. | 2009-05-21 |
20090132870 | DYNAMIC MASK MEMORY FOR SERIAL SCAN TESTING - A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs. | 2009-05-21 |
20090132871 | SYSTEM AND METHOD FOR DETECTING ERRORS IN ELECTRONIC DOCUMENT WORKFLOW - A system and method for detecting errors in a document transfer scheme. A user submits an electronic document transfer scheme to the document processing device including document handling instructions. The electronic document transfer scheme is then received by the document processing device and parsed, via the controller, to extract data representative of the destination designated by the scheme. Preferably, the destination data contained in the scheme provides the document processing device with a location to which a copy of an electronic document is to be sent. The source/destination information is then input as an arc on a graph, so as to generate a representation of the workflow associated with the document transfer scheme. A determination is then made, from the graph, whether the submitted electronic document transfer scheme represents at least one cycle on the graph. When it is determined, from an algorithmic query of the graph, that an infinite document transfer scheme exists, a notification is sent to the user submitting the most recent document transfer scheme. | 2009-05-21 |
20090132872 | Method and Application for Generating Interleaver or De-Interleaver - A method and application for generating an interleaver or a de-interleaver are described. The method for generating interleaver includes: setting interleaving information of a base interleaver and/or de-interleaving information of a base de-interleaver, and respectively performing a cyclic shift transform on the interleaving information of the base interleaver so as to generate a plurality of different interleavers. Alternatively, the method for generating interleaver includes: deducing from the de-interleaving information to obtain the interleaving information of the base interleaver and performing the cyclic shift on the interleaving information obtained by deduction so as to generate a plurality of different interleavers. The method for realizing interleaving includes: inputting a data frame of each subscriber needed to be interleaved to the base interleaver and performing the cyclic shift on the data frame output by the base interleaver so as to realize interleaving, in which different subscribers correspond to different cyclic shifts. Alternatively, the method for realizing interleaving includes: performing the cyclic shift on the data frame of each subscriber to be interleaved and inputting the data frame after the cyclic shift to the base interleaver so as to realize interleaving, in which different subscribers correspond to different cyclic shifts. | 2009-05-21 |
20090132873 | Method and System for Determining Element Voltage Selection Control Values for a Storage Device - A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization. | 2009-05-21 |
20090132874 | SYSTEM AND METHOD FOR TESTING A DATA STORAGE DEVICE WITHOUT REVEALING MEMORY CONTENT - A system and method for testing a data storage device without revealing memory content. To control the individual bits of the memory during testing each value is written into the memory according to the equation | 2009-05-21 |
20090132875 | METHOD OF CORRECTING ERROR OF FLASH MEMORY DEVICE, AND, FLASH MEMORY DEVICE AND STORAGE SYSTEM USING THE SAME - According to this invention, a highly reliable memory device that uses up a life of a flash memory can be provided. The memory device is a nonvolatile memory device including a plurality of memory cells, in which: each of the plurality of memory cells is an FET which includes a floating gate; the plurality of memory cells are divided into a plurality of deletion blocks; and the nonvolatile memory device reads data stored in a first deletion block, detects and corrects an error contained in the read data, stores, when the number of bits of the detected error exceeds a threshold, the corrected data in a second deletion block, sets a smaller value as the threshold as an error frequency detected in the first deletion block is higher, and sets a smaller value as the threshold as the number of deletion times executed in the first deletion block is larger. | 2009-05-21 |
20090132876 | Maintaining Error Statistics Concurrently Across Multiple Memory Ranks - A method and apparatus to maintain memory read error information concurrently across multiple ranks in a computer memory. An error detection unit associates a read error with a particular rank and with a particular chip in the rank. The error detection unit reports the error and the associated rank ID and chip ID to an error logging unit. The error logging unit maintains, for each rank ID and chip ID for which an error has been detected, a total number of errors that occur. A memory controller uses a fault pattern in the error logging unit to replace failing memory chips or memory ranks with a spare memory chip or a spare memory rank. | 2009-05-21 |
20090132877 | Method for Embedded Integrated End-to-End Testing - A method and system for automated testing of a system such as a billing module in a telecommunication system is disclosed. In a first embodiment, test APIs, scenarios and configuration information are embedded into the module itself in a way such that, when testing is desired, tests may be conducted without any need for a dedicated test environment. Tests can be run from within the module itself, thereby eliminating the risk, expense and time required to use external testing systems and data to test the module. In another embodiment, operational data such as live operational orders are wrapped in test headers and are used as input data for testing purposes within the billing module. In this embodiment, test APIs may be embedded into all modules of an operational support system so that complete system end-to-end testing is possible without the use of dedicated external test equipment and processes. | 2009-05-21 |