21st week of 2009 patent applcation highlights part 22 |
Patent application number | Title | Published |
20090128158 | VOLTAGE DETECTION DEVICE AND ELECTRIC VEHICLE INCLUDING VOLTAGE DETECTION DEVICE - A voltage detection device for accurately correcting detection errors with voltage greater than an internal reference voltage. The device includes a first switch group of switches for obtaining the voltage across a battery block in a battery pack. A charge-discharge unit has two or more capacitors connected in series or in parallel. A voltage detector detects discharge voltage of the capacitors. In a first period, the capacitors are series-connected and charged with the voltage of the battery block. In a second period, the capacitors charged in the first period are series-connected and discharged, and the voltage detector detects the discharge voltage. In a third period, the capacitors are parallel-connected and each capacitor is charged with an internal reference voltage. In the fourth period, the capacitors charged in the third period are series-connected and discharged, and the detection error is corrected using the discharge voltage as a reference. | 2009-05-21 |
20090128159 | BATTERY PACK ANOMALY DETECTING METHOD AND BATTERY PACK - An anomaly detecting method for a battery pack including a secondary battery made up of at least one cell and a voltage detecting circuit for measuring cell voltage of the secondary battery comprises the steps of measuring the cell voltage, judging by using the measured cell voltage whether predefined anomaly judgment conditions to be used in determining that at least one of an internal short circuit of the cell and an anomaly of the voltage detecting circuit has occurred are satisfied, and determining that at least one of the internal short circuit of the cell and the anomaly of the voltage detecting circuit has occurred if the anomaly judgment conditions are judged to have been satisfied. The anomaly detecting method prevents in advance continued execution of charge operation when the cell voltage does not reach a threshold voltage due to an internal short circuit of the cell or an anomaly of the voltage detecting circuit. | 2009-05-21 |
20090128160 | DUAL SENSOR SYSTEM HAVING FAULT DETECTION CAPABILITY - A sensor system ( | 2009-05-21 |
20090128161 | Structure for robust cable connectivity test receiver for high-speed data receiver - A design structure embodied in a machine-readable medium used in a design process may include a system for detecting a fault in a signal transmission path. Such system may include, for example, a hysteresis comparator including a latch having n-type field effect transistor (“NFET”) storage elements. The hysteresis comparator may be operable to detect a crossing of a reference voltage level by an input signal arriving from the signal transmission path such that when the comparator does not detect an expected crossing of the reference voltage level by the input signal, the fault is determined to be detected in the signal transmission path. | 2009-05-21 |
20090128162 | CALIBRATING AUTOMATIC TEST EQUIPMENT - A method for use with automatic test equipment (ATE) includes programming the ATE to generate bursts, each of which corresponds to a signal characteristic produced by the ATE, obtaining power levels for the bursts, and determining if the power levels for the bursts correspond to expected power levels for signal characteristics corresponding to the bursts. | 2009-05-21 |
20090128163 | SIMULATED BATTERY LOGIC TESTING DEVICE - A simulated battery test device and method that is capable of testing a battery charging circuit and logic circuit to determine proper operation. An operational amplifier is used that can both source and sink current to simulate the operation of the battery. A battery low signal can be generated using the simulated battery test device to test a battery charging circuit and logic circuit in a battery low condition. In addition, a battery open signal can be generated to test the battery charging and logic circuit in a battery open condition. Charging currents are detected to determine if currents fall within an acceptable range. | 2009-05-21 |
20090128164 | PHASE FREQUENCY DISTORTION MEASUREMENT SYSTEM - Disclosed is a method of measuring frequency distortions characteristics of a device under test, said device configured convert an input signal in an input frequency range to an output signal in a different output frequency range. The method includes, for each test frequency f | 2009-05-21 |
20090128165 | CAPACITANCE MEASURING APPARATUS FOR CAPACITOR - A measuring apparatus for measuring capacitance of a capacitor includes a microprocessor, a control circuit coupled to the capacitor, and an Analog-to-Digital (A/D) converting circuit. The control circuit receives a control signal from the microprocessor, and outputs an analog voltage signal of the capacitor, and the control circuit charges/discharges the capacitor according to the control signal. The A/D converting circuit receives the analog voltage signal from the control circuit, and outputs a digital voltage signal. The microprocessor receives the digital voltage signal from the A/D converting circuit, and calculates capacitance of the capacitor according to the digital voltage signal and charge/discharge time. | 2009-05-21 |
20090128166 | APPARATUS TO MEASURE THE CLEARANCE BETWEEN A FIRST COMPONENT AND A SECOND COMPONENT - An apparatus for determining a clearance between rotor blade tips of rotor blades mounted on a rotor and a stator lining mounted on a stator casing. The stator lining is movable radially relative to the stator casing. The stator lining comprises an abradable material. At least one probe is arranged to measure the clearance between blade tips and stator lining. A first portion of the at least one probe is arranged within the stator lining and a tip of the first portion of the at least one probe is arranged flush with the surface of the abradable material. The tip of the first portion of the at least one probe comprises an abradable material. A second portion of the at least one probe is secured to the stator casing. A wire-less and connector-less coupling transmits a measurement signal from the first portion to the second portion of the at least one probe to allow radial movement of the stator lining relative to the stator casing. | 2009-05-21 |
20090128167 | METHOD FOR MEASURING AREA RESISTANCE OF MAGNETO-RESISTANCE EFFECT ELEMENT - A method for measuring an area resistance of a magneto-resistance effect element which includes an upper-barrier layer having a first sheet resistivity Rt, a barrier layer, and a lower-barrier layer having a second sheet resistivity Rb, includes a resistance measurement step, a sheet resistivity measurement step and a establishing step. The resistance measurement step is the step of measuring a resistance R of the magneto-resistance effect element by using predetermined terminals. The sheet resistivity measurement step measures the first sheet resistivity Rt and the second sheet resistivity Rb. The establishing step determines the area resistance RA of the magneto-resistance effect element using the first sheet resistivity Rt, the second sheet resistivity Rb, the resistance R and the intervals among the predetermined terminals. | 2009-05-21 |
20090128168 | MULTIFUNCTIONAL CONDUCTING POLYMER STRUCTURES - The present invention includes the use of conducting polymers as sensors in distributed sensing systems, as sensors and operating elements in multifunctional devices, and for conducting-polymer based multifunctional sensing fabrics suitable for monitoring humidity, breath, heart rate, blood (location of wounds), blood pressure, skin temperature, weight and movement, in a wearable, electronic embedded sensor system, as examples. A fabric comprising conducting polyaniline fibers that can be used to distribute energy for resistive heating as well as for sensing the fabric temperature is described as an example of a multifunctional sensing fabric. | 2009-05-21 |
20090128169 | CORROSION DETECTING STRUCTURAL HEALTH SENSOR - A sensor device for monitoring and testing for potential corrosion of structural elements is disclosed. A membrane including a thin conductor sense loop within it may be disposed near a structural element to be monitored. Measured changes in the electrical properties of the conductor sense loop reveal corrosion of the conductor and can indicate potential corrosion in the structural element. The sensor may also be implemented as a gasket. Connection to the sensor device may be through a connector or using a wireless reader which remotely energizes the sensor device. | 2009-05-21 |
20090128170 | PRINT MEDIA DETECTING MODULE - A print medium detecting module includes a first conductive unit, a second conductive unit and a detector. The first conductive unit is coupled to a first reference voltage level. The detector has a detecting port, which is coupled to the second conductive unit and a second reference voltage level, for referring to an electrical characteristic of the detecting port to detect whether there is a non-conductive print media between the first and second conductive units that causes the first conductive unit to not be electrically connected to the second conductive unit. The first and second conductive units in an initial state are electrically connected to each other. The first reference voltage level is different from the second reference voltage level. | 2009-05-21 |
20090128171 | Microstructure Probe Card, and Microstructure Inspecting Device, Method, and Computer Program - An inspecting method which is for a microstructure with a movable portion and executes a highly precise inspection without damaging a probe or an inspection electrode by supressing the effect of a needle pressure in contacting the probe to the inspection electrode is provided. | 2009-05-21 |
20090128172 | CALIBRATION BOARD FOR ELECTRONIC DEVICE TEST APPARATUS - A calibration board mounted on a socket when calibrating an electronic device test apparatus for testing an IC by bringing ball contacts of the IC into electrical contact with contact terminals of the socket includes calibration terminals for electrically contacting the contact terminals; and a board comprising an insulating member and provided with the calibration terminals, wherein the calibration terminals have spherical members sticking out from the board toward the contact terminals so as to correspond to the shapes of the contact terminals. | 2009-05-21 |
20090128173 | TESTING SYSTEM AND METHOD - An exemplary testing system for measuring an electronic device includes a main controller for generating a control signal, a signal generator for outputting a predetermined test input signal according to the control signals, an instrument unit comprising a plurality of instruments, and a testing port comprising a plurality of probes. The probes are configured for connecting corresponding testing points of the electronic device to the signal generator and the instruments. The predetermined test input signal is transmitted to the electronic device via the testing port, the instrument unit processing a test result signals outputted by the electronic device and outputting a result data, and the main controller receiving the result data and computing whether the result data is within a predetermined range. A related testing method is also provided. | 2009-05-21 |
20090128174 | Probe card using thermoplastic resin - Disclosed is a probe card using thermoplastic resin. The probe card includes: a printed circuit board; a probe head that includes a plurality of terminals disposed on one surface thereof, the terminals being electrically connected to the printed circuit board; and a plurality of probe tips electrically connected to a plurality of the terminals and disposed on the other surface of the probe head, whereas the other surface of the probe head is formed of thermoplastic resin. According to the probe card, it is possible to reduce an inferior goods rate by protecting the probe head even during an etching process. | 2009-05-21 |
20090128175 | PROBE UNIT SUBSTRATE - A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the first conductor layer, which includes through-hole junction pads, flatness improvement rings surrounding the through-hole junction pads and a grounding region further surrounding the flatness improvement rings. Since the flatness improvement rings are located around the through-hole junction pads, the surface of the first insulating layer, which is located above the first conductor layer, is free from severe undulation even near the through-hole junction pads. Accordingly, the multilayer wiring division has less irregularity in shape as a whole, and thus the probe mounting pads on the surface of the second insulating layer do not slope but keep almost horizontal. The probe unit substrate according to the invention has an advantage of less surface undulation and having non-sloping probe mounting pads without using a complicated manufacturing process. | 2009-05-21 |
20090128176 | HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF - The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer. | 2009-05-21 |
20090128177 | ATTACHMENT FOR SOCKET AND SEMICONDUCTOR DEVICE-TESTING UNIT HAVING THE SAME - To provide an attachment for a socket which can cope with automatic testing of the IC devices, and which can enhance the radiation of heat from the IC devices despite of its reduced size, as well as to provide a semiconductor device-testing unit having the same. An attachment | 2009-05-21 |
20090128178 | WAFER INSPECTING APPARATUS, WAFER INSPECTING METHOD AND COMPUTER PROGRAM - There is provided a wafer inspecting apparatus which reduces a preheating time of a probe, and prevents the probe and a wafer from being damaged. The apparatus has a stage ( | 2009-05-21 |
20090128179 | Wiring Pattern Characteristic Evaluation Mounting Board - Wiring pattern characteristic evaluation mounting boards in which characteristics of wiring patterns formed on the mounting boards are previously evaluated when the mounting boards are manufactured in mass-production, and more particularly relates to such wiring pattern characteristic evaluation mounting boards in which characteristics of wiring patterns to a high frequency pulse signal or a high speed pulse signal are evaluated. | 2009-05-21 |
20090128180 | Cantilever-Type Probe and Method of Fabricating the Same - Disclosed is a cantilever-type probe and methods of fabricating the same. The probe is comprised of a cantilever being longer lengthwise relative to the directions of width and height, and a tip extending from the bottom of the cantilever and formed at an end of the cantilever. A section of the tip parallel to the bottom of the cantilever is rectangular, having four sides slant to the lengthwise direction of the cantilever. | 2009-05-21 |
20090128181 | DRIVER CIRCUIT AND TEST APPARATUS - Provided is a driver circuit that includes a first operational mode and a second operational mode and outputs an output signal according to an input signal, including a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, outputs a power supply power having a predetermined voltage and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, generates the output signal according to the input signal and outputs the thus generated signal to the outside. The second driver section includes a first transistor that, in the second operational mode, generates the output signal by operating according to the input signal and receives the power supply power from the first driver section and a second transistor that, in the second operational mode, operates differentially with respect to the first transistor and receives the power supply power from the first driver section commonly with the first transistor. | 2009-05-21 |
20090128182 | DRIVER CIRCUIT AND TEST APPARATUS - Provided is a driver circuit that has a first operational mode and a second operational mode and outputs an output signal according to an input signal. The driver circuit includes a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, is controlled to be disabled; a high precision driver section that, in the first operational mode, is controlled to be disabled and, in the second operational mode, outputs a source power having a predetermined voltage; and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, receives the source power from the high precision driver section, generates the output signal according to the input signal, and outputs the thus generated signal to the outside. | 2009-05-21 |
20090128183 | DEVICE FOR MEASURING THICKNESS AND SQUARE RESISTIVITY OF INTERCONNECTING LINES - A microelectronic device comprising one or several metallic levels provided with one or several superposed metallic interconnecting levels and at least one test structure:
| 2009-05-21 |
20090128184 | Testing High Frequency Signals on a Trace - A system, apparatus and method for testing and measuring high frequency signals on a trace is described. In one embodiment of the invention, a footprint is manufactured on a trace to allow the testing of a signal while reducing the amount of distortion caused by prior art structures and methods. The footprint is designed to reduce stub effects and capacitance on a signal being communicated on the trace. | 2009-05-21 |
20090128185 | On-die termination circuit and driving method thereof - An on-die termination circuit is capable of increasing a resolution without enlargement of a chip or a layout size. The on-die termination circuit includes a control means, a termination resistance supply means, a code signal generating means. The control means sequentially generates a plurality of control signals in a response to a driving signal. The termination resistance supply means supplies a termination resistance in response to a coarse code signal having a plurality of bits and a fine code signal having a plurality of bits. The code signal generating means controls the fine code signal and the coarse code signal in response to the plurality of the control signals in order that the termination resistance has a level which is correspondent to an input resistance. | 2009-05-21 |
20090128186 | PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL - A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads. | 2009-05-21 |
20090128187 | PRE-PROCESSING DATA SAMPLES FROM PARALLELIZED DATA CONVERTERS - An apparatus for pre-processing data samples from parallelized analog-to-digital converters (ADC). An ADC converts an analog signal into N parallel digital data samples that are output on N ADC links x | 2009-05-21 |
20090128188 | Pad invariant FPGA and ASIC devices - A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering the predetermined positions of the pads and the circuit blocks. | 2009-05-21 |
20090128189 | Three dimensional programmable devices - In a first aspect, a three dimensional programmable logic device (PLD) comprises a plurality of distributed programmable elements located in a substrate region; and a contiguous array of configuration memory cells, a plurality of said memory cells coupled to the plurality of programmable elements to configure the programmable elements, wherein: the memory array is positioned substantially above or below the substrate region; and the memory array and the substrate region layout geometries are substantially similar. In a second aspect, the 3D PLD comprises a contiguous array of metal cells, each metal cell having the configuration memory cell dimensions and a metal stub coupled to a said configuration memory cell and to one or more of said programmable elements. | 2009-05-21 |
20090128190 | Implementing Logic Functions with Non-Magnitude Based Physical Phenomena - An n-valued switch with n≧2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed. | 2009-05-21 |
20090128191 | ULTRA-LOW-POWER LEVEL SHIFTER, VOLTAGE TRANSFORM CIRCUIT AND RFID TAG INCLUDING THE SAME - A level shifter increase a voltage level of an output signal with relatively lower power consumption by adopting current-starved configuration. The level shifter includes an input unit and a driving unit. The input unit includes a current-starved inverter configured to generate a control signal in response to an input signal and a bias voltage. The input unit is powered by a first power supply voltage. The driving unit generates an output signal in response to the control signal. The output signal has a voltage level higher than the input signal, and the driving unit is powered by a second power supply voltage higher than the first power supply voltage. | 2009-05-21 |
20090128192 | DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A data receiver of a semiconductor integrated circuit includes an amplifier that outputs an amplified signal by detecting and amplifying received data using equalization function according to feedback data, a detecting unit that detects a period when data is not received in the amplifier and outputs a detecting signal, and an equalization function control unit that stops the equalization function of the amplifier in response to the detecting signal. | 2009-05-21 |
20090128193 | FAST, LOW OFFSET GROUND SENSING COMPARATOR - A fast, accurate, low offset comparator may be configured with multiple gain stages. A low gain, low input impedance, and fully differential common-gate amplifier may be configured as a first stage in the multi-stage comparator, providing a wide bandwidth for small power consumption. The inputs of the comparator may comprise a pair of differential inputs at respective source terminals of gate-coupled metal oxide semiconductor (MOS) devices configured in the input stage of the common-gate amplifier. A pair of differential outputs of the first stage may be coupled to a pair of differential inputs of a second stage, which may be a differential input current-mirror amplifier that may perform differential to single-ended conversion. The single-ended output of the second stage may serve as the input into a latch, which may be a bistable set-reset (SR) latch configured to increase the gain and response time while protecting against multiple switching, with the single-ended output of the latch configured as the output of the comparator. | 2009-05-21 |
20090128194 | Method And Device For Adjusting Or Setting An Electronic Device - Method and device for adjusting or setting an electronic device ( | 2009-05-21 |
20090128195 | INTEGRATED CIRCUIT COMPARATOR OR AMPLIFIER - An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit. | 2009-05-21 |
20090128196 | Data Holding Circuit - A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element. | 2009-05-21 |
20090128197 | Senthesizer module - To provide a synthesizer module that can be used not only in a destination area but also in the whole world and that can be readily set in output frequency. In the synthesizer module, a calculation formula table of a nonvolatile memory stores a plurality of frequency modes and the calculation formula of carrier frequencies corresponding to those frequency modes, and further stores in its certain area, a frequency mode set during an initial setting of the device. A CPU, when receiving a channel number from a rotary SW during a frequency setting, calculates, based on a calculation formula corresponding to a currently set frequency mode, a carrier frequency corresponding to the channel number. This carrier frequency is set to a CONT of a PLL part. | 2009-05-21 |
20090128198 | DIGITAL FREQUENCY SYNTHESIZER - A digital frequency synthesizer receiving a first signal corresponding to a periodic sequence of first pulses at a first frequency and providing a second signal corresponding to a periodic sequence of second pulses at a second frequency. The synthesizer includes a first circuit clocked by a third signal corresponding to a sequence of third pulses and obtained from the first signal, the first circuit providing a fourth digital signal which, for any set of third successive pulses, increases (decreases) on each pulse and decreases (increases) at the end of said set; and a second circuit receiving the first and fourth signals and providing, for each first pulse from among some at least of the first pulses, a second pulse which is shifted with respect to the first pulse by a duration which depends on the fourth signal. | 2009-05-21 |
20090128199 | BIASED CLOCK GENERATOR - A method and system for generating a pair of synchronized clock signals is described. The system includes a first device connected between a first output voltage and an input reference voltage, wherein the first device generates a first output clock signal. Further, the system includes a second device connected in series with the first device. In particular, the second device is connected between the input reference voltage and a second output voltage, wherein the second device generates a second output clock signal. In addition, a first switching circuit is connected in parallel with the first device and a second switching circuit is connected in parallel with the second device. The first switching circuit operates to toggle the first device on and off and the second switching circuit operates to toggle the second device on and off. The first and second switching circuits are coupled to a comparator, which receives a first input clock and a second input clock signal. | 2009-05-21 |
20090128200 | RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal. | 2009-05-21 |
20090128201 | CLOCK GENERATORS AND CLOCK GENERATION METHODS THEREOF - Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency. | 2009-05-21 |
20090128202 | Timer unit circuit having plurality of output modes and method of using the same - First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode, an output circuit outputs signals exhibiting normal-phase and reversed-phase PWM waveforms based on both of the signals of the first and second counter circuits. In a second output mode, the output circuit outputs signals that are each based only on either of the signals of the first and second counter circuits. | 2009-05-21 |
20090128203 | PLL-BASED TIMING-SIGNAL GENERATOR AND METHOD OF GENERATING TIMING SIGNAL BY SAME - A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency F | 2009-05-21 |
20090128204 | Time delay apparatus - A time delay apparatus for generating a plurality of phase shifted signals is described comprising a phase tuner generating a phase control signal and a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by. phase shifting the digital signal according to the phase control signal. | 2009-05-21 |
20090128205 | ELECTRONIC PULSE-GENERATING DEVICE - An electronic pulse-generating device ( | 2009-05-21 |
20090128206 | Apparatus and Method for Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler - An apparatus and method for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler are provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit. | 2009-05-21 |
20090128207 | Clock Circuitry for Generating Multiple Clocks with Time-Multiplexed Duty Cycle Adjustment - Clocking circuitry includes a first clock generator to generate a first clock signal and having a first duty cycle correction input, and a second clock generator to generate a second clock signal and having a second duty cycle correction input. Some embodiments have more than two clock generators. A multiplexer selects between the clock signals from the clock generators. The multiplexer has a first input coupled to the first clock signal and has a second input coupled to the second clock signal, and has a clock output coupled to a clock input of a duty cycle circuit. The duty cycle circuit receives the selected clock signal from the multiplexer and generates a duty cycle correction signal. | 2009-05-21 |
20090128208 | APPARATUS AND METHOD FOR DETECTING DUTY RATIO OF SIGNALS IN SEMICONDUCTOR DEVICE CIRCUIT - Apparatus for detecting duty ratio of signals in semiconductor device circuit includes a circuit for detecting a duty ratio of signals in a semiconductor device includes a comparing unit which compares a duty cycle of first and second input clock signals input differentially and generates a first output signal and a second output signal, a latching unit which stores the first and second output signals and generates a detected signal corresponding to the first and second output signals, and an adjusting unit which receives the first and the second output signals, and transmits the first and the second output signals to the latching unit based on a voltage level difference of the first and second output signals. | 2009-05-21 |
20090128209 | PULSE WIDTH MODULATION CONTROL CIRCUIT APPLIED TO CHARGE OUTPUT CAPACITOR - A pulse width modulation (PWM) control circuit is applied to a power converter with a charging capacitor. The PWM control circuit includes a PWM signal generator, a first comparator, and a reference voltage modulator. A PWM signal generator generates a PWM signal to control a power switch in the power converter. Two input terminals of the first comparator respectively receive a first reference voltage and a sensing voltage, which is proportional to a primary-side current of a transformer. When the power switch is turned on and the sensing voltage rises to the level of the first reference voltage, the first comparator outputs a first control signal to the PWM signal generator. Then, the PWM signal generator outputs a signal to turn off the power switch. The reference voltage modulator outputs the first reference voltage according to a feedback voltage relative to the output voltage of the power converter. | 2009-05-21 |
20090128210 | SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC CIRCUIT - An electric circuit has a first differential circuit for transmitting input data to a first node, a second differential circuit for holding the first node data, a first clock transmission circuit for flowing a first current in accordance with a clock signal, and a first transformer circuit for transformer-coupling the first differential circuit with the first clock transmission circuit, and the second differential circuit with the first clock transmission circuit. | 2009-05-21 |
20090128211 | NOISE FILTER CIRCUIT, NOISE FILTERING METHOD, THERMAL HEAD DRIVER, THERMAL HEAD, ELECTRONIC INSTRUMENT, AND PRINTING SYSTEM - A noise filter circuit includes a latch circuit that receives an input signal. The latch circuit includes first and second logic circuits (e.g., NAND circuits). The first and second NAND circuits are configured so that the capability of a P-type transistor that receives a set signal or a reset signal is lower than the capability of an N-type transistor that receives the set signal or the reset signal and the capability of an N-type transistor connected in series with the N-type transistor that receives the set signal or the reset signal (total capability). The noise filter circuit may include a waveform adjusting circuit that receives an output signal from the latch circuit. | 2009-05-21 |
20090128212 | Charge pump systems with adjustable frequency control - An electronic system includes a charge pump driver for generating an output to control an electronic element. The electronic system further includes a clock generator coupled to the charge pump driver. The clock generator can generate a clock signal to control the charge pump driver and adjust a frequency of the clock signal according to a status of the electronic element. | 2009-05-21 |
20090128213 | INTEGRATED CIRCUIT CLOCK STRUCTURE - An integrated circuit includes first and second circuits, and a clock structure. The clock structure consists of a crystal oscillation circuit, a plurality of buffers, and a plurality of clock generating modules. An input of each of the plurality of buffers is coupled to receive a reference clock signal from the crystal oscillation circuit. Each of the plurality of clock generating modules is coupled to a corresponding one of the plurality of buffers and, when enabled, generates a clock signal. | 2009-05-21 |
20090128214 | DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT - A data receiver includes a plurality of amplifiers for receiving data in response to clock signals having a predetermined phase difference, and amplifying the received data by performing an equalization function based on feedback data, thereby outputting amplification signals, and a plurality of latches for latching output of the amplifiers, respectively. One amplifier receives the amplification signal, as feedback data, from another amplifier receiving a clock signal having a phase more advanced than a phase of a clock signal received in the one amplifier. | 2009-05-21 |
20090128215 | LEVEL SHIFTER, INTERFACE DRIVING CIRCUIT AND IMAGE DISPLAYING SYSTEM - The present invention relates to a level shifter for receiving a control signal to produce a driving voltage, comprising: a storage capacitor, one end of the storage capacitor coupled to the control signal and a reference voltage, another end of the storage capacitor coupled to the driving voltage and a assisting voltage; and a set of selecting switches for selecting one of the driving voltage and the assisting voltage to two ends of the storage capacitor, so that the storage capacitor is capable of boosting the voltage level of the control signal while the two ends of the storage capacitor coupled to the control signal and the driving voltage. The present invention further provides an interface driving circuit and an image displaying system. | 2009-05-21 |
20090128216 | SYSTEM AND METHOD FOR TIME-TO-VOLTAGE CONVERSION WITH LOCK-OUT LOGIC - An event time stamping system comprising a current source, an integrator comprising an input and an output, and configured to output a voltage proportional to the length of time the current source is coupled to the input, and one or more switches configured to couple the current source to the input of the integrator upon receipt of an event signal and configured to de-couple the current source from the input of the integrator upon receipt of a control trigger. The system further comprises a lock-out signal generator configured to generate a lock-out signal, and a controller coupled to the one or more switches, wherein the controller is configured to generate the control trigger based on the lock-out signal to ensure a minimum integration time. | 2009-05-21 |
20090128217 | Switching circuit - The application provides a switching circuit for switchably connecting an input node and an output node. The switching circuit comprises a switch operable to switchably connect the input node to the output node in response to a switching signal. A sensor is provided for sensing the voltage between the input and output nodes and providing a sense signal in response thereto. A driver coupled to the sensor adjusts the switching signal in response to the sense signal. | 2009-05-21 |
20090128218 | METHOD AND APPARATUS FOR CONTROLLING DEVICE BY DETECTING SCR THEREOF - A method and apparatus for controlling a device by detecting a silicon controlled rectifier (SCR) thereof, as well as a method and apparatus of automatic transfer switch controller thereof are disclosed. In one embodiment, the apparatus includes an input configured to receive input power, an output configured to provide said input power to a load a switch unit electrically coupled between said input and said output, the switch unit having at least one silicon controlled rectifier (SCR), a control unit electrically coupled to the switch unit for detecting the SCR of said switch unit and configured to provide a driving signal, and a device, which is driven by said control unit, wherein the driving signal is determined by the control unit after detecting a voltage value between the gate electrode and the cathode electrode of said SCR. | 2009-05-21 |
20090128219 | SEMICONDUCTOR DEVICE, POWER SUPPLY DEVICE, AND INFORMATION PROCESSING DEVICE - A semiconductor device ( | 2009-05-21 |
20090128220 | ISOLATION CIRCUIT - An isolation circuit is provided. The isolation circuit is coupled between a master circuit and a slave circuit for isolating or conducting an inter integrated circuit (I2C) signal. While the master circuit has electricity and the slave circuit does not, the isolation circuit isolates the master circuit to prevent the I2C signal being transmitted to the slave circuit. While the master circuit and the slave circuit have electricity, the isolation circuit conducts the master circuit to transmit the I2C signal to the slave circuit. The present invention solves the signal isolation problem between the master and slave circuits, and also improves the operational stability of an I2C bus. | 2009-05-21 |
20090128221 | METAL-INSULATOR-METAL (MIM) SWITCHING DEVICES - A gated nano-electro-mechanical (NEM) switch employing metal-insulator-metal (MIM) technology and related devices and methods which can facilitate implementation of low-power, radiation-hardened, high-temperature electronic devices and circuits. In one example embodiment a gate electrode is configured as a cantilever beam whose free end is coupled to a MIM stack. The stack moves into bridging contact across a source and drain region when the applied gate voltage generates a sufficient electrostatic force to overcome the mechanical biasing of the cantilever beam. A second set of contacts can be added on the cantilever beam to form a complementary switching structure, or to a separate cantilever beam. The switching can be configured as non-volatile in response to stiction forces. NEM circuits provide a number of advantages within a variety of circuit types, including but not limited to: logic, memory, sleep circuits, pass circuits, and so forth. | 2009-05-21 |
20090128222 | APPARATUS AND METHOD FOR ADJUSTING WORKING FREQUENCY OF VRD BY DETECTING TEMPERATURE - The invention provides an apparatus for adjusting a working frequency of a VRD by detecting temperature. The apparatus includes a temperature control module, a load module and a controller. The temperature control module is used for detecting a temperature of a CPU, and judging an output load state of the VRD according to the detected temperature of the CPU, so as to output a control signal according the output load state. The load module is connected to the VRD, and is used for providing an external resistance to the VRD. The controller is respectively coupled to the load module and the temperature control module, and is used for receiving the control signal and adjusting a resistance of the load module according to the received control signal, so as to adjust a working frequency of the VRD. A power consumption of the VRD may be reduced based on the present invention. | 2009-05-21 |
20090128223 | Thermally stable semiconductor power device - A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device. | 2009-05-21 |
20090128224 | SEMICONDUCTOR DEVICE - A semiconductor device includes a light-receiving element which is connected to a negative power supply and generates conductive carriers by receiving light, an amplifier transistor which is a depletion transistor and amplifies an electrical signal obtained by the conductive carriers, and a transfer gate transistor which is a depletion transistor and is controlled by a negative potential applied to a gate to electrically connect or disconnect the light-receiving element and the amplifier transistor. | 2009-05-21 |
20090128225 | STRUCTURE OF AN APPARATUS FOR PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE SEMICONDUCTOR FUSE - A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link. | 2009-05-21 |
20090128226 | Fuse option circuit - A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal. | 2009-05-21 |
20090128227 | HIGH VOLTAGE GENERATING DEVICE OF SEMICONDUCTOR DEVICE - A high voltage generator of a semiconductor device includes a first high voltage pump unit, a second high voltage pump unit, and a clock signal generating unit. The first high voltage pump unit compares a first high voltage and a first reference voltage to generate a first enable signal, and performs a pumping operation in response to the first enable signal and a first clock signal to generate the first high voltage. The second high voltage pump unit compares a second high voltage and a second reference voltage to generate a second enable signal, and performs a pumping operation in response to the second enable signal and a second clock signal to generate the second high voltage. The clock signal generating unit generates the first clock signal or the second clock signal in response to the first enable signal and the second enable signal when at least one of the first enable signal and the second enable signal is enabled. | 2009-05-21 |
20090128228 | Charge Pump Capable of Enhancing Power Efficiency and Output Voltage - The present invention relates to a charge pump capable of enhancing power efficiency and output voltage, which comprises a pump capacitor, a switching module, a first switch, a first buffer, a first switch, and an output capacitor. The switching module is coupled to a first terminal of the pump capacitor. The first switch is coupled between a second terminal of the pump capacitor and a supply voltage. The first buffer receives a first input signal and produces a control signal for controlling the first switch to turn on or cut off. The level of the first input signal ranges between a first voltage and a second voltage, wherein the first and the second voltages are related to the gate voltage of the first switch. The gate voltage of the first switch is a multiple, which is greater than one, of the supply voltage. Thereby, the impedance of the switch is reduced, and hence the power efficiency of the charge pump, the output voltage level, and the area efficiency of integrated circuits are improved. | 2009-05-21 |
20090128229 | MULTI-CHIP PACKAGE SEMICONDUCTOR DEVICE - An efficient logic chip operating power supply having digital circuits in a multi-chip package is provided. A multi-chip package semiconductor device fabricated in common with a driver chip having analog circuits and a logic chip having digital circuits, a logic chip power supply circuit is provided in which a driver chip creates a logic chip power supply dedicated for the logic chip. The logic chip has internal logic circuitry operating by receiving a power supply from the logic chip power supply circuit via power input terminals. | 2009-05-21 |
20090128230 | BAND-GAP REFERENCE VOLTAGE GENERATOR FOR LOW-VOLTAGE OPERATION AND HIGH PRECISION - Provided is a band-gap reference voltage generator for low-voltage operation and high precision. The band-gap reference voltage generator minimizes voltage drop by connecting resistors in parallel to bipolar transistors, and cancels temperature dependence by properly adjusting a resistor of an output stage, so that it can provide a stable reference voltage that is unaffected by a change in temperature in spite of a low power supply voltage. Further, the band-gap reference voltage generator minimizes variation of the reference voltage caused by offset noise by switching of input and output voltages at input and output stages of a feedback amplifier, so that it can provide a precise reference voltage. | 2009-05-21 |
20090128231 | CIRCUITS FOR GENERATING REFERENCE CURRENT AND BIAS VOLTAGES, AND BIAS CIRCUIT USING THE SAME - A circuit for generating a reference current comprises: a first current mirror configured to current-mirror based on a second current, so as to generate a first current that is substantially in inverse proportion to a variation of a power supply voltage; a current compensation unit configured to remove a variation of the first current corresponding to the variation of the power supply voltage to form a compensated first current; a second current mirror configured to generate the second current based on the compensated first current, and configured to provide the second current to the first current mirror; and a current output unit configured to output the second current as the reference current. | 2009-05-21 |
20090128232 | SWITCHED-CAPACITOR AMPLIFIER WITH IMPROVED RESET PHASE - A switch-capacitor (“SC”) amplifier includes a two-stage operational amplifier (“OP-AMP”), an input SC network, and a feedback SC network. The two-stage OP-AMP includes a first OP-AMP stage having an output coupled to an input of a second OP-AMP stage. The input SC network is coupled to an input of the first OP-AMP stage. The feedback SC network is configured to selectively couple the output of the first OP-AMP stage to the input of the first OP-AMP stage during a first phase of operation of the scamplifier and to couple an output of the second OP-AMP stage to the input of the first OP-AMP stage during a second phase of operation of the SC amplifier. | 2009-05-21 |
20090128233 | SHARED LINEARITY MAINTENANCE IN POWER AMPLIFIERS - In some embodiments, a circuit includes a power amplifier including an input terminal configured to receive an input signal and an output terminal to provide an RF voltage, the output terminal coupled to a load, a current sensor configured to sense the current drawn by the power amplifier and provide a first sensor output signal dependent upon current consumption when the current exceeds a predetermined current threshold, a voltage sensor configured to sense the output power of the power amplifier and provide a second sensor output signal when the RF voltage during up ramp falls below a predetermined threshold voltage, and a summing circuit configured to receive the first and second sensor output signals and provide a feedback signal including a combination of a power dependent contribution and either of a voltage dependent contribution or a current dependent contribution. | 2009-05-21 |
20090128234 | TWO-PEAK-POWER-LEVEL CONTROL METHOD AND DEVICE FOR A PULSE-MODE AMPLIFIER - A device for controlling least two peak power levels for an amplifier operating in pulse mode, characterized in that it comprises at least the following elements:
| 2009-05-21 |
20090128235 | Power save mode for audio interface drive amplifier - An apparatus includes a data processor coupled with a memory that stores a program executable by the data processor; an accessory interface readably coupled with the data processor and an amplifier having an output coupled to the accessory interface and a program input coupled to the data processor. The amplifier is responsive to the program input to change a current consumption of the amplifier in accordance with at least one electrical characteristic associated with an accessory that is connected to the accessory interface. The data processor programs the amplifier to operate in a stable mode of operation while consuming as little current as needed to operate the amplifier in the stable mode of operation. The data processor directly or indirectly determines an amount of capacitance and/or impedance associated with an interface to the accessory, and programs the amplifier accordingly. | 2009-05-21 |
20090128236 | High Efficiency Amplification - A radio frequency amplification stage comprising: an amplifier for receiving an input signal to be amplified and a power supply voltage; and a power supply voltage stage for supplying said power supply voltage, comprising: means for providing a reference signal representing the envelope of the input signal; means for selecting one of a plurality of supply voltage levels in dependence on the reference signal; and means for generating an adjusted selected power supply voltage, comprising an ac amplifier for amplifying a difference between the reference signal and one of the selected supply voltage level or the adjusted selected supply voltage level, and a summer for summing the amplified difference with the selected supply voltage to thereby generate the adjusted supply voltage. | 2009-05-21 |
20090128237 | SWITCHING AMPLIFIERS - Systems and methods implemented in a switching amplifier for providing consistent, matching switching between top and bottom switching devices in a switching amplifier. One embodiment includes a half-bridge circuit output stage, a driver stage and a transformer. The driver stage, which drives the switches of the output stage, is very fast, has a low propagation delay, and has minimal input capacitance. The transformer drives the drive paths from the transformer inputs to the switches. The transformer avoids resonances within the audio band and at the amplifier switching frequencies, has low and spread free leakage inductance, has enough magnetizing inductance to keep transformer currents low in proportion to the total driver stage current drain, has low core losses at the switching frequency, has minimal inductance change and operates well below its saturation point. The amplifier stage provides a substantially constant amplitude drive signal to the output power switching devices. | 2009-05-21 |
20090128238 | Offset cancellation of a single-ended operational amplifier - A single-ended operational amplifier includes an output stage, a first transconductance amplifier and a second transconductance amplifier. In an offset cancellation mode, two inputs of the first transconductance amplifier are supplied with a reference voltage to sink two currents from two inputs of the output stage respectively, the output stage generates a third current according to the difference between the two currents to charge a capacitor, and the second transconductance amplifier generates two currents according to the voltage in the capacitor to make currents in the two inputs of the output stage equal to each other, thereby canceling the offset of the single-ended operational amplifier. | 2009-05-21 |
20090128239 | Multistage Tuning-Tolerant Equalizer Filter with Improved Detection Mechanisms for Lower and Higher Frequency Gain Loops - The present invention provides an equalizer filter for compensating a received distorted signal for frequency dependent signal modifications introduced by a transmission channel, the received signal having an amplitude. The filter comprises at least one amplifying compensation stage having a gain and a saturation level, at least one limiting amplifier, and gain control means for controlling the gain of the at least one amplifying compensation stage, the gain control means comprising at least one comparator circuit comparing filtered input and output signals of the limiting amplifier, the at least one comparator circuit comprising a bias current source. The bias current source is adapted to deliver a variable current. | 2009-05-21 |
20090128240 | OSCILLATOR, PLL CIRCUIT, RECEIVER AND TRANSMITTER - An oscillator, a PLL circuit, a receiver and a transmitter that allow the circuit scale to be reduced and that are suitable for integration. The electrostatic capacities of variable capacitance circuits | 2009-05-21 |
20090128241 | ANALOGUE SELF-CALIBRATION METHOD AND APPARATUS FOR LOW NOISE, FAST AND WIDE-LOCKING RANGE PHASE LOCKED LOOP - A method of operating a phase lock loop includes generating a control voltage based on both an output signal of a voltage-controlled oscillator and a reference signal. An operating mode is selected from one of a high-gain mode, a zero-gain mode and a low-gain mode based on the control voltage. The phase lock loop is operated in the selected one of the high-gain mode, the zero-gain mode, and the low-gain mode. The control voltage is offset to generate an offset voltage based on the selected operating mode. The output signal is generated based on the offset voltage. | 2009-05-21 |
20090128242 | FREQUENCY GENERATION IN A WIRELESS COMMUNICATION UNIT - A wireless communication unit comprises a frequency generation circuit employing a fractional-based synthesiser, a voltage controlled oscillator circuit and a charge pump. A characterising function characterises a charge pump gain at a number of synthesized frequencies. A memory element is arranged to store characterised parameters. A scaling function is operably coupled to the memory element and the voltage controlled oscillator circuit and arranged to compensate for K | 2009-05-21 |
20090128243 | SEMICONDUCTOR DEVICE OUTPUTTING OSCILLATION SIGNAL - A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit. | 2009-05-21 |
20090128244 | TRANSISTOR VOLTAGE CONTROLLED OSCILLATOR - A FET transistor voltage-controlled oscillator is provided that includes a crossed-coupled inductor capacitor tank (LC-Tank) transistor voltage-controlled circuit having a first transistor and a second transistor, as well as a transistor frequency multiplying circuit having a third transistor and a fourth transistor. In the design, the gate of the first transistor is connected to the drain of the second transistor, and the gate of the second transistor is connected to the drain of the first transistor. Then, the source of the third transistor is connected to the source of the first transistor, and the source of the fourth transistor is connected to the source of the second transistor. Last, the gate of the third transistor is connected to the gate of the fourth transistor, and the drain of the third transistor is connected to the drain of the fourth transistor. Therefore, the parasitic capacitance present in the first transistor and the parasitic capacitance present in the second transistor generate an effect similar to two capacitors connected in series, via the transistor frequency multiplying circuit. The effect reduces the total capacitance of the voltage-controlled oscillator, to increase the working frequency of the voltage-controlled circuit and allow a circuit having the voltage-controlled circuit to operate at a high frequency. | 2009-05-21 |
20090128245 | Oscillator Circuit - The present invention relates to an oscillator circuit having a resonant element, an active element, a feedback loop, and an additional loop comprising a phase shifting element. | 2009-05-21 |
20090128246 | Apparatus and method of temperature compensating an ovenized oscillator - An oscillator having improved frequency stability which includes an oscillator circuit and an SC-cut resonator connected with the oscillator circuit. The SC-cut resonator has a first turning point. A temperature compensation circuit is connected with the oscillator circuit. The temperature compensation circuit is adapted to adjust a reference frequency generated by the oscillator circuit according to a frequency response associated with a second turning point of an AT-cut resonator. | 2009-05-21 |
20090128247 | INTERMITTENT OPERATION CIRCUIT AND MODULATION DEVICE - There is provided a small-size, low-power-consumption intermittent operation circuit capable of obtaining an output waveform having a rapid rise and fall. The intermittent operation circuit includes an active circuit ( | 2009-05-21 |
20090128248 | FILTER AND MANUFACTURING METHOD THEREOF - A filter includes a first magnetic layer, a second magnetic layer, an insulating layer, a plurality of coils, a first non-magnetic layer and a second non-magnetic layer. The insulating layer is disposed between the first magnetic layer and the second magnetic layer, and the coils are disposed in the insulating layer. The first non-magnetic layer is disposed on one side of the first magnetic layer, which is far away from the insulating layer, and the second non-magnetic layer is disposed on one side of the second magnetic layer, which is far away from the insulating layer. | 2009-05-21 |
20090128249 | Variable Capacitance Circuit - The invention relates to a variable capacitance circuit which achieves reduction in both of distortion and current consumption and furthermore achieves requirements of high power handling capability, cost reduction, and downsizing of the circuit. The variable capacitance circuit includes a first variable capacitance element unit having n pieces (where n is a natural number of two or more) of variable capacitance capacitor connected in series with respect to high frequency and in parallel with respect to direct current, each of the variable capacitance capacitors including one or more variable capacitance elements, each of which includes a dielectric layer with dielectric constant varying according to an applied direct-current voltage and a pair of electrodes sandwiching the dielectric layer therebetween, and a second variable capacitance element unit which has an applied voltage amplitude smaller than a voltage amplitude of high frequency signal applied to the first variable capacitance element unit, the second variable capacitance element unit including one piece of the variable capacitance elements or having m pieces (where m is a natural number smaller than n) of the variable capacitance elements connected. | 2009-05-21 |
20090128250 | POWER LINE TRANSMISSION - A device including an element for receiving an electrical signal comprising a high-frequency data signal component and a low-frequency power supply component. The electrical signal is conveyed in an electrical cable of an electrical installation. The device further includes impedance matching operative in a band of frequencies of the high-frequency signal component, the impedance matching being determined as a function of one or more characteristics of the electrical cable. Such a device can be integrated into a socket outlet or an electrical device or take the form of a socket adaptor. | 2009-05-21 |
20090128251 | DUAL-FREQUENCY MATCHING CIRCUIT - The connection topology of input terminals ( | 2009-05-21 |
20090128252 | DUAL-FREQUENCY MATCHING CIRCUIT - The connection topology of input terminals ( | 2009-05-21 |
20090128253 | High frequency electronic component - A high frequency electronic component includes: a first input terminal that receives a first transmission signal in the form of an unbalanced signal; a second input terminal that receives a second transmission signal in the form of a balanced signal; a balun that converts the second transmission signal in the form of a balanced signal received at the second input terminal to a second transmission signal in the form of an unbalanced signal and outputs this signal; and a switch. The switch performs switching between a signal received at a first input port and a signal received at a second input port, and outputs one of the signals from an output port. The first input port receives the first transmission signal received at the first input terminal. The second input port receives the second transmission signal in the form of an unbalanced signal outputted from the balun. The output port is connected to a power amplifier. | 2009-05-21 |
20090128254 | High frequency electronic component - A high frequency electronic component includes a switch and a balun. The switch performs switching between a first transmission signal in the form of an unbalanced signal received at a first input port and a second transmission signal in the form of an unbalanced signal received at a second input port, and outputs one of the first and second transmission signals from an output port. The balun converts the transmission signal in the form of an unbalanced signal outputted form the output port of the switch to a transmission signal in the form of a balanced signal, and outputs this signal to a balanced input power amplifier. | 2009-05-21 |
20090128255 | INTEGRATED BIDIRECTIONAL COUPLER - A distributed-line directional coupler including: a first conductive line between first and second ports intended to convey a signal to be transmitted; and a second conductive line, coupled to the first one, between third and fourth ports, the second line being interrupted approximately at its middle, the two intermediary ends being connected to attenuators. | 2009-05-21 |
20090128256 | SIGNAL CARRYING APPARATUS - A signal carrying apparatus ( | 2009-05-21 |
20090128257 | Ferrite phase shifter and automatic matching apparatus - In a ferrite phase shifter, a temperature rise at ferrites can be suppressed to maintain the characteristics of the frites even when used at high power. Thus, the phase shifter can stably demonstrate high performance. The ferrite phase shifter includes a rectangular waveguide, substantially sheet-like ferrites disposed to face each other with respective mounting surfaces kept in tight contact with inner walls of wide surfaces of the rectangular waveguide facing each other, and a coil which is wound around the periphery of the rectangular waveguide in a position substantially corresponding to the position of the ferrites and through which a current is passed. | 2009-05-21 |