20th week of 2022 patent applcation highlights part 67 |
Patent application number | Title | Published |
20220157743 | PACKAGE STRUCTURE WITH STACKED SEMICONDUCTOR DIES - A package structure is provided. The package structure includes a lower semiconductor die and a first protective layer surrounding the lower semiconductor die. The package structure also includes a dielectric layer partially covering the first protective layer and the lower semiconductor die and an upper semiconductor die over the lower semiconductor die and the first protective layer. The upper semiconductor die is bonded with the lower semiconductor die through a connector. The package structure further includes an insulating film surrounding the connector and a second protective layer surrounding the upper semiconductor die. A portion of the second protective layer is between the insulating film and the dielectric layer. | 2022-05-19 |
20220157744 | ORGANIC INTERPOSER INCLUDING A DUAL-LAYER INDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME - An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper. | 2022-05-19 |
20220157745 | PACKAGE SUBSTRATE, ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire. | 2022-05-19 |
20220157746 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides an antenna module. The antenna module includes a first layer, a second layer, a first antenna, and a second antenna. The first layer has a first dielectric constant. The second layer is adjacent to the first layer. The second layer has a second Dk lower than the first Dk. The first antenna is disposed on the first layer and is configured for operating at a first frequency. The second antenna is disposed on the second layer and is configured for operating at a second frequency higher than the first frequency. | 2022-05-19 |
20220157747 | SYSTEMS FOR MILLIMETER-WAVE CHIP PACKAGING - Various system embodiments for millimeter-wave chip packaging are disclosed in the present disclosure for smooth millimeter wave signal transition and good multi-channel signal isolation. The chip packaging features a substrate and a chip electrically connected using a plurality of metal pillars. A signal pillar and surrounding metal pillar may form a ground-signal-ground (GSG) pillar structure. A chip coplanar waveguide (CPW) structure may be formed on the chip around a signal path. A substrate CPW structure may also be form around a signal strip, which is electrically connected to the signal path. Characteristic impedances of the GSG pillar structure, the chip CPW structure and the substrate CPW structure may be within a predetermined range of each other to ensure smooth millimeter wave signal transition with minimum signal loss or distortion. | 2022-05-19 |
20220157748 | RADIO FREQUENCY MODULE - A mounting substrate has one main surface (a first main surface). An electronic component has a first face, a second face, and a side face, and is provided on the one main surface of the mounting substrate. A solder bump is disposed between the mounting substrate and the electronic component, and electrically connects the mounting substrate and the electronic component. A resin layer is provided on the one main surface of the mounting substrate to cover the electronic component. The first face is a face of the electronic component at a side opposite to the mounting substrate. The side face of the electronic component is in contact with the resin layer. A space is provided between at least a part of the first face and the resin layer in a thickness direction of the mounting substrate. | 2022-05-19 |
20220157749 | Solder Ball Application for Singular Die - A method is provided. The method includes one or more of conditioning one or more die pads of a singular die, applying a nickel layer to the one or more die pads, applying a gold layer over the nickel layer, applying a solder paste over the gold layer, applying one or more solder balls to the solder paste, and mating the one or more solder balls to one or more bond pads of another die, a printed circuit board, or a substrate. | 2022-05-19 |
20220157750 | SEMICONDUCTOR STRUCTURES WITH VIA OPENINGS AND METHODS OF MAKING THE SAME - The present disclosure discloses a semiconductor structure having an insulating layer disposed on a wafer active surface of a semiconductor wafer for covering the wafer active surface. The insulating layer may be a protective layer in some embodiments and a cover layer in other embodiments. The insulating layer has via openings to expose contact pads for leading out electrical connections. In particular, the via openings are formed by a multi-step etching process (such as a two-step etching process) without damaging the contact pads. The two-step etching process includes a first laser etching process using normal pulse (P) and normal energy to form partial via openings in the cover layer. The second etching process includes either a laser etching process using low P and low E or a plasma etching process. The second etching process avoids damaging the contact pads. | 2022-05-19 |
20220157751 | BOND PAD WITH ENHANCED RELIABILITY - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bond pad disposed over a substrate and a passivation structure disposed over the substrate and the bond pad. The passivation structure has one or more sidewalls directly over the bond pad. A protective layer is disposed directly between the passivation structure and the bond pad. The passivation structure extends from directly over the protective layer to laterally past a sidewall of the protective layer that faces a central region of the bond pad. | 2022-05-19 |
20220157752 | ELECTRONIC CIRCUIT FOR A HYBRID MOLECULAR BONDING - An electronic circuit including a surface intended to be attached to another electronic circuit by hybrid molecular bonding. The electronic circuit includes an electrically-insulating layer exposed on the surface, and, distributed in the electrically-insulating layer, first electrically-conductive bonding pads exposed on a first portion of the surface, the density of the first bonding pads on the first portion of the surface being smaller than 30%, and at least one electrically-conductive test pad, exposed on a second portion of the surface containing a square having a side length greater than 30 μm. The density of electrically-conductive material of the test pad exposed on the second portion of the surface is in the range from 40% to 80%. | 2022-05-19 |
20220157753 | SEMICONDUCTOR MEMORY DEVICE STRUCTURE - A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. | 2022-05-19 |
20220157754 | MEMORY DEVICE INCLUDING MEMORY CHIP AND PERIPHERAL MEMORY CHIP AND METHOD OF MANUFACTURING THE MEMORY DEVICE - A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines. | 2022-05-19 |
20220157755 | Method and System for Packing Optimization of Semiconductor Devices - Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently. | 2022-05-19 |
20220157756 | MOLDED SEMICONDUCTOR PACKAGE AND RELATED METHODS - Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps. | 2022-05-19 |
20220157757 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package may include: a first redistribution substrate; a first die above the first redistribution substrate; a second redistribution substrate on the first die; a first bump formed on the first die, and connecting the first die to the second redistribution substrate; a first molding portion enclosing the first die and surrounding the first bump; and an outer terminal on a bottom surface of the first redistribution substrate, wherein the second redistribution substrate comprises an insulating pattern and a conductive pattern in the insulating pattern to be in contact with the first bump, and wherein, at an interface of the second redistribution substrate and the first bump, the conductive pattern of the second redistribution substrate and the first bump are formed of the same material to form a single body or structure. | 2022-05-19 |
20220157758 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a conductive member including a main surface facing one side in a thickness direction; a semiconductor element including a plurality of pads facing the main surface of the conductive member; and a plurality of electrodes protruding from the plurality of pads toward the other side in the thickness direction. The conductive member includes a plurality of recessed portions recessed from the main surface toward the other side in the thickness direction. The semiconductor device further includes a bonding layer that is conductive and that is arranged in each of the plurality of recessed portions. The plurality of electrodes are separately inserted into the plurality of recessed portions. The conductive member and the plurality of electrodes are bonded through the bonding layers. | 2022-05-19 |
20220157759 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND METHOD FOR PRODUCING SAME - A display device and a method of making the display device are discussed. The display device includes a substrate, a plurality of partition walls disposed on the substrate, a plurality of semiconductor light emitting elements disposed on the substrate and disposed between the plurality of partition walls, and a passivation layer covering at least parts of the plurality of semiconductor light emitting elements and at least parts of the plurality of partition walls, wherein the passivation layer extends from side surfaces of the plurality of partition walls in a direction toward the plurality of semiconductor light emitting elements, so as to cover at least parts of the side surfaces of the plurality of partition walls and at least the parts of the plurality of semiconductor light emitting elements. | 2022-05-19 |
20220157760 | Integrated Circuit Package and Method - In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature. | 2022-05-19 |
20220157761 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a first bonding layer on a first wafer and an etching mask on the first bonding layer; etching an edge portion of the first bonding layer by using the etching mask, such that a portion of the first wafer is exposed; removing the etching mask; and bonding a second wafer to the first bonding layer. | 2022-05-19 |
20220157762 | CHIP STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via. | 2022-05-19 |
20220157763 | WARPAGE CONTROL STRUCTURE FOR METAL BASE PLATE, SEMICONDUCTOR MODULE, AND INVERTER DEVICE - The object is to provide a technology of controlling warpage of a metal base plate occurring in temperature change from high temperature to room temperature by causing warpage in the metal base plate in temperature change from room temperature to high temperature. A dissimilar metal layer is formed on a surface of a metal base plate. An insulation substrate is joined to a surface of the dissimilar metal layer with a joining material being provided between the insulation substrate and the surface of the dissimilar metal layer, and includes metal plates disposed on both surfaces. α1>α3>α2 is satisfied, where α1 represents a linear expansion coefficient of the metal base plate, α2 represents a linear expansion coefficient of the dissimilar metal layer, and α3 represents a linear expansion coefficient of the metal plates. | 2022-05-19 |
20220157764 | DEVICE PACKAGE HAVING A LATERAL POWER TRANSISTOR WITH SEGMENTED CHIP PAD - A transistor package having four terminals includes a semiconductor transistor chip and a semiconductor diode chip. The semiconductor transistor chip includes a control electrode and a first load electrode on a first surface and a second load electrode on a second surface opposite the first surface. The semiconductor diode chip includes a first diode electrode on a first surface and a second diode electrode on a second surface opposite the first surface. The transistor package includes a first terminal electrically connected to the control electrode, a second terminal electrically connected to the first diode electrode, a third terminal electrically connected to the first load electrode and a fourth terminal electrically connected to the second load electrode. At least the first terminal, the second terminal and the third terminal protrude from one side of transistor package. The first terminal is arranged between the second terminal and the third terminal. | 2022-05-19 |
20220157765 | BONDING MATERIAL AND BONDED STRUCTURE - A bonding material includes: a copper foil; and a sinterable bonding film formed on one surface of the copper foil. The bonding film contains a copper powder and a solid reducing agent. The bonding material is used for bonding to a bonding target having, on its surface, at least one metal selected from the group consisting of gold, silver, copper, nickel, and aluminum. The bonding material is also used as a material for wire bonding. A bonded structure is also provided in which a bonding target having a metal layer formed on its surface and a copper foil are electrically connected to each other via a bonding layer formed of a sintered structure of a copper powder, wherein the metal layer contains at least one metal selected from the group consisting of gold, silver, copper, nickel, and aluminum. | 2022-05-19 |
20220157766 | BONDING WIRE - There is provided a metal-coated Al bonding wire which can provide a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the metal-coated Al bonding wire is operated. The bonding wire includes a core wire of Al or Al alloy, and a coating layer of Ag, Au or an alloy containing them formed on the outer periphery of the core wire, and the bonding wire is characterized in that when measuring crystal orientations on a cross-section of the core wire in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <111> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30 to 90% among crystal orientations in the wire longitudinal direction. Preferably, the surface roughness of the wire is 2 μm or less in terms of Rz. | 2022-05-19 |
20220157767 | SEMICONDUCTOR DEVICE, POWER CONVERTER, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first circuit, a second circuit, a wiring member, and a bonding material. The wiring member is connected to one of the first circuit and the second circuit. The bonding material is connected to the other of the first circuit and the second circuit. The wiring member includes a first end, a second end, and a top. The first end and the second end are connected to one of the first circuit and the second circuit. The top is located between the first end and the second end. The top is connected to the other of the first circuit and the second circuit with the bonding material in between. | 2022-05-19 |
20220157768 | Laser reflow apparatus and method for electronic components with micron-class thickness - Provided is a laser reflow apparatus for reflowing electronic components on a substrate disposed on a stage, the apparatus including: a laser emission unit comprised of a plurality of laser modules for emitting a laser beam having a flat top output profile in at least one section of the substrate on which the electronic components are disposed; a camera unit comprising at least one camera module for capturing a reflowing process of the electronic components performed by the laser beam; and a laser output control unit configured to generate a control signal for independently controlling the respective laser modules of the laser emission unit based on a signal output from the camera unit and apply the control signal to the laser emission unit. | 2022-05-19 |
20220157769 | DEVICE AND METHOD FOR REEL-TO-REEL LASER REFLOW - The present invention relates to a reel-to-reel layer reflow method, which emits a uniformized laser beam, which can easily adjust the emission area, and which is for the purpose of improving productivity. An embodiment of the present invention provides a reel-to-reel layer reflow method comprising the steps of: a) transferring a substrate, which has been wound in a roll type, to one side while unwinding the same; b) forming a solder portion on the substrate; c) seating an emission target element on the solder portion and seating a non-emission target element on the substrate; d) surface-emitting a laser beam to the solder portion, on which the emission target element is seated, such that the emission target element is attached to the substrate; e) inspecting the substrate structure manufactured through said step d); and f) winding the substrate structure in a roll type. | 2022-05-19 |
20220157770 | CHEMICAL BONDING METHOD AND JOINED STRUCTURE - The present invention achieves chemical bonding by means of a joined film made of oxides formed on a joined surface. In a vacuum container, amorphous oxide thin films are respectively formed on smooth surfaces of two substrates, and the two substrates overlap such that the amorphous oxide thin films formed on the two substrates come into contact with each other, thereby causing chemical bonding involving an atomic diffusion at a joined interface between the amorphous oxide thin films to join the two substrates. | 2022-05-19 |
20220157771 | SYSTEMS AND METHODS FOR OPTIMIZING LOOPING PARAMETERS AND LOOPING TRAJECTORIES IN THE FORMATION OF WIRE LOOPS - A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2). | 2022-05-19 |
20220157772 | WAFER LEVEL PACKAGE - Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip. | 2022-05-19 |
20220157773 | PRESSURE SINTERING DEVICE AND METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT - A method for manufacturing an electronic component by a pressure-assisted low-temperature sintering process, by using a pressure sintering device having an upper die and a lower die is disclosed. The upper the die and/or the lower die is provided with a first pressure pad, wherein the method includes the following steps: placing a first sinterable component on a first sintering layer provided on a top layer of a first substrate; joining the sinterable component and the top layer of the first substrate to form a first electronic component by pressing the upper die and the lower die towards each other, wherein the sintering device is simultaneously heated. | 2022-05-19 |
20220157774 | SEMICONDUCTOR PACKAGES INCLUDING ELECTRICAL REDISTRIBUTION LAYERS OF DIFFERENT THICKNESSES AND METHODS FOR MANUFACTURING THEREOF - A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer. | 2022-05-19 |
20220157775 | PACKAGE PROCESS AND PACKAGE STRUCTURE - A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer. | 2022-05-19 |
20220157776 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate, a logic chip on an upper surface of the package substrate and electrically connected to the package substrate, a heat sink contacting an upper surface of the logic chip to dissipate a heat generating from the logic chip, and a memory chip disposed on an upper surface of the heat sink and electrically connected to the package substrate. | 2022-05-19 |
20220157777 | SEMICONDUCTOR DEVICE PACKAGE HAVING DUMMY DIES AND METHOD OF FORMING THE SAME - A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate. | 2022-05-19 |
20220157778 | SEMICONDUCTOR CIRCUIT DEVICE - A layout of electrode pads on a front surface of a first semiconductor chip is different from a layout of them on a second semiconductor chip. An overall layout of the semiconductor chips mounted on the insulated substrate and the layouts of the electrode pads on the front surfaces of the semiconductor chips including the first and second semiconductor chips are determined so that a value of a resistance component and/or a value of a reactance component between each two electrode pads that are the same type respectively on different semiconductor chips and are connected in parallel become the same. As a result, current waveform oscillation between semiconductor devices fabricated on the semiconductor chips, respectively, may be suppressed. | 2022-05-19 |
20220157779 | SEMICONDUCTOR PACKAGE UTILIZING A HYBRID BONDING PROCESS AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a peripheral region having a groove and a bonding region that is disposed higher than the groove. The second semiconductor chip is disposed in the bonding region of the first semiconductor chip. The second semiconductor chip is directly electrically connected to the first semiconductor chip. The second semiconductor chip includes an overhang protruded from the bonding region. The overhang is spaced apart from a bottom surface of the groove. Thus, a bonding failure, which may be caused by particles generated during a cutting the wafer and adhered to the edge portion of the second semiconductor chip, between the first semiconductor chip and the second semiconductor chip might be avoided. | 2022-05-19 |
20220157780 | SEMICONDUCTOR PACKAGE - A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad. | 2022-05-19 |
20220157781 | ELECTRONIC DEVICE - An electronic device includes a circuit board, a package on package structure, a heat-conducting cover, and a heat-conducting fluid. The circuit board has a first surface and a second surface opposite to each other. The package on package structure is disposed on the first surface. The package on package structure has at least one heat generating element. The heat-conducting cover is disposed on the second surface and is in thermal contact with the circuit board. The heat-conducting cover and the second surface form an enclosed space. The heat-conducting fluid is filled in the enclosed space. | 2022-05-19 |
20220157782 | Fully Interconnected Heterogeneous Multi-layer Reconstructed Silicon Device - Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function. | 2022-05-19 |
20220157783 | SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor die stacks, and associated methods and systems are disclosed. The semiconductor die stack may include a first die with a memory array and a second die with CMOS circuitry configured to access the memory array. The first die may not have circuitry for accessing the memory array. Further, the first and second dies may be bonded to function as a single memory device, and front surfaces of the first and second dies are conjoined to form electrical connections therebetween. The second die may include a portion uncovered by the first die, where bond pads of the semiconductor die stack are located. The first die may provide a space for bond wires to connect to the bond pads without interfering with another die attached above the semiconductor die stack. Multiple semiconductor die stacks may be stacked on top of and in line with each other. | 2022-05-19 |
20220157784 | MEMORY DEVICE - A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug. | 2022-05-19 |
20220157785 | 3D INTEGRATED CIRCUIT (3DIC) STRUCTURE - An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector. | 2022-05-19 |
20220157786 | Packaged Semiconductor Devices Including Backside Power Rails and Methods of Forming the Same - Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds. | 2022-05-19 |
20220157787 | Backside Integrated Voltage Regulator For Integrated Circuits - The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die. | 2022-05-19 |
20220157788 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first submodule including a first power semiconductor element, a second submodule including a second power semiconductor element, a positive electrode side conductor portion and a negative electrode side conductor portion, an intermediate substrate that forms a negative electrode side facing portion facing the negative electrode side conductor portion with the first submodule sandwiched between them and a positive electrode side facing portion facing the positive electrode side conductor portion with the second submodule sandwiched between them, and a plurality of signal terminals that transmit a signal for controlling the first power semiconductor element or the second power semiconductor element. The second submodule is disposed such that directions of an electrode surface of the second power semiconductor element and an electrode surface of the first power semiconductor element are inverted, a signal relay conductor portion is disposed in a space sandwiched between a part of the second submodule and the intermediate substrate in a height direction of the second submodule, and the intermediate substrate has a wire connected to the signal relay conductor portion and electrically connected to the signal terminal. In this manner, productivity of the power semiconductor device is improved while an increase in main circuit inductance is suppressed. | 2022-05-19 |
20220157789 | MICRO LED DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A micro LED display device includes a substrate, micro LED units and a transparent insulation layer. The substrate includes conductive pads and conductive connecting portions. The conductive pads are disposed on the substrate. Each of the micro LED units includes a semiconductor epitaxial structure and electrodes. The electrodes are disposed on the semiconductor epitaxial structure, and each of the electrodes is connected to one of the conductive connecting portions adjacent to each other. The transparent insulation layer is disposed on the substrate and covers the conductive pads, the conductive connecting portions and the micro LED units, and the transparent insulation layer is filled between the electrodes of each of the micro LED units. The transparent insulation layer relative to a surface on each of the semiconductor epitaxial structures is of a first thickness and a second thickness, and the first thickness is different from the second thickness. | 2022-05-19 |
20220157790 | Emissive Element Harvest - A method is provided for the selective harvest of microLED devices from a carrier substrate. Defect regions are predetermined that include a plurality of adjacent defective microLED devices on a carrier substrate. A solvent-resistant binding material is formed overlying the predetermined defect regions and exposed adhesive is dissolved with an adhesive dissolving solvent. Non-defective microLED devices located outside the predetermined defect regions are separated from the carrier substrate while adhesive attachment is maintained between the microLED devices inside the predetermined defect regions and the carrier substrate. Methods are also provided for the dispersal of microLED devices on an emissive display panel by initially optically measuring a suspension of microLEDs to determine suspension homogeneity and calculate the number of microLEDs per unit volume. If the number of harvested microLED devices in the suspension is known, a calculation can be made of the number of microLED devices per unit of suspension volume. | 2022-05-19 |
20220157791 | System for the Characterization of Emissive Elements - A method is provided for the selective harvest of microLED devices from a carrier substrate. Defect regions are predetermined that include a plurality of adjacent defective microLED devices on a carrier substrate. A solvent-resistant binding material is formed overlying the predetermined defect regions and exposed adhesive is dissolved with an adhesive dissolving solvent. Non-defective microLED devices located outside the predetermined defect regions are separated from the carrier substrate while adhesive attachment is maintained between the microLED devices inside the predetermined defect regions and the carrier substrate. Methods are also provided for the dispersal of microLED devices on an emissive display panel by initially optically measuring a suspension of microLEDs to determine suspension homogeneity and calculate the number of microLEDs per unit volume. If the number of harvested microLED devices in the suspension is known, a calculation can be made of the number of microLED devices per unit of suspension volume. | 2022-05-19 |
20220157792 | METHOD FOR IMPROVING THE COLOUR DIFFERENCE OF LED DISPLAY SCREEN - The present application provides a method for improving colour difference of an LED display screen, comprising: drilling and polishing circuit surfaces of a plurality of LED substrates; performing screen printing on the circuit surfaces of the plurality of LED substrates, and performing oil skimming on a mesh screen during the screen printing every other preset printing cycle in such a way that an ink on the mesh screen has a viscosity within a predetermined viscosity range; performing an exposure setting process on the plurality of LED substrates that have been screen printed to obtain a plurality of LED printed circuit boards; and finally assembling the plurality of LED printed circuit boards to form an LED display screen. | 2022-05-19 |
20220157793 | LIGHT-EMITTING DEVICE AND DISPLAY SCREEN INCLUDING THE SAME - A light-emitting device includes a number (N) of light-emitting units, a number (a) of first metal pads and a number (b) of second metal pads. Each of the light-emitting units includes a number (n) of light-emitting chips each having two distinct terminals, where N and n are integers and N>1, n>≥3. The numbers (a) and (b) are integers and a>1, b>1, and the terminals of each of the light-emitting chips are electrically connected to a unique combination of one of the number (a) of first metal pads and a number (b) of second metal pads, respectively. The numbers (N), (n), (a) and (b) satisfy the equation: a*b=n*N. | 2022-05-19 |
20220157794 | PACKAGE STRUCTURE - A package structure includes a first package including a first substrate and a first molded portion disposed on the first substrate; and a rigid-flexible substrate disposed on at least a portion of the first package and having a rigid region and a flexible region. The first molded portion is disposed between the first substrate and the rigid-flexible substrate. | 2022-05-19 |
20220157795 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate. | 2022-05-19 |
20220157796 | COMPOSITE INTEGRATED FILM, COMPOSITE INTEGRATED FILM SUPPLY WAFER, AND SEMICONDUCTOR COMPOSITE DEVICE - A composite integrated film includes a base member thin film having a base member first surface and a base member second surface facing each other, one or more penetration parts penetrating the base member first surface and the base member second surface of the base member thin film, one or more electrodes each including an electrical path part formed between the base member first surface and the base member second surface via the penetration part and an electrode surface in a planar shape formed on the base member second surface's side, and one or more elements provided on the base member first surface of the base member thin film and electrically connected to the electrodes, wherein the electrode surface and the base member second surface form a same flat surface. | 2022-05-19 |
20220157797 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus includes a support substrate, a plurality of light emitting structures regularly arranged on the support substrate, and a wavelength conversion part disposed on the plurality of light emitting structures. The wavelength conversion part includes light transmitting portions and blocking portions, the light transmitting portions being disposed on the light emitting structures, respectively, and each of the light transmitting portions including a phosphor for converting a wavelength of light emitted from the corresponding light emitting structure. The support substrate includes a plurality of conductive patterns electrically connected to the light emitting structures, and the light emitting structures are coupled to the plurality of conductive patterns. | 2022-05-19 |
20220157798 | THERMALLY ISOLATED SILICON-BASED DISPLAY - A display system includes (a) a display element having an organic light emitting diode-containing display active area disposed over a silicon backplane, (b) a display driver integrated circuit (DDIC) attached to the display element and electrically connected with the display active area, and (c) a thermal barrier disposed within the silicon backplane, where the thermal barrier is configured to inhibit heat flow through the silicon backplane and into the display active area. | 2022-05-19 |
20220157799 | OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON-PACKAGE STRUCTURES - An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads. | 2022-05-19 |
20220157800 | METHOD OF OPERATING MICROELECTRONIC PACKAGE - A method of operating a microelectronic package includes a processing device stacking vertically with at least one memory device. The method includes a step of: reading data stored in a plurality of memory cells of a plurality of memory units of the memory device, with the processing device, with a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa. | 2022-05-19 |
20220157801 | POWER MODULE PACKAGE FOR DIRECT COOLING MULTIPLE POWER MODULES - According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing. | 2022-05-19 |
20220157802 | SEMICONDUCTOR DEVICE HAVING DOLMEN STRUCTURE AND METHOD FOR MANUFACTURING SAME - A semiconductor device having a dolmen structure, includes: a substrate; a first chip disposed on the substrate; a plurality of support pieces disposed around the first chip, on the substrate; and a bonding adhesive piece-attached chip supported by the plurality of support pieces and disposed to cover the first chip, in which the bonding adhesive piece-attached chip includes a second chip, and a bonding adhesive piece provided on one surface of the second chip, and a shear strength of the support pieces and the bonding adhesive piece-attached chip at 250° C. is 3.2 MPa or more. | 2022-05-19 |
20220157803 | MULTI-CHIP PACKAGING - An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die. | 2022-05-19 |
20220157804 | INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF - An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region. | 2022-05-19 |
20220157805 | SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor chip includes a first electrode connected to a gate of a power device, a second electrode connected to an emitter or a source of the power device, a third electrode, and a gate protection element. The gate protection element includes a first node and a second node, and a plurality of stages of p-n junctions formed between the first node and the second node. When one of the first electrode and the second electrode is a target electrode and the other is a non-target electrode, and the first node is connected to the third electrode and the second node is connected to the target electrode. Then, the first electrode, the second electrode, the third electrode and the gate protection element are formed in the same semiconductor chip. | 2022-05-19 |
20220157806 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode. The one or more external resistance terminals, the first external terminal, and the external control terminal are external connection terminals provided on a surface of the semiconductor device. | 2022-05-19 |
20220157807 | MOSFET DEVICE OF SILICON CARBIDE HAVING AN INTEGRATED DIODE AND MANUFACTURING PROCESS THEREOF - An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode. | 2022-05-19 |
20220157808 | SEMICONDUCTOR DEVICE - A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer. | 2022-05-19 |
20220157809 | SEMICONDUCTOR DEVICE - According to an aspect of the present disclosure, a semiconductor device includes a FWD region that has, on an upper surface side of a substrate, a p-type anode region, a first p-type contact region having a higher p-type impurity concentration than the p-type anode region, and a first trench, and an IGBT region that surrounds the FWD region in plan view via a boundary region, and has an n-type emitter region, a second p-type contact region, and a second trench on the upper surface side of the substrate, wherein the first trench is formed annularly along an outer edge of the FWD region in plan view, the second trench is formed annularly along an outer edge of the boundary region in plan view, and only a p-type region is provided on an upper surface side of the boundary region. | 2022-05-19 |
20220157810 | SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE - Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal | 2022-05-19 |
20220157811 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region, the first active pattern including first source/drain patterns and a first channel pattern between the first source/drain patterns; a second active pattern on the second region, the second active pattern including second source/drain patterns and a second channel pattern between the second source/drain patterns; and a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern, wherein a length of the first channel pattern is greater than a length of the second channel pattern, each of the first channel pattern and the second channel pattern includes a plurality of semiconductor patterns stacked on the substrate, and at least two semiconductor patterns of the first channel pattern are bent away from or toward a bottom surface of the substrate. | 2022-05-19 |
20220157812 | Gate Dielectric Having a Non-Uniform Thickness Profile - A first dielectric layer is formed over upper and side surfaces of a semiconductor fin structure. A mask layer is formed over a first portion of the first dielectric layer disposed over the upper surface of the fin structure. The mask layer and the first dielectric layer have different material compositions. Second portions of the first dielectric layer disposed on side surfaces of the fin structure are etched. The mask layer protects the first portion of the first dielectric layer from being etched. A second dielectric layer is formed over the mask layer and the side surfaces of the fin structure. An oxidation process is performed to convert the mask layer into a dielectric material having substantially a same material composition as the first or second dielectric layer. The dielectric material and remaining portions of the first or second dielectric layer collectively serve as a gate dielectric of a transistor. | 2022-05-19 |
20220157813 | HYBRID MULTI-STACK SEMICONDUCTOR DEVICE INCLUDING SELF-ALIGNED CHANNEL STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A hybrid multi-stack semiconductor device and a method of manufacturing the same are provided. The hybrid multi-stack semiconductor device includes a nanosheet stack and a fin field-effect transistor (finFET) stack formed above the nanosheet stack, wherein the nanosheet stack includes a plurality of nanosheet layers formed above a substrate and enclosed by a 1 | 2022-05-19 |
20220157814 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a substrate having a P-type device region and an N-type device region, wherein the P-type device region includes germanium dopants. A first gate oxide layer is formed on the P-type device region and a second gate oxide layer is formed on the N-type device region. The first gate oxide layer and the second gate oxide layer are formed through a same oxidation process. The first gate oxide layer includes nitrogen dopants and the second gate oxide layer does not include the nitrogen dopants. | 2022-05-19 |
20220157815 | SEMICONDUCTOR DEVICE INCLUDING SELF-ALIGNED GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device having a self-aligned gate structure includes: providing at least one channel structure above at least one substrate; depositing at least one gate masking layer on the at least one channel structure so that the at least one gate masking layer is formed on top and side surfaces of the at least one channel structure and spread outward above the at least one substrate to form outer-extended portions of the at least one gate masking layer, before a gate-cut process is performed, wherein the at least one gate masking layer is self-aligned with respect to the at least one channel structure by the depositing; and removing the outer-extended portions of the at least one gate masking layer so that the at least one gate masking layer at both sides of the at least one channel structure has a same width. | 2022-05-19 |
20220157816 | FIN STACK INCLUDING TENSILE-STRAINED AND COMPRESSIVELY STRAINED FIN PORTIONS - A fin stack including compressively strained and tensile-strained semiconductor fin regions allows CMOS fabrication to form vertically stacked p-type FinFETs and n-type FinFETs. Aspect ratio trapping within a semiconductor base region within the fin stack provides a relaxed semiconductor base region on which uniaxially strained regions are grown. A dielectric layer may be formed to electrically isolate the compressively strained semiconductor fin region from the tensile-strained semiconductor fin region. | 2022-05-19 |
20220157817 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device with less variations in transistor characteristics is provided. A first insulator, first and second oxide films, a first conductive film, a first insulating film, and a second conductive film are deposited and processed to form a first and second oxides, a first conductive layer, a first insulating layer, and a second conductive layer. In the process, a layer is formed to cover the first and second oxides, the first conductive layer, the first insulating layer, and the second conductive layer. The second conductive layer and the layer are removed. A second insulating layer in contact with side surfaces of the first and second oxides, the first conductive layer, and the first insulating layer is formed, and a second insulator is formed thereover. An opening reaching the second oxide is formed in the first conductive layer, the first insulating layer, the second insulating layer, and the second insulator. | 2022-05-19 |
20220157818 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region. | 2022-05-19 |
20220157819 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a substrate and a stack including word lines and interlayer insulating patterns alternatingly stacked on the substrate. The word lines extend in a first direction. Semiconductor patterns cross the word lines and have longitudinal axes parallel to a second direction. The semiconductor patterns are spaced apart from each other in the first direction and a third direction. Bit lines extend in the third direction and are spaced apart from each other in the first direction. Each of the bit lines contacts first side surfaces of the semiconductor patterns spaced apart from each other in the third direction. Data storage elements, which are respectively provided between vertically adjacent interlayer insulating patterns and contact second side surfaces opposite to the first side surfaces, and substrate impurity layers provided in portions of the substrate at both sides of the stack, are included. | 2022-05-19 |
20220157820 | THIN FILM TRANSISTORS WITH SPACER CONTROLLED GATE LENGTH - Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed. | 2022-05-19 |
20220157821 | MEMORY DEVICE WITH DIFFERENT TYPES OF CAPACITORS AND METHOD FOR FORMING THE SAME - A memory device includes a semiconductor substrate having a first active region and a second active region adjacent to the first active region. The memory device also includes a first word line extending across the first active region and the second active region. The memory device further includes a first source/drain region in the first active region and a second source/drain region in the second active region disposed at opposite sides of the first word line. In addition, the memory device includes a first capacitor disposed over and electrically connected to the first source/drain region in the first active region, and a second capacitor disposed over and electrically connected to the second source/drain region in the second active region. The first capacitor and the second capacitor have different sizes. | 2022-05-19 |
20220157822 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer. | 2022-05-19 |
20220157823 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a capacitor including first and second electrodes and a dielectric layer. The dielectric layer may include a zirconium aluminum oxide layer including a first zirconium region adjacent to the first electrode, a first aluminum region, a second aluminum region adjacent to the second electrode, and a second zirconium region between the first and second aluminum regions. The first and second zirconium regions may include zirconium and oxygen and may be devoid of aluminum. The first and second aluminum regions may include aluminum and oxygen and may be devoid of zirconium. The first aluminum region and the first zirconium region may be spaced apart by a first distance, and the first aluminum region and the second zirconium region may be spaced apart by a second distance shorter than the first distance. | 2022-05-19 |
20220157824 | SEMICONDUCTOR DEVICE HAVING REDUCED CONTACT RESISTANCE BETWEEN ACCESS TRANSISTORS AND CONDUCTIVE FEATURES AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a storage capacitor, an access transistor, and at least one conductive feature for electrically coupling the storage capacitor to the access transistor. The substrate includes at least one isolation feature defining a plurality of active regions, wherein a plurality of impurity regions of the access transistor are in the active region. The storage capacitor is disposed over the substrate, and the conductive feature extends from the storage capacitor and into a portion of the substrate where one of the impurity regions is disposed. As a result, a contact area between the access transistor and the conductive feature is increased, and an operation speed of the compact semiconductor device is increased. | 2022-05-19 |
20220157825 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING REDUCED CONTACT RESISTANCE BETWEEN ACCESS TRANSISTORS AND CONDUCTIVE FEATURES - The present disclosure provides a method for manufacturing a semiconductor device. The method includes providing a substrate comprising one or more isolation features defining active regions; forming at least one access transistor comprising a plurality of impurity regions, wherein the impurity regions are disposed in the substrate; depositing a dielectric layer to cover the access transistor; forming a first contact hole through the dielectric layer to expose the associated impurity region; forming a sacrificial liner in the first contact hole; removing a portion of the substrate exposed through the first contact hole and the sacrificial liner to form a second contact hole connected to the first contact hole; and forming a conductive feature in the first and second contact holes. | 2022-05-19 |
20220157826 | SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE - Provided are a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method includes: a substrate is provided, which includes a first area and a second area set adjacent to each other; multiple trenches, which are arranged at intervals along a first direction, are formed in both the first area and the second area of the substrate; a word line (WL) is formed in each of the multiple trenches, a feature size of the WL in the first area is different from that of the WL in the second area; and a contact structure is formed on the WL with the greater feature size. | 2022-05-19 |
20220157827 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND STORAGE DEVICE - A manufacturing method for a semiconductor structure includes: a semiconductor substrate is provided, the semiconductor substrate includes multiple first regions and second regions which are alternately disposed; multiple bitline structures are formed on the semiconductor substrate, any one of the bitline structures penetrates through the first regions and the second regions; the bitline structures in the first regions are etched, to enable each sidewall on two sides of each of the bitline structure to be in a step shape; and multiple electrode structures are formed, any one of the electrode structures includes a conductive plug and a contact pad in mutually electric connection, and each conductive plug is disposed at a respective first region, disposed between two neighboring bitline structures and connected to the semiconductor substrate. | 2022-05-19 |
20220157828 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a semiconductor base, a bit line and a word line. The semiconductor base includes a substrate and an isolation structure arranged above the substrate and configured to isolate a plurality of active regions from each other. The bit line is arranged in the substrate and connected to the plurality of active regions. The word line intersects with the plurality of active regions and surrounds the plurality of active regions. | 2022-05-19 |
20220157829 | SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF - Embodiments of the present application relate to a semiconductor structure and a formation method thereof. The semiconductor structure formation method includes the following steps: providing a base, the base including a memory region, the memory region including a substrate, a conductive layer, and a first mask layer located on the conductive layer; patterning the first mask layer to form a plurality of first dot patterns arranged in a first array; backfilling the first mask layer to form a second mask layer covering the first mask layer; patterning the second mask layer to form a plurality of second dot patterns arranged in a second array; and etching the conductive layer by using the first dot pattern and the second dot pattern together as a mask pattern to form a plurality of independent conductive dot patterns. | 2022-05-19 |
20220157830 | A Semiconductor Device and A Manufacturing Method - A semiconductor device manufacturing method includes: providing a substrate having a memory cell array area; forming a word line trench; forming a word line conductive layer in the word line trench; forming a photoresist on the substrate surface, and patterning it to protect the word line conductive layer in the contact areas but exposes the word line conductive layer outside the word line contact area, and etching the conductive layer. The resulting thickness of the word line conductive structure in the word line contact area is greater than outside the word line contact area. Thereby the opening of the word line contact hole is reduced. The depth of the window position reduces the process time in forming the contact hole, which reduces the excessive erosion of the sidewalls of contact hole having a shallower opening depth, so to avoid the device short circuit. | 2022-05-19 |
20220157831 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided is a three-dimensional semiconductor memory device including a first substrate that includes a cell array region and a connection region; first and second electrode layers that are sequentially stacked and spaced apart from each other on the first substrate, and an end portion of the first electrode layer and an end portion of the second electrode layer are offset from each other on the connection region; a first cell contact penetrating the second electrode layer and the first electrode layer such as to be connected to the second electrode layer on the connection region; and a first contact dielectric pattern between the first cell contact and the first electrode layer. The first cell contact includes columnar part that vertically extends from a top surface of the first substrate, and a connection part that laterally protrudes from the columnar part and contacts the second electrode layer. | 2022-05-19 |
20220157832 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, an insulating film, a ferroelectric film, a first seed layer and a control gate electrode. The semiconductor substrate includes a source region and a drain region which are formed on a main surface of the semiconductor substrate. The insulating film is formed on the main surface of the semiconductor substrate such that the insulating film is positioned between the source region and the drain region in a plan view. The ferroelectric film is formed on the insulating film and includes hafnium and oxygen. The first seed layer is formed on the ferroelectric film. The control gate electrode is formed on the ferroelectric film. A material of the first seed layer includes at least one material of the ferroelectric film and at least one material of the first conductive film. | 2022-05-19 |
20220157833 | FERROELECTRIC MEMORY DEVICE AND OPERATION METHOD THEREOF - A ferroelectric memory device comprising a plurality of ferroelectric memory elements. Each of the plurality of ferroelectric memory elements includes a channel layer containing a metal oxide, a ferroelectric layer in contact with the channel layer in which the ferroelectric layer contains hafnium oxide, a first gate electrode facing the channel layer via the ferroelectric layer, an insulating layer facing the ferroelectric layer via the channel layer; and a second gate electrode facing the channel layer via the insulating layer. | 2022-05-19 |
20220157834 | LAYOUT STRUCTURE INCLUDING ANTI-FUSE CELL - A semiconductor device includes first and second active areas, a first gate, a first conductive segment, a first via and a first continuous gate. The first and second active areas extend in a first direction. The first gate crosses over the first active area and the second active area. The first gate includes a first gate portion and a second gate portion electrically isolated from each other. The first conductive segment crosses over the first active area and the second active area. The first via is arranged above the first conductive segment. The first active area and the second active area are coupled through the first conductive segment to the first via. The first continuous gate is disposed between the first conductive segment and the first gate, and crossing over the first active area and the second active area. | 2022-05-19 |
20220157835 | LAYOUT STRUCTURE INCLUDING ANTI-FUSE CELL - A structure includes first and second active areas, first and second gates and a data line. The first gate is continuous and crosses over the first active area and the second active area. The first gate corresponds to gate terminals of first and second transistors, and first source/drain regions of the first and the second active areas correspond to first source/drain terminals of the first and second transistors. The second gate includes first and second gate portions electrically isolated from each other. The first and second gate portions correspond to gate terminals of third and fourth transistors, respectively. The first gate portion crosses over the first active area, and the second gate portion crosses over the second active area. The first data line is coupled to the first source/drain regions of the first active area and the second active area. | 2022-05-19 |
20220157836 | Integrated Components Which Have Both Horizontally-Oriented Transistors and Vertically-Oriented Transistors - Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region. | 2022-05-19 |
20220157837 | Vertical Transistor, Integrated Circuitry, Method Of Forming A Vertical Transistor, And Method Of Forming Integrated Circuitry - A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed. | 2022-05-19 |
20220157838 | SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME - A semiconductor device and a data storage system including the same, the semiconductor device including: a first structure including a peripheral circuit; and a second structure, including: a pattern structure; an upper insulating layer; a stack structure between the first structure and the pattern structure and including first and second stack portions spaced apart from each other, the first and second stack portions respectively including horizontal conductive layers and interlayer insulating layers alternately stacked; separation structures penetrating through the stack structure; memory vertical structures penetrating through the first stack portion; and a contact structure penetrating through the second stack portion, the pattern structure, and the upper insulating layer, wherein the contact structure includes a lower contact plug penetrating through at least the second stack portion and an upper contact plug contacting the lower contact plug and extending upwardly to penetrate through the pattern structure and the upper insulating layer. | 2022-05-19 |
20220157839 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first circuit structure, a first conductive line connected to the first circuit structure, a second conductive line facing the first conductive line, and a second circuit structure overlapping with the first circuit structure with the first and second conductive lines interposed therebetween, the second circuit structure being connected to the second conductive line. One of the first conductive line and the second conductive line has a region protruding toward the other of the first conductive line and the second conductive line. | 2022-05-19 |
20220157840 | SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND LOGIC DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND LOGIC DEVICE - A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device. | 2022-05-19 |
20220157841 | THREE-DIMENSIONAL MEMORY DEVICE WITH SEPARATED SOURCE-SIDE LINES AND METHOD OF MAKING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer. | 2022-05-19 |
20220157842 | THREE-DIMENSIONAL MEMORY DEVICE WITH SEPARATED SOURCE-SIDE LINES AND METHOD OF MAKING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer. | 2022-05-19 |