20th week of 2016 patent applcation highlights part 67 |
Patent application number | Title | Published |
20160141974 | POWER CONVERSION APPARATUS - According to one embodiment, a controller determines the polarity of the input voltage detected by an input voltage detector. Then, when the polarity of the input voltage is positive, the first switch is subject to pulse driving, and when the polarity of the input voltage is negative, the second switch is subject to pulse driving, where the pulse driving is carried out at an on/off timing determined on the basis of the respective detection outputs of an input voltage detector, an input current detector, an output voltage detector, and an output current detector. | 2016-05-19 |
20160141975 | Capacitor Drop Power Supply - A capacitor drop power supply is provided where excess charge is damped into a low impedance switch, avoiding the dissipation of extra energy seen in current designs. Also, because the excess charge is not dissipated, it then becomes available for when a load is applied thus increasing the efficiency of the power supply. The present disclosure therefore provides various advantages compared with existing capacitor drop power supplies. It provides the simplicity and low cost of a capacitor drop power supply, but with an efficiency that is equivalent or superior to that of a switching mode power supply. | 2016-05-19 |
20160141976 | Electrical Conversion - An electrical conversion apparatus is described which comprises a bridge rectifier | 2016-05-19 |
20160141977 | SEVEN-LEVEL INVERTER APPARATUS - It is composed of a three-phase three-level inverter | 2016-05-19 |
20160141978 | CONTROL APPARATUS FOR PHOTOVOLTAIC INVERTER - There is provided a control apparatus for a photovoltaic inverter. The control apparatus includes a system voltage detector, a DC voltage detector that detects a DC voltage applied to the inverter, an output voltage deficiency detector that detects an output voltage deficiency of the inverter based on the system voltage and the DC voltage, an output-current detector, an output-current distortion detector that detects distortion of the output current based on a harmonic included in the output current, a MPPT controller, and an output-current distortion controller that performs control to set the DC voltage applied to the inverter to a voltage at a power point less than a maximum power point when the output voltage deficiency is detected and the distortion of the output current is detected. | 2016-05-19 |
20160141979 | DRIVING DEVICE - This invention prevents a load from being applied to a piezoelectric element due to a flection deformation of a flexible substrate along with a movement of a driving device and a driving efficiency from lowering. The flexible substrate of the driving device includes a first fixing portion fixed to the piezoelectric element, a second fixing portion fixed to a second holding member, and a bending portion configured to make a flection deformation along with a movement of a vibrating plate. The second fixing portion is provided between the first fixing portion and the bending portion. | 2016-05-19 |
20160141980 | PIEZOELECTRIC ENERGY HARVESTING AND SIGNAL PROCESSING SYSTEM, AND METHOD OF USE - The present invention relates to a system comprising an energy harvester device and a signal processing device coupled to the energy harvester device. The energy harvester device includes an elongate resonator beam comprising a piezoelectric material extending between first and second ends. A base is connected to the elongate resonator beam at the first end with the second end being freely extending from the base as a cantilever. A mass attached to the second end of the elongate resonator beam. The signal processing device includes a processor and a memory coupled to the processor. The processor is configured to execute programmed instructions stored in the memory including obtaining a signal from the energy harvesting device. The obtained signal is tracked over a period of time. An environmental impact on the energy harvester device is determined based on the tracked signal. | 2016-05-19 |
20160141981 | MOTOR CONTROLLER HAVING A POWER-SAVING CONTROL, AND A MOTOR CONTROL SYSTEM INCLUDING THE MOTOR CONTROLLER - A motor controller that is configured to switch power supply phases of the motor, to perform a limit-position abutment control by rotating the motor to a movable limit of a movable range of the rotation object to learn a reference position of the motor, perform a power-saving return control afterwards, in which a power supply to the motor is stopped, thereby returning a rotation position of the motor toward a target rotation position, and stop the rotation of the motor by simultaneously supplying power to a preset phase of the motor, when the rotation position of the motor reaches the target rotation position. In such manner, the power consumption as well as the heat generation of the motor are reduced for returning the rotation position of the motor to a preset rotation position after the abutment control of the motor. | 2016-05-19 |
20160141982 | METHOD AND APPARATUS FOR CONTROLLING AN ELECTRIC MACHINE IN A SIX-STEP MODE - An inverter electrically operatively connects to a multi-phase electric machine, and a method for controlling the inverter includes executing a six-step mode to control the inverter and monitoring an electric voltage angle of the electric machine at a preset sampling frequency. When the electric voltage angle approaches a step transition associated with control of one of a plurality of switches of the inverter in the six-step mode, an intermediate duty command for the one of the switches is determined and a carrier signal is aligned based upon a present state of the one of the switches. The one of the switches is controlled employing the intermediate duty command and the aligned carrier. | 2016-05-19 |
20160141983 | METHOD AND APPARATUS FOR CONTROLLING AN ELECTRIC MACHINE IN A SIX-STEP MODE - A voltage source inverter controller for controlling an inverter electrically connected to an electric machine includes a current command generator, a six-step flux controller and a current regulator. The six-step flux controller generates a flux modifier to regulate flux in a flux-weakening speed/load operating region of the electric machine when operating the electric machine in a six-step mode. The current command generator converts a desired torque to three-phase desired currents that are input to a dq0-dq transformer and combined with the flux modifier to determine a modified-flux direct-quadrature (dq) current request. The current regulator includes a proportional-integral feedback controller, anti-windup elements, a dq voltage limit element and a voltage magnitude limiter. The proportional-integral feedback controller and the anti-windup elements perform closed-loop current control on the modified-flux dq current request to determine commanded dq voltages. | 2016-05-19 |
20160141984 | Method and System for Traction Motor Torque Ripple Compensation - Torque ripple produced by a traction motor of an electric vehicle when the motor produces torque from a motor current is compensated for by modifying operation of the motor according to a difference between an expected position of the motor to produce a desired torque from the current and the actual position of the motor when producing torque from the current. | 2016-05-19 |
20160141985 | AUTOMATIC ACTUATOR CALIBRATION USING BACK EMF - A self-calibrating linear actuator is configured to control a spring return valve with variable stroke. The actuator includes a motor, a spindle coupled to an output of the motor, a motor controller coupled to the motor, a microcontroller coupled to the motor controller, and a back electromotive force (BEMF) circuit, coupled to the motor, configured to provide to the microcontroller a BEMF value for each motor step. The microcontroller is configured to determine a difference of a number of motor steps during operation of the actuator and to store the difference as a calibrated touch point for the actuator. | 2016-05-19 |
20160141986 | FLOATING POWER GENERATOR - A floating power generator having a water wheel and electrical generator. The floating power generator can comprise a variable speed drive. | 2016-05-19 |
20160141987 | Floating Device Generator - A floating power generator having a water wheel and electrical generator. The floating power generator can comprise a variable speed drive. | 2016-05-19 |
20160141988 | System and Method For Generator Main Field Energy Extraction - A system and method for controlling the main field current in an electrical generator is disclosed. The system can include a controller to sense the voltages and currents in the system to identify load faults. The system can also comprise one or more switches and an energy dissipator to absorb, store, or dissipate the main field current in the event of a load fault, such as a short circuit. In the event of a load fault, the controller can change the position of the one or more switches to redirect the main field current from the main field windings of the rotor to the energy dissipator. The energy dissipator can absorb or store the main field current significantly reducing the time required to stop the output current of the generator. | 2016-05-19 |
20160141989 | TWO STAGE FLUX SWITCHING MACHINE FOR AN ELECTRICAL POWER GENERATION SYSTEM - An electrical power generation system includes a flux switching machine (FSM) including an FSM rotor operatively connected to an FSM stator, the FSM rotor operatively connected to a shaft, wherein the FSM includes an electrical input/output (i/o) in electrical communication with the FSM stator, and a permanent magnet machine (PMM) including a PMM rotor operatively connected to a PMM stator, the PMM rotor operatively connected to a the shaft, wherein the PMM is electrically connected to the FSM. | 2016-05-19 |
20160141990 | Method and Device for Operating an Electronically Commutated Servo Motor and Position Control Unit having a Servo Motor - A method for operating an electronically commutated servo motor includes activating the servo motor by a voltage space vector generated in accordance with a commutation pattern on the basis of a predefined torque and a rotor position of a rotor of the servo motor in accordance with an optimization target. The method further includes predefining an activation range that indicates a range of permissible voltage space vectors. The servo motor is activated in such a way that only voltage space vectors within the activation range are used. | 2016-05-19 |
20160141991 | POWER SYSTEM SUB-SYNCHRONOUS OSCILLATION DAMPER - A control circuit for power system sub-synchronous oscillation dampening is described. The control circuit is configured to provide low impedance at sub-synchronous frequencies and high impedance at the fundamental frequency. The control circuit includes an input configured to receive a direct voltage value and a quadrature voltage value. Both the direct voltage value and the quadrature voltage value are based on a three-phase voltage. At least one controller configured to determine a direct current value and a quadrature current value based at least in part on the direct voltage value and the quadrature voltage value is included. The control circuit also includes an output configured to send the direct current value and the quadrature current value as feed forward signals to a control loop for the three-phase voltage. | 2016-05-19 |
20160141992 | Linear Drive with Cross-Controller Vibration Damping - A control device, linear device, non-transitory computer readable medium and method by which optimal vibration damping can also be achieved in a simple manner when transferring a carrier from one segment to the next segment, where a primary part includes a plurality of sequentially consecutive segments that are each connected to a supply voltage via a respective converter, such that each of plurality of sequentially consecutive the segments receive respective currents of a three-phase system. | 2016-05-19 |
20160141993 | EFFICIENT DAMPING OF VIBRATIONS OF AN ELECTRIC MACHINE - A first active part of a poly-phase electric machine is connected to a converter having a control facility. The control facility updates a base commutation angle using the target speed value and determines direct-axis and quadrature-axis component values of currents and a commutation angle supplied to the machine. Target and component quadrature-axis values are provided to a quadrature-axis portion of a current controller that determines a target value of the quadrature-axis voltage component. Target and component current values are supplied to a direct-axis portion of the current controller, which determines a target value of the direct-axis voltage component therefrom. The target value of the direct-axis and quadrature-axis voltage components and the commutation angle are used to determine the target output voltages provided to the converter. A damping commutation angle determined using target values of the quadrature-axis and direct axis voltage components is used to adjust the of the voltage. | 2016-05-19 |
20160141994 | MOTOR DRIVE SYSTEM AND MOTOR CONTROL DEVICE - A motor drive system includes a motor, a motor control device, and a sensor that detects torque or acceleration of the motor. The motor control device includes an estimating unit configured to estimate at least one of speed and position of the motor, and a current control unit configured to control current to be supplied to the motor based upon an estimation result by the estimating unit. The estimating unit includes first and second estimating units, and derives an estimated value based upon estimation results by the first and second estimating units. The first estimating unit estimates based upon a detection signal detected by the sensor and a high-frequency component superimposed on an output current to the motor. The second estimating unit estimates from an estimation result of induced voltage of the motor. | 2016-05-19 |
20160141995 | Flyback Control Mode-Based Controller and Motor-Controlling Method Thereof - A flyback control mode-based controller includes a power supply circuit, a position-checking circuit, a current-checking circuit, a control circuit, and a power output circuit. The power output circuit includes a controlled energy conversion unit. The energy conversion unit includes a control switch and an energy conversion circuit. The energy conversion circuit uses the capacitor C circuit, the inductor L circuit, or the LC circuit to connect parallelly or serially with an inductor in a motor winding L so as to form an oscillation circuit, such that periodic oscillations with attenuation are enabled by relying on the energy stored in the motor winding L. By applying the controller to motors having forward control mode or motors having flyback control mode, the current to be released by the motor during discharging can be repeated used, thereby achieving maximum energy conservation. | 2016-05-19 |
20160141996 | ELECTRIC MOTOR SYSTEM FOR VEHICLES AND METHOD OF ADJUSTING COIL WINDING NUMBER OF ELECTRIC MOTOR FOR VEHICLES - Provided is an electric motor system for vehicles, which adjusts a coil winding number of a vehicle electric motor. The electric motor system for vehicles includes an inverter configured to include a power switching circuit connected to a vehicle battery in parallel and a coil switching circuit connected to the power switching circuit, wherein the coil switching circuit receives and outputs a driving current having different phases which is generated according to a switching operation of the power switching circuit, an electric motor configured to include a plurality of winding coils that receive the driving current and are wound at multi stages, and a controller configured to control a switching operation of the coil switching circuit to adjust a winding number of each of the plurality of winding coils to a maximum coil winding number by serially connecting all of the plurality of winding coils in a low speed driving mode and to adjust the winding number of each of the plurality of winding coils to a minimum coil winding number by serially connecting some of the plurality of winding coils in a high speed driving mode. | 2016-05-19 |
20160141997 | DEVICE FOR CONTROLLING A POLYPHASE INVERTER - The device according to the invention controls a polyphase inverter ( | 2016-05-19 |
20160141998 | EXTERNAL ANTENNA FOR COMMUNICATING WITH A MOTOR AND METHOD OF USING SAME - An antenna assembly for communicating with a motor comprises an antenna for mounting exterior of a motor housing and a link for coupling the antenna to a motor controller. | 2016-05-19 |
20160141999 | SYSTEM AND METHOD FOR ESTIMATING TEMPERATURE OF DRIVE MOTOR - A system for estimating a temperature of a drive motor may include: a drive motor that generates driving torque; a detector that detects a d-axis voltage, a q-axis voltage, a d-axis current, and a q-axis current of the drive motor; and a controller that determines whether zero-current control of the drive motor is performed from the d-axis current and the q-axis current detected by the detector, calculates a no-load counter-electromotive force of the drive motor from the d-axis voltage and the q-axis voltage detected by the detector, converts the no-load counter-electromotive force into a counter-electromotive force with respect to a reference rotation speed, calculates a temperature variation of the drive motor from the counter-electromotive force with respect to the reference rotation speed and a reference counter-electromotive force, and estimates the temperature of the drive motor. | 2016-05-19 |
20160142000 | MOTOR VEHICLE - In the case where an on-fixation failure occurs in one of transistors of an inverter, a shutdown signal GSDWN or MSDWN is output as ON signal for a duration of adjusting time since switching of a fail signal GFINV or MFINV to ON signal. After elapse of the adjustment time, the shutdown signal GSDWN or MSDWN is switched to OFF signal. The adjustment time is set to be longer than a time duration until completion of shutdown of the inverter but to be shorter than a time duration until start of emergency drive control. This allows for cancellation of shutdown of the inverter even when an abnormal signal is continuously output due to a failure of a sensor or the like. This causes emergency drive to be more reliably performed with three-phase on-control including a transistor having an on-fixation failure after shutdown of the inverter. | 2016-05-19 |
20160142001 | MOTOR CONTROL DEVICE AND MOTOR CONTROL SYSTEM - A motor control device includes: a control processing unit that controls driving of a motor based on a command signal input from a controller so as to command an operation of the motor and a detection signal which is a detection result of the operation of the motor; and an abnormality determining unit that detects an abnormality in the controller, the motor control device, and the motor based on the command signal, the detection signal, and a control signal generated in the motor control device and that determines a level of repeatability of the detected abnormality based on a predetermined criterion. The control processing unit transitions from a normal mode to a specific abnormality alarm mode when the abnormality determining unit determines that an specific abnormality having high repeatability has occurred. | 2016-05-19 |
20160142002 | CONTROLLER OF AN ELECTRIC MOTOR - A controller for an electric motor includes a protective circuit for limiting current or for polarity reversal protection, the protective circuit including a field effect transistor having a gate. The protective circuit further includes a control unit for providing a control voltage for the gate, a smoothing capacitor for charge storage being provided at the gate. | 2016-05-19 |
20160142003 | Motor Control Circuit - A motor control circuit for an electric motor of an electric power assisted steering system comprises a switching circuit comprising a plurality of electrical switches, a current demand signal generator which converts the torque demand signal into a current demands signal; and a fault mode motor current controller that is responsive to an error signal that represents the difference between the current demand signal and the actual current flowing in the motor and is operable in the event of a fault where one phase is open-circuit to drive the remaining two phases as a single combined phase by generating a single voltage demand signal that is representative of the voltage to be applied across the combined phases, the voltage signal being in turn fed into a drive circuit for the switches that generates pulse width modulated switching signals for the switching circuit required to apply the voltage across the combined phases. | 2016-05-19 |
20160142004 | VEHICLE CONTROL DEVICE AND RAILROAD VEHICLE - A vehicle control device according to one embodiment includes an inverter converting a DC power to a three-phase AC power and supplying the three-phase AC power to a motor driving a vehicle. A detector detects a current value between the inverter and the motor. A controller PWM-controls the inverter based on a current value detected by the detector, a speed command signal, and a rotor frequency of the motor. The controller determines occurrence of a malfunction when a PWM modulation rate is equal to or higher than a predetermined value and the rotor frequency is equal to or lower than a predetermined value. | 2016-05-19 |
20160142005 | THERMOPHOTOVOLTAIC SYSTEM HAVING A SELF-ADJUSTING GAP - A thermophotovoltaic system for generating energy can include a photovoltaic cell, a radiator separated from the photovoltaic cell by a vacuum gap having a distance of less than 10 micrometers, and an actuator operably connected with at least one of the photovoltaic cell and the radiator to adjust the gap distance. A method of thermophotovoltaic energy conversion can include heating a radiator to produce infrared radiation, irradiating a photovoltaic cell with the infrared radiation to produce an electric current, maintaining a vacuum gap between the radiator and the photovoltaic cell with a gap distance of less than 10 micrometers, and dynamically adjusting the gap distance during irradiating based on a temperature of at least one of the radiator and the photovoltaic cell. | 2016-05-19 |
20160142006 | Roof Attachment Assembly for Solar Panels and Installation Method - Disclosed herein is a roof attachment assembly for mounting a solar panel on a roof without the use of rails. The assembly includes a flashing member, a pivot bracket member, a clamp member, an array skirt and a splice member. The flashing member anchors the roof attachment assembly to the roof. The pivot bracket member is rotatably connected to the flashing member. The clamp member is connected to the pivot bracket member and is rotatably connected thereto. The clamp member includes grounding elements for electrically grounding the solar panel. The array skirt is removably connected to the clamp member. The splice member includes grounding elements for electrically grounding the solar panel and is removably connected to the array skirt. Also disclosed is a method of using the assembly and an assembly kit. | 2016-05-19 |
20160142007 | PHOTOVOLTAIC INVERTER - The present invention relates to a photovoltaic inverter capable of reducing a leakage current and a switching loss by changing a pulse width modulation (PWM) method and a configuration of an output filter. To this end, the photovoltaic inverter includes a direct-current (DC) link capacitor connected in parallel to a photovoltaic module, a switch unit including first to fourth switches and operating by a half unipolar switching method, and a reactor having one end connected to another end of the first switch and one end of the second switch, and another end connected to a grid, the reactor having a predetermined inductance. | 2016-05-19 |
20160142008 | Photovoltaic Devices With Improved Connector and Electrical Circuit Assembly - Photovoltaic devices | 2016-05-19 |
20160142009 | STATISTICAL DETERMINATION OF SOLAR SYSTEM PERFORMANCE - Power utilities may not have systematic visibility of the actual performance of customers' solar arrays. One solution to getting data on solar system performance may be through using monitoring hardware and/or software that is connected to a solar system. However, utility companies may not have access to such data since the monitoring hardware/software is commonly owned and operated by utility customers themselves and/or private solar contractors. The subject technology provide methods and systems that can be used to determine a “maximum solar production” baseline, e.g., on a daily basis in view of a set of conditions or factors. In some aspects, the maximum solar production baseline is determined by identifying similar days with “maximum solar potential” but that do not correlate with maximum production. In an example, asymmetry or a delta between maximum potential and maximum production can be used to identify underperformance of power production relative to maximum potential. | 2016-05-19 |
20160142010 | ELECTRONIC COMPONENT, ELECTRONIC APPARATUS, AND MOVING OBJECT - An electronic component includes a wiring substrate, a heating element, a first support, a second support, and a container. The heating element, the first support, and the second support are electrically connected to the wiring substrate. Each of the first support and the second support includes a protrusion portion, and the protrusion portion of the second support is shorter than the protrusion portion of the first support. | 2016-05-19 |
20160142011 | SEMICONDUCTOR DEVICE - A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP | 2016-05-19 |
20160142012 | SPIN CURRENT GENERATION WITH NANO-OSCILLATOR - A device including a spin channel to transport a spin current, a nano-oscillator, and a magnetoresistive device that receives the spin current from the nano-oscillator. The nano-oscillator includes a magnetization state that oscillates between a first state and a second state in response to an input voltage or current. The oscillation of the nano-oscillator may induce the spin current within the spin channel. The magnetoresistive device includes a magnetization state that is set based at least in part on the received spin current. | 2016-05-19 |
20160142013 | SUPPLY MODULATION FOR RADIO FREQUENCY POWER AMPLIFICATION - The subject matter described herein relates to supply modulation for power amplification. In one embodiment, the voltage level of the envelope with a tunable threshold voltage. The high level part of the envelope above the threshold voltage is maintained and amplified, for example, by the linear amplification process. On the other hand, the low level part of the envelope is replaced with the constant low voltage level. In amplification, the shaped low level part can be prompted to the predefined low supply voltage which may be directly output to the RFPA. By eliminating complicated amplification process on the lower level part of the envelope, the efficiency and bandwidth of the supply modulation can be improved and the circuitry can be simplified, without introducing any timing mismatch or delays. | 2016-05-19 |
20160142014 | BIAS CIRCUIT FOR USE WITH AMPLIFIER CIRCUIT, CONTROL METHOD THEREOF, AND SIGNAL AMPLIFIER - A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor. | 2016-05-19 |
20160142015 | HIGH FREQUENCY AMPLIFIER - A high frequency amplifier includes a high frequency amplifier transistor integrated in a first die of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor has an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The matching circuit includes at least a first inductive bondwire, a second inductive bondwire and a capacitive element arranged in series with said inductive bondwires. The capacitive element is integrated in a second die of a second semiconductor technology different from the first semiconductor technology. The second semiconductor technology includes an isolating substrate for conductively isolating the capacitive element from a support attached at a first side to the second die. The capacitive element includes a first plate electrically coupled to a first bondpad of the second die and a second plate electrically coupled to a second bondpad of the second die. | 2016-05-19 |
20160142016 | OPERATIONAL AMPLIFIER BASED CIRCUIT WITH COMPENSATION CIRCUIT BLOCK USED FOR STABILITY COMPENSATION - An operational amplifier based circuit has an operational amplifier, a feedback circuit, and a compensation circuit block. The feedback circuit is coupled between an output port and an input port of the operational amplifier. The compensation circuit block has circuits involved in stability compensation of the operational amplifier, wherein there is no stability compensation circuit driven at the output port of the operational amplifier. | 2016-05-19 |
20160142017 | RECONFIGURABLE OPERATIONAL AMPLIFIER - A reconfigurable operational amplifier includes: a first signal input terminal; a second signal input terminal; an output terminal; an operational amplifier having a non-inverting input, an inverting input, and an output; a negative feedback circuit path from the output of the operational amplifier to the inverting input of the operational amplifier; a first input circuit path from the first signal input terminal to the non-inverting input of the operational amplifier; a second input circuit path from the second signal input terminal to the inverting input of the operational amplifier; an output circuit path from the output of the operational amplifier to the output terminal; and logic units, wherein one or more of the logic units are provided in at least one of the negative feedback circuit path, the first input circuit path, the second input circuit path, and the output circuit path. | 2016-05-19 |
20160142018 | POWER MOSFETS WITH IMPROVED EFFICIENCY FOR MULTI-CHANNEL CLASS D AUDIO AMPLIFIERS AND PACKAGING THEREFOR - A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (Vcc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits. | 2016-05-19 |
20160142019 | AMPLIFYING DEVICE AND OFFSET VOLTAGE CORRECTION METHOD - An output voltage delay time caused by the relationship between offset voltage and input voltage is shortened. A single power supply amplifying device includes first and second amplifying units, a state detecting unit, and an offset voltage correcting unit. The first amplifying unit has differential pair transistors and amplifies the difference between input voltages. The second amplifying unit amplifies a first output voltage of the first amplifying unit. The state detecting unit detects a state where a negative offset voltage that causes a second output voltage of the second amplifying unit to be lower than the input voltage occurs, and a potential of the input voltage is lower than the absolute value of the negative offset voltage. The offset voltage correcting unit then corrects the negative offset voltage to a positive offset voltage that causes the second output voltage to be higher than the input voltage. | 2016-05-19 |
20160142020 | POWER AMPLIFIER FOR AMPLIFYING RADIO FREQUENCY SIGNAL - Power amplifiers for amplifying a radio frequency signal are provided. The power amplifier may include an envelope tracking power supply, a carrier amplifier coupled with the envelope tracking power supply and configured to amplify the radio frequency signal, an input matching network configured to split the amplified radio frequency signal from the carrier amplifier such that one part of the amplified radio frequency signal passes along a peak amplifier path and another part of the amplified radio frequency signal passes along an impedance transformer path, a peak amplifier coupled with the envelope tracking power supply and configured to amplify the one part of the amplified radio frequency signal from the input matching network, an impedance transformer configured to perform impedance transformation on the other part of the amplified radio frequency signal from the input matching network, an output matching network configured to combine the output of the peak amplifier and the impedance transformer, wherein the peak amplifier is configured to be switched off in a lower power mode and switched on in a high power mode based at least in part on an input power level of the radio frequency signal. With the claimed solutions, more powerful and efficient power amplifiers that are capable of operating over broader frequency ranges may be achieved. | 2016-05-19 |
20160142021 | AMPLIFIER CIRCUIT AND METHOD - An amplifier arrangement comprises N amplifier stages ( | 2016-05-19 |
20160142022 | Multiband Power Amplification Apparatus - The present application provides a multiband power amplification apparatus. The first input terminal receives a signal in a frequency band f | 2016-05-19 |
20160142023 | MULTI-BROADBAND DOHERTY POWER AMPLIFIER - Radio frequency (RF) amplification devices are disclosed that include Doherty amplification circuits and methods of operating the same. In one embodiment, a Doherty amplification circuit includes a main carrier RF amplifier, a peaking RF amplifier, and a periodic quadrature coupler. To provide Doherty amplification, the peaking RF amplifier is configured to be deactivated while an RF signal is below a threshold level and is configured to be activated while the RF signal is above the threshold level. The periodic quadrature coupler is configured to combine a first RF split signal from the main carrier RF amplifier and a second RF split signal from the peaking RF amplifier into the RF signal, such that the RF signal is output from an output port while the peaking RF amplifier is activated. The periodic quadrature coupler allows the Doherty amplification circuit to provide broadband amplification in various RF communication bands. | 2016-05-19 |
20160142024 | ADVANCED CURRENT LIMIT FUNCTION FOR AUDIO AMPLIFIER - A class-D audio amplifier incorporates an overcurrent protection scheme implementing two overcurrent thresholds to avoid a dynamic impedance drop. When output current reaches the first threshold as a result of an impedance drop across the speaker, the overcurrent protection circuitry limits the output current to the value of the first threshold, but does not shut down the circuit. The second threshold is used to detect an overcurrent condition to shut down the circuit. Current limiting logic of a first channel monitors the overcurrent condition of a second channel and controls the first channel output in response thereto. This permits the second channel output current to reach the second threshold if the circuit is experiencing a short-circuit condition. This scheme also allows the output current to drop below the first threshold if the overcurrent condition of the second channel is caused by an impedance drop across the output speaker. | 2016-05-19 |
20160142025 | INTEGRATED MATCHING CIRCUIT FOR A HIGH FREQUENCY AMPLIFIER - An integrated matching circuits for a high frequency amplifier transistor having an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The integrated matching circuit comprises an inductive element, and a capacitive element arranged in a series arrangement with the inductive element. The series arrangement has a first terminal end connected to the input terminal or to the output terminal and a second terminal end connected to the reference terminal. The first terminal end and the second terminal end are arranged at a same lateral side of the integrated matching circuit to obtain a geometry with the first terminal end adjacent to the input terminal or to the output terminal and the second terminal end adjacent to the reference terminal. | 2016-05-19 |
20160142026 | REGULATED CASCODE (RGC)-TYPE BURST MODE OPTIC PRE-AMPLIFIER HAVING EXTENDED LINEAR INPUT RANGE - A Regulated Cascode (RGC)-type burst mode optic pre-amplifier having an extended linear input range. The burst mode optic pre-amplifier comprises an RGC-type Trans Impedance Amplifier (TIA), wherein a current path is added in the circuit of the RGC-type TIA to control a linearity state of the RGC-type TIA, and a main voltage gain is controlled in other circuit blocks after the RGC-type TIA. | 2016-05-19 |
20160142027 | AMPLIFIER AND RELATED METHOD - An amplifier applicable to an intra-band non-contiguous carrier aggregation (NCCA) band includes a first amplifier circuit and a second amplifier circuit. The NCCA band includes at least a primary component carrier (PCC) channel and a secondary component carrier (SCC) channel not adjacent to each other. The first amplifier circuit receives a first input signal, and generates a first output signal for undergoing down-conversion of one of the PCC channel and the SCC channel. The second amplifier circuit receives at least one second input signal, and generates a second output signal for undergoing down-conversion of another of the PCC channel and the SCC channel. The at least one second input signal received by the second amplifier circuit is provided by the first amplifier circuit according to the first input signal. | 2016-05-19 |
20160142028 | HIGH SPEED SIGNAL LEVEL DETECTOR AND BURST-MODE TRANS IMPEDANCE AMPLIFIER USING THE SAME - A signal level detector comprising and a Burst-Mode Trans Impedance Amplifier (BM-TIA) using the same. The signal level detector includes a level detector configured to detect peak voltage of an input voltage signal, a reference voltage generator configured to generate second reference voltage by receiving first reference voltage, a comparator configured to compare the peak voltage and the second reference voltage and output a discrimination value according to a comparison result, and a latch configured to store the differential output from the comparator, wherein the level detector and the reference voltage generator have differential amplifier in the same structure. | 2016-05-19 |
20160142029 | VOLUME CONTROL RATES - A volume controller may maintain a volume mapping including a plurality of zones of volume level, each zone defined according to a range of included volume levels and specifying a volume ramp up control rate and a volume ramp down control rate for adjustment of volume levels within the range, determine, according to the volume mapping based on a current volume level and a direction of a requested volume change, a step value for adjusting the current volume level, and adjust the current volume level according to the step value. | 2016-05-19 |
20160142030 | CABLE ASSEMBLY HAVING A SIGNAL-CONTROL COMPONENT - Cable assembly is provided that includes a communication cable having first and second insulated wires. Each of the first and second insulated wires has a signal conductor and an insulation layer that surrounds the signal conductor. The cable assembly also includes a circuit carrier that is coupled to the communication cable and has first and second signal pathways. Each of the first and second signal pathways includes a leading conductive surface and a trailing conductive surface that are separated from each other. The signal conductors of the first and second insulated wires are coupled to the trailing conductive surfaces of the first and second signal pathways, respectively. Each of the first and second signal pathways includes a corresponding signal-control component that electrically couples the separated leading and trailing conductive surfaces. | 2016-05-19 |
20160142031 | COMMON MODE FILTER AND ESD-PROTECTION-CIRCUIT-EQUIPPED COMMON MODE FILTER - On a first-signal-line side, a first resonant circuit is defined by a first inductance element, a first capacitance element, a second capacitance element, a third inductance element and a fifth inductance element, a third resonant circuit is defined by the first inductance element, the first capacitance element and the second capacitance element, and a fifth resonant circuit is defined by the first inductance element, the third inductance element, the first capacitance element, the second capacitance element and the fifth capacitance element. Similarly, on a second-signal-line side, a second resonant circuit, a fourth resonant circuit and a sixth resonant circuit are provided. | 2016-05-19 |
20160142032 | COMPOSITE ELECTRONIC COMPONENT AND BOARD HAVING THE SAME - A composite electronic component includes a composite body in which a common mode filter and a multilayer ceramic capacitor array are coupled to each other, the common mode filter including a first body in which a common mode choke coil is disposed, and the multilayer ceramic capacitor array including a second body in which a plurality of dielectric layers are stacked. | 2016-05-19 |
20160142033 | COMPOSITE ELECTRONIC COMPONENT AND BOARD HAVING THE SAME - A composite electronic component includes a composite body in which a common mode filter and a multilayer ceramic capacitor array are coupled to each other, the common mode filter including a first body having a common mode choke coil, and the multilayer ceramic capacitor array including a second body in which a plurality of dielectric layers are stacked. | 2016-05-19 |
20160142034 | COMPOSITE ELECTRONIC COMPONENT AND BOARD HAVING THE SAME - A composite electronic component includes a composite body including a common mode filter and a resistor that are coupled to each other, the common mode filter including a common mode choke coil; and a plurality of input terminals disposed on a first side surface of the composite body, a plurality of output terminals, and a ground terminal. | 2016-05-19 |
20160142035 | AUTOMATIC IMPEDANCE MATCHING METHOD AND MODULE, PARTICULARLY FOR A RADIO-FREQUENCY TRANSMISSION OR RECEPTION CHAIN - An automatic impedance matching method for a radio-frequency chain comprises: an impedance matching network having an input and an output, a first radio-frequency device connected to the input and a second radio-frequency device connected to the output, the impedance matching network exhibiting a reconfigurable topology and comprising a plurality of reactive elements, at least one of which exhibits a variable reactance, the method comprising the choice of the configuration of the impedance matching network allowing the implementation of impedance matching while minimizing losses. An automatic impedance matching module for implementing the method is provided. Radio-frequency transmission and reception chains comprising a module are also provided. | 2016-05-19 |
20160142036 | BALUNS FOR RF SIGNAL CONVERSION AND IMPEDANCE MATCHING - A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance. | 2016-05-19 |
20160142037 | BALUN TRANSFORMER - A balun transformer includes an input terminal into which an unbalanced signal is input, a converter that includes at least a first signal line connected to the input terminal and that converts the unbalanced signal into a balanced signal, a first output terminal connected to the first signal line, a second output terminal from which the balanced signal is output, the balanced signal being also output from the first output terminal, and a capacitor connected between the input terminal and the second output terminal. | 2016-05-19 |
20160142038 | PIEZOELECTRIC THIN FILM RESONATOR, FILTER, AND DUPLEXER - A piezoelectric thin film resonator includes: a substrate; a piezoelectric film located on the substrate; a lower electrode and an upper electrode facing each other across at least a part of the piezoelectric film; and an insertion film inserted in the piezoelectric film, located in at least a part of an outer peripheral region within a resonance region where the lower electrode and the upper electrode face each other across the piezoelectric film, and not located in a center region of the resonance region, wherein a difference between a total film thickness of the piezoelectric film and the insertion film in a first region, in which the insertion film is inserted, within the resonance region and a film thickness of the piezoelectric film in a second region, in which the insertion film is not inserted, is less than a film thickness of the insertion film. | 2016-05-19 |
20160142039 | CONTOUR-MODE PIEZOELECTRIC MICROMECHANICAL RESONATORS - A contour mode micromechanical piezoelectric resonator. The resonator has a bottom electrode; a top electrode; and a piezoelectric layer disposed between the bottom electrode and the top electrode. The piezoelectric resonator has a planar surface with a cantilevered periphery, dimensioned to undergo in-plane lateral displacement at the periphery. The resonator also includes means for applying an alternating electric field across the thickness of the piezoelectric resonator. The electric field is configured to cause the resonator to have a contour mode in-plane lateral displacement that is substantially in the plane of the planar surface of the resonator, wherein the fundamental frequency for the displacement of the piezoelectric resonator is set in part lithographically by the planar dimension of the bottom electrode, the top electrode or the piezoelectric layer. | 2016-05-19 |
20160142040 | DEMULTIPLEXING APPARATUS - An elastic wave filter includes a transmission circuit provided on a first main surface of a first piezoelectric substrate and a reception circuit provided on a second main surface of a second piezoelectric substrate. A mounting board on which the elastic wave filter is mounted includes a first ground electrode opposed to the transmission circuit; a first rear surface ground electrode overlapped with the transmission circuit in plan view of a rear surface; a second ground electrode opposed to the reception circuit; a second rear surface ground electrode overlapped with the reception circuit in plan view of the rear surface; a line electrode used for connection between the first ground electrode and the second ground electrode; and a first via electrode and a second via electrode passing through the mounting board. An amount of heat transfer per unit time of the second via electrode is greater than an amount of heat transfer per unit time of the first via electrode. | 2016-05-19 |
20160142041 | ACOUSTIC WAVE DEVICE, TRANSCEIVER DEVICE, AND MOBILE COMMUNICATION DEVICE - An acoustic wave device includes: an acoustic wave chip including an acoustic wave element formed therein; a multilayered substrate including the acoustic wave chip mounted on an upper surface thereof; a first ground terminal formed on a lower surface of the multilayered substrate and electrically coupled to a ground electrode of the acoustic wave chip; a second ground terminal formed on the lower surface; a signal terminal formed on the lower surface and electrically coupled to a signal electrode of the acoustic wave chip; and a shield layer formed at least on the upper surface, on the lower surface, or between the lower surface and the upper surface of the multilayered substrate so as to overlap with at least a part of the acoustic wave chip, not electrically coupled to the first ground terminal in the multilayered substrate, and electrically coupled to the second ground terminal. | 2016-05-19 |
20160142042 | ELIMINATION METHOD FOR COMMON SUB-EXPRESSION - A common sub-expression elimination method for simplifying hardware logic of a hardware filter circuit by eliminating a common sub-expression included in a plurality of sub-expressions is provided. Each of the sub-expressions includes a corresponding two or more of inputs constituting a plurality of coefficients used by the hardware filter circuit. The method is implemented on a computing device and includes: identifying for each coefficient of the plurality of coefficients, a combination of the inputs constituting the coefficient; counting occurrences of the sub-expressions in each of the coefficients; identifying one or more of the sub-expressions having a maximum one of the counts and including the corresponding two or more of the inputs; selecting one of the one or more of the sub-expressions as the common sub-expression; eliminating the common sub-expression; and repeating these steps to eliminate more of the sub-expressions common to multiple ones of the coefficients. | 2016-05-19 |
20160142043 | OUTPUT DRIVER - In one example, a method includes, in response to a voltage level of an input signal satisfying an input voltage threshold, activating a first driver of a plurality of drivers configured to collectively generate an output signal. In this example, the method also include, in response to the voltage level of the input signal satisfying the input voltage threshold and a voltage level of the output signal satisfying an output voltage threshold, toggling activation of a second driver of the plurality of drivers, wherein the second driver is configured to switch more current when activated than the first driver, and wherein the first driver has a faster slew rate than the second driver. | 2016-05-19 |
20160142044 | SIGNAL PROCESSING DEVICE - A signal processing device includes: a signal processing circuit that processes an input signal, and outputs a signal corresponding to the input signal; an offset input device that inputs a diagnosis offset signal as an internal signal in a passage between an input side and an output side of the signal processing circuit; a self-diagnosis device that performs a self-diagnosis of the signal processing circuit based on a variation in the signal output from the signal processing circuit when the diagnosis offset signal input by the offset input device is varied by a predetermined amount; and an extraction device that removes a component of the diagnosis offset signal from the signal output from the signal processing circuit, and extracts only a signal corresponding to the input signal. | 2016-05-19 |
20160142045 | ASYNCHRONOUS CLOCK ENABLEMENT - An asynchronous clock enable system includes a clock generation device configured to generate a first clock signal to operate a target resource. The asynchronous clock enable system also includes a clock gating device coupled to the clock generation device to determine when the first clock signal achieves stability. The clock gating device generates a clock gating signal to enable the first clock signal when the first clock signal achieves stability. The clock gating device is asynchronous relative to the clock request signal. | 2016-05-19 |
20160142046 | SELF CLOCKING COMPARATOR FOR A CHARGE PUMP - A self clocking comparator for clocking a charge pump providing a high voltage output including multiple gain stages and a reset circuit. The gain stages are configured to assert the compare voltage at a first voltage level in a default state when the sense voltage is greater than the reference voltage, and to assert the compare voltage to a second voltage level in a reset state when the sense voltage falls below the reference voltage. The reset circuit resets, or otherwise forces, the gain stages back to the default state in response to the compare voltage transitioning to the second voltage level. The compare voltage oscillates while the sense voltage is less than the reference voltage at a frequency based on a magnitude of a difference between the sense voltage and the reference voltage up to a predetermined maximum frequency level. | 2016-05-19 |
20160142047 | SEMICONDUCTOR DEVICE - A sample-and-hold circuit including a transistor and a capacitor is connected to the differential circuit. The sample-and-hold circuit acquires voltage for correcting the offset voltage of the differential circuit by charging or discharging the capacitor through sampling operation. Then, it holds the potential of the capacitor through holding operation. In normal operation of the differential circuit, the output potential of the differential circuit is corrected by the potential held by the capacitor. The transistor in the sample-and-hold circuit is preferably a transistor whose channel is formed using an oxide semiconductor. An oxide semiconductor transistor has extremely low leakage current; thus, a change in the potential held in the capacitor of the sample-and-hold circuit can be minimized. | 2016-05-19 |
20160142048 | SYSTEM AND METHOD FOR DRIVING A POWER SWITCH - A gate driver circuit for the power switch is disclosed. The gate driver circuit includes a resistor network coupled to the power switch. The resistor network includes a plurality of resistors. The gate driver circuit further includes a control unit operatively coupled to the resistor network. The control unit is configured to control the resistor network such that the resistor network provides different resistance values in at least two of a delay phase, a commutation phase, and a saturation phase when the power switch is transitioned to a first state. A method for driving the power switch is also disclosed. | 2016-05-19 |
20160142049 | POWER SUPPLY CIRCUITS FOR GATE DRIVERS - An embodiment of a power supply circuit to generate a supply voltage for a gate driver circuit can include an isolated power supply circuit to receive a first voltage in a first isolated system and provide power to a cyclic charging power supply circuit, the cyclic charging power supply circuit providing a supply voltage to the gate driver circuit in a second isolated system, the isolated power supply circuit providing the power to the cyclic charging power supply circuit while the gate driver circuit drives a transistor in an on state. The isolated power supply circuit can include a control circuit to regulate the power provided to maintain or increase the supply voltage while the gate driver circuit drives the transistor in an on state. The power supply circuit can also include the cyclic charging power supply circuit to receive a second voltage in the second isolated system and provide the supply voltage to the gate driver circuit. The cyclic charging power supply circuit can include one or more of a bootstrap power supply circuit or a charge pump power supply circuit. | 2016-05-19 |
20160142050 | MULTIPLE-UNIT SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME - Provided are a multiple-unit semiconductor device that enables space savings and a method for controlling such a semiconductor device. A multiple-unit semiconductor device is brought into conduction by a Si-FET being brought into conduction first and a GaN device being brought into conduction after the Si-FET has been brought into conduction. | 2016-05-19 |
20160142051 | DRIVER OUTPUT WITH DYNAMIC SWITCHING BIAS - A circuit of an output stage of a push-pull driver having dynamic biasing may include a stacked configuration of field effect transistors (PFETs) having a first PFET, a second PFET, and a third PFET, whereby the first PFET is connected to a first supply voltage, the third PFET is connected to an output of a switchable voltage bias generator circuit, and the second PFET is electrically connected between the first PFET and the third PFET. A transmission gate may be connected to a second supply voltage, whereby the transmission gate electrically connects the second supply voltage to an electrical connection between the first PFET and the second PFET based on a first operating state for preventing a voltage breakdown condition associated with the stacked configuration of PFETs. The third PFET is bias controlled via the switching of the output of the switchable voltage bias generator circuit. | 2016-05-19 |
20160142052 | FINGER SENSING DEVICE AND METHOD - A finger sensing device includes a first conductive plate, wherein the area between the finger and the first conductive plate increases in response to the finger moving in a first direction proximate the first conductive plate. A second conductive plate is located proximate the first conductive plate, wherein the area between the finger and the second conductive plate decreases in response to the finger moving in the first direction proximate the second conductive plate. A first capacitance detector is coupled to the first conductive plate for measuring a first capacitance between the finger and the first conductive plate. A second capacitance detector is coupled to the second conductive plate for measuring a second capacitance between the finger and the second conductive plate. | 2016-05-19 |
20160142053 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. | 2016-05-19 |
20160142054 | VOLTAGE SCALING FOR HOLISTIC ENERGY MANAGEMENT - A method for scaling voltages provided to different modules of a system-on-chip (SOC) includes receiving, at an energy-performance engine of the SOC, a first indication of usage history for a first module of the SOC and a second indication of usage history for a second module of the SOC. The method includes receiving a battery life indication that indicates a remaining battery life for a battery of the SOC. The method also includes adjusting a first supply voltage provided to the first module of the SOC based on the first indication, the second indication, and the battery life indication. The method further includes adjusting a second supply voltage provided to the second module of the SOC based on the first indication, the second indication, and the battery life indication. | 2016-05-19 |
20160142055 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying a first voltage to a first node and converting a voltage level of the first node into a second logic level different from the first logic level, and a second circuit applying an enable signal having the second logic level and a clock signal having the first logic level, supplying a second voltage to a second node different from the first node and converting a voltage level of the second node into the second logic level. The second circuit includes an operation circuit performing a NAND operation on the logic level of the enable signal and the voltage level of the second node, and a switch turned on in response to an output of the operation circuit and supplying the second voltage to the second node. | 2016-05-19 |
20160142056 | LEVEL SHIFTER OF DRIVING CIRCUIT - A level shifter applied to a driving circuit of a display is disclosed. The level shifter at least includes a first stage of level shifting unit, a second stage of level shifting unit, and two third stage of level shifting units belonging to different power domains and used to perform boost conversion of voltage signals in different power domains. The first stage of level shifting unit includes eight transistors. The second stage of level shifting unit includes four transistors. The two third stage of level shifting units both include six transistors and two output terminals. The level shifter of the driving circuit in this invention makes the output terminals of the two third stage of level shifting units belonging to different power domains to synchronously output the voltage-shifted voltage signals. | 2016-05-19 |
20160142057 | COMPACT LOGIC EVALUATION GATES USING NULL CONVENTION - Compact logic evaluation gates are built using null convention logic (NCL) circuits. The inputs to a null convention circuit include a NCL true input and a NCL complement input. The NCL circuit includes a gate coupled to the pair of inputs, where the gate comprises a plurality of transistors. The transistors allow for logical signal capture, provide a pair of cross-coupled inverters for data storage, and include a first and second pull-down device. The first pull-down device causes a first side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL true input, and the second pull-down device causes a second side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL complement input. | 2016-05-19 |
20160142058 | DELAY CIRCUIT - A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit. | 2016-05-19 |
20160142059 | Differential Odd Integer Divider - A differential odd integer divider provides low power and compact sub-harmonics of an applied square or sinusoidal clock signal with self-aligned 50% duty cycle. The odd integer divider circuit includes a set of low power delay cells connected in a ring fashion. Each delay cell includes two differential dual port inputs connected to the gates of MOS transistors. For instance, these odd integer dividers include a series of low power latch circuits that are custom configured for minimum headroom and low power consumption. These output phasors can then be combined with an appropriate weight factor to provide a near-sinusoidal waveshape from the input square waveshape. Intrinsic 50% duty cycle maybe shortened or stretched by using combinatorial logic circuits. | 2016-05-19 |
20160142060 | DELAY LOCKED LOOP CIRCUIT AND OPERATION METHOD THEREOF - A delay locked loop (DLL) circuit may include: an input clock control unit suitable for transmitting first and second internal clocks generated based on an external clock, and controlling transmission of the second internal clock based on a clock control signal which is activated during a predetermined period; a clock delay unit suitable for generating a first delay locked clock by delaying the first internal clock by a delay time required for locking, and generating a second delay locked clock by delaying the second internal clock based on the clock control signal; and an output clock control unit suitable for outputting the first delay locked clock and the second delay locked clock during a period in which the clock control signal is activated. | 2016-05-19 |
20160142061 | PHASE DETECTOR AND ASSOCIATED PHASE DETECTING METHOD - A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals. | 2016-05-19 |
20160142062 | DIFFERENTIAL PHASE-FREQUENCY DETECTOR - A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals. | 2016-05-19 |
20160142063 | PHASE LOCKED LOOP AND ASSOCIATED METHOD FOR LOOP GAIN CALIBRATION - A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider and a phase error processing circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit receives a calibration signal and generates a charge pump output according to the calibration signal when the PLL operates in a calibration mode. The type II loop filter receives the charge pump output, and generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider receives the oscillating signal and an adjusting signal, and refers to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit receives the feedback signal and a reference signal, and outputs the adjusting signal based on a comparison result of the reference signal and the feedback signal. | 2016-05-19 |
20160142064 | AUTOMATIC FREQUENCY CONTROL - An automatic frequency control device, a method for automatic frequency control, a receiver, a mobile station and a non-transitory computer-readable digital storage medium are provided. The automatic frequency control device may include a quality calculation unit to calculate quality of a received signal, a state machine controller to generate a control signal based on the calculated quality of the received signal, and a filter to filter an estimated frequency offset of the received signal based on the control signal. | 2016-05-19 |
20160142065 | DIGITAL PHASE LOCKED LOOP - A phase locked loop circuit ( | 2016-05-19 |
20160142066 | FREQUENCY DIVISION CLOCK ALIGNMENT - Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal; at a first leaf node of the clock distribution network, detecting a reference event and generating a synchronizing signal based on the detection of the reference event; passing the synchronizing signal along a synchronizing signal path from the first leaf node to the root node via one or more clocked storage cells, each storage cell being clocked from a corresponding point within the clock distribution network; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal received at the root node, and distributing the second clock signal to the leaf nodes of the clock distribution network, the generating of the second clock signal resulting in the second clock signal received at the first leaf node being synchronized to the detected reference event. | 2016-05-19 |
20160142067 | FREQUENCY DIVISION CLOCK ALIGNMENT USING PATTERN SELECTION - Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal generated based on a reference clock signal; at a first leaf node, detecting a reference event associated with the reference clock signal and generating a synchronizing signal; passing the synchronizing signal from the first leaf node to the root node; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal, and distributing the second clock signal to the leaf nodes. Generating the second clock signal includes selecting a repeating pattern of cycles of the first clock signal including fewer than all of the cycles of the first clock signal, and at least every cycle of the first clock signal that is shifted in time by a propagation delay with respect to a rising edge of the reference clock signal. | 2016-05-19 |
20160142068 | ANALOG-TO-DIGITAL CONVERTER - Improvement of conversion precision in an analog-to-digital converter is realized. Therefore, a voltage of a correction signal and a voltage obtained by attenuating the voltage with a fixed attenuation rate by an attenuation circuit | 2016-05-19 |
20160142069 | Multi-path, series-switched, passively-summed digital-to-analog converter - A digital-to-analog converter which minimizes noise and optimizes dynamic range by apportioning a least significant bits portion of an incoming digital signal to a low-path circuit and a most significant bits portion of the incoming digital signal to a high-path circuit. The low-path circuit has a low-path digital-to-analog converter, which feeds a low-path amplifier, which feeds a low-path resistive element, which feeds an output node. The high-path circuit has a high-path digital-to-analog converter, which feeds a high-path amplifier, which feeds a high-path resistive element when a high-path switching element is closed, which feeds an output node. The output node is a simple electrical connection of the outputs of the low-path and high-path resistive elements. The high-path switching element is closed when the incoming digital signal has an amplitude above a switching threshold level. Parameters of the circuit, including the sizes of the least significant bits portion and most significant bits portion of the incoming digital signal, are selected such that the switching threshold level is significantly above the noise level produced by the high-path circuit thereby providing psychoacoustic masking of noise produced by the high-path circuit. | 2016-05-19 |
20160142070 | GENERATING AN ENTROPY SIGNAL - A method includes using an analog-to-digital converter (ADC) to provide an entropy signal at an output of the ADC. The method includes controlling a reference signal to the ADC to cause an internal noise level of the ADC to correspond to more than one least significant bit (LSB) of the ADC. | 2016-05-19 |
20160142071 | RECEIVER, TRANSMITTER, METHOD FOR DETERMINING A VALUE ENCODED IN A PWM SIGNAL, AND METHOD FOR TRANSMITTING A VALUE ENCODED IN A PWM SIGNAL - A receiver includes a receiver circuit to receive a pulse width modulated signal, which assumes a first signal level, a second signal level and an intermediate signal level between the first signal level and the second signal level. The receiver further includes a quantization circuit to determine a value encoded in the signal based on an intermediate time period between a first transition and an intermediate transition and based on a main time period between the first transition and a second transition. The first transition comprises the first signal level, wherein the intermediate transition includes the intermediate signal level. The second transition includes the second signal level. | 2016-05-19 |
20160142072 | METHOD AND ARRANGEMENT FOR SETTING AN EFFECTIVE RESOLUTION OF AN OUTPUT SIGNAL IN INCREMENTAL DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS - A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set. | 2016-05-19 |
20160142073 | Access Control in a Network - The teachings relates to a method | 2016-05-19 |