20th week of 2011 patent applcation highlights part 60 |
Patent application number | Title | Published |
20110119434 | System And Method For Safely Updating Thin Client Operating System Over A Network - A method for updating a thin client image includes the steps of writing a service operating system (OS) from a network device to limited capacity memory of a thin client device, writing a large part of a new image from the network to the memory of the thin client in a series of portions, without writing over the service OS, and writing a final small part of the new image over the service OS. | 2011-05-19 |
20110119435 | FLASH MEMORY STORAGE SYSTEM - A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration. | 2011-05-19 |
20110119436 | FLASH MEMORY SYSTEM AND DATA WRITING METHOD THEREOF - Provided are a flash memory system and a data reading method thereof, the method including serially reading groups of data and parity codes corresponding to each of the respective groups from a page buffer; calculating the parity for each serially read group; checking for errors in each serially read group by comparing each calculated parity with a corresponding serially read parity code, respectively; and providing an output signal indicative of any comparative parity errors detected, wherein the reading of each group of data is followed by the reading of the parity code for the group, and the checking for errors in each group of data is done during the serial reading operation. | 2011-05-19 |
20110119437 | Sequentially Written Journal in a Data Store - Systems, methods, and computer storage media for storing and retrieving data from a data store in a distributed computing environment are provided. An embodiment includes receiving data at a data store comprising a sequential journal store, RAM, and a non-sequential target store. When RAM utilization is below a threshold, received data is stored to the RAM as a write cache for the target store and the journal store. But, when the utilization is above the threshold, the data is stored to the journal store without write-caching to the RAM for the target store. When the RAM utilization falls below a threshold, data committed to the journal store, but not write-cached to the RAM for the target store, is later read from the journal store and write-cached to the RAM for a target store. | 2011-05-19 |
20110119438 | FLASH MEMORY FILE SYSTEM - Apparatus having corresponding methods and computer-readable media comprise: a plurality of flash modules, wherein each of the flash modules comprises a cache memory; a flash memory; and a flash controller in communication with the cache memory and the flash memory; wherein the flash controller of a first one of the flash modules is configured to operate the cache memories together as a global cache; wherein the flash controller of a second one of the flash modules is configured to operate a second one of the flash modules as a directory controller for the flash memories. | 2011-05-19 |
20110119439 | Spacing Periodic Commands to a Volatile Memory for Increased Performance and Decreased Collision - A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis. | 2011-05-19 |
20110119440 | DYNAMIC PROGRAMMABLE INTELLIGENT SEARCH MEMORY - Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory derived using randomly accessible dynamic memory circuits that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the dynamic Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata and then programmed in dynamic PRISM for evaluating content with the search rules. | 2011-05-19 |
20110119441 | SELECTIVE DEVICE ACCESS CONTROL - Various method, system, and computer program product embodiments for selective device access control in a data storage system are provided. In one such embodiment, a plurality of access groups associated with logical devices used to access the data storage system is initialized. Each of the plurality of access groups corresponds to a range of the logical devices. An access group name of one of the access groups is bound to a logical volume of the data storage system at a volume creation. The logical volume, once bound to the access group name, is granted access by those of the logical devices in a range of the logical devices corresponding to the one of the access groups. | 2011-05-19 |
20110119442 | NON-VOLATILE WRITE CACHE FOR A DATA STORAGE SYSTEM - The present disclosure provides a data storage system. In one example, the data storage system includes a data storage media component having a plurality of data storage locations. A first set of the plurality of data storage locations are allocated for a main data storage area. The data storage system also includes a controller configured to define a write cache for the main data storage area by selectively allocating a second set of the plurality of data storage locations. | 2011-05-19 |
20110119443 | Apparatus and Method for Distributing Writes Asymmetrically Among Drives - An apparatus and method are disclosed for distributing writes asymmetrically. An asymmetric distribution module calculates an asymmetric distribution of writes for a plurality of drives. A write module writes data to each drive in accordance with the asymmetric distribution of writes. | 2011-05-19 |
20110119444 | ADAPTIVE CACHING OF DATA - Data access is facilitated by employing local caches and an adaptive caching strategy. Specific data is stored in each local cache and consistency is maintained between the caches. To maintain consistency, adaptive caching structures are used. The members of an adaptive caching structure are selected based on a sharing context, such as those members having a chosen association identifier or those members not having the chosen association identifier. | 2011-05-19 |
20110119445 | HEAP/STACK GUARD PAGES USING A WAKEUP UNIT - A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response. | 2011-05-19 |
20110119446 | CONDITIONAL LOAD AND STORE IN A SHARED CACHE - A method, system and computer program product are disclosed for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that one of the processor units. If an address in the memory cache is reserved for that one of the processors, the data are stored at this reserved address. | 2011-05-19 |
20110119447 | METHOD AND APPARATUS FOR MANAGING MEMORY IN A MOBILE ELECTRONIC DEVICE - According to embodiments described in the specification, a method and apparatus for managing memory in a mobile electronic device are provided. The method comprises: receiving a request to install an application; receiving at least one indication of data intended to be maintained in a shared cache; determining, based on the at least one indication, whether data corresponding to the intended data exists in the shared cache; upon a negative determination, writing the intended data to the shared cache; and repeating the receiving at least one indication, the determining and the writing for at least one additional application. | 2011-05-19 |
20110119448 | Data store maintenance requests in interconnects - Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The interconnect circuitry comprises: at least one input for receiving transaction requests from the initiator device(s); at least one output for outputting transaction requests to the recipient device(s); a plurality of paths for transmitting said transaction requests between the at least one input and the at least one output; wherein at least one of said transaction requests comprises a data store maintenance request requesting a data store maintenance operation to be performed on data stores within the data processing apparatus; and control circuitry for routing the received transaction requests from the at least one input to the at least one output; wherein the control circuitry is configured to respond to receipt of the data store maintenance operation by transmitting the data store maintenance operation along at least one of the plurality of paths followed by a barrier transaction request, the control circuitry being configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along the at least one of said plurality of paths, such that at least some transaction requests subsequent to the data store maintenance request in the stream of transaction requests are held behind the data store maintenance request by the barrier transaction request. | 2011-05-19 |
20110119449 | APPLICATION INFORMATION CACHE - A request for application information can be received from an application running in a process. The application information can be requested from an information repository, and received back from the repository in a first format. The application information can be converted to a second format, and passed to the application in the second format. In addition, the application information can be saved in the second format in a cache in the process. Also, when application information has been cached in response to a request for the information for a first user object, and a subsequent request for the application information for a second user object is received, it can be determined whether the second user object is authorized to access the application information. If so, then the application information can be fetched from the cache and returned for use by the second user object. | 2011-05-19 |
20110119450 | MULTI-PROCESSOR AND APPARATUS AND METHOD FOR MANAGING CACHE COHERENCE OF THE SAME - A cache consistency management device according to example embodiments comprises a ping-pong monitoring unit monitoring a ping-pong migration sequence generated between a plurality of processors; a counting unit counting the number of successive generations of the ping-pong migration sequence in response to the monitoring result; and a request modifying unit modifying a migration request to a request of a non-migratory sharing method on the basis of the counting result. | 2011-05-19 |
20110119451 | NON-BLOCKING DATA TRANSFER VIA MEMORY CACHE MANIPULATION - A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented. | 2011-05-19 |
20110119452 | Hybrid Transactional Memory System (HybridTM) and Method - A computer processing system having memory and processing facilities for processing data with a computer program is a Hybrid Transactional Memory multiprocessor system with modules | 2011-05-19 |
20110119453 | METHOD AND SYSTEM FOR IMPLEMENTING MULTI-CONTROLLER SYSTEMS - A method for implementing a high-availability system that includes a plurality of controllers that each includes a shared memory. The method includes storing in the shared memory, by each controller, status data related to each of a plurality of failure modes, and calculating, by each controller, an availability score based on the status data. The method also includes determining, by each controller, one of the plurality of controllers having a highest availability score, and identifying the one of the plurality of controllers having the highest availability score as a master controller. | 2011-05-19 |
20110119454 | DISPLAY SYSTEM FOR SIMULTANEOUS DISPLAYING OF WINDOWS GENERATED BY MULTIPLE WINDOW SYSTEMS BELONGING TO THE SAME COMPUTER PLATFORM - A display system for simultaneous displaying of windows generated by a plurality of window systems belonging to the same desktop or laptop platform includes a master computer device with its display device and at least one slave computer device, a shared memory, an input means and an output means, as described herein. Each of the master computer device and the at least one slave computer device has a corresponding window system. The shared memory is coupled to the computer devices and is accessible by the master computer device and the at least one slave computer device. The input means receives multiple windows simultaneously generated by the window systems of the master computer device and the at least one slave computer device. The output means generates the multiple windows for the display device of the master computer device. In support of these operations, the master computer device and the at least one slave computer device simultaneously read and write window data stored in the shared memory. | 2011-05-19 |
20110119455 | METHODS OF UTILIZING ADDRESS MAPPING TABLE TO MANAGE DATA ACCESS OF STORAGE MEDIUM WITHOUT PHYSICALLY ACCESSING STORAGE MEDIUM AND RELATED STORAGE CONTROLLERS THEREOF - A method of managing data access of a storage medium includes establishing an address mapping table to record a physical address of a first data stored in the storage medium, where the physical address of the first data is mapped to a logical address of the first data; and when receiving a command for handling the first data stored in the storage medium internally, processing the address mapping table to serve the command without physically accessing the first data stored in the storage medium. | 2011-05-19 |
20110119456 | EFFICIENCY OF HARDWARE MEMORY ACCESS USING DYNAMICALLY REPLICATED MEMORY - Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages. | 2011-05-19 |
20110119457 | Computing system and method controlling memory of computing system - Provided is a computing system and method. The computing system may back up, based on an overlay scheme, a task of an internal memory in an external memory, and the task may be restored to the internal memory from the external memory. The computing system may include a first memory to store data associated with a first task processed in a processor, as a first data structure, a second memory to store backup data of the data associated with the first task, and a memory controller to copy, to the second memory, data other than data previously backed up in the second memory among the data associated with the first task, when the data associated with the first task is backed up in the second memory to process a second task in the processor. | 2011-05-19 |
20110119458 | RELAY DEVICE - In order to allow a user to backup data, a backup system is used to transfer data from an information terminal to a backup device via a relay device. The information terminal includes a storing unit storing the data to be backed up, and includes a communication unit transmitting the data to the relay device and transferring condition information indicating a condition to be satisfied by the relay device. Further, the relay device includes (i) a storing unit storing information relating to transfer destination devices, (ii) a receiving unit receiving the data and the transfer condition information, and (iii) a transfer control unit selecting a transfer destination device that satisfies the condition indicated by the transfer condition information, and controlling transfer of the received data in accordance with the selection. The backup device includes a receiving unit receiving the data transferred by the relay device, and a storing unit storing the received data. | 2011-05-19 |
20110119459 | SNAPSHOT SYSTEM - A storage system including: a storage device which configures an original volume for storing data which is read/written by a host, a copy volume for storing a copy of the original volume at a predetermined timing, and a snapshot volume for storing a snapshot data which is a snapshot of the original volume; and a controller which controls access from the host to the storage device; wherein the controller: copies data of the original volume to the copy volume at a predetermined timing; stores the snapshot data in the snapshot volume corresponding to a write request to the original volume without decreasing a performance of the original volume; manages a generation of the stored snapshot according to predetermined copy volume blocks and snapshot volume blocks, and manages a generation of the copy volume; and reads data from the snapshot volume and/or the copy volume when a read request to a volume of a generation different from that of the original volume is received from the host, without decreasing a performance of the original volume. | 2011-05-19 |
20110119460 | RESTRICTING ACCESS TO OBJECT BASED STORAGE - A method, in one embodiment, can include a server receiving a message to deactivate a partition key of an object based storage system. A token of the object based storage system is signed by the partition key. The object based storage system includes the server. Additionally, after receiving the message, the server can deactivate the partition key to block access to a partition of the object based storage system by a client. The server includes the partition. | 2011-05-19 |
20110119461 | FILE SYSTEM QUOTA AND RESERVATION - A method, in one embodiment, can include allowing storage allocation of data of a file system within an object based storage system. Furthermore, the method can include determining if storage allocation usage for the file system is below a threshold. If the storage allocation usage for the file system is not below the threshold, a client is requested to flush its dirty data associated with the file system. After requesting a client flush, the method can include determining the storage allocation usage for the file system. In addition, the method can include determining periodically if the storage allocation usage has reached a quota. If the quota is reached, the quota is enforced for the data of the file system. | 2011-05-19 |
20110119462 | METHOD FOR RESTORING AND MAINTAINING SOLID-STATE DRIVE PERFORMANCE - A method of maintaining a solid-state drive so that free space within memory blocks of the drive becomes free usable space to the drive. The drive comprises cells organized in pages that are organized in memory blocks in which at least user files are stored. A defragmentation utility is executed to cause at least some of the memory blocks that are partially filled with data and contain file fragments to be combined or aligned and to cause at least some of the memory blocks that contain only invalid data to be combined or aligned. A block consolidation utility is then executed to eliminate at least some of the partially-filled blocks by consolidating the file fragments into a fewer number of the memory blocks. The consolidation utility also increases the number of memory blocks that contain only invalid memory. All of the memory blocks containing only invalid data are then erased. | 2011-05-19 |
20110119463 | COMPUTING SYSTEM AND METHOD CONTROLLING MEMORY OF COMPUTING SYSTEM - Provided is a computing system having a hierarchical memory structure. When a data structure is allocated with respect to a task processed in the computing system, the data structure is divided and a portion of the data structure is allocated to a high speed memory of the hierarchical memory structure and a remaining data structure is allocated to a low speed memory of the hierarchical memory. | 2011-05-19 |
20110119464 | DATA STORAGE SYSTEM COMPRISING A MAPPING BRIDGE FOR ALIGNING HOST BLOCK SIZE WITH PHYSICAL BLOCK SIZE OF A DATA STORAGE DEVICE - A data storage system is disclosed comprising a non-volatile memory and a first interface operable to receive a write command from a host, the write command comprising a host write data block having a host logical block size. A block mapping bridge divides the host write data block into a plurality of transfer data blocks, wherein each transfer data block having a device logical block size smaller than the host logical block size. The transfer data blocks are transmitted through a second interface to control circuitry that accumulates the transfer data blocks into a physical data block having a device physical block size equal to a first integer multiple of the device logical block size, wherein the host logical block size is a second integer multiple of the device physical block size. The physical data block is then written to the non-volatile memory. | 2011-05-19 |
20110119465 | DATA PROCESSING SYSTEM - The data processing system including: a memory block; a data-processing control block; a demultiplex-processing block; a multiplex-processing block; a decode-processing block; and an encode-processing block. In the system, the demultiplex-processing block, multiplex-processing block, decode-processing block, and encode-processing block each execute a process using memory regions in the memory block. During the execution, the data-processing control block changes a memory region to assign to the processing in response to a processing request based on results of processing which the block concerned executed in response to the preceding processing request. With the data processing system, a memory region can be used effectively even if a memory region size required for processing cannot be determined in advance. | 2011-05-19 |
20110119466 | Clearing Selected Storage Translation Buffer Entries Bases On Table Origin Address - An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof. | 2011-05-19 |
20110119467 | MASSIVELY PARALLEL, SMART MEMORY BASED ACCELERATOR - Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The cores further include multiple of smart memory blocks configured to store and process data, each memory block accepting the output of one of the plurality of processing chains. The cores communicate with at least one off-chip memory bank. | 2011-05-19 |
20110119468 | MECHANISM OF SUPPORTING SUB-COMMUNICATOR COLLECTIVES WITH O(64) COUNTERS AS OPPOSED TO ONE COUNTER FOR EACH SUB-COMMUNICATOR - A system and method for enhancing barrier collective synchronization on a computer system comprises a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program being executed by a processor. The system includes providing a plurality of communicators for storing state information for a bather algorithm. Each communicator designates a master core in a multi-processor environment of the computer system. The system allocates or designates one counter for each of a plurality of threads. The system configures a table with a number of entries equal to the maximum number of threads. The system sets a table entry with an ID associated with a communicator when a process thread initiates a collective. The system determines an allocated or designated counter by searching entries in the table. | 2011-05-19 |
20110119469 | BALANCING WORKLOAD IN A MULTIPROCESSOR SYSTEM RESPONSIVE TO PROGRAMMABLE ADJUSTMENTS IN A SYNCRONIZATION INSTRUCTION - In a multiprocessor system with threads running in parallel, workload balancing is facilitated by recognizing a plurality of levels of sub-tasks of a memory synchronization instruction and selectively choosing for at least one thread to do less than all of levels of these sub-tasks in response to the memory synchronization instruction. Which thread waits to synchronize can be impacted by this choice. The programmer can cause a thread expected to be a bottleneck to wait less than other threads. Where one thread is a producer and another thread is a consumer, types of memory synchronization can be adapted to these roles. | 2011-05-19 |
20110119470 | GENERATION-BASED MEMORY SYNCHRONIZATION IN A MULTIPROCESSOR SYSTEM WITH WEAKLY CONSISTENT MEMORY ACCESSES - In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another. | 2011-05-19 |
20110119471 | Method and apparatus to extract integer and fractional components from floating-point data - A method is presented including decomposing a first value into many parts. Decomposing includes shifting ( | 2011-05-19 |
20110119472 | BRANCH PREDICTING DEVICE, BRANCH PREDICTING METHOD THEREOF, COMPILER, COMPILING METHOD THEREOF, AND MEDIUM FOR STORING BRANCH PREDICTING PROGRAM - A branch prediction mechanism | 2011-05-19 |
20110119473 | Virtual Platform Configuration Validation - Systems and methods are provided for unambiguously checking and/or validating a hardware configuration. Configuration rules based upon an actual hardware specification are written and applied to a software use case before the software use case is run. Actual hardware is modeled to create a virtual hardware via a virtual platform system. Upon initiating execution of the software use case on the virtual hardware, a comparison is performed to determine if current settings pertaining to the virtual hardware matches the configuration rules applicable to the software use case. If the configuration rules match the current settings, the software use case can be run on the virtual hardware. If the configuration rules do not match the current settings, execution of the software use case can be stopped and/or alternatively, a notification can be generated, where the notification indicates that the configuration rules and the current settings do not match. | 2011-05-19 |
20110119474 | Serial Peripheral Interface BIOS System and Method - Various embodiments disclosed herein are directed to a serial peripheral interface-based (SPI-based) BIOS system for improved upgrading of a BIOS software image in a gaming machine. The system includes a flash BIOS chip and a SPI BIOS chip. The flash BIOS chip is operable to be written to by an Intel chipset for storage of an onboard Ethernet controller's information, wherein the flash BIOS chip may contain a new BIOS software image. The SPI BIOS chip comprises a traditional BIOS including gaming extensions to the BIOS. The SPI BIOS chip can be disabled from write actions at a jumper/circuit level. When a SPI BIOS write enable jumper circuit is ON, a write protect pin of the serial peripheral interface BIOS is in the disabled state. In this regard, when the write protect pin is in the disabled state, the SPI BIOS content may be updated to the new BIOS software image from a BIOS install compact flash. When the BIOS write enable jumper circuit is OFF, the write protect pin of the serial peripheral interface BIOS is in enabled state. In this regard, when the write protect pin is in the enabled state the serial peripheral interface BIOS content cannot be updated | 2011-05-19 |
20110119475 | GLOBAL SYNCHRONIZATION OF PARALLEL PROCESSORS USING CLOCK PULSE WIDTH MODULATION - A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system. | 2011-05-19 |
20110119476 | HARDWARE RESET BUTTON EQUIVALENT SOFTWARE RESET METHOD FOR NETWORK DEVICE - A software reset method that can be used to reset a network device | 2011-05-19 |
20110119477 | MEMORY SYSTEM AND MEMORY MANAGEMENT METHOD INCLUDING THE SAME - A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors. | 2011-05-19 |
20110119478 | System and method for providing object triggers - The present invention provides for systems and methods of dynamically controlling a cluster or grid environment. The method comprises attaching a trigger to an object and firing the trigger based on a trigger attribute. The cluster environment is modified by actions initiated when the trigger is fired. Each trigger has trigger attributes that govern when it is fired and actions it will take. The use of triggers enables a cluster environment to dynamically be modified with arbitrary actions to accommodate needs of arbitrary objects. Example objects include a compute node, compute resources, a cluster, groups of users, user credentials, jobs, resources managers, peer services and the like. | 2011-05-19 |
20110119479 | EOOBE-Application to collect information for new computer and manufacturing process - A system and method for enhancing the Electronic Out Of Box Experience (eOOBE) for individuals who are ordering a new or replacement device from the device manufacturer. The user is able to select an option to complete the eOOBE setup prior to receiving the new device, where the new device may be a computer, phone, PDA, or other electronic device. An application such as an applet is downloaded from the manufacturer and the application collects device settings and user preferences, as well as file system information, storing the information to a file on the local device file system. This gathered information may include acquiescence to Electronic User License Agreements (EULA), such that these licenses may be pre-configured with the user's agreement before the device is shipped to the user. The collected information is encrypted and sent to the manufacturer, where the manufacturer then builds and configures the new device in accordance with the received data file. The new device is delivered to the user and the user is able to operate the new device in fully configured and activated mode directly out of the manufacturers shipping container. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. | 2011-05-19 |
20110119480 | METHODS AND APPARATUSES FOR SELECTIVE DATA ENCRYPTION - A method of encryption, using an encryption key K with key length k, of at least one message M comprising uniformly distributed symbols, k bits are encrypted of messages at least k bits long, while shorter messages are lengthened, e.g. by padding or concatenation, to obtain a lengthened message at least k bits long before encryption. The encryption efficiency is thus optimized while the encryption security is retained. The encryption method is particularly suitable for JPEG2000 encoded packets comprising a message M. Also provided are an encryption apparatus, a decryption method and a decryption apparatus. | 2011-05-19 |
20110119481 | CONTAINERLESS DATA FOR TRUSTWORTHY COMPUTING AND DATA SERVICES - A digital escrow pattern and trustworthy platform is provided for data services including mathematical transformation techniques, such as searchable encryption techniques, for obscuring data stored at remote site or in a cloud service, distributing trust across multiple entities to avoid a single point of data compromise. Using the techniques of a trustworthy platform, data (and associated metadata) is decoupled from the containers that hold the data (e.g., file systems, databases, etc.) enabling the data to act as its own custodian through imposition of a shroud of mathematical complexity that is pierced with presented capabilities, such as keys granted by a cryptographic key generator of a trust platform. Sharing of, or access to, the data or a subset of that data is facilitated in a manner that preserves and extends trust without the need for particular containers for enforcement. | 2011-05-19 |
20110119482 | Method and system for establishing a communications pipe between a personal security device and a remote computer system - A method and a system is provided for establishing a communications path over a communications network between a personal security device (PSD) and a remote computer system without requiring the converting of high-level messages such as API-level messages to PSD-formatted messages such as APDU-formatted messages (and inversely) to be installed on a local client device in which the PSD is connected. | 2011-05-19 |
20110119483 | Computing System With Off-Load Processing For Networking Related Tasks - A method is described that comprises executing a service selection method on an off load processor of a computing system to select an available network service for handling traffic sent to/from a handheld device. The execution of the service selection method is performed while a main CPU of said computing system is in a low power state. | 2011-05-19 |
20110119484 | Systems and Methods for Securely Providing and/or Accessing Information - The invention is directed to a system for use with a first device in communication with a second device. The system includes a storage medium that is connectable with the first device, a hardened, stand alone, web browser stored on the storage medium, and client authentication data. The web browser uses the client authentication data to facilitate secure communication between the first device and the second device, and the first device communicates with a third device that provides configuration data that includes one or more approved addresses. | 2011-05-19 |
20110119485 | METHOD AND APPARATUS FOR PROVIDING RADIO COMMUNICATION WITH AN OBJECT IN A LOCAL ENVIRONMENT - A method and apparatus for providing radio communication with an electronic object in a local environment are disclosed. For example the method receives via a mobile endpoint device of a user at least one first digital certificate associated with the local environment from a trusted source, and a second digital certificate from the electronic device deployed in the local environment via a wireless connection. The method then authenticates the electronic device using the at least one first digital certificate and the second digital certificate. | 2011-05-19 |
20110119486 | METHOD AND APPARATUS FOR MANAGING ACCESS RIGHTS TO INFORMATION SPACES - An approach is provided for managing access rights of users to information spaces using signatures stored in a memory tag. A signature manager caused reading of a memory tag to initiate a request, from a device, for an initial access to an information space. The request includes an authorization signature associated with the device. The signature manager determines a level of access to the information space by comparing the authorization signature against a lattice of signature primitives associated with the information space. The signature manager then modifies the authorization signature based on the determination and stores the modified authorization signature for validation of subsequent access to the information space by the device. | 2011-05-19 |
20110119487 | System and method for encryption rekeying - Disclosed is a system and method for maintaining a secure, encrypted networking session across a communications network by dynamically replacing encryption keys during the networking session and without terminating the session. A secure control channel is embedded within the general encrypted network connection and is used to transport encrypted control messages from one network endpoint to another. In order to hide that fact that such control messages are being transferred (as opposed to general network data traffic), the control message data packets are formatted in a way to simulate the standard general network data packets. | 2011-05-19 |
20110119488 | METHOD AND SYSTEM FOR FACILITATING THROTTLING OF INTERPOLATION-BASED AUTHENTICATION - One embodiment provides a system that facilitates throttling of interpolation-based authentication at a client. During operation, the system receives data points encrypted with a public key associated with a throttle server. The system then applies offsets to the data points, wherein a respective offset for a data point is associated with a user input. The system blinds the offset data points, and sends to the throttle server the blinded offset data points, thereby allowing the throttle server to perform an interpolation on the blinded offset data points and maintain a count of interpolation attempts from the client. Subsequently, the system receives from the throttle server an evaluation point based at least on the interpolation. In response, the system unblinds the evaluation point, and uses the unblinded evaluation point as a secret for a subsequent authentication process. | 2011-05-19 |
20110119489 | NETWORK AND METHOD FOR ESTABLISHING A SECURE NETWORK - The invention relates to a network with a first node ( | 2011-05-19 |
20110119490 | Controlling Communications - A gateway, program and method for use in a packet-based communication system. The gateway comprises: a connection to a public packet-based network comprising a public-network server and a plurality of public-network user terminals; a connection to a private packet-based network comprising a private-network server and a plurality of private-network user terminals each installed with a public-network communication client; a processing device arranged to receive a login request from a public-network client of a private-network user terminal, and in response to initiate both a private-network authentication procedure involving the private-network server and a public-network authentication procedure involving the public-network server, so as subject to both authentication procedures to enable establishment of a communication channel between one of the public-network user terminals and the public-network client of the private-network user terminal; wherein the processing device is further configured to apply a control policy to communications occurring over said channel. | 2011-05-19 |
20110119491 | SIMPLIFIED PAIRING FOR WIRELESS DEVICES - A first wireless device is paired with a second wireless device for communication over a wireless connection. The first wireless device receives an input that indicates a device identifier of the second wireless device, and then matches the device identifier with one of the data entries in a data repository to obtain a code of the second wireless device without user interactions. The data repository contains a plurality of data entries associating a plurality of wireless devices with their corresponding codes. Based on the code of the second wireless device, the first wireless device authenticates the second wireless device and establishes the wireless connection. | 2011-05-19 |
20110119492 | Apparatus and Method for Over-the-Air (OTA) Provisioning of Authentication and Key Agreement (AKA) Credentials Between Two Access Systems - A method and apparatus for over-the-air provisioning of authentication credentials at an access device via a first access system, wherein the authentication credentials are for a second access system lacking an over-the-air provisioning procedure. For example, the second access system may be a 3GPP system using AKA authentication methods. The first access system may be CDMA, using an OTASP or IOTA procedure. Provisioning the authentication credentials may include provisioning any of a 3GPP AKA authentication root key (K), AKA authentication related parameters, an AKA authentication algorithm to be used in the 3GPP authentication, or authentication algorithm customization parameters. | 2011-05-19 |
20110119493 | UNAUTHORIZED CONTENTS DETECTION SYSTEM - Processing load on an executing device for conducting playback is high during the playback of contents since the executing device performs verification of the contents validity in parallel with the contents playback, and therefore the executing device has to be equipped with a highly efficient processor. The present invention reduces the processing load involved in the verification by using, for the verification, only a predetermined number of encrypted units selected randomly from multiple encrypted units constituting encrypted contents recorded on the DVD. In addition, the present invention is capable of improving the accuracy of detecting unauthorized contents to some extent by randomly selecting a predetermined number of encrypted units every time the verification is performed. | 2011-05-19 |
20110119494 | METHOD AND APPARATUS FOR SHARING LICENSES BETWEEN SECURE REMOVABLE MEDIA - A method and an apparatus for sharing a license between SRMs are disclosed. The method includes: a DRM agent obtains the license from a first SRM, and sets the license to a forwarding state locally; the DRM agent deducts one right of sharing the license; and the DRM agent sends the license to a second SRM. In the prior art, one moving right is deducted when the license moves from SRM1 to the device, and the other moving right is deducted when the license moves from the device to SRM2. By contrast, in the technical solution under the present invention, the license forwarded by the DRM agent is set to the forwarding state, and only one sharing right needs to be deducted, and therefore, the consumption of the sharing rights is reduced and the subscriber's rights are protected. | 2011-05-19 |
20110119495 | METHOD AND ARRANGEMENT RELATING TO ENCRYPTION/DECRYPTION OF A MEMORY UNIT - A memory unit is disclosed comprising a security driver application providing an interface, a storage arrangement and a driver application for activation when connected to a memory accessing arrangement. The driver application is configured, when accessed, to authenticate a user using a password whereby the interface is configured to secure and/or unsecure data transactions to and from the storage arrangement. | 2011-05-19 |
20110119496 | Methods, Systems, And Computer Program Products For Entering Sensitive And Padding Data Using User-Defined Criteria - Disclosed are methods, systems, and computer program products for identifying sensitive data from a user-entered input sequence based on user-defined criteria. According to one method, user-defined criteria for identifying sensitive data within user-entered input sequences that include sensitive data and padding data are received. A request for sensitive data from a requesting agent is presented. A user-entered input sequence that includes sensitive data and padding data is received in response to the request for sensitive data. Sensitive data is identified within the user-entered input sequence using the user-defined criteria. The identified sensitive data is provided to the requesting agent in response to the request for sensitive data. | 2011-05-19 |
20110119497 | SMART CARD AND ACCESS METHOD THEREOF - A smart card and an access method thereof for use with a smart card management system are provided. The smart card management system comprises a smart card access apparatus and a card server. The smart card access apparatus is electrically connected to the smart card. The smart card is configured to store a plurality of application data and management information corresponding to the application data. The smart card access apparatus may transmit a modification signal of a user to the smart card. The smart card may modify the management information according to the modification signal to generate modified management information when the smart card access apparatus is disconnected from the card serve. Therefore, the contents of the smart card may be managed when the smart card access apparatus is disconnected from the card server. | 2011-05-19 |
20110119498 | IMPLEMENTING DATA CONFIDENTIALITY AND INTEGRITY OF SHINGLED WRITTEN DATA - A method, apparatus and a data storage device are provided for implementing data confidentiality and integrity of data stored in overlapping, shingled data tracks on a recordable surface of a storage device. A unique write counter is stored for each zone written to the recordable surface of the storage device. An encryption key is used together with the write counter information and a logical block address to encrypt each sector being written, and to decrypt all sectors being read. An individual sector is decrypted, obtaining the write counter information and reading the data sector. A message authentication code is stored for each zone. All sectors of the zone are read to perform integrity check on a sector. | 2011-05-19 |
20110119499 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR THE SAME, PROGRAM AND STORAGE MEDIUM - An information processing apparatus that generates private information used as one of an encryption key for encrypting data or a generation key for generating falsification detection information used in detecting falsification of data, comprises a storage unit adapted to prestore key information, an input unit adapted to input calculation target information, a calculating unit adapted to perform a calculation on targeted information based on the key information held in the storage unit, a detecting unit adapted to detect a predetermined event, and a control unit adapted, when triggered by detection of the event by the detecting unit, to perform controls to generate the private information by making the calculating unit perform the calculation with the input calculation target information as the targeted information, and to place the key information stored in the storage unit in an unusable state. | 2011-05-19 |
20110119500 | SAVING AND RETRIEVING DATA BASED ON PUBLIC KEY ENCRYPTION - In accordance with certain aspects, data is received from a calling program. Ciphertext that includes the data is generated, using public key encryption, in a manner that allows the data to be obtained from the ciphertext only if one or more conditions are satisfied. In accordance with another aspect, a bit string is received from a calling program. Data in the bit string is decrypted using public key decryption and returned to the calling program only if one or more conditions included in the bit string are satisfied. | 2011-05-19 |
20110119501 | SAVING AND RETRIEVING DATA BASED ON PUBLIC KEY ENCRYPTION - In accordance with certain aspects, data is received from a calling program. Ciphertext that includes the data is generated, using public key encryption, in a manner that allows the data to be obtained from the ciphertext only if one or more conditions are satisfied. In accordance with another aspect, a bit string is received from a calling program. Data in the bit string is decrypted using public key decryption and returned to the calling program only if one or more conditions included in the bit string are satisfied. | 2011-05-19 |
20110119502 | SAVING AND RETRIEVING DATA BASED ON PUBLIC KEY ENCRYPTION - In accordance with certain aspects, bound key operations on ciphertext and/or data are implemented. A bound key operation can receive both data to be signed and a bound key blob that is bound to one or more processors, recover a private key from the bound key blob, and generate a digital signature over the data using the private key. A bound key operation can alternatively receive both ciphertext and a bound key or bound key structure bound to one or more processors, recover or reconstruct a private key based on the bound key or bound key structure, and use the private key to generate plaintext corresponding to the ciphertext. | 2011-05-19 |
20110119503 | COPY-PROTECTED SOFTWARE CARTRIDGE - A cartridge preferably for use with a game console. The cartridge comprises a ROM, a non-volatile memory, a processor and an encryption unit. An application running on the console may read data from the ROM, read data from the non-volatile memory, and write data in the non-volatile memory. Data to be written in the non-volatile memory is encrypted by the encryption unit, but data to be read is returned in encrypted form for decryption by a decryption function of the game application. Data may also be received encrypted to be decrypted and returned. The encryption or decryption unit may also receive data from the non-volatile memory and send it to the interface. The invention improves on the prior art copy protection as a hacker must reverse engineer the game application in order to copy it, if the encryption unit is unknown. The invention also provides an optical medium equipped with a RFID circuit. | 2011-05-19 |
20110119504 | CONTENT PROTECTING METHOD, CONTENT REPRODUCING APPARATUS, AND PROGRAM - A content reproducing apparatus includes a viewing expiration time determining unit which determines lapse of a viewing expiration time, a decryption key temporary storage unit which temporarily stores a decryption key, a decryption key moving unit which moves the decryption key from a recording medium to the decryption key temporary storage unit and returns the decryption key onto the recording medium, and a content protection control unit which controls the movement and the return of the decryption key. The content protection control unit performs control to move, when a reproduction start instruction is received, the decryption key from the recording medium to the decryption key temporary storage unit, return, when the reproduction of the content ends, the decryption key onto the recording medium when the viewing expiration time has not lapsed, and not return the decryption key onto the recording medium if the viewing expiration time has lapsed. | 2011-05-19 |
20110119505 | SAVING AND RETRIEVING DATA BASED ON PUBLIC KEY ENCRYPTION - In accordance with certain aspects, data is received and a digital signature is generated and output. The digital signature can be a digital signature of the data and one or more conditions that are to be satisfied in order for the data to be revealed, or a digital signature over data generated using a private key associated with a bound key that is bound to one or more processors. | 2011-05-19 |
20110119506 | POWERED DEVICE - An exemplary powered device (PD) connected to a local power source and a power sourcing equipment (PSE) includes a constant current source drawing at least 10 mA direct current from the PSE when the local power source is in operation. The PD includes a first conversion circuit, a first diode, and a second diode. The first conversion circuit comprises a first input and is configured for converting a voltage input to the first input into the rated working voltage of the PD. The positive terminal of the first diode is connected to the local power source and the negative terminal thereof is connected to the first input. The voltage of the local power source is higher than that of the PSE. | 2011-05-19 |
20110119507 | SYSTEM AND METHOD FOR CONTROLLING BUS-NETWORKED DEVICES VIA AN OPEN FIELD BUS - A system for controlling bus-networked devices, the system including a gateway, an open field bus electrically connected to the gateway, and a first power supply unit electrically connected to the gateway and configured to supply primary power for the gateway and a plurality of bus subscribers. An auxiliary power supply unit is included configured to supply auxiliary power for the plurality of bus subscribers independent of bus functionality. A pluggable connection cable is included configured to electrically connect the gateway to the plurality of bus subscribers and configured to transmit the primary and the auxiliary power and at least one of control information and status information between the gateway and the plurality of bus subscribers. | 2011-05-19 |
20110119508 | Power Efficient Stack of Multicore Microprocessors - A computing system has a stack of microprocessor chips that are designed to work together in a multiprocessor system. The chips are interconnected with 3D through vias, or alternatively by compatible package carriers having the interconnections, while logically the chips in the stack are interconnected via specialized cache coherent interconnections. All of the chips in the stack use the same logical chip design, even though they can be easily personalized by setting specialized latches on the chips. One or more of the individual microprocessor chips utilized in the stack are implemented in a silicon process that is optimized for high performance while others are implemented in a silicon process that is optimized for power consumption i.e. for the best performance per Watt of electrical power consumed. The hypervisor or operating system controls the utilization of individual chips of a stack. | 2011-05-19 |
20110119509 | STORAGE SYSTEM HAVING POWER SAVING FUNCTION - A controller of a storage system associates a portion of the logical area of logical storage devices with one or more pool area of a pool. The frequency of I/O (Input/Output) of any of the portion of the logical areas is higher than the I/O frequency of the remaining logical areas of the logical storage devices. In the event of I/O, if a first physical storage device group which forms the basis of the physical storage devices is in a power saving state, then the controller performs I/O of a data element to/from the pool area corresponding to the logical area of the I/O destination, without canceling the power saving state of the first physical storage device group. | 2011-05-19 |
20110119510 | APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION IN PORTABLE TERMINAL - An apparatus and method for reducing power consumption in a portable terminal are provided. The apparatus includes a mode manager for, if determining data reception before sleep mode entry, processing to convert a state of a controller into a wakeup state and to complete the data reception and, if determining data non-reception before the sleep mode entry, converting a state of the controller into a sleep state at the same time as the sleep mode entry. | 2011-05-19 |
20110119511 | SYSTEM FOR MANAGING POWER OF PERIPHERAL COMMUNICATIONS BY AUTOMATICALLY CLOSING COMMUNICATIONS CHANNEL IMMEDIATELY AFTER FINISHING A COMMUNICATION WITH A PERIPHERAL DEVICE - An improved method and apparatus manages communications port contention and power consumption for a handheld computer, particularly handheld computers with a communications protocol that boosts power consumption when active, such as an RS-232 protocol. The improved method provides communications channel management that automatically opens the communications channel in response to a wake-up signal sent to a handheld computer from a peripheral device. The computer peripheral device is explicitly and/or implicitly identified. The opened communications channel is closed in response to receiving some data from the peripheral device, and/or after a device timeout expires without the handheld computer receiving data from the computer peripheral device. | 2011-05-19 |
20110119512 | METHOD AND APPARATUS FOR WAKING UP A SLEEPING SYSTEM - One embodiment of the present invention provides a system that wakes up a sleeping target system located on a target LAN (Local Area Network) from a remote system located on a remote LAN. Because the sleeping target system is in a sleep state, it receives packets of a lower-layer protocol which cannot be used by the remote system to directly send packets to the sleeping target system. During operation, the remote system creates a wake-up packet. The remote system then uses a second protocol to send the wake-up packet to a relay agent located on the target LAN. Upon receiving the first wake-up packet, the relay agent uses the lower-layer protocol to send a second wake-up packet to the sleeping target system, which causes the sleeping target system to wake up. | 2011-05-19 |
20110119513 | SEENSORLESS DIGITAL AVP IMPLEMENTATION FOR VOLTAGE REGULATORS - A voltage regulator may include a voltage converter to generate an output voltage based on an input voltage and a control signal. The voltage regulator may also include a control loop to adjust the control signal based on a magnitude of an error between a digital representation of the output voltage and an adaptive digital reference voltage. Additionally, the voltage regulator can have adaptive voltage positioning logic to modify the adaptive digital reference voltage based on the magnitude of the error. | 2011-05-19 |
20110119514 | POWER CONTROL APPARATUS AND METHOD FOR CLUSTER SYSTEM - A power control apparatus for a cluster system, includes a cluster including a plurality of nodes, each equipped with a battery; and a power control unit connected to the cluster over a network and configured to monitor power management information and performance information of the cluster and to set a power capping threshold based on the monitored power management information and performance information of the cluster. Accordingly, the power control unit enables power of the cluster to be limited by turning on and off the batteries when power of the cluster system increases up to the power capping threshold. | 2011-05-19 |
20110119515 | Power Monitoring and Control System - A power monitoring system is disclosed which enables monitoring of power consumption and optionally control of power delivery. An embodiment of the power monitoring system includes a client device and a server device. The client device includes a power meter, a client-side microcontroller, and a client-side communication transceiver, for transacting with other clients or servers. The client-side microcontroller reads power usage statistics from the power meter and transmits them to the server device. The server device includes a server-side microcontroller that receives the power usage statistics from the client device. Some embodiments of the server-side microcontroller include a LAN/WAN interface, for public or private network access, and a software application that reports the power usage, and offers control opportunities to users on those networks. | 2011-05-19 |
20110119516 | Power control device - A power control device coupled to a power supply device and an information processing device, and configured to control a power supply from the power supply device to the information processing device, the power control device including: a first input/output unit configured to input/output data from/to the information processing device; a second input/output unit configured to input/output data from/to the power supply device by a change of state of signal lines; a storage unit configured to store data input from the first input/output unit and the second input/output unit; and a control unit configured to execute a conversion process for converting data input from the first input/output unit to a change of state of a signal line that can be output from the second input/output unit, and converting a change of state of a signal line input from the second input/output unit to a data format that can be output from the first input/output unit. | 2011-05-19 |
20110119517 | Systems and Methods for Classifying Power Network Failures - Systems and methods for classifying a possible failure in a power network are provided. In one embodiment, a method may include receiving network device status information for multiple network devices in communication with a communications network and capable of receiving primary power from a power network; and determining that a possible power network failure exists based on a first portion of the network devices associated with an inactive status and a second portion of the network devices associated with an active status, wherein the first portion comprises network devices without battery back-up capabilities and the second portion comprises network devices with battery back-up capabilities. | 2011-05-19 |
20110119518 | METHOD FOR PROVIDING A GUARANTEED PLAYOUT RATE - A method for delivering data to first and second processes comprising: identifying a first process communicatively connected to a first data access port; identifying a second process communicatively connected to a second data access port; identifying a data-throughput requirement of the first process via the first data access port; identifying a current data-throughput being delivered to the first process via the first data access port; identifying a data-throughput difference representing a difference between the data-throughput requirement of the first process and the current data-throughput being delivered to the first process; and delivering data to the first process via the first data access port at a rate that meets the data-throughput requirement at an expense, if necessary, of a data rate delivered to the second process via the second data access port. | 2011-05-19 |
20110119519 | METHOD AND APPARATUS FOR PROVIDING SYMMETRICAL OUTPUT DATA FOR A DOUBLE DATA RATE DRAM - An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal. | 2011-05-19 |
20110119520 | Hardware Function Generator Support in a DSP - The present invention relates to digital signal processors with an integrated module configured to compute a Coordinate Rotation Digital Computer (CORDIC) in a pipeline. The pipelined module can advantageously complete computation of one CORDIC computation for each clock pulse applied to the CORDIC module, thereby providing a CORDIC computation for each clock pulse. One embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a CORDIC algorithm. Advantageously, data in a CORDIC pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline. This allows information to be retrieved from the CORDIC pipeline with relatively little overhead. The automatic starting and stopping of the CORDIC pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as-needed basis. | 2011-05-19 |
20110119521 | REPRODUCIBILITY IN A MULTIPROCESSOR SYSTEM - Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state. | 2011-05-19 |
20110119522 | ELECTRONIC DEVICE WITH REDUCED POWER CONSUMPTION IN EXTERNAL MEMORY - An electronic device for data processing is disclosed having a CPU ( | 2011-05-19 |
20110119523 | ADAPTIVE REMOTE DECISION MAKING UNDER QUALITY OF INFORMATION REQUIREMENTS - A system and method for adaptive remote decision making includes steps of: receiving from an application layer a target range for a level of reporting quality for processed data; setting data collection parameters to meet the target range; collecting the data from a plurality of remote data collecting devices deployed in the distributed computing system, a portion of said data being compromised during the collecting process; processing the collected data to produce the processed data; evaluating the processed data based on observable metrics of current collected data and reported data losses; forecasting an expected reporting quality while continuing to collect the data; comparing the expected reporting quality with the target range; and reporting the processed data when the expected reporting quality falls within the target range for the level of reporting quality. | 2011-05-19 |
20110119524 | Maintaining Communication Continuity - A computer program product includes a computer usable memory, storage medium or physical medium having computer usable program code embodied therewith, the computer usable program code including: | 2011-05-19 |
20110119525 | CHECKPOINTING IN MASSIVELY PARALLEL PROCESSING - One embodiment is a method that performs a local checkpoint at a processing node in a massively parallel processing (MPP) system that executes a workload with a plurality of processing nodes. The local checkpoint is stored in local memory of the processing node. While the workload continues to execute, a global checkpoint is performed from the local checkpoint stored in the local memory. | 2011-05-19 |
20110119526 | LOCAL ROLLBACK FOR FAULT-TOLERANCE IN PARALLEL COMPUTING SYSTEMS - A control logic device performs a local rollback in a parallel super computing system. The super computing system includes at least one cache memory device. The control logic device determines a local rollback interval. The control logic device runs at least one instruction in the local rollback interval. The control logic device evaluates whether an unrecoverable condition occurs while running the at least one instruction during the local rollback interval. The control logic device checks whether an error occurs during the local rollback. The control logic device restarts the local rollback interval if the error occurs and the unrecoverable condition does not occur during the local rollback interval. | 2011-05-19 |
20110119527 | STORAGE CONTROL SYSTEM AND STORAGE CONTROL METHOD - Unique information including a logical type name is stored in a user data area of a management area as a media of the alternative disk drive to become an alternative of the storage device. Upon using the alternative disk drive, a disk controller reads the unique information of the alternative disk drive, and determines that copy back is unnecessary when the rotating speed and capacity belonging to the unique information of the alternative disk drive are the same as the rotating speed and capacity of the failed disk drive belonging to RAID, and otherwise determines that copy back is necessary. | 2011-05-19 |
20110119528 | HARDWARE TRANSACTIONAL MEMORY ACCELERATION THROUGH MULTIPLE FAILURE RECOVERY - The described embodiments provide a processor (e.g., processor | 2011-05-19 |
20110119529 | VIRTUAL HARD DISK DRIVE - A virtual hard disk drive includes at least one test transmission interface and a processing unit, wherein the test transmission interface is used for electrically connecting with the processing unit. The test transmission interface can electrically connect with a transmission interface under test of a computer. The processing unit includes an obtaining module and a simulation module. When an access instruction is received through the test transmission interface from the transmission interface under test of the computer, the obtaining module obtains a number of accessed blocks from the access instruction. The simulation module simulates a step of accessing a set of accessed data with the number of accessed blocks with respect to the transmission interface under test via the test transmission interface. | 2011-05-19 |
20110119530 | SERVICE MODELING IMPACT ANALYSIS - A computer system includes a plurality of computer processor dependent nodes and a plurality of computer processor antecedent nodes. Each node includes a severity value relating to an operational state of the node. A dependent node and an antecedent node pair include a significance value relating to a criticality that the antecedent node has to its paired dependent node. The antecedent node comprises a relevance value, wherein the relevance value is a function of the severity value of the antecedent node and the significance value for the antecedent node and the dependent node. The relevance value is used to determine an impact that the antecedent node has on the paired dependent node. | 2011-05-19 |
20110119531 | Architecture, System And Method For Compressing Repair Data In An Integrated Circuit (IC) Design - Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances. | 2011-05-19 |
20110119532 | METHOD OF DETECTING A FAULT ATTACK - A method of detecting a fault attack including generating a first signature of a first group of data values by performing a single commutative non-Boolean arithmetic operation between all the data values of the first group; generating a second set of data values by performing a permutation of the first set of data values; generating a second signature of the second group of data values by performing said single commutative non-Boolean arithmetic operation between all the data values of the second group; and comparing the first and second signatures to detect a fault attack. | 2011-05-19 |
20110119533 | PROGRAM TRACE MESSAGE GENERATION FOR PAGE CROSSING EVENTS FOR DEBUG - A data processing system has a trace message filtering circuit. A method includes: receiving a current page address corresponding to a current instruction in a sequence of instructions; determining that the current page address is for a different page of memory than a previous page address corresponding to a previous instruction in the sequence of instructions; comparing the current page address with a plurality of page addresses stored in a message filtering circuit; and when the current page address is determined to be different than any of the plurality of page addresses, storing the current page address in the message filtering circuit. | 2011-05-19 |