20th week of 2017 patent applcation highlights part 59 |
Patent application number | Title | Published |
20170141086 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns. | 2017-05-18 |
20170141087 | PACKAGED DEVICES WITH MULTIPLE PLANES OF EMBEDDED ELECTRONIC DEVICES - A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant. | 2017-05-18 |
20170141088 | THREE LAYER STACK STRUCTURE - Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level molding and fan out structure, and a second level molding and fan out structure between the first and third levels. The second level molding and fan out structure includes back-to-back facing die, with a front surface of each die bonded to a redistribution layer. | 2017-05-18 |
20170141089 | Power Semiconductor Arrangement Having a Plurality of Power Semiconductor Switching Elements and Reduced Inductance Asymmetry - A multiplicity of power semiconductor switching elements of the same type parallel have a load current terminal for a load current input and a load current terminal for a load current output. At least one outer load current terminal and at least one inner load current terminal per load current direction include a load current input and a load current output. At least one contacting device for common electrical contacting all of the load current terminals of the same load current direction includes a load current input and a load current output. The contacting device includes a plurality of terminal tongues which are respectively fastened on an associated load current terminal. The geometry and/or profile of the terminal tongue of an outer load current terminal differs from the geometry and/or profile of the terminal tongue of an inner load current terminal of the same contacting device, | 2017-05-18 |
20170141090 | SEMICONDUCTOR DEVICES FOR INTEGRATION WITH LIGHT EMITTING CHIPS AND MODULES THEREOF - A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad. | 2017-05-18 |
20170141091 | DISPLAY MODULE AND SYSTEM APPLICATIONS - A display module and system applications including a display module are described. The display module may include a display substrate including a front surface, a back surface, and a display area on the front surface. A plurality of interconnects extend through the display substrate from the front surface to the back surface. An array of light emitting diodes (LEDs) are in the display area and electrically connected with the plurality of interconnects, and one or more driver circuits are on the back surface of the display substrate. Exemplary system applications include wearable, rollable, and foldable displays. | 2017-05-18 |
20170141092 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump. | 2017-05-18 |
20170141093 | SEMICONDUCTOR APPARATUS INSTALLING PASSIVE DEVICE - A semiconductor apparatus that comprises a package, an active device, and a passive device is disclosed. The package includes a metal base, a shell, and a lid. The active device is mounted of the metal base. The passive device is soldered on the metal base. The passive device includes an insulating substrate with a rectangular outer shape and a bottom electrode with a plane shape reflecting the rectangular outer shape of the insulating substrate. The insulating substrate is made of material with brittleness greater than that of the metal base. A feature of the invention is that the bottom electrode has cut corners. | 2017-05-18 |
20170141094 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts. | 2017-05-18 |
20170141095 | Package with SoC and Integrated Memory - A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die. | 2017-05-18 |
20170141096 | PROXIMITY COUPLING OF INTERCONNECT PACKAGING SYSTEMS AND METHODS - Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad. | 2017-05-18 |
20170141097 | TVS Structures for High Surge AND Low Capacitance - A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type. | 2017-05-18 |
20170141098 | FinFET-Based ESD Devices and Methods for Forming the Same - A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material. | 2017-05-18 |
20170141099 | SEMICONDUCTOR DEVICE - Connection patterns of plural diodes include a first series connection pattern and a second series connection pattern. The first series connection pattern extends from an input terminal in the X direction. The second series connection pattern has a portion through which a current flows to approach the input terminal. The first series connection pattern includes a first diode, which is the first diode counted from the input terminal. The second series connection pattern includes a second diode, which is the last diode counted from the input terminal. The second diode is disposed separately from the first diode with some distance therebetween in the Y direction. An N-type region of the first diode and a P-type region of the second diode directly oppose each other as viewed in a planar direction. | 2017-05-18 |
20170141100 | ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION - Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads. | 2017-05-18 |
20170141101 | METHOD OF IMPROVING BIPOLAR DEVICE SIGNAL TO NOISE PERFORMANCE BY REDUCING THE EFFECT OF OXIDE INTERFACE TRAPPING CENTERS - An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base. | 2017-05-18 |
20170141102 | GATE STACK INTEGRATED METAL RESISTORS - Described herein are semiconductor devices and methods of forming the same. In some aspects, methods of forming a semiconductor device includes forming a gate stack having a self-aligning cap and a gate metal on a substrate, depositing a resist mask onto the semiconductor device, and patterning the resist mask such that the gate stack is exposed. Additionally, methods include removing the self-aligning cap and the gate metal from the exposed gate stack, depositing a resistor metal on the semiconductor device such that a metal resistor is formed within the exposed gate stack, and forming a bar contact and contact via above the metal resistor. | 2017-05-18 |
20170141103 | SEMICONDUCTOR DEVICE - An influence of a gate interference is suppressed and a reverse recovery property of a diode is improved. A diode includes a diode region located between the first boundary trench and the second boundary trench and a first and second IGBT regions. An emitter region and a body region are provided in each of the first and second IGBT regions. Each body region includes a body contact portion. An anode region is provided in the diode region. The anode region includes an anode contact portion. An interval between the first and second boundary trenches is equal to or longer than 200 μm. An area ratio of the anode contact portion in the diode region is lower than each of an area ratio of the body contact portion in the first IGBT region and an area ratio of the body contact portion in the second IGBT region. | 2017-05-18 |
20170141104 | METHOD AND STRUCTURE FOR SEMICONDUCTOR MID-END-OF-LINE (MEOL) PROCESS - A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes. | 2017-05-18 |
20170141105 | SEMICONDUCTOR DEVICE COMPRISING A FIRST TRANSISTOR AND A SECOND TRANSISTOR - A semiconductor device includes a first transistor and a second transistor in a semiconductor substrate. The first transistor includes a first drain contact electrically connected to a first drain region, the first drain contact including a first drain contact portion and a second drain contact portion. The first drain contact portion includes a drain conductive material in direct contact with the first drain region. The second transistor includes a second source contact electrically connected to a second source region. The second source contact includes a first source contact portion and a second source contact portion. The first source contact portion includes a source conductive material in direct contact with the second source region. | 2017-05-18 |
20170141106 | FIN FIELD EFFECT TRANSISTOR, SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators. | 2017-05-18 |
20170141107 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film. | 2017-05-18 |
20170141108 | FINFET ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a first semiconductor fin, a second semiconductor fin, an air gap and a dielectric cap layer. The first semiconductor fin is disposed on the semiconductor substrate, and the second semiconductor fin is disposed on the semiconductor substrate. The air gap is located between the first semiconductor fin and the second semiconductor fin, and the dielectric cap layer caps a top of the air gap. | 2017-05-18 |
20170141109 | SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET STANDARD CELLS - Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions. | 2017-05-18 |
20170141110 | DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME - Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact. | 2017-05-18 |
20170141111 | FINFET DEVICES AND METHODS OF FORMING THE SAME - FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates. | 2017-05-18 |
20170141112 | Multi-Gate Device and Method of Fabrication Thereof - A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer. | 2017-05-18 |
20170141113 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including a first active area extending in a first direction and a second active area extending in a second direction and connected to the first active area; first and second gate structures respectively crossing the first and second active areas; a first region in an area where the first and second active areas are connected to each other, the first region being on a first side of each of the first and second gate structures; a second region in the first active area on the other side of the first gate structure; and a third region formed in the second active area on the other side of the second gate structure. | 2017-05-18 |
20170141114 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper part of the first well region; a current suppression layer of the first conductivity type provided in a lower part of the semiconductor substrate immediately below the first well region, separated from the first well region; and an isolation region of the second conductivity type provided in an upper part of the semiconductor substrate, separated from the first well region, a reference potential being applied to the isolation region. The semiconductor substrate is the second conductivity type. | 2017-05-18 |
20170141115 | PRINTED CAPACITORS - A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of printed capacitors stacked on top of each other with an offset between each capacitor along at least one edge of the capacitors; and wherein each printed capacitor includes a plurality of electrically connected capacitors. Each printed capacitor of the plurality of printed capacitors can be a horizontal or a vertical capacitor. Each printed capacitor can include a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors | 2017-05-18 |
20170141116 | Multi-Die Fine Grain Integrated Voltage Regulation - A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used. | 2017-05-18 |
20170141117 | MEMORY DEVICE WITH MANUFACTURABLE CYLINDRICAL STORAGE NODE - A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer. | 2017-05-18 |
20170141118 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes a memory string including a plurality of memory cells connected in series with each other, and a select gate transistor connected to a first end of the memory string. The film thickness of a first hard mask on a select gate electrode of the select gate transistor is greater than the film thickness of a second hard mask film on a control gate electrode of the memory cells. The level of an upper surface of a first side wall insulating film provided on a side surface of the select gate transistor is higher than the level of an upper surface of the first hard mask film. The level of an upper surface of a second side wall insulating film provided on a side surface of the memory cells is higher than the level of an upper surface of the second hard mask film. | 2017-05-18 |
20170141119 | Integrated Structures and Methods of Forming Integrated Structures - Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed. | 2017-05-18 |
20170141120 | DISCRETE STORAGE ELEMENT FORMATION FOR THIN-FILM STORAGE DEVICE - Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor. | 2017-05-18 |
20170141121 | VERTICAL MEMORY BLOCKS AND RELATED DEVICES AND METHODS - Vertical memory blocks for semiconductor devices include a memory cell region including an array of memory cell pillars and at least one via region including a dielectric stack of alternating dielectric materials and at least one conductive via extending through the dielectric stack. Semiconductor devices including a vertical memory block include at least one vertical memory block, which includes slots extending between adjacent memory cells of a three-dimensional array. The slots are separated by a first distance in a first portion of the block, and by a second, greater distance in a second portion of the block. Methods of forming vertical memory blocks include forming slots separated by a first distance in a memory array region and by a second, greater distance in a via region. At least one conductive via is formed through a stack of alternating first and second dielectric materials in the via region. | 2017-05-18 |
20170141122 | A THREE-DIMENSIONAL MEMORY DEVICE - According to one embodiment, the plurality of contact vias extend in the stacking direction in the insulating layer, and are in contact with the end parts of the electrode layers. The plurality of second columnar parts extend in the stacking direction in the second stacked part, and include a plurality of second semiconductor bodies being different in length in the stacking direction. | 2017-05-18 |
20170141123 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a first semiconductor film including a first portion and a second portion; a first insulating film having a lower surface; and a second semiconductor film having a lower surface. The first portion is provided as one body inside the stacked body. The first portion has a first crystal structure different from a crystal structure of the substrate. The second portion is provided between the first portion and the substrate. The second portion contacts the substrate and has a second crystal structure different from the first crystal structure. | 2017-05-18 |
20170141124 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers stacked with an insulating layer interposed; a first semiconductor film; a first insulating film including a charge storage film; and a second semiconductor film. The first semiconductor film includes a first semiconductor portion and a second semiconductor portion. The first insulating film includes a first insulating unit having a lower surface contacting the second semiconductor portion, and a second insulating unit. The second semiconductor film includes a third semiconductor portion having a lower surface lower than a height of the lower surface of the first insulating unit, and a fourth semiconductor portion. | 2017-05-18 |
20170141125 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of manufacturing the semiconductor device which enable a hard copy of a reconfigurable circuit, which employs a resistance variable element, to be formed at low cost. The method of manufacturing a semiconductor device is for manufacturing a hard copy from a reconfigurable circuit chip that employs a resistance-variable non-volatile element formed inside a multi-layered wiring layer on a semiconductor substrate, wherein the hard copy is manufactured by using a semiconductor substrate base that is the same as that of the semiconductor substrate for forming the reconfigurable circuit chip. | 2017-05-18 |
20170141126 | Butted Body Contact for SOI Transistor - Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described. | 2017-05-18 |
20170141127 | METHOD FOR MANUFACTURING TFT SUBSTRATE AND STRUCTURE THEREOF - The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing the TFT substrate uses a connection semiconductor ( | 2017-05-18 |
20170141128 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire. | 2017-05-18 |
20170141129 | DISPLAY PANEL INCLUDING STATIC ELECTRICITY PREVENTING PATTERN AND DISPLAY DEVICE HAVING THE SAME - A display device comprising a display panel that includes an active area, the active area including a data line positioned on a substrate in a first direction and transferring a data signal, a gate line positioned on the substrate in a second direction and transferring a gate signal, a thin film transistor connected to the gate line and the data line, and a plurality of pixels driven by the thin film transistor, a first pad coupled to a first signal line disposed in a data signal area wherein the first signal line is connected to the data line, and a first non-signal line disposed in a first non-signal area wherein the first non-signal line is disconnected from the data line, the first non-signal area being disposed outside the data signal area, a second pad coupled to a second signal line disposed in a gate signal area wherein the second signal line is connected to the gate line, and a second non-signal line disposed in a second non-signal area wherein the second non-signal line is disconnected from the gate line, the second non-signal area being disposed outside the gate signal area; and a dummy pattern disposed between the data signal area and the first non-signal area, or disposed between the gate signal area and the second non-signal area. | 2017-05-18 |
20170141130 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a highly reliable semiconductor device that is suitable for miniaturization and an increase in density. The semiconductor device includes a first insulator over a substrate, a transistor including an oxide semiconductor over the first insulator, a second insulator over the transistor, and a third insulator over the second insulator. The first insulator and the third insulator have a barrier property with respect to oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor is enclosed with the first insulator and the third insulator that are in contact with each other in an edge of a region where the transistor is positioned. | 2017-05-18 |
20170141131 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a substrate, a semiconductor layer, a source electrode, a drain electrode, first insulating portion and second insulating portions. The semiconductor layer includes an oxide and is separated from the substrate in a first direction. The source electrode is electrically connected to the semiconductor layer. The drain electrode is electrically connected to the semiconductor layer and is arranged with the source electrode in a second direction crossing the first direction. The first insulating portion is provided between the substrate and the semiconductor layer. The semiconductor layer is provided between the first and second insulating portions. The first insulating portion includes a first silicon nitride layer, and a first aluminum oxide layer stacked with the first silicon nitride layer. The second insulating portion includes a second aluminum oxide layer, and a second silicon nitride layer stacked with the second aluminum oxide layer. | 2017-05-18 |
20170141132 | Pixel Unit and Method for Producing the Same, Array Substrate and Display Apparatus - The present disclosure provides a pixel unit and a method for producing the same, an array substrate and a display apparatus. The pixel unit includes: a thin film transistor; an insulation layer formed at least on a drain electrode of the thin film transistor and formed therein with a via hole which extends through the insulation layer to expose the drain electrode of the thin film transistor below the insulation layer; a pixel electrode formed on the insulation layer and electrically connected to the drain electrode of the thin film transistor at the via hole; and at least one elevating layer formed below the via hole and located below a part of the drain electrode exposed from the via hole such that the exposed part has a height greater than the height of the parts of the drain electrode adjacent to the exposed part. The depth and slope of the via hole is reduced by adding the elevating layer below the via hole. The elevating layer may be made from the gate metal layer and/or the active layer that are not etched off in process without increasing any production cost and process difficulty. | 2017-05-18 |
20170141133 | DISPLAY PANEL - A display panel is provided, which includes a first substrate, a first insulating layer on the first substrate, a semiconductor layer on the first insulating layer, and a second insulating layer on the semiconductor layer and the first insulating layer. The second insulating layer has a surface in contact with the first insulating layer. The second insulating layer has a first region. The first region has a thickness of 40 nm from the surface of the second insulating layer, and the second insulating layer has a fluoride ion gain ratio of 80% to 95% in the first region. | 2017-05-18 |
20170141134 | Butted Body Contact for SOI Transistor - Systems, methods, and apparatus for an improved body tie construction that produces all the benefits of conventional body tie (H-gate, T-gate), without the limitations and degradations associated with those constructions are described. The improved body tie construction is configured to have a lower resistance body tie when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. | 2017-05-18 |
20170141135 | CARRIER SUBSTRATE HAVING A PLURALITY OF FLUID PASSAGES AND METHOD OF FABRICATING DISPLAY APPARATUS UTILIZING THE SAME - The present application discloses a method of fabricating a display apparatus, comprising providing a carrier substrate comprising a base substrate and an adhesive layer over the base substrate, wherein the base substrate comprises a plurality of fluid passages between the base substrate and the adhesive layer, and a plurality of fluid inlets connected with the plurality of fluid passages; forming a product substrate on a side of the adhesive layer distal to the base substrate; dispensing a detaching agent through the plurality of fluid inlets to the plurality of fluid passages, and contacting the detaching agent with the adhesive layer through the plurality of fluid passages; and detaching the product substrate from the carrier substrate. | 2017-05-18 |
20170141136 | Display Module Manufacturing Method and Display Module - A display module substrate and a manufacturing method thereof are provided. The display module substrate includes a substrate body and a plurality of signal circuits. The substrate body has a supporting surface. The supporting surface includes a viewing area and a signal circuit area on one side of the viewing area. The signal circuits are disposed on the supporting surface and located at the signal circuit area. The signal circuit area has a plurality of apertures running through the substrate body, wherein the apertures are not shielded by the signal circuits. In a manufacturing thereof, the substrate body is disposed on a transparent carrier plate. When high-energy light is applied through the transparent carrier plate to etch a bottom surface of the substrate body to separate the substrate body and the transparent carrier plate, the resulting gas leaves through the apertures. | 2017-05-18 |
20170141137 | Manufacturing Method and Structure thereof of TFT Backplane - The disclosure provides a manufacturing method and a structure thereof of a TFT backplane. In the manufacturing method of the TFT backplane, after a polysilicon layer ( | 2017-05-18 |
20170141138 | LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME - An LTPS array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a source and a drain of the TFT on the polycrystalline silicon layer; forming a pixel electrode on the insulating layer and part of the source; forming a plain passivation layer on a source-drain electrode layer; forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is connected to the gate, the source, and the drain via the contact hole. The use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced. | 2017-05-18 |
20170141139 | LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME - An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole. The use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced. | 2017-05-18 |
20170141140 | MANUFACTURE METHOD OF DUAL GATE TFT SUBSTRATE AND STRUCTURE THEREOF - The present invention provides a manufacture method of a dual gate TFT substrate and a structure thereof. The manufacture method of a dual gate TFT substrate, comprises sequentially manufacturing a bottom gate ( | 2017-05-18 |
20170141141 | MANUFACTURE METHOD OF DUAL GATE OXIDE SEMICONDUCTOR TFT SUBSTRATE AND STRUCTURE THEREOF - The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer ( | 2017-05-18 |
20170141142 | OPTOELECTRONICS AND CMOS INTEGRATION ON GOI SUBSTRATE - A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device. | 2017-05-18 |
20170141143 | IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME - An image sensor includes a semiconductor substrate integrated with at least one of a first photo-sensing device that may sense a first wavelength spectrum of visible light and a second photo-sensing device that may sense second wavelength spectrum of visible light, and a third photo-sensing device on the semiconductor substrate that may selectively sense third wavelength spectrum of visible light in a longer wavelength spectrum of visible light than the first wavelength spectrum of visible light and the second wavelength spectrum of visible light. The first photo-sensing device and the second photo-sensing device may overlap with each other in a thickness direction of the semiconductor substrate. | 2017-05-18 |
20170141144 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - The present disclosure relates to a semiconductor device and an electronic apparatus capable of reducing a leak current of a PN junction region. In a Si substrate, an N+ region is formed in a P-type Well (P_Well region). A depletion layer is formed in the circumference of a boundary (metallurgic boundary of a PN junction) between the P_Well region and the N+ region. On the surface of the Si substrate, a fixed charge layer having positive fixed charge is formed on the N+ region to be spanned to the depletion layer. The present disclosure is applicable to a CMOS solid-state imaging device used in an imaging apparatus such as a camera. | 2017-05-18 |
20170141145 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor structure and a method for forming the same are provided. The image sensor structure includes a substrate having a front side and a backside and a light-sensing region formed in the substrate. The image sensor structure further includes a front side isolation structure formed at the front side of the substrate and a backside isolation structure formed at the back side of the substrate. | 2017-05-18 |
20170141146 | IMAGE SENSORS WITH IMPROVED SURFACE PLANARITY - A backside illuminated image sensor with an array of pixels formed in a substrate is provided. To improve surface planarity, bond pads formed at the periphery of the array of pixels may be recessed into a back surface of the substrate. The bond pads may be recessed into a semiconductor layer of the substrate, may be recessed into a window in the semiconductor layer, or may be recessed in a passivation layer and covered with non-conductive material such as resin. In order to further improve surface planarity, a window may be formed in the semiconductor layer at the periphery of the array of pixels, or scribe region, over alignment structures. By providing an image sensor with improved surface planarity, device yield and time-to-market may be improved, and window framing defects and microlens/color filter non-uniformity may be reduced. | 2017-05-18 |
20170141147 | HYBRID ANALOG-DIGITAL PIXEL IMPLEMENTED IN A STACKED CONFIGURATION - A hybrid analog-digital pixel circuit is fabricated on two wafers. A first wafer includes the analog pixel circuitry and a second wafer includes the digital control and processing circuitry. Externally accessible contact structures for electrically interconnecting the two wafers are arranged in groups. Each group includes externally accessible contact structures for carrying signals associated solely with operation of a corresponding pixel. | 2017-05-18 |
20170141148 | INFRARED IMAGE SENSOR COMPONENT AND MANUFACTURING METHOD THEREOF - An infrared image sensor component includes at least one III-V compound layer on the semiconductor substrate, in which the portion of the III-V compound layer(s) uncovered by the patterns is utilized as active pixel region for detecting the incident infrared ray. The infrared image sensor component includes at least one transistor coupled to the active pixel region, and charge generated by the active pixel region is transmitted to the transistor. | 2017-05-18 |
20170141149 | IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME - An electronic device may include at least one image sensor that includes a plurality of photo-sensing devices, a photoelectric device on one side of the semiconductor substrate and configured to selectively sense first visible light, and a plurality of color filters on separate photo-sensing devices. The plurality of color filters may include a first color filter configured to selectively transmit a second visible light that is different from the first visible light and a second color filter transmitting first mixed light including the second visible light. The electronic device may include multiple arrays of color filters. The electronic device may include different photoelectric devices on the separate arrays of color filters. The different photoelectric devices may be configured to sense different wavelength spectra of light. | 2017-05-18 |
20170141150 | COLOR SEPARATION ELEMENT ARRAY, IMAGE SENSOR INCLUDING THE COLOR SEPARATION ELEMENT ARRAY, AND IMAGE PICKUP APPARATUS INCLUDING THE COLOR SEPARATION ELEMENT ARRAY - A color separation element array includes color separation elements which are two-dimensionally arranged to separate an incident light according to a wavelength such that a light of a first wavelength is directed to a first direction and a light of a second wavelength that is different from the first wavelength is directed to a second direction that is different from the first direction. Each of the color separation elements includes a first element and a second element that are sequentially arranged along a traveling direction of the incident light, and the first element and the second element of the color separation elements are symmetrically shifted with respect to a center area of the color separation element array, to be aligned to fit to the traveling direction of the incident light that is obliquely incident. | 2017-05-18 |
20170141151 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE - The present disclosure relates to a solid-state imaging device capable of further decreasing reflectivity, a method of manufacturing the same, and an electronic device. | 2017-05-18 |
20170141152 | STACKED PHOTODIODE MULTISPECTRAL IMAGER - A photodiode architecture comprises first, second, and third independent photodiodes, and a shared electrode. The first, second, and third photodiodes are each connected to respective sources of bias voltage and to a common shared electrode, whereby the photodiode architecture comprises at least one of a shared anode and shared cathode photodiode architecture. The photodiode architecture selectively reverse biases the first, second, and third photodiodes so that, during operation, at least one of the first, second and third photodiodes is always operating in a photoconducting mode, to enable capture and storage of charge from any photodiode in the architecture operating in photoconducting mode. Advantageously, the first photodiode can be configured to respond to a first wavelength of light and at least one of the second and third is photodiodes can be configured to be responsive to a respective second or third wavelength of light shorter than the first wavelength of light. | 2017-05-18 |
20170141153 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) IMAGE SENSOR WITH SILICON AND SILICON GERMANIUM - A complementary metal-oxide-semiconductor (CMOS) image sensor with silicon and silicon germanium is provided. A silicon germanium layer abuts a silicon layer. A photodetector is arranged in the silicon germanium layer. A transistor is arranged on the silicon layer with a source/drain region that is buried in a surface of the silicon layer and that is electrically coupled to the photodetector. A method for manufacturing the CMOS image sensor is also provided. | 2017-05-18 |
20170141154 | LIGHT SOURCE MODULE AND DISPLAY APPARATUS HAVING THE SAME - A display apparatus may include a light source module that may include a substrate having a plurality of chip mounting areas of which each has a connection pad disposed therein, and a plurality of semiconductor light emitting devices electrically coupled to separate connection pads. The display apparatus may include a black matrix on the substrate and having a plurality of holes corresponding to the pattern of chip mounting areas. The semiconductor light emitting devices may be in separate, respective holes to be electrically coupled to separate connection pads. The display apparatus may include unit pixels, where each unit pixel includes multiple adjacent semiconductor light emitting devices. The semiconductor light emitting devices may be removably coupled to separate connection pads, and a semiconductor light emitting device may be interchangeably swapped from a connection pad. | 2017-05-18 |
20170141155 | REDUNDANCY IN INORGANIC LIGHT EMITTING DIODE DISPLAYS - Methods and apparatus for use in the manufacture of a display device including pixels. Each pixel includes a plurality of sub-pixels, each sub-pixel configured to provide light of a given wavelength. The method may include: performing, using a pick up tool (PUT), a first placement cycle comprising picking up first light emitting diode (LED) dies, and placing a first LED die on a substrate of the display device at a location corresponding to a sub-pixel the display device. The method further includes performing one or more subsequent placement cycles comprising picking up a second LED die, and placing the second LED die on the substrate of the display device at a second location corresponding to the sub-pixel of the display device. Multiple first and second LED dies may be picked and placed during each placement cycle to populate each pixel of the display device to provide redundancy of LED dies at each sub-pixel. | 2017-05-18 |
20170141156 | B2-MTJ DESIGN WITH TEXTURE BLOCKING DECOUPLING LAYER FOR SUB-25 NM STT-MRAM - A magnetic tunnel junction device and a method to make the device are disclosed. The magnetic tunnel junction device comprises a first reference magnetic material layer, a tunnel barrier material layer, a free magnetic material layer between the first reference magnetic material layer and the tunnel barrier material layer, and a second reference magnetic material layer disposed on an opposite side of the tunnel barrier material layer from the free magnetic material layer, in which the second reference magnetic material layer is anti-magnetically exchanged coupled with the first reference magnetic material layer. A shift field H | 2017-05-18 |
20170141157 | MAGNETIC STORAGE DEVICE - According to an embodiment, a magnetic storage device includes a semiconductor region including a trench; a gate electrode disposed in the trench; an insulation film covering the gate electrode and provided in a manner to fill the trench; and a magnetoresistive effect element including at least a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, the non-magnetic layer in a side surface of the magnetoresistive effect element including the non-magnetic layer being provided on a top surface of the insulation film. | 2017-05-18 |
20170141158 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a conductive nonmagnetic layer including a first terminal, a second terminal, and a region between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer disposed between the region and the first magnetic layer; and a nonmagnetic intermediate layer disposed between the first magnetic layer and the second magnetic layer; a transistor including a third terminal, a fourth terminal, and a control terminal, the third terminal being electrically connected to the first terminal; a first wiring electrically connected to the first magnetic layer and the fourth terminal; a second wiring electrically connected to the control terminal; and a third wiring electrically connected to the second terminal. | 2017-05-18 |
20170141159 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - Implementations of the disclosed technology provide an electronic device including a semiconductor memory and a method for fabricating the same, in which processes are easily performed and the characteristics of a variable resistance element are improved. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate; a conductive contact plug formed over the first conductive layer and including a stack of a conductive low-resistance structure and a conductive planarizing layer; and a variable resistance pattern coupled to the contact plug, wherein the low-resistance structure comprises a diffusion barrier layer, a low-resistance material layer and a gap-fill layer. | 2017-05-18 |
20170141160 | PROTECTIVE ELEMENTS FOR NON-VOLATILE MEMORY CELLS IN CROSSBAR ARRAYS - Protective elements are provided for non-volatile memory cells in crossbar arrays in which each memristor is situated at a crosspoint of the array. Each memristor is provided with a protective element. The protective element includes a layer of a first oxide that upon heating converts to a second oxide having a higher resistivity than the first oxide. | 2017-05-18 |
20170141161 | NON-VOLATILE MEMORY DEVICE CONTAINING OXYGEN-SCAVENGING MATERIAL PORTIONS AND METHOD OF MAKING THEREOF - A middle electrode can be inserted at each intersection between a non-volatile memory element layer located on an electrically conductive word line and a non-linear element located on an electrically conductive bit line in a three-dimensional memory device. An oxygen-scavenging material portion can be provided between each electrically conductive word line and an adjoining insulator layer to scavenge oxygen from contacting portions of the non-volatile memory element layer, thereby forming an oxygen-scavenged non-volatile memory element portion that facilitates programming. The middle electrode and the oxygen-scavenged non-linear memory element portion can alter the programming characteristics of the non-volatile memory cells to provide easier and more reliable programming. | 2017-05-18 |
20170141162 | DISPLAY PANEL AND APPARATUS INCLUDING THE SAME - A display panel for simplifying a manufacturing process and having high energy efficiency using an OLED as a light source and also using RGB, QDs, and an LPR layer capable of improving color reproducibility. In an aspect, an LPR layer is interposed between a color filter layer and a fluorescent substance layer so that light is circulated within the fluorescent substance layer again. Accordingly, there is provided a display panel capable of reducing the amount of light absorbed through the color filler by increasing the light absorption coefficient of the fluorescent substance layer and of maximizing energy efficiency by increasing the intensity of light passing through the color filter. | 2017-05-18 |
20170141163 | DISPLAY DEVICE AND MANUFACTURE METHOD THEREOF - The present disclosure provides a display device and a manufacture method thereof. The pixel definition layer includes a plurality of openings. The organic light emitting layer includes an opening region of the transparent conductive layer and a non-opening region of the transparent conductive layer. The opening region of the transparent conductive layer + disposed in the plurality of openings of the pixel definition layer. The organic light emitting layer being formed over the opening region of the transparent conductive layer to correspondingly form the plurality of sub-pixels. A three-dimensional recess is disposed in the substrate module below at least one of the color sub-pixels, each three-dimensional recess corresponds to one of the openings. The opening region of the transparent conductive layer and the organic light emitting layer are disposed in the three-dimensional recess. | 2017-05-18 |
20170141164 | DISPLAY DEVICE, MANUFACTURING METHOD AND DISPLAY APPARATUS - The present disclosure provides a method for manufacturing a display device and a display apparatus. The display device includes a substrate including a display region, a driving circuit formed at a vicinity of the display region, a passivation layer covering the driving circuit and including a contact hole exposing the driving circuit, a first conductive layer covering the passivation layer and contacting the driving circuit through the contact hole, and a display element formed in the display region and including a first electrode layer extending from the display region to the driving circuit. The first electrode layer is electrically connected to the driving circuit through the first conductive layer. According to the display device and the manufacturing method thereof, a distance between the packaging region and the display region is shortened, so as to narrow the width of the bezel and realize a narrow bezel structure. | 2017-05-18 |
20170141165 | OLED DISPLAY DEVICE - The present invention provides an OLED display device, which includes: a substrate ( | 2017-05-18 |
20170141166 | METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - A method of manufacturing an organic light-emitting apparatus includes: disposing a pixel electrode on a substrate in a display region; disposing a pixel defining layer covering the pixel electrode; exposing the pixel electrode by forming an opening in the pixel defining layer; and ashing residue of the pixel defining layer by using a laser, the residue remaining on the exposed pixel electrode in the opening. | 2017-05-18 |
20170141167 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE - There is provided a display device including a plurality of pixels, a bank layer located at boundaries among the plurality of pixels and separating each of the plurality of pixels, lower electrodes respectively provided in the plurality of pixels, a light emitting layer arranged on at least a lower electrode of the lower electrodes, and an upper electrode arranged on the light emitting layer, in which the light emitting layer has a first surface opposing the lower electrode, a second surface located on an opposite side of the light emitting layer from the first surface, and a side surface intersecting the first surface and the second surface, and the bank layer is located on an opposite side of the light emitting layer from the lower electrode and covers a part of the second surface and the side surface of the light emitting layer. | 2017-05-18 |
20170141168 | FLEXIBLE DISPLAY DEVICE - A flexible display apparatus includes a flexible display panel configured to wind around a winding axis unit, and a cushion unit arranged on the flexible display panel, wherein the cushion unit is arranged on a surface of the flexible display panel facing a circumferential surface of the winding axis unit. | 2017-05-18 |
20170141169 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus is provided as follows. A thin film transistor is disposed on a substrate. A first insulating layer covers the thin film transistor. The first insulating layer includes a barrier wall and a flat portion. The barrier wall protrudes from the flat portion. A pixel electrode is disposed on the flat portion surrounded by the barrier wall. The pixel electrode is electrically connected to the thin film transistor. A pixel defining layer is disposed on the pixel electrode and partially exposes the pixel electrode. | 2017-05-18 |
20170141170 | Light-Emitting Element and Display Device Using Same - A display device includes plurality of light-emitting elements aligned on a TFT substrate in a formation of a matrix. The plurality of light-emitting elements each have a flat surface portion and including a light-emitting layer, an anode, and a cathode, an insulating layer formed on the TFT substrate and under the light emitting element, and a tilted metal surface provided on a peripheral area surrounding the flat surface portion of the light-emitting element and having a tilt angle with respect to the flat surface portion of the light-emitting element. The tilted metal surface is provided on a surface of a slope of a bank that is provided on the insulation layer, and a width of a cross-section of the bank becomes smaller as the cross section comes farther away from a surface of the TFT substrate. A counter substrate is placed on the TFT substrate. | 2017-05-18 |
20170141171 | ELECTRICAL DEVICE TO MASK SYSTEMATIC LUMINANCE VARIATION - An electrical device containing pixel circuits, where at least one resistor is present within one pixel circuit to mask systematic luminance variation in organic light emitting diodes. The resistor can be located at one or more locations between electrodes. Each resistor has a defined resistor density, with distinct resistor values among pixel circuits to produce random variations in pixel luminance across a display containing plurality of pixel circuits. | 2017-05-18 |
20170141172 | ORGANIC LIGHT-EMITTING DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light-emitting display that includes a substrate comprising a pixel area, a thin film transistor arranged within the pixel area, a wiring electrically connected to the a thin film transistor, an insulating layer covering the thin film transistor and the wiring, a pixel electrode arranged over the insulating layer, a pixel-defining layer having an opening that exposes the pixel electrode, an opposite electrode facing the pixel electrode and an organic emission layer interposed between the pixel electrode and the opposite electrode, the insulating layer having a first region that is overlapped by the pixel electrode and a second region that is not overlapped by the pixel electrode, the second region being thicker than the first region to reduce parasitic capacitance between the opposite electrode and the wiring. | 2017-05-18 |
20170141173 | FOLDABLE DISPLAY APPARATUS - A foldable display apparatus includes: a first flexible panel and a second flexible panel, the first and second flexible panels being separate from each other; a first case supporting the first flexible panel and a second case supporting the second flexible panel; and a link member foldably connecting the first and second cases, and adjacent boundary regions of the first and second flexible panels are curved. | 2017-05-18 |
20170141174 | DISPLAY APPARATUS, MANUFACTURING METHOD OF DISPLAY APPARATUS, AND ELECTRONIC DEVICE - A display apparatus including: a display region provided with a plurality of pixel portions; wires installed to the respective pixel portions within the display region from an outside of the display region for transmitting a signal to drive the respective pixel portions; connection pads provided on the outside of the display region and serving as input portions to provide the wires with a signal while electrically conducting with the wires; switch elements provided on the outside of the display region in a middle of the wires; and a light shielding covering portion shielding the switch elements from light and formed to cover the connection pads while electrically conducting with the connection pads. | 2017-05-18 |
20170141175 | DISPLAY DEVICE AND A MANUFACTURING METHOD THEREOF - A display device includes a substrate, first through fourth metal wires, first and second insulating layers, and a compensation pattern. The first metal wire is positioned on the substrate and extends in a first direction. The first insulating layer is positioned on the first metal wire and the substrate. The second metal wire is positioned on the first insulating layer, extends in the first direction, and is adjacent to the first metal wire. The second insulating layer is positioned on the first insulating layer and the second metal wire. The compensation pattern is positioned on the second insulating layer and is disposed between the first metal wire and the second metal wire. The third metal wire and the fourth metal wire are positioned on the second insulating layer and extend in a second direction that is different from the first direction. | 2017-05-18 |
20170141176 | Organic Light Emitting Display Device and Method of Manufacturing the Same - An organic light emitting display device is disclosed that includes a substrate including an active area and a pad area; a thin-film transistor (TFT) including a drain electrode, a source electrode, and a gate electrode; an anode electrode; an organic emitting layer; a cathode electrode; and a pad area of the substrate provided with a signal pad that is in a same layer as the drain electrode and the source electrode, the pad area including a first pad electrode on the signal pad, and a second pad electrode on the first pad electrode. | 2017-05-18 |
20170141177 | DISPLAY DEVICE - A display device is disclosed. In one aspect, the device includes a plurality of pixels arranged in rows and columns, each pixel including a transistor that includes first and second electrodes in a column direction, and a channel curved between the first and second electrodes, and a capacitor overlapping the transistor. The device also includes a first data line connected to at least one first pixel in an odd row of the pixels arranged in the columns, and overlapping a first electrode of a transistor of the first pixel and a second data line connected to at least one second pixel in an even row of the pixels arranged in the columns, and overlapping a first electrode of a transistor of the second pixel. The first and second data lines are arranged in the columns and are parallel to one another. | 2017-05-18 |
20170141178 | DISPLAY DEVICE AND SEMICONDUCTOR DEVICE - An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased. | 2017-05-18 |
20170141179 | FLEXIBLE DISPLAY APPARATUS - A flexible display apparatus includes: a flexible substrate including a bending area and a non-bending area; and a wiring line extending across the bending area. The bending area is configured to bend along a bending axis, and a portion of the wiring line at the bending area includes a plurality of recessed portions recessed in a width direction of the wiring line. | 2017-05-18 |
20170141180 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes a display portion that includes a plurality of pixels; common potential supply main wiring that is disposed so as to surround the display portion on an outside of the display portion; a common potential wiring layer that extends to a gap region between the plurality of pixels in the display portion and is electrically connected to the common potential supply main wiring; an organic film that is disposed to cover the plurality of pixels; and a common electrode film that covers the display portion and the common potential supply main wiring, and is disposed to be in contact with the common potential supply main wiring. The common potential wiring layer has a plurality of contact regions in the gap region and the common electrode film is in contact with the plurality of contact regions. | 2017-05-18 |
20170141181 | Display Device with Panel Test Circuit - The present patent application is related to the field of display devices, and provides a display device with panel test circuit the attenuation of data voltage signal could be reduced in the programs of testing pixel array. The display device comprises a plurality of first and second type of bonding pads located on the substrate and around periphery of the pixel array, and the panel test circuit has transistors, the transistors are disposed on the substrate and around periphery of the pixel array, a plurality of data lines of the pixel array are electrically connected with the second type of bonding pads one-to-one, and data detection signal applied to the first type of bonding pads is transmitted to the second type of bonding pads through the panel test circuit. | 2017-05-18 |
20170141182 | METAL-INSULATOR-METAL CAPACITOR FABRICATION WITH UNITARY SPUTTERING PROCESS - A metal-insulator-metal capacitor includes a bottom electrode comprising a nitride of a metal, an insulator disposed on the bottom electrode and comprising an oxide of the metal, and a top electrode disposed on the insulator and comprising a nitride of the metal. Optionally, the insulator further includes an oxynitride of the metal, at least a portion of the oxynitride being characterized by a progressive change in the ratio of oxygen to nitrogen over thickness. | 2017-05-18 |
20170141183 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING WITH A RESERVIOR CAPACITOR - A semiconductor integrated circuit device may include a through silicon via (TSV), a keep out zone and a plurality of dummy patterns. The TSV may be arranged in a selection region of a semiconductor substrate. The keep out zone may be configured to define a peripheral region of the TSV. The dummy patterns may be arranged in the keep out zone to receive a conductive signal. The dummy patterns may function as an electrode of a reservoir capacitor. | 2017-05-18 |
20170141184 | CAPACITORS - Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between adjacent wiring lines. The method further includes forming an air gap within spacing between the adjacent wiring lines by deposition of a capping material. The method further includes opening the air gap between selected adjacent wiring lines. The method further includes depositing conductive material within the opened air gap. | 2017-05-18 |
20170141185 | SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor structure and a method of fabricating thereof are provided. The method includes following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess. | 2017-05-18 |