20th week of 2017 patent applcation highlights part 57 |
Patent application number | Title | Published |
20170140886 | ROTATIONAL MOVEMENT DETECTION DEVICE - A rotational movement detection device includes a rotating member including a through hole passing therethrough from a first surface to a second surface opposite the first surface, the rotating member rotating around the through hole to generate a magnetic field around the rotating member, a rotation angle detection part that detects a rotation angle of the rotating member, a movement detection part that detects a movement along a rotational axis of the rotating member, and a holding part including a guide part and an arrangement part formed integrally therein, the guide part being inserted into the through hole to guide the rotation of the rotating member and to hold the rotating member, the arrangement part having thereon the movement detection part arranged facing a side surface of the rotating member. | 2017-05-18 |
20170140887 | PORT CONTROLLER WITH POWER CONTRACT NEGOTIATION CAPABILITY - At least some embodiments are directed to an electronic device port system comprising a first device configured to negotiate power supply contracts from a power source via a universal serial bus (USB) cable. The system also comprises a second device configured to negotiate power supply contracts from the power source via the USB cable when the first device is unable to negotiate power supply contracts from the power source. The second device is configured to activate a switch after the second device negotiates a power supply contract with the power source. The switch is configured to permit the provision of power from the power source to a battery system of the electronic device per the negotiated power supply contract. | 2017-05-18 |
20170140888 | Solenoid Current Control with Fault Detection, Override, and Shutdown Features - A DC solenoid coil current controller includes a rectifier, pulse width modulator, and power driver. The rectifier inputs an alternating current signal and a direct current signal, and outputs a rectified signal using at least one of the alternating current signal and the direct current signal. The pulse width modulator outputs a pulse width modulated signal in response to the rectified signal. The power driver controls a DC solenoid coil using the pulse width modulated signal, thereby enabling a direct current DC solenoid coil to be controlled in response to the alternating current signal. A method of controlling current to a DC solenoid coil is also disclosed. | 2017-05-18 |
20170140889 | ELECTRICAL SWITCHING APPARATUS AND CLINCH JOINT ASSEMBLY THEREFOR - A movable contact assembly for an electrical switching apparatus is provided. The movable contact assembly includes a number of shunts, and, a carriage assembly including two sidewalls and a contact arm assembly. The carriage assembly sidewalls are disposed in a spaced relation. The contact arm assembly includes a plurality of contact arms, a number of isolation members, a number of movable contacts, and an axle. Each contact arm defines an opening, One movable contact is disposed on each contact arm. Each contact arm is rotatably coupled to the axle with the axle extending through the contact arm opening. Each isolation member is disposed adjacent at least one contact arm. Each isolation member is coupled to, and in electrical communication with the adjacent contact arm. The shunts are coupled to, and in electrical communication with, the isolation members. In this configuration, no shunt operatively engages a contact arm. | 2017-05-18 |
20170140890 | SAFETY SWITCH AND ASSOCIATED METHODS - A cable pull switch includes a polychotomous sensor configured to provide a reading of at least one of a plurality of values, the reading corresponding to a tension on a pull cable or a linear displacement of an end of a pull cable. A processing device is configured to receive the reading, determine whether a value of the reading is outside of a non-tripped value window, a limit edge being a pull threshold value, and responsively generate an output signal indicative of a cable pull event. Other features and improvements are described. | 2017-05-18 |
20170140891 | FUSE STRUCTURES AND FORMING AND OPERATION METHODS THEREOF - Fuse structures and forming and operation methods thereof are disclosed. One of the fuse structures includes a dielectric strip and a fuse strip extending in different directions. The dielectric strip is sandwiched by a first conductive strip and a second conductive strip. The fuse strip is insulated from each of the first conductive strip and the second conductive strip and has a blowing region corresponding to the dielectric strip. | 2017-05-18 |
20170140892 | TRAVELING WAVE TUBE AND HIGH-FREQUENCY CIRCUIT SYSTEM - Provided are a traveling wave tube and a high-frequency circuit system such that the product life span of the traveling wave tube operating in multiple modes can be extended while variations in gain and amplification efficiency that accompany switching of the operation modes can be suppressed. The traveling wave tube comprises: an electron gun equipped with a cathode that releases electrons, and a heater that provides the cathode with heat energy for releasing the electrons; a helix causing an RF signal to interact with an electron beam formed from the electrons released by the electron gun; a collector for catching the electron beam emitted by the helix; an anode whereby the electrons released from the electron gun are guided into the helix; and a magnetic field application device for generating a magnetic field in order to change the diameter of the electron beam, said magnetic field application device being supplied with electric power for generating the magnetic field from the outside. | 2017-05-18 |
20170140893 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF - The present application discloses an array substrate comprising a first substrate, a first electrode on the first substrate, a passivation layer on a side of the first electrode distal to the first substrate, the passivation layer comprising a plurality of first vias, each of which corresponds to a different part of the first electrode, an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias, and a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias. The at least one electron emission source comprises a first portion having a first end and a second portion having a second end. The first end is in contact with the first electrode, the first portion is within a corresponding one of the plurality of dielectric blocks. The second portion and the second end are outside the corresponding one of the plurality of dielectric blocks. | 2017-05-18 |
20170140894 | Device for generating a composition-controlled and intensity-controlled ionic flow and related method | 2017-05-18 |
20170140895 | LOW PROFILE EXTRACTION ELECTRODE ASSEMBLY - A low profile extraction electrode assembly including an insulator having a main body, a plurality of spaced apart mounting legs extending from a first face of the main body, a plurality of spaced apart mounting legs extending from a second face of the main body opposite the first face, the plurality of spaced apart mounting legs extending from the second face offset from the plurality of spaced apart mounting legs extending from the first face in a direction orthogonal to an axis of the main body, the low profile extraction electrode assembly further comprising a ground electrode fastened to the mounting legs extending from the first face, and a suppression electrode fastened to the mounting legs extending from the second face, wherein a tracking distance between the ground electrode and the suppression electrode is greater than a focal distance between the ground electrode and the suppression electrode. | 2017-05-18 |
20170140896 | Systems and Methods for Using Multimodal Imaging to Determine Structure and Atomic Composition of Specimens - An imaging system that selectively alternates a first, non-destructive imaging mode and a second, destructive imaging mode to analyze a specimen so as to determine an atomic structure and composition of the specimen is provided. The field ionization mode can be used to acquire first images of ionized atoms of an imaging gas present in a chamber having the specimen disposed therein, and the field evaporation mode can be used to acquire second images of ionized specimen atoms evaporated from a surface of the specimen with the imaging gas remaining in the chamber. The first and second image data can be analyzed in real time, during the specimen analysis, and results can be used to dynamically adjust operating parameters of the imaging system. | 2017-05-18 |
20170140897 | MICROSCOPY IMAGING METHOD AND SYSTEM - Notches or chevrons with known angles relative to each other are formed on a surface of the sample, where each branch of a chevron appears in a cross-sectional face of the sample as a distinct structure. Therefore, when imaging the cross-section face during the cross-sectioning operation, the distance between the identified structures allows unique identification of the position of the cross-section plane along the Z axis. Then a direct measurement of the actual position of each slice can be calculated, allowing for dynamic repositioning to account for drift in the plane of the sample and also dynamic adjustment of the forward advancement rate of the FIB to account for variations in the sample, microscope, microscope environment, etc. that contributes to drift. An additional result of this approach is the ability to dynamically calculate the actual thickness of each acquired slice as it is acquired. | 2017-05-18 |
20170140898 | ION GENERATOR AND METHOD OF CONTROLLING ION GENRATOR - An ion generator includes an ion source control unit that controls a gas supply unit and a plasma excitation source in accordance with a current ion source condition and a new ion source condition to be employed subsequent to the current ion source condition, a retention time obtaining unit that obtains retention time for the current ion source condition, and a pre-treatment condition setting unit that sets a pre-treatment condition defining a pre-treatment for forming a surface layer region suitable for the new ion source condition on a plasma chamber inner wall based on the current ion source condition, the retention time, and the new ion source condition. The ion source control unit is configured to control the gas supply unit and the plasma excitation source in accordance with the pre-treatment condition when the current ion source condition is changed to the new ion source condition. | 2017-05-18 |
20170140899 | Etching Method For A Structure Pattern Layer Having A First Material and Second Material - Provided is a method of plasma etching on a substrate using an etchant gas mixture to meet integration objectives, the method comprising: disposing a substrate having a structure pattern layer, a neutral layer, and an underlying layer, the structure pattern layer comprising a first material and a second material and the underlying layer comprising a silicon anti-reflective (SiARC) layer, a spin-on carbon hardmask (CHM) layer, an oxide layer, and a target layer; performing an first etch process to selectively remove the second material and the neutral layer using a first etchant gas mixture to form a first pattern; performing an second etch process to selectively remove the SiARC layer to form a second pattern; performing an third etch process to selectively remove the CHM layer to form a third pattern; concurrently controlling selected two or more operating variables wherein the first etchant gas include oxygen and sulfur-containing gases. | 2017-05-18 |
20170140900 | UNIFORM LOW ELECTRON TEMPERATURE PLASMA SOURCE WITH REDUCED WAFER CHARGING AND INDEPENDENT CONTROL OVER RADICAL COMPOSITION - To generate a plasma for processing a workpiece, an electron beam is introduced into a plasma reactor chamber by radial injection using an annular electron beam source distributed around the circular periphery of the chamber to provide azimuthal uniformity. The electron beam propagation path is tilted upwardly away from the workpiece, either by tilting the electron beam source or by a magnetic field. In other embodiments, there are plural opposing electron beams from linear electron beam sources directed toward the center of the plasma reactor chamber. | 2017-05-18 |
20170140901 | PNEUMATIC EXHAUST SYSTEM - An apparatus, for use in a processing chamber is provided. A pneumatic cylinder is provided. A manifold with a supply and an exhaust is controllably connected to the pneumatic cylinder. A dry gas supply is in fluid connection with and provides positive pressure to the exhaust of the manifold. | 2017-05-18 |
20170140902 | CORROSION-RESISTANT COMPONENTS AND METHODS OF MAKING - A corrosion-resistant component configured for use with a semiconductor processing reactor, the corrosion-resistant component comprising: a) a ceramic insulating substrate; and, b) a corrosion-resistant non-porous layer associated with the ceramic insulating substrate, the corrosion-resistant non-porous layer having a composition comprising at least 15% by weight of a rare earth compound based on total weight of the corrosion-resistant non-porous layer; and, the corrosion-resistant non-porous layer characterized by a microstructure substantially devoid of microcracks and fissures, and having an average grain size of at least about 100 nm and at most about 100 μm. Assemblies including corrosion-resistant components and methods of making are also disclosed. | 2017-05-18 |
20170140903 | METHOD OF PRODUCING PLASMA BY MULTIPLE-PHASE ALTERNATING OR PULSED ELECTRICAL CURRENT - A method of producing a plasma is provided. The method includes providing at least three hollow cathodes, including a first hollow cathode, a second hollow cathode, and a third hollow cathode. Each hollow cathode has a plasma exit region. The method further includes providing a source of power capable of producing multiple output waves, including a first output wave, a second output wave, and a third output wave. The first output wave and the second output wave are out of phase, the second output wave and the third output wave are out of phase, and the first output wave and the third output wave are out of phase. Each hollow cathode is electrically connected to the source of power such that the first hollow cathode is electrically connected to the first output wave, the second hollow cathode is electrically connected to the second output wave, and the third hollow cathode is electrically connected to the third output wave. Electrical current flows between the at least three hollow cathodes that are out of electrical phase. A plasma is generated between the hollow cathodes. | 2017-05-18 |
20170140904 | PLASMA DEVICE DRIVEN BY MULTIPLE-PHASE ALTERNATING OR PULSED ELECTRICAL CURRENT - A plasma source is provided. The plasma source includes at least three hollow cathodes, including a first hollow cathode, a second hollow cathode, and a third hollow cathode, each hollow cathode having a plasma exit region. The plasma source includes a source of power capable of producing multiple output waves, including a first output wave, a second output wave, and a third output wave, wherein the first output wave and the second output wave are out of phase, the second output wave and the third output wave are out of phase, and the first output wave and the third output wave are out of phase. Each hollow cathode is electrically connected to the source of power such that the first hollow cathode is electrically connected to the first output wave, the second hollow cathode is electrically connected to the second output wave, and the third hollow cathode is electrically connected to the third output wave. Electrical current flows between the at least three hollow cathodes that are out of electrical phase. The plasma source is capable of generating a plasma between the hollow cathodes. | 2017-05-18 |
20170140905 | ADVANCED OPTICAL SENSOR AND METHOD FOR PLASMA CHAMBER - An advanced optical sensor and method for detection of optical events in a plasma processing system. The method includes detecting at least one light emission signal in a plasma processing chamber. The at least one detected light emission signal including light emissions from an optical event. The method further includes processing the at least one light emission signal and detecting a signature of the optical event from the processed light emission signal. | 2017-05-18 |
20170140906 | COOLING WATER JET PACK FOR HIGH POWER ROTARY CATHODES - A sputtering target assembly, including a cylindrical backing tube, a magnet assembly disposed within the backing tube, and a conduit disposed within the backing tube and adapted for transporting coolant. The conduit includes at least one first opening positioned for providing the coolant in a substantially circumferential direction from the conduit toward an inner surface of the backing tube into a gap volume between a front side of the magnet assembly and the inner surface of the backing tube. | 2017-05-18 |
20170140907 | SPUTTERING APPARATUS AND PROCESSING APPARATUS - A sputtering apparatus includes a space defining member defining a sputtering space for forming a film on a substrate. The space defining member includes a concave portion, and an opening portion is provided in the bottom portion of the concave portion. The sputtering apparatus includes a shield member configured to shield the opening portion from the sputtering space. The opening portion is formed so that a pressure gauge capable of measuring the pressure in the sputtering space can be attached, and the shield member is arranged so that at least a part of the shield member is buried in the concave portion. | 2017-05-18 |
20170140908 | Ion Mobility Spectrometry Data Directed Acquisition - A method of analysing ions, comprising performing an initial multidimensional survey scan comprising separating parent ions according to a first physico-chemical property and separating said parent ions according to a second physico-chemical property, producing a two-dimensional data set comprising data corresponding to said first physico-chemical property and data corresponding to said second physico-chemical property, identifying one or more target ion species of interest and determining a mode of operation of a mass spectrometer for said target ion species of interest using data relating to said target ion species of interest in said two-dimensional data set, wherein said mode of operation comprises the location of fragmentation of said target ions of interest. | 2017-05-18 |
20170140909 | MS/MS MASS SPECTROMETRIC METHOD AND MS/MS MASS SPECTROMETER - When, in performing MS/MS analysis on a multivalent ion originated from a target component, an analyzing operator inputs at least two values of a mass value m | 2017-05-18 |
20170140910 | Photo-Dissociation of Proteins and Peptides in a Mass Spectrometer - A method of mass spectrometry is disclosed comprising directing first photons from a laser onto ions located within a 2D or linear ion guide or ion trap. The frequency of the first photons is scanned and first photons and/or second photons emitted by the ions are detected. The ions are then mass analysed using a Time of Flight mass analyser. | 2017-05-18 |
20170140911 | DEVICE FOR MANIPULATING CHARGED PARTICLES - The present invention is concerned with a device for charged particle transportation and manipulation. Embodiments provide a capability of combining positively and negatively charged particles in a single transported packet. Embodiments contain an aggregate of electrodes arranged to form a channel for transportation of charged particles, as well as a source of power supply that provides supply voltage to be applied to the electrodes, the voltage to ensure creation, inside the said channel, of a non-uniform high-frequency electric field, the pseudopotential of which field has one or more local extrema along the length of the channel used for charged particle transportation, at least, within a certain interval of time, whereas, at least one of the said extrema of the pseudopotential is transposed with time, at least within a certain interval of time, at least within a part of the length of the channel used for charged particle transportation. | 2017-05-18 |
20170140912 | SYSTEMS AND METHODS FOR ANALYZING A SAMPLE FROM A SURFACE - The invention generally relates to systems and methods for analyzing a sample from a surface. In certain aspects, the invention provides systems that include a sample introduction member that has an inlet, an outlet, and an opening along a wall of the sample introduction member. The sample introduction member may be configured such that the opening couples with a surface that includes a sample in a manner in which molecules of the sample enter the sample introduction member via the opening and exit the sample introduction member via the outlet. A mass spectrometer is configured to receive the molecules of the sample. | 2017-05-18 |
20170140913 | STRONG FIELD PHOTOIONIZATION ION SOURCE FOR A MASS SPECTROMETER - An ion source for a mass spectrometer comprises: an evacuated chamber having an interior receiving a gaseous sample effluent stream; a source of light pulses of pulse width 150 femtoseconds or less; a window of the evacuated chamber through which the light pulses pass into the evacuated chamber interior; one or more mirrors within the evacuated chamber disposed such that the light pulses are reflected from each of the one or mirrors such that the reflected pulses are caused to focus at one or more focal regions within the effluent stream within the evacuated chamber interior; and a pair of electrodes disposed at opposite sides of the one or more focal regions. | 2017-05-18 |
20170140914 | ADDITION OF REACTIVE SPECIES TO ICP SOURCE IN A MASS SPECTROMETER - Disclosed is a method of inductively coupled plasma mass spectrometry (ICP-MS), comprising steps of introducing at least one sample comprising at least one sample species, and at least one reactive species, into an inductively coupled plasma source, such that at least one molecular adduct ion of the at least one reactive species and the at least one sample species is formed; transferring the at least one molecular adduct ion into a collision cell that is arranged between the inductively coupled plasma source and at least one mass analyzer, transferring the at least one molecular adduct ion, or a product thereof, into the at least one mass analyzer, and analyzing the mass of the at least one molecular adduct ion, or the product thereof, in the at least one mass analyzer. Also disclosed is a mass spectrometer that is adapted to perform the method. | 2017-05-18 |
20170140915 | SYSTEM AND METHOD FOR REDUCING THE SPACE CHARGE EFFECT IN A LINEAR ION TRAP - The present invention provides a system and a method for reducing the space charge effect in a linear ion trap. The system includes a linear ion trap, a first AC power supply, a second AC power supply, and a RF power supply. The linear ion trap includes four identical electrode rods, where two poles of the first AC power supply are respectively connected to two of the electrode rods, and two poles of the second AC power supply are respectively connected to the other two electrode rods. Two poles of the RF power supply are respectively connected to the first AC power supply and the second AC power supply. The first AC power supply and the second AC power supply provide sinusoidal AC signals. The present invention reduces the resolution decrease caused by the space charge effect, thereby improving analytical performance in mass spectroscopy. | 2017-05-18 |
20170140916 | Ion Trap with Spatially Extended Ion Trapping Region - A mass or mass to charge ratio selective ion trap is disclosed which directs ions into a small ejection region. A RF voltage acts to confine ions in a first (y) direction within the ion trap. A DC or RF voltage acts to confine ions in a second (x) direction. A quadratic DC potential well acts to confine ions in a third (z) direction within the ion trap. The profile of the quadratic DC potential well progressively varies along the second (x) direction. | 2017-05-18 |
20170140917 | MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An adhesion liquid is supplied onto a front side of a wafer having a disk-shape while a rinse liquid is discharged onto a backside of the wafer that is rotating. The rinse liquid is discharged to a position close to a rotational center of the wafer and a position close to an outer peripheral edge of the wafer. The rinse liquid reaches an outer peripheral end surface of the wafer, and thus adhesion of the adhesion liquid to the outer peripheral end surface is reduced. | 2017-05-18 |
20170140918 | ATOMIC LAYER DEPOSITION OF ANTIMONY OXIDE FILMS - Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl | 2017-05-18 |
20170140919 | ENHANCED DEFECT REDUCTION FOR HETEROEPITAXY BY SEED SHAPE ENGINEERING - A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region. | 2017-05-18 |
20170140920 | LOW VAPOR PRESSURE AEROSOL-ASSISTED CVD - Systems and methods for processing films on the surface of a substrate are described. The systems possess aerosol generators which form droplets from a condensed matter (liquid or solid) of one or more precursors. A carrier gas is flowed through the condensed matter and push the droplets toward a substrate placed in a substrate processing region. An inline pump connected with the aerosol generator can also be used to push the droplets towards the substrate. A direct current (DC) electric field is applied between two conducting plates configured to pass the droplets in-between. The size of the droplets is desirably reduced by application of the DC electric field. After passing through the DC electric field, the droplets pass into the substrate processing region and chemically react with the substrate to deposit or etch films. | 2017-05-18 |
20170140921 | METHOD OF REVERSE TONE PATTERNING - Methods of reversing the tone of a pattern having non-uniformly sized features. The methods include depositing a highly conformal hard mask layer over the patterned layer with a non-planar protective coating and etch schemes for minimizing critical dimension variations. | 2017-05-18 |
20170140922 | GENERATING METHOD, IMPRINTING METHOD, IMPRINT APPARATUS, PROGRAM, AND METHOD OF MANUFACTURING ARTICLE - Disclosed is a method of generating a recipe for supplying an imprint material onto a substrate, the imprint material being used in imprint processing of forming a pattern on the substrate with the imprint material and a mold. The method includes obtaining first information about a volume of a pattern of the mold, and obtaining second information about a concentration of a condensable gas to be supplied to a space between the mold and the imprint material on the substrate. The condensable gas has a property of being liquefied by contact between the mold and the imprint material. The method further includes generating the recipe based on the first information and the second information. | 2017-05-18 |
20170140923 | ETCHING METHOD - There is provided an etching method for etching an antireflection film including silicon according to a pattern of a resist film by using plasma processing with respect to a processing object, the processing object including an etching object film, the antireflection film including silicon laminated on the etching object film, and the resist film laminated on the antireflection film including silicon. The method includes generating plasma of a processing gas containing a fluorocarbon gas in a processing chamber, the processing object being disposed in the processing chamber, and generating plasma of a processing gas containing an inactive gas in the processing chamber, the processing object being disposed in the processing chamber. A set of the first generating and the second generating are repeatedly performed. | 2017-05-18 |
20170140924 | FORMATION OF SiOCN THIN FILMS - Methods for depositing silicon oxycarbonitride (SiOCN) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOCN films having improved acid-based wet etch resistance. | 2017-05-18 |
20170140925 | FORMATION OF SiOCN THIN FILMS - Methods for depositing silicon oxycarbonitride (SiOCN) thin films on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor and a second reactant that does not include oxygen. In some embodiments the methods allow for the deposition of SiOCN films having improved acid-based wet etch resistance. | 2017-05-18 |
20170140926 | PROCESS FOR DEPOSITION OF TITANIUM OXYNITRIDE FOR USE IN INTEGRATED CIRCUIT FABRICATION - A process is provided for depositing a substantially amorphous titanium oxynitride thin film that can be used, for example, in integrated circuit fabrication, such as in forming spacers in a pitch multiplication process. The process comprises contacting the substrate with a titanium reactant and removing excess titanium reactant and reaction byproducts, if any. The substrate is then contacted with a second reactant which comprises reactive species generated by plasma, wherein one of the reactive species comprises nitrogen. The second reactant and reaction byproducts, if any, are removed. The contacting and removing steps are repeated until a titanium oxynitride thin film of desired thickness has been formed. | 2017-05-18 |
20170140927 | FOCUSED RADIATION BEAM INDUCED DEPOSITION - A semiconductor device fabrication method includes irradiating a first surface of a substrate with a radiation beam. While irradiating the first surface of the substrate, a precursor gas is introduced near the first surface to deposit a layer including a first material. The precursor gas is removed from near the first surface after the depositing the layer. After the removing the precursor gas and prior to forming another layer over the layer, while irradiating a second surface of the layer, a cleaning gas is introduced near the second surface of the layer to transform the first material into a second material. | 2017-05-18 |
20170140928 | PROTECTIVE FILM FORMING METHOD - A method for forming a water-soluble resin film on a wafer having a plurality of devices thereon. The wafer is supported through an adhesive tape to an annular frame. The method includes removing the resin scattered onto the surface of the frame in forming the film on the wafer held on a spinner table, and this step further includes: rotating the spinner table; positioning a water nozzle above the frame held on the spinner table, supplying water from the nozzle to the frame, positioning an air nozzle adjacent to the water nozzle on the downstream side thereof in the rotational direction of the spinner table, and supplying air from the air nozzle against the flow of the water on the frame, whereby the water is forced to temporarily stay on the surface of the frame by the air supplied and is then expelled outward of the frame. | 2017-05-18 |
20170140929 | COATING FILM FORMING METHOD, COATING FILM FORMING APPARATUS, AND STORAGE MEDIUM - A method of forming a coating film includes horizontally supporting a substrate, supplying a coating solution to a central portion of the substrate and spreading the coating solution by a centrifugal force by rotating the substrate at a first rotational speed, decreasing a speed of the substrate from the first rotational speed toward a second rotational speed and rotating the substrate at the second rotational speed to make a surface of a liquid film of the coating solution even, supplying a gas to a surface of the substrate when the substrate is rotated at the second rotational speed to reduce fluidity of the coating solution, and drying the surface of the substrate by rotating the substrate at a third rotational speed faster than the second rotational speed. | 2017-05-18 |
20170140930 | Treatment Process and System - A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials. | 2017-05-18 |
20170140931 | LOW K DIELECTRIC DEPOSITION VIA UV DRIVEN PHOTOPOLYMERIZATION - Provided are methods and apparatus for ultraviolet (UV) assisted capillary condensation to form dielectric materials. In some embodiments, a UV driven reaction facilitates photo-polymerization of a liquid phase flowable material. Applications include high quality gap fill in high aspect ratio structures and por sealing of a porous solid dielectric film. According to various embodiments, single station and multi-station chambers configured for capillary condensation and UV exposure are provided. | 2017-05-18 |
20170140932 | METHOD OF FORMING ULTRA-THIN NANOWIRES - Provided is a method of forming a nanowire-based device. The method includes forming a first mask layer over a substrate; forming a first opening in the first mask layer; growing a first nanowire that protrudes through the first opening in the first mask layer, wherein the first nanowire has a first diameter; removing the first mask layer; oxidizing a sidewall of the first nanowire; etching the oxidized sidewall of the first nanowire; forming a second mask layer overlaying the substrate; removing the first nanowire thereby forming a second opening in the second mask layer; and growing a second nanowire that protrudes through the second opening in the second mask layer, wherein the second nanowire has a second diameter and the second diameter is different than the first diameter. | 2017-05-18 |
20170140933 | METHOD FOR FORMING STACKED NANOWIRE TRANSISTORS - A method includes forming a first semiconductor stack using an epitaxial growth process, the first semiconductor stack comprising a first plurality of semiconductor layers alternating with a second plurality of semiconductor layers, the first plurality of semiconductor layers comprising a first semiconductor material and the second plurality of semiconductor layers comprising a second semiconductor material that is different than the first semiconductor material. The method further includes patterning the first semiconductor stack to form a set of semiconductor stack features, forming isolation features between the semiconductor stack features, removing at least one of the semiconductor stack features, thereby forming at least one trench, and forming, within the trench, a second semiconductor stack using an epitaxial growth process, the second semiconductor stack having different characteristics than the first semiconductor stack. | 2017-05-18 |
20170140934 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 μm or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c). | 2017-05-18 |
20170140935 | SEMICONDUCTOR DEVICE FABRICATION METHOD - With a semiconductor device fabrication method, an oxide film and a thermal oxide film formed over a semiconductor substrate are etched and ions are implanted in the semiconductor substrate in a high-temperature environment with the etched oxide film as a mask. Furthermore, the thermal oxide film has high adhesion to the semiconductor substrate. As a result, even if a difference in linear expansion coefficient arises between the semiconductor substrate and the oxide film due to a change in the linear expansion coefficient of the semiconductor substrate, the oxide film does not peel off the semiconductor substrate or crack because the oxide film is formed over the semiconductor substrate with the thermal oxide film therebetween. | 2017-05-18 |
20170140936 | TRENCH STRUCTURE ON SIC SUBSTRATE AND METHOD FOR FABRICATING THEREOF - A trench structure on a SiC substrate and method for fabricating thereof is provided. The fabricating method includes: providing a SiC substrate; forming a protection layer on the SiC substrate; forming an resisting layer on the protection layer; patterning the resisting layer and the protection layer to form an opening; patterning the SiC substrate by using the patterned resisting layer as a hard mask to form a trench; removing the patterned resisting layer; performing a high-temperature annealing process to form a rounded bottom of the trench; and removing the protection layer. | 2017-05-18 |
20170140937 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING PERFORMING AN ATOMIC LAYER ETCHING PROCESS - Provided are a semiconductor device fabricating apparatus configured to perform an atomic layer etching process and a method of fabricating a semiconductor device including performing the atomic layer etching process. The method includes loading a wafer onto an electrostatic chuck in a chamber, performing a first periodical process in which a first gas is supplied to an inside of the chamber and the first gas is adsorbed onto the wafer, performing a second periodical process in which a second gas is supplied to the inside of the chamber and the first gas remaining in the chamber is exhausted to an outside of the chamber, performing a third periodical process in which a third gas is supplied to the inside of the chamber, plasma including the third gas is generated, the plasma collides with the wafer, and the first gas adsorbed onto the wafer is removed, and unloading the wafer to the outside of the chamber. | 2017-05-18 |
20170140938 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes irradiating a semiconductor body with particles. Dopant ions are implanted into the semiconductor body such that the dopant ions are configured to be activated as donors or acceptors. Thereafter, the semiconductor body is processed thermally. | 2017-05-18 |
20170140939 | PROCESS OF FORMING SEMICONDUCTOR DEVICE - A process of forming a semiconductor device using plasma processes is disclosed. The semiconductor device includes a device area, a scribed area, and a peripheral area on a wafer, where these areas have respective conductive regions. The process includes steps of (a) implanting ions to isolate the conductive regions in the device area from the conductive region in the scribed area; (b) forming a metal film so as to cover a back surface, a side, and the peripheral area in the top surface of the wafer; (c) deposing insulating film on a whole surface of the wafer; and (d) selectively etching, by the plasma process, the insulating film so as to expose the conductive regions in the device area and the scribed area. During the plasma process, the metal film in the back surface of the wafer is connected the apparatus ground that effectively dissipates charges induced by the plasm to the apparatus ground through the metal film. | 2017-05-18 |
20170140940 | GATE STACK FORMED WITH INTERRUPTED DEPOSITION PROCESSES AND LASER ANNEALING - Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous. | 2017-05-18 |
20170140941 | ALUMINUM OXIDE LANDING LAYER FOR CONDUCTIVE CHANNELS FOR A THREE DIMENSIONAL CIRCUIT DEVICE - A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer. | 2017-05-18 |
20170140942 | Self-Aligned Dual-Metal Silicide and Germanide Formation - A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy. | 2017-05-18 |
20170140943 | METHOD FOR FORMING A CAVITY AND A COMPONENT HAVING A CAVITY - A method for forming a cavity in a silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate, and situation of an etching mask on the surface of the silicon substrate. The etching mask has a retarding structure that protrudes into the mask opening, and a first etching projection region. All further edges of the mask opening outside the first etching projection region are situated essentially parallel to {111} planes of the silicon substrate. The method includes an anisotropic etching of the silicon substrate during a defined etching duration. An etching rate in the <111> directions of the silicon substrate is lower than in other spatial directions, and the first retarding structure is undercut in a first undercut direction going out from the first etching projection region. | 2017-05-18 |
20170140944 | SEMICONDUCTOR DEVICE, CORRESPONDING METHODS OF PRODUCTION AND USE AND CORRESPONDING APPARATUS - A semiconductor device includes a quadrilateral package with a first pair of opposed sides and a second pair of opposed sides. Both sides of the first pair of opposed sides are provided with electrical contact leads. Only one side of the second pair of opposed sides is provided with electrical contact leads. The side of the second pair of opposed sides without electrical contact leads is a leadless side. That side is not a molded side of the package, but rather is defined by a cut surface. | 2017-05-18 |
20170140945 | THERMALLY CONDUCTIVE STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES - A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip. | 2017-05-18 |
20170140946 | Method of Manufacturing a Cooler for Semiconductor Modules - A cooling apparatus is manufactured by: receiving a discrete module by a first singular part, the discrete module including a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound, and a first cooling plate at least partly uncovered by the mold compound; attaching a second singular part to a periphery of the first part to form a housing, the housing surrounding a periphery of the discrete module, the second part having a cutout which exposes the first cooling plate and a sealing structure facing a side of the discrete module with the first cooling plate; and filling the sealing structure with a sealing material which forms a water-tight seal around the periphery of the discrete module at the side of the discrete module with the first cooling plate. | 2017-05-18 |
20170140947 | Semiconductor Device and Method - In accordance with an embodiment a method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer. | 2017-05-18 |
20170140948 | SEMICONDUCTOR PACKAGE MANUFACTURING METHOD - A method is provided for manufacturing a semiconductor package capable of preventing positional dislocation of semiconductor chip(s) as a result of contraction due to thermal curing of resin(s). This relates to a semiconductor package manufacturing method comprising an operation in which semiconductor chip(s) is/are arranged over semiconductor backside protective film which is arranged over an adhesive sheet; an operation in which semiconductor backside protective film is cured; and an operation in which semiconductor chip(s) is/are sealed with resin. | 2017-05-18 |
20170140949 | PURGE STOCKER AND PURGING METHOD - A purge stocker includes a first supply unit including N first purge apparatuses, each having a first supply unit configured to support a storage container, a first supply pipe configured to supply the purge gas into the storage container supported by the first supporting unit, and a first flow rate adjusting unit configured to adjust the flow rate of the purge gas in the first supply pipe; and a second supply unit including M second purge apparatuses, each having a second supporting unit configured to support the storage container and a second supply pipe configured to supply the purge gas into the storage container supported by the second supporting unit. When the storage containers are supported by a certain number of second supporting units, the second supply unit supplies the storage containers with the purge gas through the respective second supply pipes. | 2017-05-18 |
20170140950 | SPRAY ASSEMBLY AND WET ETCHING DEVICE HAVING THE SAME - A spray assembly including a spray pipe with a bottom provided with a plurality of first through holes, each having a nozzle, wherein the nozzle includes a slider with an area larger than the first through hole, to cover the first through hole. The nozzle is connected to the slider and protrudes from the first through hole; the nozzle also includes a locking member to connect the slider to the spray pipe. The slider can move to adjust the position of the nozzle in the first through hole. There also provides a wet etching device including a spray unit, wherein the spray unit includes a plurality of spray assemblies as mentioned above, and a plurality of spray pipes in the plurality of spray assemblies are arranged in parallel with each other or approximately in parallel with each other. | 2017-05-18 |
20170140951 | THREE-DIMENSIONAL WAFER SURFACE WASHING METHOD AND DEVICE - Disclosed is an apparatus for removing residues present on the surface of a three-dimensional wafer formed with three-dimensional surface structures to clean the surface of the three-dimensional wafer. The apparatus includes a wafer support for supporting a three-dimensional wafer and a CO | 2017-05-18 |
20170140952 | METHODS AND APPARATUS FOR CLEANING SEMICONDUCTOR WAFERS - A method for cleaning semiconductor substrate using ultra/mega sonic device comprising holding a semiconductor substrate by using a chuck, positioning a ultra/mega sonic device adjacent to the semiconductor substrate, injecting chemical liquid on the semiconductor substrate and gap between the semiconductor substrate and the ultra/mega sonic device, changing gap between the semiconductor substrate and the ultra/mega sonic device for each rotation of the chuck during the cleaning process. The gap can be increased or reduced by 0.5 | 2017-05-18 |
20170140953 | SYSTEMS AND METHODS FOR ION BEAM ETCHING - An ion system for use in an etching system for etching at least a wafer using a gas. The ion system may include an ion chamber for containing charged particles generated from the gas. The ion system may also include a magnetic device surrounding at least a portion of the ion chamber. The magnetic device may affect the distribution of the charged particles in the ion chamber. The ion system may also include a grid assembly disposed between the ion chamber and the wafer when the wafer is etched. The charged particles may be provided through the grid assembly to etch the wafer when the wafer is etched. | 2017-05-18 |
20170140954 | PLACING TABLE AND PLASMA TREATMENT APPARATUS - A placing table on an embodiment includes a supporting member and a base. The supporting member includes a placing region provided with a heater, and an outer peripheral region surrounding the placing region. The base includes a first region supporting the placing region thereon, and a second region surrounding the first region. In the second region, through holes are formed. Wirings electrically connected to the heater passes through the through holes of the second region. | 2017-05-18 |
20170140955 | APPARATUS AND METHOD FOR WAFER LEVEL BONDING - A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by one or more shared flexible membranes. The method also includes setting a first profile of the surface of the first wafer chuck. Setting a first profile of the surface of the first wafer chuck includes adjusting a first volume of a first profile control zone of the multiple first profile control zones. Setting a first profile of the surface of the first wafer chuck also includes adjusting a second volume of a second profile control zone of the multiple first profile control zones, the first volume of the first profile control zone being adjusted independently from the second volume of the second profile control zone, and the second adjustable volume encircling the first adjustable volume. | 2017-05-18 |
20170140956 | Single Piece Ceramic Platen - A single piece ceramic platen is disclosed. This platen may be manufactured using additive manufacturing. The single piece ceramic platen may be manufactured using additive manufacturing processes. As such, the single piece ceramic platen may include a plurality of embedded features. Electrodes, cooling channels, heating elements, temperature sensors, strain gauges and back side gas channels may each be embedded in the electrode. Incorporation of cooling channels and heating elements allows the platen to operate over a wider range of temperatures. Further, these features may be disposed on a plurality of different depths following a planar or non-planar pathway. For example, the heating elements may be configured such that heating element in one region of the platen, such as an outer edge, are disposed closer to the top surface of the platen. | 2017-05-18 |
20170140957 | POWER FEEDING MECHANISM AND METHOD FOR CONTROLLING TEMPERATURE OF A STAGE - A heater power feeding mechanism is provided that divides a stage on which a substrate is placed into zones by using a plurality of heaters and can control a temperature of each of the zones. The heater power feeding mechanism includes a plurality of sets of heater terminals connected to any of the plurality of heaters by a segment unit when a set of the heater terminals is made one segment, a heater interconnection, and an interconnection structure configured to connect at least any of the plurality sets of the heater terminals with each other by using the heater interconnection by the segment unit. | 2017-05-18 |
20170140958 | HEATER POWER FEEDING MECHANISM - A heater power feeding mechanism for independently controlling temperatures of zones of a stage on which a substrate is placed. The respective zones of the stage include heaters. The heater power feeding mechanism includes a plurality of heater terminals configured to be connected to the heaters, a plurality of heater wires connected to the heater terminals, and an offset structure that offsets the heater wires from each other. The heater terminals are disposed on the periphery of a holding plate for holding the stage. | 2017-05-18 |
20170140959 | Apparatus and Method for Direct Transfer of Semiconductor Devices - An apparatus that directly transfers a semiconductor device die from a first substrate to a second substrate. The semiconductor device die is disposed on the first side of the first substrate. The apparatus includes a first frame to hold the first substrate, and a second frame to hold the second substrate adjacent to the first side of the first substrate. A needle is disposed adjacent to the first frame and extends in a direction toward the second side of the first substrate. A needle actuator is connected to the needle to move the needle, during a direct transfer process, to a die transfer position at which the needle contacts the second side of the first substrate to press the semiconductor device die into contact with the second substrate such that the semiconductor device die is released from the first substrate and is attached to the second substrate. | 2017-05-18 |
20170140960 | DIE MOUNTING SYSTEM AND DIE MOUNTING METHOD - In a die mounting system in which a die supply device is set on a component mounter and dies supplied from a die supply device are mounted on a circuit board by a mounting head of the component mounter, the position of a die is recognized by processing an image of the die on a dicing sheet captured by a camera, a supply head is moved to a die pickup position by a supply head moving mechanism, the die is picked up, the supply head is vertically inverted and moved to a die transfer position, and the die held by the supply head is picked up by a mounting head of the component mounter at a component transfer position and mounted on the circuit board. The die transfer position is set at a position such that die transfer and die imaging are able to be performed in parallel. | 2017-05-18 |
20170140961 | Pick-and-Remove System and Method for Emissive Display Repair - A system and method are provided for repairing an emissive display. Following assembly, the emissive substrate is inspected to determine defective array sites, and defect items are removed using a pick-and-remove process. In one aspect, the emissive substrate includes an array of wells, with emissive elements located in the wells, but not electrically connected to the emissive substrate. If the emissive elements are light emitting diodes (LEDs), then the emissive substrate is exposed to ultraviolet illumination to photoexcite the array of LED, so that LED illumination can be measured to determine defective array sites. The defect items may be determined to be misaligned, mis-located, or non-functional emissive elements, or debris. Subsequent to determining these defect items, the robotic pick-and-remove process is used to remove them. The pick-and-remove process can also be repurposed to populate empty wells with replacement emissive elements. | 2017-05-18 |
20170140962 | SUBSTRATE TREATING APPARATUS - A substrate treating apparatus includes a treating section for treating substrates. The treating section has a front face and a rear face both connectable to an indexer section for feeding the substrates to the treating section. Such substrate treating apparatus can improve the degree of freedom for arranging the treating section and the indexer section. | 2017-05-18 |
20170140963 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes a substrate retaining mechanism; a detecting unit detecting a placed state of the substrate retained by the substrate retaining mechanism; a first determination unit comparing detection data of the substrate obtained by the detecting unit with master data that is a reference to determine if the detection data is within a first allowed value; a confirmation unit confirming substrate type; a second determination unit comparing the detection data of the substrate with the master data to determine if the detection data is within a second allowed value; and a transfer control unit controlling the substrate retaining mechanism depending on a determination result of the second determination unit when substrate type is confirmed as a predetermined type by the confirmation unit when it is determined that the detection data is not within the first allowed value as determined by the first determination unit. | 2017-05-18 |
20170140964 | WAFER BOAT SUPPORT TABLE AND HEAT TREATMENT APPARATUS USING THE SAME - There is provided a wafer boat support table that supports a wafer boat having a plurality of posts from below, the plurality of posts being configured to arrange and support a plurality of wafers at intervals in a vertical direction, the wafer boat support table including: a plurality of support points installed on each of linear lines defined by connecting a center of the wafer boat and the plurality of posts and configured to support a bottom surface of the wafer boat while being brought into contact with the bottom surface of the wafer boat. | 2017-05-18 |
20170140965 | Container Transport Facility - A transport apparatus transports a container that includes a flow hole forming portion in which a flow hole through which gas can flow between the outside and the inside of the container is formed. A connecting portion that has a flow path through which gas can flow and a filling gas supply source that allows a filling gas to flow through the flow path are provided in the transport apparatus. The connecting portion is configured to be switchable between a non-connected state in which the connecting portion is retracted to the outside of a moving region of the container that moves along a transport path and a connected state in which the connecting portion enters the inside of the moving region and is connected to the flow hole forming portion of the container. | 2017-05-18 |
20170140966 | HIGH CAPACITY OVERHEAD TRANSPORT (OHT) RAIL SYSTEM WITH MULTIPLE LEVELS - An overhead transport (OHT) system with multiple levels of rails for the transport of semiconductor workpieces is provided. A first vehicle is configured to travel on, and move a semiconductor workpiece along, a first rail. A second vehicle is configured to travel on, and move the semiconductor workpiece along, a second rail overlying the first rail. A controller is configured to control the first and second vehicles to transfer the semiconductor workpiece along the first and second rails, between process or inspection tools. A method for transferring semiconductor workpieces across multiple levels of rails is also provided. | 2017-05-18 |
20170140967 | Apparatus and Method for Direct Transfer of Semiconductor Devices via Stacking - An apparatus includes a first frame to hold a wafer tape, and a second frame to hold a substrate adjacent to the first side of the wafer tape. A needle is disposed adjacent to the second side of the wafer tape and extends in a direction toward the wafer tape. A needle actuator is connected to the needle to move the needle, during a direct transfer process, to a die transfer position at which the needle contacts the second side of the wafer tape to press the first semiconductor device die into contact with a second semiconductor device die. An energy-emitting device is disposed adjacent to the substrate to induce a bond between the first semiconductor device die and the second semiconductor device die such that the first semiconductor device die is released from the wafer tape and is attached to the second semiconductor device die. | 2017-05-18 |
20170140968 | Systems and Methods for Controlling Plasma Instability in Semiconductor Fabrication - An apparatus for supporting a wafer during a plasma processing operation includes a pedestal configured to have bottom surface and a top surface and a column configured to support the pedestal at a central region of the bottom surface of the pedestal. An electrical insulating layer is disposed over the top surface of the pedestal. | 2017-05-18 |
20170140969 | ALUMINUM NITRIDE ELECTROSTATIC CHUCK USED IN HIGH TEMPERATURE AND HIGH PLASMA POWER DENSITY SEMICONDUCTOR MANUFACTURING PROCESS - Disclosed is an aluminum nitride electrostatic chuck, comprising: a positioning electrostatic chuck and a carrier structure. The positioning electrostatic chuck includes a groove structure layer, a dielectric insulation layer, and a heat conduction layer. In the groove structure layer on the surface of the electrostatic chuck is provided with cooling gas channels, to facilitate control of the temperature distribution of a wafer. The electrostatic chuck is especially designed for use in a semiconductor manufacturing process of high temperature and high plasma power density. The dielectric insulation layer is provided with embedded electrodes, such that voltage conversion can be carried out to effect wafer absorption/release. The cooling gas channels are used to control temperature of the absorbed wafer, by means of heat conduction of aluminum nitride electrostatic chuck. Therefore, wafer temperature distribution is controlled through aspect ratio and geometry of cooling gas channel. | 2017-05-18 |
20170140970 | SUBSTRATE SUPPORT ASSEMBLY WITH DEPOSITED SURFACE FEATURES - A method of manufacturing an electrostatic chuck includes polishing a surface of a ceramic body of the electrostatic chuck to produce a polished surface and depositing a ceramic coating onto the polished surface of the ceramic body to produce a coated ceramic body. The method further includes disposing a mask over the coated ceramic coating, the mask comprising a plurality of elliptical holes and depositing a ceramic material through the plurality of elliptical holes of the mask to form a plurality of elliptical mesas on the coated ceramic body, wherein the plurality of elliptical mesas have rounded edges. The mask is then removed from the coated ceramic body and the plurality of elliptical mesas are polished. | 2017-05-18 |
20170140971 | ADHESIVE WITH TUNABLE ADHESION FOR HANDLING ULTRA-THIN WAFER - Described is an apparatus which comprises a wafer tray having an adhesive layer, with dynamically adjustable adhesion properties, deposited on a surface of the wafer tray; a wafer positioned on the wafer tray; and a cooling agent which is operable to cool at least a portion of the adhesive layer below its glass transition temperature (T | 2017-05-18 |
20170140972 | LAMINATED BODY AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A laminated body comprising a dicing sheet and a semiconductor backside protective film, in which the dicing sheet comprises a base layer and an adhesive layer arranged over the base layer, the semiconductor backside protective film is arranged over the adhesive layer, the dicing sheet is provided with a property such that application of heat thereto causes contraction thereof, and with a property such that heat treatment thereof for one minute at 100° C. causes a second length in an MD direction following heat treatment to be not greater than 95% when expressed as a percentage such that a first length in the MD direction prior to heat treatment is taken to be 100%. | 2017-05-18 |
20170140973 | LAMINATE BODY AND COMPOSITE BODY; SEMICONDUCTOR DEVICE MANUFACTURING METHOD - [PROBLEM] To provide a laminated body and so forth that makes it possible to reduce cracking that would otherwise occur at the chip side face during dicing. | 2017-05-18 |
20170140974 | LAMINATED BODY AND COMPOSITE BODY; ASSEMBLY RETRIEVAL METHOD; AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - [PROBLEM] To provide a laminated body and so forth that makes it possible to prevent pieces of post-dicing semiconductor backside protective film from sticking to one another. | 2017-05-18 |
20170140975 | SPIN HEAD, APPARATUS AND METHOD FOR TREATING A SUBSTRATE INCLUDING THE SPIN HEAD - The present disclosure relates to a spin head, apparatus and method for treating a substrate including the spin head. The spin head includes a supporting plate where a substrate is placed and a chuck pin placed on the supporting plate and supporting a lateral portion of the substrate, wherein the chuck pin includes an outer body and an inner body inserted in the outer body and provided with a different material from the outer body, wherein each outer body and the inner body is provided with any one of a first material or a second material, and wherein one material of the first material and the second material is provided with a material having lower heat conductivity and better thermal resistance than another one | 2017-05-18 |
20170140976 | HEAT TREATMENT APPARATUS FOR HEATING SUBSTRATE BY IRRADIATION WITH FLASH LIGHT - A susceptor of a holding part for holding a semiconductor wafer includes a disc-shaped holding plate, an annular shaped guide ring, and a plurality of support pins. The guide ring has an inside diameter greater than the diameter of the semiconductor wafer and is installed on the peripheral portion of the top face of the holding plate. The guide ring has a tapered surface along the inner circumference. The semiconductor wafer before irradiated with flash light is supported by the support pins. The annular shape of the guide ring increases the contact area when the semiconductor wafer that has jumped off the susceptor and fallen when irradiated with flash light collides with the guide ring, thus reducing the impact of the collision and preventing cracks in the substrate. | 2017-05-18 |
20170140977 | CHUCK PIN, METHOD FOR MANUFACTURING A CHUCK PIN, APPARATUS FOR TREATING A SUBSTRATE - A chuck pin, method for manufacturing a chuck pin, and an apparatus for treating substrate. The substrate treating apparatus includes a container having a treating space in its inner side, a supporting unit supporting the substrate inside of the treating space, and a liquid supply unit providing a solution to the supported substrate of the supporting unit. The supporting unit is placed in a supporting plate where the substrate is placed and in the above supporting plate, and includes a chuck pin supporting a side part of the substrate. The chuck pin is formed on a body and on the above surface of the body, and includes a first coating film provided as a silicon carbide material. | 2017-05-18 |
20170140978 | CARRIER AND A METHOD FOR PROCESSING A CARRIER - According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench structure extending from the surface of the carrier to the hollow chamber and laterally surrounding a first region of the carrier, the trench structure including one or more trenches extending from the surface of the carrier to the hollow chamber, and one or more support structures intersecting the one or more trenches and connecting the first region of the carrier with a second region of the carrier outside the trench structure, wherein the one or more support structures including an electrically insulating material. | 2017-05-18 |
20170140979 | Multi-Barrier Deposition for Air Gap Formation - A method includes forming a first conductive line and a second conductive line in a dielectric layer, etching a portion of the dielectric layer to form a trench between the first conductive line and the second conductive line, and forming a first etch stop layer. The first etch stop layer extends into the trench. A second etch stop layer is formed over the first etch stop layer. The second etch stop layer extends into the trench, and the second etch stop layer is more conformal than the first etch stop layer. A dielectric material is filled into the trench and over the second etch stop layer. An air gap is formed in the dielectric material. | 2017-05-18 |
20170140980 | MECHANISMS FOR FORMING FINFETS WITH DIFFERENT FIN HEIGHTS - A semiconductor device is provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and a second fin partially surrounded by a second isolation structure. The second isolation structure has a dopant concentration higher than that of the first isolation structure, and a height difference is between a top surface of the first isolation structure and a top surface of the second isolation structure. | 2017-05-18 |
20170140981 | INTERCONNECT STRUCTURE - Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer. | 2017-05-18 |
20170140982 | METHOD FOR FORMING CONDUCTIVE STRUCTURE IN SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a sacrificial layer over the first dielectric layer. The method further includes forming an opening in the sacrificial layer and etching the first dielectric layer to form a via hole through the opening. The method further includes forming a conductive structure in the via hole and the opening and removing the sacrificial layer to expose an upper portion of the conductive structure. The method further includes forming a second dielectric layer around the upper portion of the conductive material. | 2017-05-18 |
20170140983 | TECHNIQUES FOR FILLING A STRUCTURE USING SELECTIVE SURFACE MODIFICATION - A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an exposure of the cavity to a moisture-containing ambient, and introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material is selectively deposited on the bottom surface of the cavity with respect to a sidewall of the cavity. | 2017-05-18 |
20170140984 | INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER - An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact. | 2017-05-18 |
20170140985 | SELF-ALIGNED CONDUCTIVE POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER - A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer. | 2017-05-18 |