20th week of 2014 patent applcation highlights part 46 |
Patent application number | Title | Published |
20140134727 | DEFINITIVE ENDODERM - Disclosed herein are cell cultures comprising definitive endoderm cells and methods of producing the same. Also disclosed herein are cell populations comprising substantially purified definitive endoderm cells as well as methods for enriching, isolating and purifying definitive endoderm cells from other cell types. | 2014-05-15 |
20140134728 | METHODS FOR ADJUSTING EXPRESSION OF MITOCHONDRIAL GENOME BY MICRORNA - The present invention relates to a method for adjusting the expression of the mitochondrial genome in a human cell comprising a step consisting of modulating the expression of a least one mi RNA selected from the group consisting of hsa-mi R-1973, hsa-mi R-1275, hsa-mi R-494, hsa-mi R-513a-5p, hsa-mi R-1246, hsa-mi R-328, hsa-mi R-1908, hsa-mi R-1972, hsa-mi R-1974, hsa-mi R-1977, hsa-mi R-638, hsa-mi R-1978 and hsa-mi R-1201. | 2014-05-15 |
20140134729 | Synthetic Surfaces for Culturing Stem Cell Derived Oligodendrocyte Progenitor Cells - Synthetic surfaces suitable for culturing stem cell derived oligodendrocyte progenitor cells contain acrylate polymers formed from one or more acrylate monomers. The acrylate surfaces, in many cases, are suitable for culturing stem cell derived oligodendrocyte progenitor cells in chemically defined media. | 2014-05-15 |
20140134730 | METHOD FOR INHIBITING CELL PROLIFERATION BY OXIDATIVE STRESS - The present invention relates to an intracellular oxidative stress promoter, comprising a monoclonal antibody having an inhibitory activity of intracellular uptake of neutral amino acids or an antibody fragment thereof as an active ingredient. Also, the present invention relates to a cell proliferation inhibitor, comprising a monoclonal antibody having an inhibitory activity of intracellular uptake of neutral amino acids or an antibody fragment thereof as an active ingredient and promoting intracellular oxidative stress. | 2014-05-15 |
20140134731 | Clerodendrum viscosum and Methods of Use - The present invention provides for a composition and formulations comprising an extract from | 2014-05-15 |
20140134732 | Simplified Compositions and Methods for Generating Neural Stem Cells From Human Pluripotent Stem Cells - Simplified methods and compositions for directed differentiation of human pluripotent stem cells into neural stem cells are described. Methods and compositions for deriving neural stem cells from human pluripotent stem cells under defined, xeno-free conditions are also described. | 2014-05-15 |
20140134733 | CHEMICALLY DEFINED PRODUCTION OF CARDIOMYOCYTES FROM PLURIPOTENT STEM CELLS - Methods are provided for producing a cardiomyocyte population from a mammalian pluripotent stem cell population. Aspects of the methods include using a Wnt signaling agonist and antagonist, each in minimal media, to modulate Wnt signaling. Also provided are kits for practicing the methods described herein. | 2014-05-15 |
20140134734 | CELL CULTURE SYSTEM AND SERUM-FREE METHOD FOR CULTIVATING CELLS - The disclosure provides a cell culture system and a serum-free method for cultivating cells. The cell culture system includes a substratum, wherein the substratum has a surface. A polymer is disposed on the surface of the substratum, wherein the polymer is prepared by polymerizing a first monomer with a second monomer. The first monomer has a structure as represented by Formula (I), and the second monomer has a structure as represented by Formula (II): | 2014-05-15 |
20140134735 | Plant Cell Differentiation Promoter - The present invention addresses the problem of providing a plant cell differentiation promoter with which it is possible to promote differentiation from a callus to a normal adventitious embryo, or promote differentiation of an adventitious root or adventitious bud from a plant cutting, and as a result, obtain a regenerated plant with stability. The present invention provides a plant differentiation promoter comprising as the active ingredient a specific ketole fatty acid or derivative thereof. | 2014-05-15 |
20140134736 | MICROBIAL METABOLISM OF CHLORINE OXYANIONS AS A CONTROL OF BIOGENIC HYDROGEN SULFIDE PRODUCTION - The present disclosure relates to methods of controlling the sulfide (S2˜) content in systems, such as oil and gas reservoirs and pipelines, by the use of chlorine oxyanions and microorganisms with (per)chlorate-reducing activity. | 2014-05-15 |
20140134737 | Alternative Splicing Modulators and Splice Variants and Their Use in the Control and Detection of Pluripotency and Differentiation - Nucleotide sequences encoding novel splice variants of FOXP1, proteins encoded by the novel splice variants and antibodies thereto are disclosed. In addition, methods are described for maintaining a population of homogenous self-renewing and pluripotent stem cells, suppressing stem cell differentiation, and reprogramming somatic cells into pluripotent stem cells comprising the use of the novel splice variants. Also disclosed are modulators of alternative splicing such as MBNL1 and MBNL2 and methods and uses thereof for promoting pluripotency. | 2014-05-15 |
20140134738 | METHODS FOR REGULATING NEURAL DIFFERENTIATION - Methods of producing populations of predominantly astrocytes, neurons or oligodendrocytes are provided. In addition, methods of treating mammals having astroglial tumors, oligodendrocyte tumors, or neuronal tumors are provided. | 2014-05-15 |
20140134739 | METHOD OF GENETICALLY ALTERING AND PRODUCING ALLERGY FREE CATS - A transgenic cat with a phenotype characterized by the substantial absence of the major cat allergen, Fel d I. The phenotype is conferred in the transgenic cat by disrupting the coding sequence of the target gene with a specialized construct. The phenotype of the transgenic cat is transmissible to its offspring. | 2014-05-15 |
20140134740 | NOVEL DNA-BINDING PROTEINS AND USES THEREOF - Disclosed herein are polypeptides, polynucleotides encoding, cells and organisms comprising novel DNA-binding domains, including TALE DNA-binding domains. Also disclosed are methods of using these novel DNA-binding domains for modulation of gene expression and/or genomic editing of endogenous cellular sequences. | 2014-05-15 |
20140134741 | NOVEL DNA-BINDING PROTEINS AND USES THEREOF - Disclosed herein are polypeptides, polynucleotides encoding, cells and organisms comprising novel DNA-binding domains, including TALE DNA-binding domains. Also disclosed are methods of using these novel DNA-binding domains for modulation of gene expression and/or genomic editing of endogenous cellular sequences. | 2014-05-15 |
20140134742 | EFFECTS OF ALTERATION OF EXPRESSION OF THE MtfA GENE AND ITS HOMOLOGS ON THE PRODUCTION OF FUNGAL SECONDARY METABOLITES - Many fungal secondary metabolites are of industrial interest, such as antibiotics, while others are undesirable compounds such as mycotoxins. Overexpression of mtfA enhances production of fungal compounds with applications in the medical field, and overexpression or impaired mtfA expression decreases the production of compounds that negatively affect health/agriculture/economy such as mycotoxins. | 2014-05-15 |
20140134743 | METHOD FOR IDENTIFYING LAYERS PROVIDING CORROSION PROTECTION IN CRUDE OIL FRACTIONS - A method for determining and identifying corrosion protective layers that provide corrosion protection against crude oils and crude oil fractions is disclosed. The method identifies naturally occurring constituents in crude oils that indirectly provide corrosion protection. A method assessing the potential of these constituents is also disclosed. The method includes exposing metal coupons with the crude oil or crude fraction of interest at the expected operating temperature of concern. The corrosion potential assessment further analyzes the exposed coupons with transmission electron microscopy and an additional high temperature exposure that challenges the tenacity of the protection offered by the corrosion protective layer. | 2014-05-15 |
20140134744 | DETECTION DEVICE FOR MOLTEN METAL - A detection device for molten metal is provided. The detection device includes a sample cup having a cavity configured to receive a sample of molten metal and a blob arranged in the cavity. The blob includes a carbide stabilizing element and a hydrogen releasing material including a hydroxide of an alkaline earth metal. The blob is provided for use in detecting phase change temperatures during solidification of a sample of molten cast iron. The blob is also resistant to moisture gain and moisture loss during transport and storage. A method of detecting phase change temperatures of the molten iron or molten cast iron sample using the blob and a method of manufacturing the blob are also provided. | 2014-05-15 |
20140134745 | METHOD FOR EVALUATION OF LIGNIN - According to one aspect of the present method, a method for evaluation of lignin may comprise the steps of: providing lignin from a source, wherein the composition of lignin is unknown; analyzing the lignin by molecular spectroscopy methods and/or physical-chemical analysis; determining the composition of the lignin; and using the determination of the composition to predict at least one biobased product produced from the lignin. Within the method, a statistical analysis of the lignin may provide a prediction for one or more products produced and/or the yield of one or more products. | 2014-05-15 |
20140134746 | BIPHENOL ETHER COMPOUNDS AS MARKERS FOR LIQUID HYDROCARBONS AND OTHER FUELS AND OILS - A method for marking a petroleum hydrocarbon or a liquid biologically derived fuel by adding to the petroleum hydrocarbon or liquid biologically derived fuel at least one compound having formula (I), | 2014-05-15 |
20140134747 | METHODS FOR DETERMINING IF AN ANIMAL'S METABOLISM IS KETOGENIC - The invention provides methods for determining if an animal's metabolism has been shifted to ketogenic status by collecting a first urine sample from the animal when the animal's metabolism is not in a ketogenic status; collecting a second urine sample from the animal when the animal's metabolism is possibly in a ketogenic status; analyzing the first urine sample and the second urine sample for beta-hydroxy butyrate; and determining that the animal's metabolism has been shifted to ketogenic status if the concentration of beta-hydroxy butyrate in the second urine sample exceeds the concentration of beta-hydroxy butyrate in the first urine sample by ten percent (10%) or more. | 2014-05-15 |
20140134748 | INTEGRATED ELECTRO-MICROFLUIDIC PROBE CARD, SYSTEM AND METHOD FOR USING THE SAME - The present disclosure provides a biological field effect transistor (BioFET) device testing and processing methods, system and apparatus. A wafer-level bio-sensor processing tool includes a wafer stage, an integrated electro-microfluidic probe card, and a fluid supply and return. The integrated electro-microfluidic probe card includes a fluidic mount that may be transparent, a microfluidic channels in the fluidic mount, at least one microfluidic probe and a number of electronic probe tips at the bottom of the fluidic mount, fluidic and electronic input and output ports on the sides of the fluidic mount, and at least one handle lug on the fluidic mount. The method includes aligning a wafer, mounting the integrated electro-microfluidic probe card, flowing a test fluid, and measuring electrical properties. The tool may also be used for stamping or printing a fluid in the device area on the wafer. | 2014-05-15 |
20140134749 | SAMPLING PROCEDURE FOR POLYMER-BASED SOLUTIONS USED IN UNDERGROUND FORMATIONS - This invention concerns a sampling procedure for an aqueous hydrosoluble polymer solution flowing in a main circuit, enabling a sample to be collected to undergo at least one analysis under ambient air giving at least one property of the hydrosoluble polymer characterised in that a stabilizing solution is added to the aqueous hydrosoluble polymer solution, according to a discontinuous addition method, before or after sampling from the main circuit, so as to obtain a sample comprising a mixture of aqueous hydrosoluble polymer solution and stabilizing solution in which the hydrosoluble polymer is protected against attacks it may undergo in an atmosphere containing at least 10% by volume of oxygen. | 2014-05-15 |
20140134750 | TEST DEVICE AND METHODS OF USE - A test device for analyzing fluid samples. The test device includes a planar support member for supporting reagent pads, and a handle attached to, or for attaching to the planar support member. The test device can be treated with a fluid sample by disposing a fluid sample on the reagent pads. The fluid sample can be disposed onto the reagent pads by the handle, or by dipping the test device into the fluid sample. | 2014-05-15 |
20140134751 | DIAGNOSTIC METHOD - Disclosed herein is a method for diagnosing hepatic cancer by analysing a sample and determining the level of at least one compound selected from the group consisting of glycine, trimethylamine-N-oxide, hippurate and citrate and comparing the levels in the sample with control levels. The analysis of the sample can involve the determination of a profile for the sample. The methods disclosed are useful in distinguishing between a patient having hepatic cancer and a patient having cirrhosis. | 2014-05-15 |
20140134752 | METHOD FOR SPECIFIC IDENTIFICATION OF TARGET BIOMOLECULES - The present invention relates to a method for identification of specific target proteins in a protein sample following a detection procedure, such as a Western blotting procedure, wherein the membrane is probed with at least two primary antibodies directed against the same and/or different epitopes of the same target protein, and wherein specific binding to the target protein in a sample is differentiated from unspecific binding to the target protein by comparing the resulting sample patterns, such as bands or spot patterns, with each other. | 2014-05-15 |
20140134753 | METHODS FOR TREATING TRANSTHYRETIN AMYLOID DISEASES - Kinetic stabilization of the native state of transthyretin is an effective mechanism for preventing protein misfolding. Because transthyretin misfolding plays an important role in transthyretin amyloid diseases, inhibiting such misfolding can be used as an effective treatment or prophylaxis for such diseases. Treatment methods are disclosed. | 2014-05-15 |
20140134754 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM - A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma. | 2014-05-15 |
20140134755 | METHOD AND DEVICE FOR REPAIRING OPEN LINE DEFECT IN LIQUID CRYSTAL DISPLAY ARRAY SUBSTRATE - The present invention provides a method for repairing open line defect on LCD array substrate, which includes: when discovering open line defect on a pattern on LCD array substrate, identifying a repair line path of the open line on the pattern and scanning the repair line path; based on the result of scanning the repair line path, dividing the repair line path into at least two path segments and disposing corresponding coating speed for each path segment; and for each path segment, performing coating at the corresponding speed to form connected coating on the repair line path. The present invention also provides a device for repairing open line defect on LCD array substrate. As such, the present embodiment can increase success rate for repairing open lines. | 2014-05-15 |
20140134756 | BIOMOLECULAR RECOGNITION OF CRYSTAL DEFECTS - Discrete and diffuse defects in a surface are detected. Discrete defects that may compromise the performance may be repaired. | 2014-05-15 |
20140134757 | Method to Form Multiple Trenches Utilizing a Grayscale Mask - The present disclosure relates to a method to form a plurality of openings within a substrate with a single photo exposure and a single etch process. A photoresist layer is disposed over a substrate and aligned with a photomask, wherein the photomask comprises a transparent area, a grayscale area, and an opaque area. The photomask and substrate are exposed to radiation comprising a single illumination step to form a first 3-dimensional pattern within the photoresist layer. The 3-dimensional pattern comprises a first opening comprising a first thickness formed by transmitting the radiation through the transparent area with full intensity, and a second opening comprising a second thickness formed by transmitting the radiation through the grayscale area with partial intensity. The 3-dimensional pattern is transferred to form a plurality of openings of varying depths within the substrate through a single etch step. | 2014-05-15 |
20140134758 | TECHNIQUES FOR MATCHING SPECTRA - A method of controlling processing of a substrate includes measuring a spectrum reflected from the substrate, for each partition of a plurality of partitions of the measured spectrum, computing a partition value based on the measured spectrum within the partition to generate a plurality of partition values, for each reference spectrum signature of a plurality of reference spectrum signatures, determining a membership function for each partition, for each partition, computing a membership value based on the membership function for the partition and the partition value for the partition to generate a plurality of groups of membership values with each group of the plurality of groups associated with a reference spectrum signature, selecting a best matching reference spectrum signature from the plurality of reference spectra signatures based on the plurality of groups of membership values, and determining a characterizing value associated with the best matching reference spectrum signature. | 2014-05-15 |
20140134759 | METHOD OF FORMING A PATTERN - An embodiment of a method of forming a substrate pattern including forming a bottom layer and an overlying middle layer on the substrate. A photo resist pattern is formed on the middle layer. An etch coating layer is deposited on the photo resist pattern. The etch coating layer and the photo resist pattern are used as a masking element to pattern at least one of the middle layer and the bottom layer. The substrate is etched to form the substrate pattern using the at least one of the patterned middle layer and the patterned bottom layer as a masking element. The substrate pattern may be used as an element of an overlay measurement process. | 2014-05-15 |
20140134760 | DEVICES AND METHODS FOR EMBEDDING SEMICONDUCTORS IN PRINTED CIRCUIT BOARDS - Methods and devices for embedding semiconductors in printed circuit boards (PCBs) are provided. In one example, a method of manufacturing a PCB having a die assembly embedded therein includes removing a release film from an adhesive layer of the die assembly. The method also includes disposing the die assembly on a first layer of the PCB such that the adhesive layer contacts the first layer of the PCB. The method includes disposing a second layer of the PCB over the first layer such that the die assembly is within an intermediate portion between the first layer and the second layer. The method also includes filling the intermediate portion with resin and subjecting the PCB to a press cycle to cure the resin. | 2014-05-15 |
20140134761 | METHOD OF ATTACHING WAFER TO SHEET - A wafer attaching method of attaching a wafer having a warp to a sheet includes a wafer warp detecting step of detecting a surface shape of the wafer, a wafer positioning step of applying a photocuring liquid resin to the sheet and positioning the wafer so that a predetermined surface of the wafer corresponding to attaching conditions preset in a resin bonding apparatus is opposed to the sheet and the liquid resin according to the preset attaching conditions and the surface shape detected above, and a wafer attaching step of pressing the wafer against the liquid resin to thereby spread the liquid resin over the entire area where the wafer and the sheet are superimposed, next removing the pressure applied to the wafer, and next applying light to the liquid resin to cure the liquid resin, thereby attaching the predetermined surface of the wafer to the sheet. | 2014-05-15 |
20140134762 | METHOD AND APPARATUS FOR MANUFACTURING ORGANIC EL DEVICE - Provided are a method and an apparatus for manufacturing an organic EL device which enable deposition of a vaporized material onto a substrate in a desired pattern, while eliminating the need for a conventional strip-shaped shadow mask. A shielding portion is configured to be switchable between a shield position where the shielding portion is arranged between an evaporation source and a substrate so as to shield the substrate and a shield release position where the shielding portion is withdrawn from between the evaporation source and the substrate so as to release the shielding of the substrate. The shielding portion is moved in a transportation direction at the same speed as the substrate when the shielding portion is located at the shield position, whereas the shielding portion is moved in a direction opposite to the transportation direction when the shielding portion is located at the shield release position. | 2014-05-15 |
20140134763 | METHOD OF CUTTING FLEXIBLE DISPLAY DEVICE AND METHOD OF FABRICATING FLEXIBLE DISPLAY DEVICE USING THE SAME - The present disclosure relates to a method of cutting a flexible display device, capable of preventing a generation of a defect at the time of cutting the flexible display device, the method including providing a glass mother substrate having a flexible substrate attached thereon and an insulating layer formed on the flexible substrate; melting the flexible substrate and the insulating layer on the mother substrate by irradiating with a first laser beam; and cutting the mother substrate exposed by the irradiation of the first laser beam using a cutting device. | 2014-05-15 |
20140134764 | WHITE LIGHT EMITTING DIODE (LED) LIGHTING DEVICE DRIVEN BY PULSE CURRENT - A white LED lighting device driven by a pulse current is provided, which consists of blue, violet or ultraviolet LED chips, blue afterglow luminescence materials A and yellow luminescence materials B. Wherein the weight ratio of the blue afterglow luminescence materials A to the yellow luminescence materials B is 10-70 wt %:30-90 wt %. The white LED lighting device drives the LED chips with a pulse current having a frequency of not less than 50 Hz. Because of using the afterglow luminescence materials, the light can be sustained when an excitation light source disappears, thereby eliminating the influence of LED light output fluctuation caused by current variation on the illumination. At the same time, the pulse current can keep the LED chips being at an intermittent work state, so as to overcome the problem of chip heating. | 2014-05-15 |
20140134765 | LED ON SILICON SUBSTRATE USING ZINC-SULFIDE AS BUFFER LAYER - A vertical GaN-based blue LED has an n-type GaN layer that was grown over a ZnS layer that in turn was grown directly on a silicon substrate. In one example, the ZnS layer is a transitional buffer layer that is 50 nm thick, and the n-type GaN layer is at least 2000 nm thick. Growing the n-type GaN layer on the ZnS buffer layer reduces lattice defect density in the n-type layer. The ZnS buffer layer provides a good lattice constant match with the silicon substrate and provides a compound polar template for subsequent GaN growth. After the epitaxial layers of the LED are formed, a conductive carrier is wafer bonded to the structure. The silicon substrate and the ZnS buffer layer are then removed. Electrodes are added and the structure is singulated to form finished LED devices. | 2014-05-15 |
20140134766 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE PACKAGE - A method of manufacturing a light emitting device package, includes following steps: providing a base which having a first surface and an opposite second surface, and electrical structures formed on the first surface, defining two through holes through the first and second surfaces; mounting a light emitting element on the first surface, the light emitting element having one pad on a top surface thereof; forming a mask on the first surface, the mask covering the light emitting element and defining at least one opening for exposing the at least one pad; electrically connecting the at least one pad to the electrical structures via at least one metal wire; filling liquid encapsulating material in a space between the mask and the first surface to form an encapsulating layer that encapsulating the light emitting element, the encapsulating layer being separated from the at least one metal wire and comprising phosphors therein. | 2014-05-15 |
20140134767 | LED LIGHT SOURCE, ITS MANUFACTURING METHOD, AND LED-BASED PHOTOLITHOGRAPHY APPARATUS AND METHOD - Structurally-simple LED light source preventing temperature variations among multiple LED elements arranged densely on LED-mounting substrate is described. LED light source includes a plurality of LED elements each of which is formed by connecting an LED chip to electrodes formed on a ceramic substrate; LED-mounting substrate on which to mount the plurality of LED elements, the LED-mounting substrate having through holes therein; and heat sink plate for releasing heat from the LED-mounting substrate, wherein a thermally conductive resin is present between the LED-mounting substrate and the heat sink plate and wherein part of the thermally conductive resin protrudes from the through holes of the LED-mounting substrate and covers the top surface of the LED-mounting substrate on which the plurality of LED elements are mounted, so thermally conductive resin is in contact with the plurality of LED elements. | 2014-05-15 |
20140134768 | VAPOR DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - A vapor deposition apparatus for depositing a thin film on a substrate, by which a deposition process is efficiently performed and deposition film characteristics are easily improved, and a vapor deposition apparatus including: a stage onto which a substrate is disposed; and a supply unit disposed to face the substrate and having a main body member and a nozzle member disposed on one surface of the main body member facing the substrate, to sequentially supply a plurality of gases towards the substrate, and a method of manufacturing an organic light-emitting display apparatus using the same. | 2014-05-15 |
20140134769 | NANOSTRUCTURE OPTOELECTRONIC DEVICE WITH INDEPENDENTLY CONTROLLABLE JUNCTIONS - Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may have one or more intermediate electrical contacts that are physically and electrically connected to sidewalls of the array of nanostructures. The contacts may allow different photo-active regions of the optoelectronic device to be independently controlled. For example, one color light may be emitted or detected independently of another using the same group of one or more nanostructures. The optoelectronic device may be a pixilated device that may serve as an LED display or imaging sensor. The pixilated device may have an array of nanostructures with alternating rows and columns of sidewall electrical contacts at different layers. A pixel may be formed at the intersection of a row contact and a column contact. As one example, a single group of one or more nanostructures has a blue sub-pixel, a green sub-pixel, and a red sub-pixel. | 2014-05-15 |
20140134770 | METHODS OF MANUFACTURING OPTICAL FILTERS AND METHODS OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICES HAVING OPTICAL FILTERS - A method of manufacturing an optical filter includes preparing a substrate having a panel region, a peripheral region, and an alignment region, forming an outer black matrix on the substrate, such that the outer black matrix surrounds the panel region, forming a dummy black matrix on the substrate, such that the dummy black matrix is in the peripheral region while exposing the alignment region, forming a first color photoresist layer on the substrate to cover the outer black matrix and the dummy black matrix, forming a first color pattern in the panel region and an alignment pattern in the alignment region by patterning the first color photoresist layer, forming a second color photoresist layer on the substrate, forming a second color pattern in the panel region by patterning the second color photoresist layer, and forming a third color pattern in the panel region. | 2014-05-15 |
20140134771 | Light Emitting Device and Method of Manufacturing the Same - It is an object of the present invention to provide a high-contrast light-emitting device without using a polarization plate. In particular, it is an object of the present invention to make contrast control simpler for a light-emitting device provided with a color filter. | 2014-05-15 |
20140134772 | ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic electroluminescent (EL) display device and a method of manufacturing the same are provided. The organic electroluminescent display device includes a rear substrate, a organic EL portion formed on one surface of the rear substrate with a first electrode, an organic layer and a second electrode sequentially laminated. The front substrate is coupled to the rear substrate to seal an internal space in which the organic EL portion is accommodated, for isolating the organic EL portion from the outside. The front substrate further has a transparent moisture-absorbing layer coated on its internal surface. | 2014-05-15 |
20140134773 | Patterned Layer Design for Group III Nitride Layer Growth - A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. | 2014-05-15 |
20140134774 | METHOD FOR MAKING LIGHT EMITTING DIODE CHIP - A method for making a light emitting diode chip includes following steps: providing a sapphire substrate, the sapphire substrate having a plurality of protrusions on an upper surface thereof; forming an un-doped GaN layer on the upper surface of the sapphire substrate, the un-doped GaN layer partly covering the protrusions to expose a part of each of the protrusions; etching the un-doped GaN layer to expose a top end of each of the protrusions; and forming an n-type GaN layer, an active layer, and a p-type GaN layer sequentially on the top ends of the protrusions and the un-doped GaN layer. | 2014-05-15 |
20140134775 | LIGHT EMITTING DEVICES HAVING DISLOCATION DENSITY MAINTAINING BUFFER LAYERS - A method for forming a light emitting device comprises forming a buffer layer having a plurality of layers comprising a substrate, an aluminum gallium nitride layer adjacent to the substrate, and a gallium nitride layer adjacent to the aluminum gallium nitride layer. During the formation of each of the plurality of layers, one or more process parameters are selected such that an individual layer of the plurality of layers is strained. | 2014-05-15 |
20140134776 | DYE ADSORPTION DEVICE AND DYE ADSORPTION METHOD - The purpose of the present invention is to improve the throughput of a dye adsorption process in which a dye is adsorbed in a porous semiconductor layer on a substrate and to improve dye use efficiency. In a dye adsorption device of the present invention, a dye solution drop-coating unit | 2014-05-15 |
20140134777 | MANUFACTURING METHOD FOR SOLAR MODULE - Provided is a method for manufacturing solar modules with an improved yield. A heat and pressure applying step is performed in which an opposing solar cell ( | 2014-05-15 |
20140134778 | AQUEOUS ALKALINE COMPOSITIONS AND METHOD FOR TREATING THE SURFACE OF SILICON SUBSTRATES - An aqueous alkaline composition for treating the surface of silicon substrates, the said composition comprising: (A) a quaternary ammonium hydroxide; and (B) a component selected from the group consisting of water-soluble acids and their water-soluble salts of the general formulas (I) to (V): (R | 2014-05-15 |
20140134779 | METHOD OF PRODUCING EPITAXIAL SILICON WAFER, EPITAXIAL SILICON WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE - Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher gettering capability and a method of producing the epitaxial wafer. | 2014-05-15 |
20140134780 | METHOD OF PRODUCING EPITAXIAL SILICON WAFER, EPITAXIAL SILICON WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE - Provided is an epitaxial silicon wafer with reduced metal contamination achieved by higher gettering capability and a method of efficiently producing the same. | 2014-05-15 |
20140134781 | Solution Processed Metal Oxide Thin Film Hole Transport Layers For High Performance Organic Solar Cells - A method for the application of solution processed metal oxide hole transport layers in organic photovoltaic devices and related organic electronics devices is disclosed. The metal oxide may be derived from a metal-organic precursor enabling solution processing of an amorphous, p-type metal oxide. An organic photovoltaic device having solution processed, metal oxide, thin-film hole transport layer. | 2014-05-15 |
20140134782 | ULTRAVIOLET SENSOR AND METHOD FOR MANUFACTURING THE SAME - An ultraviolet sensor that includes a p-type semiconductor layer principally composed of (Ni, Zn)O, an n-type semiconductor layer composed of ZnO which is joined to the p-type semiconductor layer, an internal electrode embedded in the p-type semiconductor layer, and first and second terminal electrodes formed at both ends of the p-type semiconductor layer. The surface roughness of the p-type semiconductor layer is 1.5 μm or less, and preferably 0.3 μm or more and 1.0 μm or less. In a manufacturing process, the formed product prior to firing and/or the p-type semiconductor layer after firing is polished by barrel polishing so that the surface roughness Ra thereof is 1.0 μm or less. Thereby, light absorption efficiency can be improved to directly detect a desired large photocurrent and secure high reliability, and a spectral property can be controlled to strongly respond to various wavelength bands of ultraviolet light. | 2014-05-15 |
20140134783 | TANDEM SOLAR CELL - This application is related to a method of manufacturing a solar cell device comprising providing a substrate comprising Ge or GaAs; forming a first tunnel junction on the substrate, wherein the first tunnel junction comprises a first n-type layer comprising InGaP:Te, and a first alloy layer comprising AlxGa(1-x)As and having a lattice constant; adding a material into the first alloy layer to change the lattice constant; and forming a first p-n junction on the first tunnel junction. | 2014-05-15 |
20140134784 | METAL-BASED SOLUTION TREATMENT OF CIGS ABSORBER LAYER IN THIN-FILM SOLAR CELLS - A method for manufacturing a thin film solar cell device includes forming a back contact layer on a substrate, forming an CIGS absorber layer on the back contact layer, treating the CIGS absorber layer with a metal-based alkaline solution, and forming a buffer layer on the CIGS absorber layer where the treatment of the CIGS absorber layer improves the adhesion between the CIGS absorber layer and the buffer layer and also improves the quality of the p-n junction at the CIGS absorber layer/buffer layer interface. | 2014-05-15 |
20140134785 | SODIUM DOPED THIN FILM CIGS/CIGSS ABSORBER FOR HIGH EFFICIENCY PHOTOVOLTAIC DEVICES AND RELATED METHODS - A method of processing a thin-film absorber material with enhanced photovoltaic efficiency. The method includes providing a soda-lime glass substrate having a surface region and forming a barrier material overlying the surface region, followed by formation of a stack structure including a first thickness of a first precursor, a second thickness of a second precursor, and a third thickness of a third precursor. The first thickness of the first precursor is sputtered with a first target device including a first mixture of copper, gallium, and a first sodium species. The method further includes subjecting the soda-lime glass substrate having the stack structure in a thermal treatment process with at least H | 2014-05-15 |
20140134786 | CdTe Devices and Method of Manufacturing Same - A method of producing polycrystalline CdTe materials and devices that incorporate the polycrystalline CdTe materials are provided. In particular, a method of producing polycrystalline p-doped CdTe thin films for use in CdTe solar cells in which the CdTe thin films possess enhanced acceptor densities and minority carrier lifetimes, resulting in enhanced efficiency of the solar cells containing the CdTe material are provided. | 2014-05-15 |
20140134787 | SOLAR CELL CONTACT FORMATION USING LASER ABLATION - The formation of solar cell contacts using a laser is described. A method of fabricating a back-contact solar cell includes forming a poly-crystalline material layer above a single-crystalline substrate. The method also includes forming a dielectric material stack above the poly-crystalline material layer. The method also includes forming, by laser ablation, a plurality of contacts holes in the dielectric material stack, each of the contact holes exposing a portion of the poly-crystalline material layer; and forming conductive contacts in the plurality of contact holes. | 2014-05-15 |
20140134788 | METHOD OF FABRICATING A SOLAR CELL WITH A TUNNEL DIELECTRIC LAYER - Method of fabricating solar cells with tunnel dielectric layers are described. Solar cells with tunnel dielectric layers are also described. | 2014-05-15 |
20140134789 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 2014-05-15 |
20140134790 | Germanium Photodetector - A method for forming a photodetector device includes forming an insulator layer on a substrate, forming a germanium (Ge) layer on the insulator layer and a portion of the substrate, forming a second insulator layer on the Ge layer, patterning the Ge layer, forming a capping insulator layer on the second insulator layer and a portion of the first insulator layer, heating the device to crystallize the Ge layer resulting in an single crystalline Ge layer, implanting n-type ions in the single crystalline Ge layer, heating the device to activate n-type ions in the single crystalline Ge layer, and forming electrodes electrically connected to the single crystalline n-type Ge layer. | 2014-05-15 |
20140134791 | Solution-Processed Metal-Selenide Semiconductor Using Selenium Nanoparticles - A method is provided for forming a solution-processed metal and mixed-metal selenide semiconductor using selenium (Se) nanoparticles (NPs). The method forms a first solution including SeNPs dispersed in a solvent. Added to the first solution is a second solution including a first material set of metal salts, metal complexes, or combinations thereof, which are dissolved in a solvent, forming a third solution. The third solution is deposited on a conductive substrate, forming a first intermediate film comprising metal precursors, from corresponding members of the first material set, and embedded SeNPs. As a result of thermally annealing, the metal precursors are transformed and the first intermediate film is selenized, forming a first metal selenide-containing semiconductor. In one aspect, the first solution further comprises ligands for the stabilization of SeNPs, which are liberated during thermal annealing. In another aspect, the metal selenide-containing semiconductor comprises copper, indium, gallium diselenide (CIGS). | 2014-05-15 |
20140134792 | Solution-Processed Metal Selenide Semiconductor using Deposited Selenium Film - Methods are provided for fabricating a solution-processed metal and mixed-metal selenide semiconductor using a selenium (Se) film layer. One aspect provides a conductive substrate and deposits a first Se film layer over the conductive substrate. A first solution, including a first material set of metal salts, metal complexes, or combinations thereof, is dissolved in a solvent and deposited on the first Se film layer. A first intermediate film comprising metal precursors is formed from corresponding members of the first material set. In one aspect, a plurality of intermediate films is formed using metal precursors from the first material set or a different material set. In another aspect, a second Se film layer is formed overlying the intermediate film(s). Thermal annealing is performed in an environment including hydrogen (H | 2014-05-15 |
20140134793 | METHODS FOR MAKING LARGE-AREA, FREE-STANDING METAL OXIDE FILMS - The present invention provides continuous, free-standing metal oxide films and methods for making said films. The methods are able to produce large-area, flexible, thin films having one or more continuous, single-crystalline metal oxide domains. The methods include the steps of forming a surfactant monolayer at the surface of an aqueous solution, wherein the headgroups of the surfactant molecules provide a metal oxide film growth template. When metal ions in the aqueous solution are exposed to the metal oxide film growth template in the presence of hydroxide ions under suitable conditions, a continuous, free-standing metal oxide film can be grown from the film growth template downward into the aqueous solution. | 2014-05-15 |
20140134794 | Nonvolatile Memory Device Having An Electrode Interface Coupling Region - Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another. | 2014-05-15 |
20140134795 | SEMICONDUCTOR ELEMENT MANUFACTURING METHOD - There is provided a method of manufacturing a semiconductor element including: forming a semiconductor film of which a principal constituent is an oxide semiconductor; forming a first insulation film on a surface of the semiconductor film; applying a heat treatment in an oxidizing atmosphere; and, forming a second insulation film on a surface of the first insulation film, wherein a thickness of the first insulation film and a temperature of the heat treatment in the third step are adjusted such that, if the thickness of the first insulation film is represented by Z (nm), the heat treatment temperature is represented by T (° C.) and a diffusion distance of oxygen into the first insulation film and the semiconductor film is represented by L (nm), the relational expression 02014-05-15 | |
20140134796 | Method And System For A Semiconductor Device Package With A Die To Interposer Wafer First Bond - Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process. | 2014-05-15 |
20140134797 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips. | 2014-05-15 |
20140134798 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes. | 2014-05-15 |
20140134799 | WETTABLE LEAD ENDS ON A FLAT-PACK NO-LEAD MICROELECTRONIC PACKAGE - Methods of manufacturing a flat-pack no-lead microelectronic package ( | 2014-05-15 |
20140134800 | Methods For Temporary Wafer Molding For Chip-On-Wafer Assembly - Methods for temporary wafer molding for chip-on-wafer assembly may include bonding one or more semiconductor die to an interposer wafer, applying a temporary mold material to encapsulate the bonded die, and backside processing the interposer, which may be singulated to generate assemblies comprising the bonded die, the interposer die, which may be bonded to packaging substrates. The temporary mold material may be removed and the bonded die may be tested. Additional die may be bonded to the assemblies based on the electrical testing. The interposer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The backside processing may comprise thinning the interposer wafer to expose through-silicon-vias (TSVs) and placing metal contacts on the exposed TSVs. The die may be bonded to the interposer utilizing a mass reflow or thermal compression process. | 2014-05-15 |
20140134801 | Methods for Fabricating Integrated Passive Devices on Glass Substrates - A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers. | 2014-05-15 |
20140134802 | Chip-on-Wafer Structures and Methods for Forming the Same - A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level. | 2014-05-15 |
20140134803 | Method And System For A Semiconductor Device Package With A Die-To-Die First Bond - Methods for a semiconductor device package with a die-to-die first bond are disclosed and may include bonding one or more semiconductor die comprising electronic devices to an interposer die. An underfill material may be applied between the semiconductor die and the interposer die, and a mold material may be applied to encapsulate the semiconductor die. The interposer die may be thinned to expose through-silicon-vias (TSVs). The bonding of the semiconductor die may comprise adhering the semiconductor die to an adhesive layer, and bonding the semiconductor die to the interposer die. The semiconductor die may comprise micro-bumps for coupling to the interposer die, wherein the bonding comprises: positioning the micro-bumps in respective wells in a layer disposed on the interposer die; and bonding the micro-bumps to the interposer die. The semiconductor die may be bonded to the interposer die utilizing a mass reflow process or a thermal compression process. | 2014-05-15 |
20140134804 | Method And System For A Semiconductor For Device Package With A Die-To-Packaging Substrate First Bond - Methods and systems for a semiconductor device package with a die-to-packing substrate first bond are disclosed and may include bonding a first semiconductor die to a packaging substrate, applying an underfill material between the first semiconductor die and the packaging substrate, and bonding one or more additional die to the first semiconductor die. The additional die may comprise electronic devices. The first semiconductor die may comprise an interposer die or may comprise electronic devices. The first semiconductor die may be bonded to the packaging substrate utilizing a mass reflow process or a thermal compression process. The additional die may be bonded to the first die utilizing a mass reflow process or a thermal compression process. The bonded die may be encapsulated in a mold material, which may comprise a polymer. The one or more additional die may comprise micro-bumps for coupling to the first semiconductor die. | 2014-05-15 |
20140134805 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package is provided, including: providing a heat dissipating structure having a heat dissipating portion, a deformable supporting portion coupled to the heat dissipating portion, and a coupling portion coupled to the supporting portion; coupling a carrier having a semiconductor element carried thereon to the coupling portion of the heat dissipating structure to form between the carrier and the heat dissipating portion a receiving space for the semiconductor element to be received therein; and forming in the receiving space an encapsulant that encapsulates the semiconductor element. The use of the supporting portion enhances the bonding between the heat dissipating structure and a mold used for packaging, thereby preventing the heat dissipating structure from having an overflow of encapsulant onto an external surface of the heat-dissipating portion. | 2014-05-15 |
20140134806 | MANUFACTURING METHODS OF SEMICONDUCTOR SUBSTRATE, PACKAGE AND DEVICE - A manufacturing method of semiconductor substrate includes following steps: providing a base layer; forming a plurality of traces on the base layer; forming a plurality of studs correspondingly on the traces; forming a molding material layer on the base layer to encapsulate the traces and studs; forming a concave portion on the molding material layer; and, removing the base layer. | 2014-05-15 |
20140134807 | IGBT TRANSISTOR WITH PROTECTION AGAINST PARASITIC COMPONENT ACTIVATION AND MANUFACTURING PROCESS THEREOF - An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant regions, arranged at respective depths from the surface of the drift region. | 2014-05-15 |
20140134808 | RECESSED GATE FIELD EFFECT TRANSISTOR - A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode. | 2014-05-15 |
20140134809 | METHOD FOR MANUFACTURING FAN-OUT LINES ON ARRAY SUBSTRATE - A method for manufacturing fan-out lines on an array substrate is disclosed. The fan-out lines comprise an amorphous silicon layer, an ohmic contact layer and a source-drain electrode layer disposed on a gate insulating layer. The manufacturing processes can be conducted by forming a first layer of photoresist on the source-drain electrode layer and performing a half-exposure development process on the first layer of photoresist; etching the amorphous silicon layer, the ohmic contact layer and the source-drain electrode layer by an etching process; removing the first layer of photoresist; foiming a second layer of photoresist and performing full-exposure development process on the second layer of photoresist; and etching the amorphous silicon layer by etching process to form the fan-out lines. | 2014-05-15 |
20140134810 | Thin Film Transistor Substrate and Method for Fabricating the Same - The present invention relates to methods for fabricating a thin film transistor substrate. | 2014-05-15 |
20140134811 | CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES - First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate. | 2014-05-15 |
20140134812 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a trench in a substrate, forming a pre-gate insulating film along side surfaces and a bottom surface of the trench, and oxidizing the pre-gate insulating film through a densification process. | 2014-05-15 |
20140134813 | FABRICATION OF SHIELDED GATE TRENCH MOSFET WITH INCREASED SOURCE-METAL CONTACT - Fabricating a semiconductor device includes: forming a gate trench on a semiconductor substrate; forming a spacer inside the gate trench; forming one or more gate electrodes within the gate trench; implanting a body region; implanting a source region; forming a contact trench; disposing dielectric material within the gate trench; removing at least a portion of the dielectric material such that at least a portion of the source region extends above the dielectric material; and depositing a metal layer over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench. | 2014-05-15 |
20140134814 | METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING FINFET STRUCTURES WITH EPITAXIALLY FORMED SOURCE/DRAIN REGIONS - Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure. An un-merged source/drain region is formed in the void and a merged source/drain region is formed on the un-etched fin structure. | 2014-05-15 |
20140134815 | High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio - A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region. | 2014-05-15 |
20140134816 | Methods of Forming Metal Silicide-Comprising Material and Methods of Forming Metal Silicide-Comprising Contacts - A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material. | 2014-05-15 |
20140134817 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer. | 2014-05-15 |
20140134818 | METHOD FOR FORMING EPITAXIAL FEATURE - The present disclosure provides an integrated circuit device and method for manufacturing the integrated circuit device. The disclosed method provides substantially defect free epitaxial features. An exemplary method includes forming a gate structure over the substrate; forming recesses in the substrate such that the gate structure interposes the recesses; and forming source/drain epitaxial features in the recesses. Forming the source/drain epitaxial features includes performing a selective epitaxial growth process to form an epitaxial layer in the recesses, and performing a selective etch back process to remove a dislocation area from the epitaxial layer. | 2014-05-15 |
20140134819 | NANOPILLAR FIELD-EFFECT AND JUNCTION TRANSISTORS - Methods for fabrication of nanopillar field effect transistors are described. These transistors can have high height-to-width aspect ratios and be CMOS compatible. Silicon nitride may be used as a masking material. These transistors have a variety of applications, for example they can be used for molecular sensing if the nanopillar has a functionalized layer contacted to the gate electrode. The functional layer can bind molecules, causing an electrical signal in the transistor. | 2014-05-15 |
20140134820 | METHODS FOR PRODUCING BIPOLAR TRANSISTORS WITH IMPROVED STABILITY - Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface. | 2014-05-15 |
20140134821 | METHOD FOR FABRICATING CAPACITOR HAVING RUTILE TITANIUM OXIDE DIELECTRIC FILM - A method for fabricating a capacitor includes: (1) forming a bottom electrode on a substrate; (2) forming a template layer on the bottom electrode; (3) performing a plurality of atomic layer deposition (ALD) cycles by using water vapor as an oxidant thereby depositing a first TiO2 layer on the template layer; and (4) performing ozone pulse and purge step to transform entire thickness of the first TiO2 layer into rutile phase. | 2014-05-15 |
20140134822 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SEMICONDUCTIVE RESISTOR STRUCTURES IN A FINFET ARCHITECTURE - A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers. | 2014-05-15 |
20140134823 | HIGH-K PEROVSKITE MATERIALS AND METHODS OF MAKING AND USING THE SAME - High-k materials and devices, e.g., DRAM capacitors, and methods of making and using the same. Various methods of forming perovskite films are described, including methods in which perovskite material is deposited on the substrate by a pulsed vapor deposition process involving contacting of the substrate with perovskite material-forming metal precursors. In one such method, the process is carried out with doping or alloying of the perovskite material with a higher mobility and/or higher volatility metal species than the metal species in the perovskite material-forming metal precursors. In another method, the perovskite material is exposed to elevated temperature for sufficient time to crystallize or to enhance crystallization of the perovskite material, followed by growth of the perovskite material under pulsed vapor deposition conditions. Various perovskite compositions are described, including: (Sr, Pb)TiO | 2014-05-15 |
20140134824 | METHOD OF FABRICATING DIELECTRIC LAYER AND SHALLOW TRENCH ISOLATION - A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma. | 2014-05-15 |
20140134825 | LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE - A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer. | 2014-05-15 |
20140134826 | FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES - A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants. | 2014-05-15 |