20th week of 2020 patent applcation highlights part 66 |
Patent application number | Title | Published |
20200152725 | DISPLAY SUBSTRATE, DRIVING METHOD THEREOF, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - A display substrate, a method of driving the same, a method of manufacturing the same and a display device are provided. The display substrate includes a plurality of non-foldable display regions and a plurality of foldable display regions. The display substrate further includes a first signal line connected to a first electrode and a second signal line connected to a second electrode. The first signal line includes a plurality of secondary signal lines independent of each other. Each secondary signal line corresponds to one of the non-foldable display regions and is configured to control whether to supply power to the corresponding non-foldable display region. | 2020-05-14 |
20200152726 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - An organic light-emitting display device including a plurality of pixels, each of which includes an organic light-emitting device including a pixel electrode, an organic emission layer, and an opposing electrode; a pixel defining layer covering an edge of the pixel electrode and being configured to define a light-emission region by having an opening which exposes a portion of the pixel electrode; and a reference line overlapping the pixel electrode with an insulating layer between the reference line and the pixel electrode and extending in a first direction. The reference line overlaps with a center point of the opening, and the opening is shifted to one side of the pixel electrode in a second direction perpendicular to the first direction. | 2020-05-14 |
20200152727 | DISPLAY DEVICE - A display device includes a non-display area adjacent a display area, a thin film transistor, a display element, a thin film encapsulation layer, an organic insulating layer, a power voltage line, and a protective layer. The thin film transistor is on the display area and is connected to the display element. The thin film encapsulation layer covers the display element. The organic insulating layer is between the thin film transistor and display element and extends to the non-display area. The organic insulating layer includes a central portion corresponding to the display area, an outer portion surrounding the central portion, and a division region dividing the central portion and the outer portion and surrounding the display area. The power voltage line is in the non-display area and includes a portion corresponding to the division region. The protective layer covers an upper surface of the power voltage line in the division region. | 2020-05-14 |
20200152728 | SEMICONDUCTOR STRUCTURE HAVING INTEGRATED INDUCTOR THEREIN - A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer; wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm. | 2020-05-14 |
20200152729 | INTEGRATED TRENCH CAPACITOR FORMED IN AN EPITAXIAL LAYER - A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches. | 2020-05-14 |
20200152730 | VERTICAL PLATE CAPACITORS EXHIBITING HIGH CAPACITANCE MANUFACTURED WITH DIRECTED SELF-ASSEMBLY - A semiconductor structure includes a substrate and a first trench including a dielectric material disposed in the substrate. The first trench includes a transferred pattern of a first polymer of a directed self-assembly stack including the first polymer and a second polymer. The semiconductor structure also includes a second trench including a first vertical metal plate disposed in the substrate adjacent a first sidewall of the first trench, and a third trench including a second vertical metal plate disposed in the substrate adjacent a second sidewall of the first trench. The first vertical metal plate in the second trench, the dielectric material in the first trench, and the second vertical metal plate in the third trench provide a metal-insulator-metal vertical plate capacitor. | 2020-05-14 |
20200152731 | Etching Process Control in Forming MIM Capacitor - A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0. | 2020-05-14 |
20200152732 | CAPACITOR STRUCTURE - Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. | 2020-05-14 |
20200152733 | Semiconductor Device with Superjunction and Oxygen Inserted Si-Layers - A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. | 2020-05-14 |
20200152734 | NANOSHEET FIELD-EFFECT TRANSISTOR WITH SUBSTRATE ISOLATION - Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A sacrificial layer is epitaxially grown on a bulk semiconductor substrate, a plurality of epitaxial semiconductor layers are epitaxially grown over the sacrificial layer, and the sacrificial layer and the plurality of epitaxial semiconductor layers are patterned to form a fin. A first portion of the first sacrificial layer is removed to form a first cavity arranged between the plurality of epitaxial semiconductor layers and the bulk semiconductor substrate, and a first dielectric material is deposited in the first cavity. A second portion of the first sacrificial layer, which is located adjacent to the first dielectric material in the first cavity, is removed to form a second cavity between the first fin and the bulk semiconductor substrate. A second dielectric material is deposited in the second cavity. | 2020-05-14 |
20200152735 | FIN DAMAGE REDUCTION DURING PUNCH THROUGH IMPLANTATION OF FINFET DEVICE - Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer. | 2020-05-14 |
20200152736 | GATE CUT ISOLATION INCLUDING AIR GAP, INTEGRATED CIRCUIT INCLUDING SAME AND RELATED METHOD - A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap. | 2020-05-14 |
20200152737 | STACKED NANOSHEET TECHNOLOGY WITH UNIFORM VTH CONTROL - A stacked nanosheet semiconductor device and method of forming are provided. In an illustrative embodiment, a gate all around (GAA) stacked nanosheet field effect transistor (FET) includes a plurality of stacked semiconductor channel nanosheet layers and a dummy nanosheet layer formed above a top one of the stacked semiconductor channel nanosheet layers, the dummy nanosheet formed from a dielectric material. The GAA stacked nanosheet FET also includes a high dielectric constant (high-k) material formed around each of the plurality of stacked semiconductor channel nanosheet layers and around the dummy nanosheet layer and a first work function (WF) metal formed around the plurality of stacked semiconductor channel nanosheet layers and the dummy nanosheet layer. | 2020-05-14 |
20200152738 | INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES - A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region. | 2020-05-14 |
20200152739 | TRANSISTORS WITH LOW CONTACT RESISTANCE AND METHOD OF FABRICATING THE SAME - A transistor comprises a substrate, a first buffer layer on the substrate, a source region, a drain region, and a channel region on the first buffer layer, a gate on the channel region, a source contact, and a drain contact. The source contact is configured to contact at least three sides of the source region and the drain contact is configured to contact at least three sides of the drain region to lower contact resistance in the source region and in the drain region. | 2020-05-14 |
20200152740 | SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN REGION - A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction. | 2020-05-14 |
20200152741 | FIELD EFFECT TRANSISTOR WITH CONTROLLABLE RESISTANCE - A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer. | 2020-05-14 |
20200152742 | Fully Strained Channel - The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF | 2020-05-14 |
20200152743 | Method of Manufacturing Silicon Carbide Semiconductor Devices - A method of manufacturing a silicon carbide device includes: forming a trench in a process surface of a silicon carbide substrate that has a body layer forming second pn junctions with a drift layer structure, wherein the body layer is between the process surface and the drift layer structure and wherein the trench exposes the drift layer structure; implanting dopants through a bottom of the trench to form a shielding region that forms a first pn junction with the drift layer structure; forming dielectric spacers on sidewalls of the trench; and forming a buried portion of an auxiliary electrode in a bottom section of the trench, the buried portion adjoining the shielding region. | 2020-05-14 |
20200152744 | DIRECT FORMATION OF HEXAGONAL BORON NITRIDE ON SILICON BASED DIELECTRICS - A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN) | 2020-05-14 |
20200152745 | DIRECT FORMATION OF HEXAGONAL BORON NITRIDE ON SILICON BASED DIELECTRICS - A scalable process for fabricating graphene/hexagonal boron nitride (h-BN) heterostructures is disclosed herein. The process includes (BN) | 2020-05-14 |
20200152746 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer. | 2020-05-14 |
20200152747 | FIELD PLATE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; a semiconductor structure arranged on the substrate, the semiconductor structure including at least one first semiconductor layer; an insulator layer arranged on the semiconductor structure; a field plate covering a part of the insulator layer, wherein the insulator layer includes a non-linear dielectric material having a permittivity that decreases as an electric field traversing the dielectric material increases. | 2020-05-14 |
20200152748 | SEMICONDUCTOR DEVICE - In a trench-gate MOSFET, between a channel and an n | 2020-05-14 |
20200152749 | MIDDLE OF LINE STRUCTURES - The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers. | 2020-05-14 |
20200152750 | INTEGRATED CIRCUIT CONTACT STRUCTURES - Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element. | 2020-05-14 |
20200152751 | SOURCE AND DRAIN CONTACT CUT LAST PROCESS TO ENABLE WRAP-AROUND-CONTACT - A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions. | 2020-05-14 |
20200152752 | MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE - Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed. | 2020-05-14 |
20200152753 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate trench crossing an active region, and a gate structure in the gate trench. The gate structure includes a gate dielectric layer disposed on an inner wall of the gate trench, a gate electrode disposed on the gate electric layer and partially filling the gate trench, a gate capping insulating layer disposed on the gate electrode, and a gap-fill insulating layer disposed in the gate trench and disposed on the gate capping insulating layer. The gate capping insulating layer includes a material formed by oxidizing a portion of the gate electrode, nitriding the portion of the gate electrode, or oxidizing and nitriding the portion of the gate electrode. | 2020-05-14 |
20200152754 | SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND MEMORY CELL HAVING THE SAME - A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer. | 2020-05-14 |
20200152755 | VERTICAL FIN-TYPE BIPOLAR JUNCTION TRANSISTOR WITH SELF-ALIGNED BASE CONTACT - A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region. | 2020-05-14 |
20200152756 | SOURCE AND DRAIN CONTACT CUT LAST PROCESS TO ENABLE WRAP-AROUND-CONTACT - A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions. | 2020-05-14 |
20200152757 | METAL GATE STRUCTURE AND METHODS THEREOF - Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process. | 2020-05-14 |
20200152758 | MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR - An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10 | 2020-05-14 |
20200152759 | FORMATION OF AIR GAP SPACERS FOR REDUCING PARASITIC CAPACITANCE - A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions. | 2020-05-14 |
20200152760 | FORMATION OF AIR GAP SPACERS FOR REDUCING PARASITIC CAPACITANCE - A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions. | 2020-05-14 |
20200152761 | FORMATION OF AIR GAP SPACERS FOR REDUCING PARASITIC CAPACITANCE - A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions. | 2020-05-14 |
20200152762 | VERTICAL TRANSPORT FETS WITH ASYMMETRIC CHANNEL PROFILES USING DIPOLE LAYERS - Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric. | 2020-05-14 |
20200152763 | Method of Forming a Contact with a Silicide Region - Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region. | 2020-05-14 |
20200152764 | GATE SPACER AND INNER SPACER FORMATION FOR NANOSHEET TRANSISTORS HAVING RELATIVELY SMALL SPACE BETWEEN GATES - Embodiments of the invention are directed to method of fabricating a semiconductor device. A non-limiting embodiment of the method includes performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include forming gate spacers along a gate region of the nanosheet FET device, wherein each of the gate spacers comprises an upper segment and a lower segment. | 2020-05-14 |
20200152765 | FORMING REPLACEMENT LOW-K SPACER IN TIGHT PITCH FIN FIELD EFFECT TRANSISTORS - A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon. | 2020-05-14 |
20200152766 | VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR INCLUDING DUAL LAYER TOP SPACER - A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a multi-layer top spacer that includes an oxygen barrier layer beneath a top dielectric layer. Techniques for fabricating the transistor include depositing the oxygen barrier layer over the gate stack prior to depositing the top dielectric layer. The oxygen barrier layer blocks oxygen diffusion during deposition of the top dielectric layer, thereby avoiding damage to underlying interfacial and gate dielectric layers. | 2020-05-14 |
20200152767 | SELF-ALIGNED NANOWIRE - A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate. | 2020-05-14 |
20200152768 | METHOD OF FORMING FIN FORCED STACK INVERTER - A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method. | 2020-05-14 |
20200152769 | Vertical FET with Differential Top Spacer - VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided. | 2020-05-14 |
20200152770 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - In one aspect, a method of forming a semiconductor device includes removing a first dummy gate part extending across a first fin within a first gate trench section in an insulating layer, wherein the first dummy gate part is removed selectively to a second dummy gate part extending across a second fin within a second gate trench section in the insulating layer, and wherein each of the first and second fins is formed by a layer stack including a first layer and a second layer on the first layer, the first layer including Si | 2020-05-14 |
20200152771 | Selective Silicon Growth for Gapfill Improvement - Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film. | 2020-05-14 |
20200152772 | Method of Forming a Metal Gate Using Monolayers - Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer. | 2020-05-14 |
20200152773 | FIN STRUCTURES HAVING VARIED FIN HEIGHTS FOR SEMICONDUCTOR DEVICE - A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure. | 2020-05-14 |
20200152774 | GATE STRUCTURE OF FIELD EFFECT TRANSISTOR WITH FOOTING - In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure. | 2020-05-14 |
20200152775 | Structure of a Fin Field Effect Transistor (FinFET) - A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material. | 2020-05-14 |
20200152776 | Semiconductor Process for Quantum Structures with Staircase Active Well - A novel and useful modified semiconductor process having staircase active well shapes that provide variable distances between pairs of locations (i.e. quantum dots) resulting in modulation of the quantum interaction strength from weak/negligible at large separations to moderate and then strong at short separations. To achieve a modulation of the distance between pairs of locations, diagonal, lateral, and vertical quantum particle/state transport is employed. As examples, both implementations of semiconductor quantum structures with tunneling through an oxide layer and with tunneling through a local well depleted region are disclosed. These techniques are applicable to both planar semiconductor processes and 3D (e.g. Fin-FET) semiconductor processes. Optical proximity correction is used to accommodate the staircase well layers. Each gate control circuit in the imposer circuitry functions to control more than one set of control gates. Thus, each gate control circuit is shared across several qubits which are located sufficiently far from each other to prevent interference. This substantially reduces the number of control signals and control logic that required in the structure. | 2020-05-14 |
20200152777 | INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - An insulated gate bipolar transistor includes: a semiconductor substrate; an emitter electrode arranged on one main surface of the semiconductor substrate; and a trench gate arranged in a rectangular trench having a rectangular shape and disposed on the one main surface of the semiconductor substrate. The semiconductor substrate includes a body contact region and an emitter region in a rectangular region surrounded by the rectangular trench. The rectangular trench has a straight trench that constitutes one side of the rectangular trench. The body contact region is in contact with a side of the straight trench. The emitter region is in contact with the side of the straight trench, and is adjacent to the body contact region. The body contact region has a protrusion portion protruding in a depth direction from a center portion of the body contact region. | 2020-05-14 |
20200152778 | SEMICONDUCTOR DEVICE - A doping concentration distribution in an accumulation region in a depth direction of a semiconductor substrate has a maximum portion at which a doping concentration reaches a maximum value, an upper gradient portion in which the concentration decreases from the maximum portion to a base region, and a lower gradient portion in which the concentration decreases from the maximum portion to a drift region. When a full width at half maximum determined by setting a depth position of the maximum portion as a range of impurity implantation with reference to a range-full width at half maximum characteristic according to a material of the substrate and a type of impurities contained in the accumulation region is set as a standard full width at half maximum, a full width at half maximum of the distribution in the accumulation region is 2.2 times the standard full width at half maximum or greater. | 2020-05-14 |
20200152779 | NORMALLY-OFF HEMT TRANSISTOR WITH SELECTIVE GENERATION OF 2DEG CHANNEL, AND MANUFACTURING METHOD THEREOF - A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer. | 2020-05-14 |
20200152780 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Semiconductor device and fabrication method are provided. The method includes providing a substrate with a fin including a plurality of channel layers and a sacrificial layer; forming a dummy gate structure across the fin; forming first grooves in the fin on two sides of the dummy gate structure; forming a first protection layer on sidewalls of the first channel layer and the dummy gate structure; forming second grooves by etching the fin at bottoms of the first grooves; removing a portion of sidewalls of the initial second channel layer to form a second channel layer; removing the first protection layer; forming a doped source/drain layer in the first grooves and the second grooves; forming a dielectric layer over the substrate and the fin; removing the dummy gate structure and the sacrificial layers to form a gate opening; and forming a gate structure in the gate opening. | 2020-05-14 |
20200152781 | SEMICONDUCTOR DEVICES WITH METAL CONTACTS INCLUDING CRYSTALLINE ALLOYS - Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less. | 2020-05-14 |
20200152782 | Structure and Method for FinFET Device with Contact Over Dielectric Gate - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate. | 2020-05-14 |
20200152783 | NON-CONTACT MEASUREMENT OF A STRESS IN A FILM ON A SUBSTRATE - A method for non-contact measurement of stress in a thin-film deposited on a substrate is disclosed. The method may include measuring first topography data of a substrate having a thin-film deposited thereupon. The method may also include comparing the first topography data with second topography data of the substrate that is measured prior to thin-film deposition. The method may further include obtaining a vertical displacement of the substrate based on the comparison between the first topography data and the second topography data. The method may also include detecting a stress value in the thin-film deposited on the substrate based on a fourth-order polynomial equation and the vertical displacement. | 2020-05-14 |
20200152784 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD FOR THE SAME - The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner. | 2020-05-14 |
20200152785 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·μm·cm | 2020-05-14 |
20200152786 | VERTICAL BI-DIRECTIONAL SWITCHES AND METHOD FOR MAKING SAME - A vertical bi-directional device includes first and second conductive gates in a semiconductor layer with a first vertical gate oxide on a sidewall of the first conductive gate and a second vertical gate oxide on a sidewall of the second conductive gate. A first heavily doped region of a first conductivity type is at the surface adjacent the first conductive gate, and a second heavily doped region of the first conductive type is at the surface adjacent to the second conductive gate. Doped regions of the first conductivity type extend below the conductive gates towards a substrate. A doped region of a second conductivity type extends laterally from the first vertical gate oxide to the second vertical gate oxide, and a heavily doped region of the second conductivity type is at the surface of the semiconductor layer, between the first and second heavily doped regions of the first conductivity type. | 2020-05-14 |
20200152787 | LATERAL INSULATED-GATE BIPOLAR TRANSISTOR AND METHOD THEREFOR - A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region. | 2020-05-14 |
20200152788 | DRAIN EXTENDED TRANSISTOR WITH TRENCH GATE - A semiconductor device includes a semiconductor substrate with a trench, a body region under the trench with majority carrier dopants of a first type, and a transistor, including a source region under the trench with majority carrier dopants of a second type, a drain region spaced from the trench with majority carrier dopants of the second type, a gate structure in the trench proximate a channel portion of a body region, and an oxide structure in the trench proximate a side of the gate structure. | 2020-05-14 |
20200152789 | TUNNEL FIELD-EFFECT TRANSISTOR WITH REDUCED SUBTHRESHOLD SWING - A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer. | 2020-05-14 |
20200152790 | TUNNEL FIELD-EFFECT TRANSISTOR WITH REDUCED SUBTHRESHOLD SWING - A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer. | 2020-05-14 |
20200152791 | VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR STRUCTURE WITH SELF-ALIGNED TOP JUNCTION THROUGH EARLY TOP SOURCE/DRAIN EPITAXY - A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer. | 2020-05-14 |
20200152792 | Semiconductor Structure and Methods of Forming Same - A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin. | 2020-05-14 |
20200152793 | CHANNEL CONDUCTIVITY IN MEMORY STRUCTURES - A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel. | 2020-05-14 |
20200152794 | MULTI-GATE DEVICE AND METHOD OF FABRICATION THEREOF - A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer. | 2020-05-14 |
20200152795 | FLAT STI SURFACE FOR GATE OXIDE UNIFORMITY IN FIN FET DEVICES - Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment. | 2020-05-14 |
20200152796 | SEMICONDUCTOR DEVICE - A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity. | 2020-05-14 |
20200152797 | NANOWIRE STRUCTURES HAVING NON-DISCRETE SOURCE AND DRAIN REGIONS - Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires. | 2020-05-14 |
20200152798 | VERTICAL NANO-WIRE COMPLIMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR WITH CYLINDRICAL III-V COMPOUND AND GERMANIUM CHANNEL - A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a first source/drain layer in contact with at least the substrate. A vertical channel including indium gallium arsenide or germanium contacts at least the first/source drain layer. A gate structure contacts at least the vertical channel. A second source/drain layer contacts at least inner sidewalls of the vertical channel. The method includes epitaxially growing one or more fin structures comprising gallium arsenide in contact with a portion of a substrate. A separate channel layer comprising indium gallium arsenide or germanium is formed in contact with a respective one of the one or more fin structures. | 2020-05-14 |
20200152799 | THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY, AND METHOD FOR DETECTING AN OBJECT TO BE DETECTED - The present disclosure provides a thin film transistor, a thin film transistor array, and a method for detecting an object to be detected, wherein the thin film transistor is configured to detect a parameter of an object to be detected bound with a metal ion and includes an active layer, wherein: a carrier of the active layer without a metal element contained in the metal ion bound is of a first mobility, and a carrier of the active layer with the metal element bound is of a second mobility different from the first mobility. | 2020-05-14 |
20200152800 | CMOS INVERTER AND ARRAY SUBSTRATE - The present invention provides a CMOS inverter and array substrate. The CMOS inverter comprises a P-type low-temperature polysilicon thin film transistor electrically coupled to a N-type metal-oxide thin film transistor; the P-type low-temperature polysilicon thin film transistor and the N-type metal-oxide thin film transistor satisfy the relationship: | 2020-05-14 |
20200152801 | NANOSHEET FIELD EFFECT TRANSISTOR CELL ARCHITECTURE - A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance. | 2020-05-14 |
20200152802 | ACTIVE-MATRIX SUBSTRATE AND DISPLAY DEVICE - An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer. When viewed in a normal direction of the substrate, the upper gate electrode does not overlap a first electrode which is one of the source electrode and the drain electrode, and a second electrode which is the other of the source electrode and the drain electrode does not overlap the lower gate electrode. | 2020-05-14 |
20200152803 | SEMICONDUCTOR DEVICE - Gate fingers ( | 2020-05-14 |
20200152804 | STRESS SENSOR SUITABLE FOR MEASURING MECHANICAL STRESS IN A LAYERED METALLIZATION STRUCTURE OF A MICROELECTRONIC COMPONENT - A sensor for measuring mechanical stress in a layered metallization structure such as the back end of line portion of an integrated circuit die is provided. The sensor operates as a field effect transistor comprising a gate electrode, gate dielectric, channel and source and drain electrodes, wherein the gate electrode is a conductor of a first metallization level and the source and drain electrodes are two interconnect vias, connecting the channel to respective conductors in an adjacent level. At least one of the interconnect vias is formed of a material whereof the electrical resistance is sensitive to mechanical stress in the direction of the via. The sensitivity of the electrical resistance to the mechanical stress is sufficient to facilitate measurement of the stress by reading out the drain current of the transistor. The sensor thereby allows monitoring of stress in the BEOL prior to cracking. | 2020-05-14 |
20200152805 | SEMICONDUCTOR DEVICE - A semiconductor device with an enhanced semiconductor characteristics that is useful for power devices. A semiconductor device including: a semiconductor region; a barrier electrode arranged on the semiconductor region; and two or more adjustment regions of barrier height that are on a surface of the semiconductor region and arranged between the semiconductor region and the barrier electrode, the adjustment regions are configured such that barrier height at an interface between the adjustment regions and the barrier electrode is higher than barrier height at an interface between the semiconductor region and the barrier electrode. | 2020-05-14 |
20200152806 | Schottky Device and Method of Manufacturing the Same - A Schottky device includes a silicon carbide (SiC) substrate of a first conductivity type, a drift layer of the first conductivity type, a trench, a barrier layer of a second conductivity type, an electrically conductive material that at least partially fills the trench and contacts the barrier layer, a first electrode, and a second electrode. The drift layer is formed of SiC and is situated onto the SiC substrate. The trench extends from the top surface of the drift layer towards the SiC substrate. The barrier layer contacts the drifting layer and covers a sidewall and a bottom wall of the trench. The first electrode forms a Schottky junction with the drift layer and forms a low resistivity contact with the barrier layer and the electrically conductive material. The second electrode forms an ohmic contact with the SiC substrate. | 2020-05-14 |
20200152807 | SPAD DEVICE FOR EXCESS BIAS MONITORING - The SPAD device comprises a single-photon avalanche diode and a further single-photon avalanche diode having breakdown voltages, the single-photon avalanche diodes being integrated in the same device. The breakdown voltages are equal or differ by less than 10%. The single-photon avalanche diode is configured to enable to induce triggering or to have a dark count rate that is higher than the dark count rate of the further single-photon avalanche diode. | 2020-05-14 |
20200152808 | BROADBAND MULTI-PURPOSE OPTICAL DEVICE AND METHODS OF MANUFACTURING AND OPERATING THE SAME - A broadband multi-purpose optical device includes a semiconductor layer having a light absorption characteristic, a first active layer having a light absorption band different from a light absorption band of the semiconductor layer, a first two-dimensional (2D) material layer adjacent to the first active layer, and a first interfacial layer configured to control a pinning potential of the semiconductor layer and the first active layer. The broadband multi-purpose optical device may further include at least one second active layer, and may include a tandem structure that further includes at least one second 2D material layer. The first active layer and the second active layer may have different light absorption bands. The broadband multi-purpose optical device may further include a second interfacial layer adjacent to the first 2D material layer. | 2020-05-14 |
20200152809 | DOUBLE LAYERED TRANSPARENT CONDUCTIVE OXIDE FOR REDUCED SCHOTTKY BARRIER IN PHOTOVOLTAIC DEVICES - A device and method for fabricating a photovoltaic device includes forming a double layer transparent conductive oxide on a transparent substrate. The double layer transparent conductive oxide includes forming a doped electrode layer on the substrate, and forming a buffer layer on the doped electrode layer. The buffer layer includes an undoped or p-type doped intrinsic form of a same material as the doped electrode layer. A light-absorbing semiconductor structure includes a p-type semiconductor layer on the buffer layer, an intrinsic layer and an n-type semiconductor layer. | 2020-05-14 |
20200152810 | CONDUCTIVE PASTE, ELECTRODE AND SOLAR CELL - The present invention relates to a conductive paste for forming a conductive track or coating on a substrate, particularly suitable for use in solar cells. The paste comprises a solids portion dispersed in an organic medium, the solids portion comprising electrically conductive material and an inorganic particle mixture wherein the inorganic particle mixture comprises substantially crystalline particles. The present invention also relates to a method of preparing a conductive paste, a method for the manufacture of a surface electrode of a solar cell, an electrode for a solar cell and a solar cell. | 2020-05-14 |
20200152811 | FLEXIBLE AND STRECHABLE IMAGER, METHOD OF MAKING A FLEXIBLE AND STRETCHABLE IMAGER, AND METHOD OF USING AN IMAGING DEVICE HAVING A FLEXIBLE AND STRETCHABLE IMAGER - A flexible and stretchable imager includes a first rigid substrate carrying at least one first photodetector, a second rigid substrate carrying at least one second photodetector, and a flexible and stretchable arm connected to the first and second rigid substrates. The first rigid substrate, the second rigid substrate, and the flexible and stretchable arm are made of a same material. | 2020-05-14 |
20200152812 | STABLE PEROVSKITE MODULE INTERCONNECTS - Thin-film solar cell modules and serial cell-to-cell interconnect structures and methods of fabrication are described. In an embodiment, solar cell module and interconnect includes a conformal transport layer over a subcell layer. The conformal transport layer may also laterally surround an outside perimeter the subcell layer. | 2020-05-14 |
20200152813 | ONE-DIMENSIONAL METALLIZATION FOR SOLAR CELLS - Approaches for fabricating one-dimensional metallization for solar cells, and the resulting solar cells, are described. In an example, a solar cell includes a substrate having a back surface and an opposing light-receiving surface. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the back surface of the substrate and parallel along a first direction to form a one-dimensional layout of emitter regions for the solar cell. A conductive contact structure is disposed on the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal lines corresponding to the plurality of alternating N-type and P-type semiconductor regions. The plurality of metal lines is parallel along the first direction to form a one-dimensional layout of a metallization layer for the solar cell. | 2020-05-14 |
20200152814 | Nanoscale solar energy conversion - A system for converting solar energy to electric power and a glass for a layer of solar cells in the system. A solar panel installation comprises a solar panel with at least one solar cell formed with a stack of plural layers of photovoltaic wafer material. Each layer of wafer material has an edge direction from a recipient edge to a back edge, and the solar cell is retained within the solar panel installation with the photovoltaic wafer material disposed with the edge direction aligned with incident solar direction. Reflective material applied to facing surfaces of the photovoltaic wafer material facilitates internal reflection of photons. A glass layer has plural sheets of Graphene layered to form a Graphene Cube constructed to exhibit Multiple Excitation Generation (MEG). A method for assembling the glass fixes a top glass above a bottom glass with photovoltaic wafer material establishing a fixed distance therebetween. | 2020-05-14 |
20200152815 | High Work Function MoO2 Back Contacts for Improved Solar Cell Performance - Improved high work function back contacts for solar cells are provided. In one aspect, a method of forming a solar cell includes: forming a completed solar cell having a substrate coated with an electrically conductive material, an absorber disposed on the electrically conductive material, a buffer layer disposed on the absorber, a transparent front contact disposed on the buffer layer, and a metal grid disposed on the transparent front contact; removing the substrate and the electrically conductive material using exfoliation, exposing a backside surface of the solar cell; depositing a high work function material onto the back side surface of the solar cell; and depositing a back contact onto the high work function material. A solar cell formed by the present techniques is also provided. Yield of the exfoliated device can be improved by removing bubbles from adhesive used for exfoliation and/or forming contact pads to access the metal grid. | 2020-05-14 |
20200152816 | Optoelectronic Semiconductor Component - An optoelectronic semiconductor component is disclosed. In an embodiment an optoelectronic semiconductor component includes a front side, a first diode and a second diode arranged downstream of one another in a direction away from the front side and electrically connected in series such that the first diode is located closer to the front side than the second diode and an electrical tunnel contact between the first and the second diodes, wherein the second diode comprises a diode layer of Si | 2020-05-14 |
20200152817 | PHOTO DETECTION ELEMENT, OPTICAL SENSOR, AND METHOD OF MANUFACTURING PHOTO DETECTION ELEMENT - A photo detection element includes: a substrate; a light-receiving layer formed over the substrate, the light-receiving layer including graphene layers and spacer layers that are alternately stacked, light passing through each of the spacer layers, the spacer layers being made of insulating material; a first electrode that is in contact with the light-receiving layer; and a second electrode that is in contact with the light-receiving layer, a material of the second electrode being different from a material of the first electrode. | 2020-05-14 |
20200152818 | PROXIMITY SENSING MODULE WITH DUAL TRANSMITTERS - A proximity sensing module with dual transmitters includes a circuit board, a package housing, a sensing assembly and a transmitter unit. The sensing assembly includes a sensor disposed on the circuit board. The transmitter unit is shielded from the sensing assembly through the package housing and includes a first transmitter and a second transmitter both disposed on the circuit board. One of the first transmitter and the second transmitter is closer to the sensing assembly. | 2020-05-14 |
20200152819 | SOLAR CELL AND METHOD FOR PREPARING SAME - A method for preparing a solar cell, includes: forming a first electrode on a substrate; forming a light absorbing layer on the first electrode; and forming a second electrode on the light absorbing layer, wherein the method further comprises forming an impurity material layer including an impurity element on the light absorbing layer adjacent to the first electrode or the second electrode in any one side or both sides thereof, and forming a doping layer by diffusing the impurity element into a portion of the light absorbing layer. | 2020-05-14 |
20200152820 | RADIATION DETECTOR AND A METHOD OF MAKING IT - Disclosed herein are a radiation detector and a method of making it. The radiation detector is configured to absorb radiation particles incident on a semiconductor single crystal of the radiation detector and to generate charge carriers.. The semiconductor single crystal may be a CdZnTe single crystal or a CdTe single crystal. The method may comprise forming a recess into a substrate of semiconductor; forming a semiconductor single crystal in the recess; and forming a heavily doped semiconductor region in the substrate. The semiconductor single crystal has a different composition from the substrate. The heavily doped region is in electrical contact with the semiconductor single crystal and embedded in a portion of intrinsic semiconductor of the substrate. | 2020-05-14 |
20200152821 | Fabrication Processes for Effectively Transparent Contacts - In conventional solar cells with metal contacts, a non-negligible fraction of the incoming solar power is immediately lost either through absorption or reflection upon interaction with the contacts. Effectively transparent contacts (“ETCs”) for solar cells can be referred to as three-dimensional contacts designed to redirect incoming light onto a photoabsorbing surface of a solar cell. In many embodiments, the ETCs have triangular cross-sections. Such ETCs can be placed on a photoabsorbing surface such that at least one of their sides forms an angle with the photoabsorbing surface. In this configuration, the ETCs can redirect incident light onto the photoabsorbing surface, mitigating or eliminating reflection loss compared to conventional solar cells. When constructed in accordance with a number of embodiments of the invention, ETCs can be effectively transparent and highly conductive. | 2020-05-14 |
20200152822 | Method for Producing an Electronic Device and Electronic Device - A method for producing an electronic device and an electronic device are disclosed. In an embodiment a method for producing an electronic device includes attaching semiconductor chips on a carrier, applying a fluoropolymer to main surfaces of the semiconductor chips facing away from the carrier and a main surface of the carrier facing the semiconductor chip thereby forming an encapsulation layer including a fluoropolymer, structuring the encapsulation layer thereby forming cavities in the encapsulation layer and applying a metal layer in the cavities. | 2020-05-14 |
20200152823 | LIGHT-EMITTING METAL-OXIDE-SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS - Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light. | 2020-05-14 |
20200152824 | METHOD FOR FABRICATING GRAPHENE LIGHT EMITTING TRANSISTOR - A method is provided for fabricating a graphene light emitting transistor. The method includes: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate and the gate electrode; forming a graphene oxide layer on the gate insulating layer; reducing two ends of the graphene oxide layer to respectively form a source electrode and a drain electrode made of graphene; forming a graphene quantum dot layer on an unreduced part of the graphene oxide layer, the source electrode, and the drain electrode; and forming a water and oxygen resistant layer on the graphene quantum dot layer. | 2020-05-14 |