20th week of 2015 patent applcation highlights part 17 |
Patent application number | Title | Published |
20150129925 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer opposing to a bottom surface and a side surface of a gate electrode. An insulation film is provided between the bottom surface of the gate electrode and the semiconductor layer and between the side surface of the gate electrode and the semiconductor layer. A first conduction-type drain layer is provided in the semiconductor layer on a side of an end part of one of the bottom surface and the side surface of the gate electrode. A second conduction-type source layer is provided in the semiconductor layer opposing to the other one of the bottom surface and the side surface of the gate electrode. A second conduction-type extension layer is provided in the semiconductor layer opposing to a corner part between the side surface and the bottom surface of the gate electrode and has a lower impurity concentration than that of the source layer. | 2015-05-14 |
20150129926 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A field effect transistor is provided. The field effect transistor includes a semiconductor region formed on a substrate, wherein the semiconductor region comprises an undoped channel region, a source region including a first dopant type, and a drain region including a second dopant type, and wherein the channel region is formed of a group III-V compound semiconductor material. The field effect transistor further includes a high-K gate formed on the channel region, wherein the high-K gate is configured to generate electron tunneling between the source region and the drain region when a gate voltage is applied, and wherein a first contact surface between the source region and the channel region and a second contact surface between the drain region and the channel region are inclined. | 2015-05-14 |
20150129927 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductivity-type drift layer, a second conductivity-type base layer formed in a front surface portion of the drift layer, a second conductivity-type collector layer formed in the drift layer and separated from the base layer, gate insulation layers formed on a surface of the base layer, gate electrodes individually formed on the gate insulation layers, an emitter layer formed in a front surface portion of the base layer, an emitter electrode electrically connected to the emitter layer and the base layer, and a collector electrode electrically connected to the collector layer. A rate of change in a gate voltage of a part of the gate electrodes is smaller than a rate of change in a gate voltage of a remainder of the gate electrodes. The emitter layer is in contact with only the gate insulation layers provided with the part of the gate electrodes. | 2015-05-14 |
20150129928 | PACKAGED SEMICONDUCTOR DEVICE, A SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A PACKAGED SEMICONDUCTOR DEVICE - A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region. At least part of the second P-type region is arranged in between the first semiconductor component and the second semiconductor component, and at least part of the third N-type region is arranged in between the at least part of the first P-type region and the second semiconductor component. | 2015-05-14 |
20150129929 | Semiconductor Device - A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage enhancement-mode transistor. The high voltage depletion-mode transistor is stacked on the low voltage enhancement-mode transistor so that an interface is formed between the high voltage depletion-mode transistor and the low voltage enhancement-mode transistor. The low voltage enhancement-mode transistor includes a current path coupled in series with a current path of the high voltage depletion-mode transistor, and a control electrode is arranged at the interface. | 2015-05-14 |
20150129930 | INSULATING GATE-TYPE BIPOLAR TRANSISTOR - An object of the present invention is to provide a trench gate type IGBT achieving both retention of withstand voltage and lowering of ON-state voltage and to provide a method for manufacturing the trench gate type IGBT. The IGBT according to the present invention is an SJ-RC-IGBT which includes a drift layer having super junction structure, and includes an IGBT area and an FWD area on the rear surface. In the IGBT according to the present invention, a first drift layer has an impurity concentration of 1×10 | 2015-05-14 |
20150129931 | TRANSISTOR, METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel. | 2015-05-14 |
20150129932 | SYSTEMS AND METHODS FOR A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE SEMICONDUCTOR-DEVICE LAYERS - A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the channel material is different from the lattice constant of the bulk substrate to introduce strain to the channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate. | 2015-05-14 |
20150129933 | TUCK STRATEGY IN TRANSISTOR MANUFACTURING FLOW - When forming field effect transistors with a semiconductor alloy layer, e.g., SiGe, embedded in the source/drain regions, a strategy called tucking has been developed in order to improve formation of the semiconductor alloy layer. An improved tucking strategy is hereby proposed, wherein the interface between the isolation region and the active region is not straight, but it rather defines an indentation, so that the active region protrudes into the isolation region in correspondence to the indentation. A gate is then formed on the surface of the device in such a way that a portion of the indentation is covered by the gate. An etching process is then performed, during which the gate acts as a screen. The etching thus gives rise to a cavity defined by a sidewall comprising portions exposing silicon, alternated to portions exposing the dielectric material of the isolation region. | 2015-05-14 |
20150129934 | METHODS OF FORMING SUBSTANTIALLY SELF-ALIGNED ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device. | 2015-05-14 |
20150129935 | Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells - A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed. | 2015-05-14 |
20150129936 | Biosensor Device and Related Method - A device includes a biosensor, a sensing circuit electrically connected to the biosensor, a quantizer electrically connected to the sensing circuit, a digital filter electrically connected to the quantizer, a selective window electrically connected to the digital filter, and a decision unit electrically connected to the selective window. | 2015-05-14 |
20150129937 | SEMICONDUCTOR DEVICE AND SELECTIVE HEATING THEREOF - One or more semiconductor devices and array arrangements and methods of formation are provided. A semiconductor device includes an ion sensing device and a heating element proximate the ion sensing device. The ion sensing device has an active region, including a source, a drain, and a channel, the channel situated between the source and the drain. The ion sensing device also has an ion sensing film situated over the channel, and an ion sensing region over the ion sensing film. Responsive to a temperature sensed by a thermal sensor proximate the ion sensing device, the heating element is selectively activated to alter a temperature of the ion sensing region to promote desired operation of the semiconductor device, such as to function as a bio sensor. Multiple semiconductor devices can be formed into an array. | 2015-05-14 |
20150129938 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region. | 2015-05-14 |
20150129939 | METHOD AND STRUCTURE FOR FORMING CONTACTS - Embodiments of the present invention provide an improved structure and method for forming high aspect ratio contacts. A horizontally formed contact etch stop layer is deposited in a narrow area where a contact is to be formed. A gas cluster ion beam (GCIB) process is used in the deposition of the horizontally formed contact etch stop layer. | 2015-05-14 |
20150129940 | MECHANISM FOR FORMING GATE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure. | 2015-05-14 |
20150129941 | DEVICE AND STRUCTURE AND METHOD FOR FORMING THE SAME - In various embodiments, a method for forming a device may be provided. The method may include forming a contact layer at least partially on a substrate. The method may also include forming a device structure adhered to the contact layer. In addition, the method may include depositing a transfer medium such that the device structure is at least partially covered by the transfer medium. The method may further include solidifying the transfer medium. The method may also include separating the contact layer, the device structure and the transfer medium from the substrate. The contact layer may have a greater adhesion to the device structure than to the substrate. | 2015-05-14 |
20150129942 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. A semiconductor structure includes a device substrate, a conductive film, a dielectric film and a conductive plug. The device substrate includes a semiconductor substrate and a conductive structure on an active surface of the semiconductor substrate. The device substrate has a substrate opening passing through the semiconductor substrate and exposing the conductive structure. The conductive film, the conductive plug and the dielectric film between the conductive film and the conductive plug are disposed in the substrate opening. | 2015-05-14 |
20150129943 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - Provided is a solid-state imaging device including a lamination-type backside illumination CMOS (Complementary Metal Oxide Semiconductor) image sensor having a global shutter function. The solid-state imaging device includes a separation film including one of a light blocking film and a light absorbing film between a memory and a photo diode. | 2015-05-14 |
20150129944 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion. | 2015-05-14 |
20150129945 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory includes a semiconductor layer including a trench which extends in a first direction, the trench having a first portion with a first depth and a second portion with a second depth deeper than the first depth, a gate insulating layer covering the semiconductor layer in the first portion, an element isolation layer covering the semiconductor layer in the second portion, the element isolation layer extending in a second direction from the second portion, a gate electrode provided on the gate insulating layer in the first portion and the element isolation layer in the second portion, the gate electrode filling the trench, and a third impurity region provided in the semiconductor layer direct below the first portion, the third impurity region being continuously in the first direction. | 2015-05-14 |
20150129946 | SELF REFERENCE THERMALLY ASSISTED MRAM WITH LOW MOMENT FERROMAGNET STORAGE LAYER - A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM) with reduced power for reading and writing. A tunnel barrier is disposed adjacent to a ferromagnetic sense layer and a ferromagnetic storage layer, such that the tunnel barrier is sandwiched between the ferromagnetic sense layer and the ferromagnetic storage layer. An antiferromagnetic pinning layer is disposed adjacent to the ferromagnetic storage layer. The pinning layer pins a magnetic moment of the storage layer until heating is applied. The storage layer includes a non-magnetic material to reduce a storage layer magnetization as compared to not having the non-magnetic material. The sense layer includes the non-magnetic material to reduce a sense layer magnetization as compared to not having the non-magnetic material. A reduction in the storage layer magnetization and sense layer magnetization reduces the magnetostatic interaction between the storage layer and sense layer, resulting in less read/write power. | 2015-05-14 |
20150129947 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes a NAND string including memory cells disposed in a first direction and a select gate disposed first-directionally adjacent to a first memory cell located at an end of the memory cells. A first gap is disposed between the memory cells and a second gap is disposed between the first memory cell and the select gate. Further, in a cross sectional shape, an upper end of the second gap is higher than an upper end of a first gap and an upper portion of the second gap is curved. | 2015-05-14 |
20150129948 | INSULATING FILM AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - It is made possible to provide an insulating film that can reduce the leakage current. An insulating film includes: an amorphous oxide dielectric film containing a metal, hydrogen, and nitrogen. The nitrogen amount [N] and the hydrogen amount [H] in the oxide dielectric film satisfy the following relationship: | 2015-05-14 |
20150129949 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a substrate including a device isolation layer defining an active region, a floating gate and a selection gate arranged side by side at intervals of a first gap over the substrate, a coupling plate formed in the device isolation layer and overlapped with the floating gate, and a contact plug suitable for electrically coupling the coupling plate and the selection gate. | 2015-05-14 |
20150129950 | Semiconductor Device and Method of Making Same - A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly. | 2015-05-14 |
20150129951 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE OF CONTROL GATE, AND SEMICONDUCTOR DEVICE - A method of forming a semiconductor structure of a control gate is provided, including depositing a first dielectric layer overlying a substrate, forming a surface modification layer from the first dielectric layer; and forming semiconductor dots on the surface modification layer. The surface modification layer has a bonding energy to the semiconductor dots less than the bonding energy between the first dielectric layer and the semiconductor dots. Therefore the semiconductor dots have higher density to form on the surface modification layer than that to directly form on the first dielectric layer. And a semiconductor device is also provided to tighten threshold voltage (Vt) and increase programming efficiency. | 2015-05-14 |
20150129952 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal. | 2015-05-14 |
20150129953 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device with nonvolatile memory, having improved performance. | 2015-05-14 |
20150129954 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel. | 2015-05-14 |
20150129955 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME - A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed. | 2015-05-14 |
20150129956 | METHOD TO MANUFACTURE SHORT CHANNEL TRENCH MOSFET - Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2015-05-14 |
20150129957 | SEMICONDUCTOR DEVICE - A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches. | 2015-05-14 |
20150129958 | SEMICONDUCTOR APPARATUS - According to one embodiment, a semiconductor apparatus divides each of a first area in which a first transistor is formed and a second area in which a second transistor is formed into two or more areas, and alternately arranges the divided areas of the first area and the second area. Further, the semiconductor apparatus according to one embodiment configures the second area to have a total area larger than that of the first area or to have the number of divisions greater than that of the first area. Furthermore, in the semiconductor apparatus according to one embodiment, a gate pad of the first transistor and a gate pad of the second transistor are provided in the second area. | 2015-05-14 |
20150129959 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate comprising a WELL region, a gate electrode comprising a gate length disposed on the WELL region, and first and second drift regions which overlap with the gate electrode. The first and second draft regions may overlap with the gate electrode at an overlapping length which is a percentage of the gate length. | 2015-05-14 |
20150129960 | SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate, and first and second transistors of first and second conductivity types on the substrate. The first transistor includes a first gate electrode on the substrate, a first source region of the second conductivity type and a first drain region of the first conductivity type disposed to sandwich the first gate electrode, and a first channel region of the first or second conductivity type disposed between the first source region and the first drain region. The second transistor includes a second gate electrode on the substrate, a second source region of the first conductivity type and a second drain region of the second conductivity type disposed to sandwich the second gate electrode, and a second channel region disposed between the second source region and the second drain region and having the same conductivity type as the first channel region. | 2015-05-14 |
20150129961 | BRIDGING LOCAL SEMICONDUCTOR INTERCONNECTS - A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates. | 2015-05-14 |
20150129962 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES AND FINS ON FINFET DEVICES AND THE RESULTING DEVICES - One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure. | 2015-05-14 |
20150129963 | ARRAY SUBSTRATE AND A DISPLAY DEVICE HAVING THE SAME - An array substrate includes a substrate, a plurality of gate lines extending in a first direction on the substrate, a plurality of data lines including first and second data line pairs separated by cutting portions and a plurality of active patterns electrically connected to the first and second data line pairs. The data lines extend in a second direction crossing the first direction. The active patterns overlap the cutting portion and overlap a first gate line. | 2015-05-14 |
20150129964 | NANOWIRE TRANSISTOR DEVICE - A semiconductor device is provided including a semiconductor substrate and a nanowire formed over the semiconductor substrate and wherein the nanowire includes a first layer exhibiting tensile stress and a second layer exhibiting compressive stress. | 2015-05-14 |
20150129965 | DEVICES AND METHODS RELATED TO RADIO-FREQUENCY SWITCHES HAVING REDUCED-RESISTANCE METAL LAYOUT - Devices and methods related to radio-frequency (RF) switches having reduced-resistance metal layout. In some embodiments, a field-effect transistor (FET) based RF switch device can include a plurality of fingers arranged in an interleaved configuration such that a first group of the fingers are electrically connected to a source contact and a second group of the fingers are electrically connected to a drain contact. At least some of the fingers can have a current carrying capacity that varies as a function of location along a direction in which the fingers extend. Such a configuration of the fingers can desirably reduce the on-resistance (Ron) of the FET based RF switch device. | 2015-05-14 |
20150129966 | TRANSISTOR INCLUDING A GATE ELECTRODE EXTENDING ALL AROUND ONE OR MORE CHANNEL REGIONS - A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode. | 2015-05-14 |
20150129967 | DUAL GATE FD-SOI TRANSISTOR - Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module. | 2015-05-14 |
20150129968 | SYSTEMS AND METHODS FOR A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE SEMICONDUCTOR-DEVICE LAYERS - A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included. The bottom surface of the SOI substrate is bonded to the patterned top surface of the first semiconductor device layer via the bonding surface. | 2015-05-14 |
20150129969 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first area and a second area divided by a shallow trench isolation (STI) area, a first dummy structure on the STI area, a second dummy structure located on the STI area, a first semiconductor structure on the first area, and a second semiconductor structure on the second area of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a high-k dielectric first, high-k metal gate last procedure. | 2015-05-14 |
20150129970 | METHODS AND STRUCTURES FOR ELIMINATING OR REDUCING LINE END EPI MATERIAL GROWTH ON GATE STRUCTURES - One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon. | 2015-05-14 |
20150129971 | SEMICONDUCTOR ARRANGEMENT FACILITATING ENHANCED THERMO-CONDUCTION - A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area. | 2015-05-14 |
20150129972 | METHODS OF SCALING THICKNESS OF A GATE DIELECTRIC STRUCTURE, METHODS OF FORMING AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUITS - Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate. | 2015-05-14 |
20150129973 | SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION IN TRANSISTORS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively. | 2015-05-14 |
20150129974 | TRANSISTOR INCLUDING A STRESSED CHANNEL, A METHOD FOR FABRICATING THE SAME, AND AN ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes a first channel, a second channel, a first strained gate electrode including a first lattice-mismatched layer for applying a first stress to the first channel, and a second strained gate electrode including a second lattice-mismatched layer for applying a second stress to the second channel. | 2015-05-14 |
20150129975 | MULTI-TIME PROGRAMMABLE DEVICE - Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region. | 2015-05-14 |
20150129976 | Semiconductor Device With Silicide Cap - A semiconductor device includes a substrate, an epi-layer, an etch stop layer, an interlayer dielectric (ILD) layer, a silicide layer cap and a contact plug. The substrate has a first portion and a second portion neighboring to the first portion. The etch stop layer is disposed on the second portion. The ILD layer is disposed on the etch stop layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the ILD layer. | 2015-05-14 |
20150129977 | SEMICONDUCTOR ELECTROSTATIC DISCHARGE PROTECTION APPARATUS - A semiconductor electrostatic discharge (ESD) protection apparatus comprises at least one elementary transistor with a first conductivity type, a well region with a second conductivity type, a guard ring with the second conductivity type and a semiconductor interval region. The elementary transistor is formed in the well region. The guard ring surrounds the at least one elementary transistor. The semiconductor interval region is disposed between the elementary transistor and the guard ring in order to surrounds the elementary transistor, wherein the semiconductor interval region is an undoped region, a doped region with the first conductivity type or a doped region with the second conductivity type that has a doping concentration substantially less than that of the well region. | 2015-05-14 |
20150129978 | SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE - A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate. | 2015-05-14 |
20150129979 | SEMICONDUCTOR DEVICE WITH A STRAINED REGION AND METHOD OF MAKING - A semiconductor device with a strained region is provided. The semiconductor device includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the second dielectric layer having a first fin disposed therein and an interface disposed proximate the first fin. The interface includes a first oxide region disposed in the first dielectric layer and a second oxide region disposed in the second dielectric layer. The interface induces strain in a region of the semiconductor device. A method of making a semiconductor device with a strained region is also provided. | 2015-05-14 |
20150129980 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure comprises a substrate, a plurality of fins, an oxide layer and a gate structure. The fins protrude from the substrate and are separated from each other by the oxide layer. The surface of the oxide layer is uniform and even plane. The gate structure is disposed on the fins. The fin height is distance between the top of the fins and the oxide layer, and at least two of the fins have different fin heights. | 2015-05-14 |
20150129981 | SEMICONDUCTOR DEVICE HAVING FIN-TYPE CHANNEL AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel. | 2015-05-14 |
20150129982 | FinFET DEVICE INCLUDING FINS HAVING A SMALLER THICKNESS IN A CHANNEL REGION, AND A METHOD OF MANUFACTURING SAME - A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate to a first thickness, forming a sacrificial gate stack on portions of the fins, forming source drain junctions using ion implantation, forming a dielectric layer on the substrate, removing the sacrificial gate stack to expose the portions of the fins, thinning the exposed portions of the fins to a second thickness less than the first thickness, and forming a gate stack on the thinned exposed portions of the fins to replace the removed sacrificial gate stack. | 2015-05-14 |
20150129983 | FIN-TYPE TRANSISTOR STRUCTURES WITH EXTENDED EMBEDDED STRESS ELEMENTS AND FABRICATION METHODS - Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure. | 2015-05-14 |
20150129984 | PIXEL ARRAY - A pixel array includes a plurality of scan lines, a plurality of data lines, a first active device, a second active device, a first pixel electrode and a second pixel electrode. The first active device and the second active device are electrically connected to the corresponding scan line and data line respectively. The first pixel electrode is electrically connected to the first active device through a contact hole. The second pixel electrode is electrically connected to the second active device through the contact hole. | 2015-05-14 |
20150129985 | DISPLAY PANEL - A display apparatus includes a first base substrate that includes an upper surface and a lower surface facing the upper surface and includes a transmission area and a light blocking area, a low reflection conductive line disposed on the lower surface of the first base substrate, in which a portion of the lower reflection conductive line is overlapped with the transmission area to transmit a portion of an incident light, a second base substrate facing the lower surface of the first base substrate, and a pixel disposed between the first and second base substrates, at least a portion of the pixel being overlapped with the transmission area. | 2015-05-14 |
20150129986 | DISPOSABLE PILLARS FOR CONTACT FORMATION - Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts. | 2015-05-14 |
20150129987 | MECHANISM FOR FORMING SEMICONDUCTOR DEVICE WITH GATE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate. | 2015-05-14 |
20150129988 | REDUCED RESISTANCE FINFET DEVICE WITH LATE SPACER SELF ALIGNED CONTACT - Embodiments include a method of fabricating a reduced resistance finFET device comprising providing a fin in a semiconductor substrate. A dummy gate is formed over a portion of the fin such that the dummy gate does not initiate selective epitaxy. A source/drain region is formed on the fin such that the source/drain region directly contacts the dummy gate. The dummy gate is replaced with a replacement metal gate structure that directly contacts the source/drain region. A portion of the fin that includes a portion of the source/drain region is replaced with a contact material. | 2015-05-14 |
20150129989 | GATE INSULATING LAYER AND METHOD FOR FORMING THE SAME - The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer. | 2015-05-14 |
20150129990 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE - A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape. | 2015-05-14 |
20150129991 | CMOS-MEMS INTEGRATED DEVICE INCLUDING MULTIPLE CAVITIES AT DIFFERENT CONTROLLED PRESSURES AND METHODS OF MANUFACTURE - An integrated MEMS device comprises two substrates where the first and second substrates are coupled together and have two enclosures there between. One of the first and second substrates includes an outgassing source layer and an outgassing barrier layer to adjust pressure within the two enclosures. The method includes depositing and patterning an outgassing source layer and a first outgassing barrier layer on the substrate, resulting in two cross-sections. In one of the two cross-sections a top surface of the outgassing source layer is not covered by the outgassing barrier layer and in the other of the two cross-sections the outgassing source layer is encapsulated in the outgassing barrier layer. The method also includes depositing conformally a second outgassing barrier layer and etching the second outgassing barrier layer such that a spacer of the second outgassing barrier layer is left on sidewalls of the outgassing source layer. | 2015-05-14 |
20150129992 | MEMS MICROPHONE HAVING DUAL BACK PLATE AND METHOD FOR MANUFACTURING SAME - Disclosed herein are a microelectromechanical systems (MEMS) microphone with a dual-back plate, and a method of manufacturing the same. The MEMS microphone according to an exemplary embodiment of the present invention includes: a substrate having a first back plate formed at a central portion thereof; a membrane plate disposed on first support parts formed at both sides on the substrate and vibrated depending on external sound pressure; and a second back plate disposed on second support parts formed at both sides of the membrane plate. | 2015-05-14 |
20150129993 | METHOD AND SYSTEM FOR PROVIDING A BULK PERPENDICULAR MAGNETIC ANISOTROPY FREE LAYER IN A PERPENDICULAR MAGNETIC JUNCTION USABLE IN SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS - A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer includes at least one of a hybrid perpendicular magnetic anisotropy (PMA) structure and tetragonal bulk perpendicular magnetic anisotropy (B-PMA) structure. At least one of the free layer and the pinned layer have a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 2015-05-14 |
20150129994 | SPIN-POLARISED CURRENT SOURCE - Method of filtering electrons to obtain spin-polarisation of a current conducting at least 75% of electrons at the Fermi level, used with a spin-polarised current source comprising:
| 2015-05-14 |
20150129995 | MAGNETIC MEMORY BITS WITH PERPENDICULAR MAGNETIZATION SWITCHED BY CURRENT-INDUCED SPIN-ORBIT TORQUES - A basic Spin-Orbit-Torque (SOT) structure with lateral structural asymmetry is provided that produces a new spin-orbit torque, resulting in zero-field current-induced switching of perpendicular magnetization. More complex structures can also be produced incorporating the basic structure of a ferromagnetic layer with a heavy non-magnetic metal layer having strong spin-orbit coupling on one side, and an insulator layer on the other side with a structural mirror asymmetry along the in-plane direction. The lateral structural asymmetry and new spin-orbit torque, in effect, replaces the role of the external in-plane magnetic field. The direction of switching is determined by the combination of the direction of applied current and the direction of symmetry breaking in the device. | 2015-05-14 |
20150129996 | METHOD AND SYSTEM FOR PROVIDING A TOP PINNED LAYER PERPENDICULAR MAGNETIC ANISOTROPY MAGNETIC JUNCTION USABLE IN SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS - A method for providing a magnetic junction usable in a magnetic device and the magnetic junction are described. A free layer and nonmagnetic spacer layer are provided. The free layer and nonmagnetic spacer layer are annealed at an anneal temperature of at least three hundred fifty degrees Celsius. A pinned layer is provided after the annealing step. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 2015-05-14 |
20150129997 | DUAL PERPENDICULAR MAGNETIC ANISOTROPY MAGNETIC JUNCTION USABLE IN SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY APPLICATIONS - A method for providing a dual magnetic junction usable in a magnetic device and the dual magnetic junction are described. First and second nonmagnetic spacer layers, a free layer and pinned are provided. The first pinned layer, free layer and nonmagnetic spacer layer may be annealed at an anneal temperature of at least three hundred fifty degrees Celsius before a second pinned layer is provided. The second pinned layer may include Co, Fe and Tb. The nonmagnetic spacer layers are between the pinned layers and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 2015-05-14 |
20150129998 | METHODS FOR MANUFACTURING CARBON RIBBONS FOR MAGNETIC DEVICES - In one embodiment of the invention, there is provided a method for manufacturing a magnetic memory device, comprising: depositing a carbon layer comprising amorphous carbon on a substrate; annealing the carbon layer to activate dopants contained therein; and selectively etching portions of the carbon layer to forms lines of spaced apart carbon conductors. | 2015-05-14 |
20150129999 | METHOD OF WAFER-SCALE INTEGRATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE - The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer ( | 2015-05-14 |
20150130000 | CHIP PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A chip package structure includes a nanometer deposition layer and a chip having an electrical connection circuit, a photo sensing region and a plurality of electrical connection pads. The electrical connection pads and the photo sensing region are formed on the upper surface of the chip. The photo sensing region is covered with the nanometer deposition layer, which exposes the electrical connection pads. The nanometer deposition layer is used to provide electrical insulation, isolation and protection. The method for manufacturing the chip package structure includes cleaning the wafer with the chips, forming the nanometer deposition layer, and scribing the wafer to separate the chips. The present invention replaces the process of mold filling by directly forming the nanometer deposition layer so as to simplify the manufacturing steps, reduce the cost and facilitate the production, thereby shrinking the size of the chip package. | 2015-05-14 |
20150130001 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THEREOF - An image sensor is provided including a substrate, an array of photosensitive units, a grid and a plurality of color filters. In the image sensor, the grid has a first portion and a second portion disposed on the first portion. The second portion of the grid can cause reflection or refraction of incident lights targeted for one image sensor element back into the same image sensor element, so as to avoid crosstalk occurred. Further, a method for manufacturing the image sensor also provides herein. | 2015-05-14 |
20150130002 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THEREOF - An image sensor is provided including a substrate, an array of photosensitive units, a grid, a light-tight layer and a plurality of color filters. In the image sensor, the grid has a top surface, and the light-tight layer is disposed on the top surface of the grid. Due to the light-tight layer on the grid, an incident light entering into the grid can be blocked by the light-tight layer, so that the crosstalk effect is reduced significantly. Further, a method for manufacturing the image sensor also provides herein. | 2015-05-14 |
20150130003 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes a substrate including photoelectric conversion regions, a magnetic layer disposed on a back side of the substrate and suitable for generating a magnetic field, and color filters and microlenses disposed on the magnetic layer. | 2015-05-14 |
20150130004 | SOLID-STATE IMAGE PICKUP DEVICE - A portion on the light exit end surface side of a fiber optic plate includes a first portion and a second portion. The first portion corresponds to a peripheral portion of a semiconductor photodetecting element. The second portion corresponds to a thin portion of the semiconductor photodetecting element and projects more toward the semiconductor photodetecting element than the first portion. A height of a step made between the first portion and the second portion of the fiber optic plate is lower than a height of a step made between the thin portion and the peripheral portion of the semiconductor photodetecting element. The semiconductor photodetecting element and the fiber optic plate are fixed by a resin, in a state in which the first portion and the peripheral portion are in contact and in which the second portion and the thin portion are separated. | 2015-05-14 |
20150130005 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - Example embodiments disclose an image sensor and a fabricating method thereof. An image sensor may include a semiconductor layer with a light-receiving region and a light-blocking region, the semiconductor layer including photoelectric conversion devices, a light-blocking layer on a surface of the semiconductor layer, color filters on the semiconductor layer and the light-blocking layer, and micro lenses on the color filters. The color filters are absent from an interface region between the light-receiving region and the light-blocking region. | 2015-05-14 |
20150130006 | SOLID-STATE IMAGE SENSOR - An image sensor includes first to fourth microlenses. A first height difference between a first valley between the first and second microlenses and tops of the first and second microlenses is larger than a second height difference between a second valley between the third and fourth microlenses and tops of the third and fourth microlens, a first angle formed by a tangent in an outermost portion of the first microlens, which contacts the first valley and a plane perpendicular to the normal is equal to or smaller than a second angle formed by a tangent in an outermost portion of the third microlens, which contacts the second valley and the plane. | 2015-05-14 |
20150130007 | SEMICONDUCTOR DEVICE, AND METHOD FOR FORMING THE SAME - A semiconductor device is improved in performance by preventing the generation of color mixing in its pixels which form an image pickup device. In a region between adjacent pixels, which is a region for separating regions where respective color filters of the pixels from each other, septum walls are formed. The septum walls are each made of an insulator film smaller in refractive index than the color filters, and an insulator film which is formed to cover side walls of the insulator film and is larger in refractive index than the color filters. In this way, a light ray radiated into the upper surface of each of the septum walls can be prevented from invading the pixels adjacent to the wall. | 2015-05-14 |
20150130008 | NEAR-INFRARED ABSORPTIVE COMPOSITION, NEAR-INFRARED CUT FILTER USING NEAR-INFRARED ABSORPTIVE COMPOSITION, METHOD FOR MANUFACTURING NEAR-INFRARED CUT FILTER, AND CAMERA MODULE AND METHOD FOR MANUFACTURING CAMERA MODULE - Provided is a near-infrared absorptive compositions capable of reducing unevenness in the coated surface profile and variation in near-infrared absorptive ability when the near-infrared absorptive compositions are formed into films. The near-infrared absorptive composition comprises a copper complex and a solvent, wherein the near-infrared absorptive composition has a solid content of 10 to 90% by mass and the solvent has a boiling point of 90 to 200° C. | 2015-05-14 |
20150130009 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer. | 2015-05-14 |
20150130010 | Dual Pixel-Sized Color Image Sensors And Methods For Manufacturing The Same - A dual pixel-size color image sensor, including an imaging surface, for imaging of incident light, and a plurality of color pixels, each color pixel including (a) four large photosites, including two large first-color photosites sensitive to a first color of the incident light, and (b) four small photosites including two small first-color photosites sensitive to the first color of the incident light. The large and small first-color photosites are arranged such that connected regions of the imaging surface, not associated with large and/or small first-color photosites, are not continuous straight lines. A method for manufacturing a color filter array on an imaging surface of a dual pixel-size image sensor includes forming a first-color coating on first portions of the imaging surface to form large and small first-color photosites sensitive to a first color, wherein connected portions of the imaging surface, different from the first portions, are not continuous straight lines. | 2015-05-14 |
20150130011 | IMAGE SENSOR PACKAGES - An image sensor package may include: a package substrate including a chip attachment area on an upper surface thereof, a pad area having a plurality of pads around the chip attachment area, and a holder attachment area at an outside of the pad area, wherein an upper surface of the holder attachment area is at a lower level than an upper surface of the pad area; an image sensor chip mounted on the chip attachment area of the package substrate; a transparent member above the package substrate and configured to cover the image sensor chip; and a holder on the holder attachment area of the package substrate and configured to fix the transparent member. | 2015-05-14 |
20150130012 | THERMOELECTRIC DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a thermoelectric device and a method of manufacturing the same. The method may include forming nanowires on a substrate, forming a barrier layer on the nanowires, forming a bulk layer on the barrier layer, forming a lower electrode under the substrate, and forming an upper electrode on the bulk layer. | 2015-05-14 |
20150130013 | Semiconductor Device and Method for Forming a Semiconductor Device - A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one Schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one ohmic contact region is arranged adjacent to the at least one Schottky contact region. The semiconductor substrate includes a first doping layer arranged adjacent to the electrically conductive structure. An average doping concentration of the surface region of the first doping layer in an area of the at least one ohmic contact region differs from an average doping concentration of the surface region of the first doping layer in an area of the at least one Schottky contact region by less than 10%. | 2015-05-14 |
20150130014 | FAST RECOVERY RECTIFIER - The present disclosure provides a rectifier. The rectifier includes a N-type epitaxial layer, a plurality of P-type diffusion regions and a plurality of N-type diffusion regions. The P-type diffusion regions are disposed in the N-type epitaxial layer, and the N-type diffusion regions are respectively disposed in the P-type diffusion regions. Wherein, the P-type diffusion regions are electronically coupled to the N-type diffusion regions. | 2015-05-14 |
20150130015 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ANTENNA SWITCH MODULE - Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer. | 2015-05-14 |
20150130016 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a deep trench isolation (DTI). The silicon substrate has a deep trench. The spacer is formed on an upper portion of the sidewall of the deep trench. The doped region is formed on a lower portion of the sidewall of the deep trench. The deep trench isolation is formed in the deep trench. | 2015-05-14 |
20150130017 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE DEVICE - An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material. | 2015-05-14 |
20150130018 | VIA-FUSE WITH LOW DIELECTRIC CONSTANT - In an embodiment of the present invention, a semiconductor device comprises a non-fuse area that has a non-fuse via, a non-fuse line, and a non-fuse dielectric stack. The semiconductor device further comprises a fuse area that has a fuse via, a fuse line, and a fuse dielectric stack. The fuse dielectric stack comprises at least a first dielectric and a second dielectric material. The fuse via is at least partially embedded in the first dielectric material and the fuse line is embedded in the second dielectric material. | 2015-05-14 |
20150130019 | ELECTRONIC FUSE HAVING AN INSULATION LAYER - A structure including a dual damascene feature in a dielectric layer, the dual damascene feature including a first via, a second via, and a trench, the first via, the second via being filled with a conductive material, a fuse line at the bottom of the trench on top of the first via and the second via, the fuse line including the conductive material; an insulating layer on top of the fuse line and along a sidewall of the trench, and a fill material on top of the insulating layer and substantially filling the trench. | 2015-05-14 |
20150130020 | SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. | 2015-05-14 |
20150130021 | SOLONOID INDUCTOR IN A SUBSTRATE - Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings. | 2015-05-14 |
20150130022 | Semiconductor Device - In a first semiconductor chip, a first multilayer interconnect layer is formed on a first substrate, and a first inductor is formed in the first multilayer interconnect layer. In a second semiconductor chip, a second multilayer interconnect layer is formed on a second substrate. A second inductor is formed in the second multilayer interconnect layer. The first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other. In addition, the first inductor and the second inductor overlap each other when seen in a plan view. At least one end of a first insulating film does not overlap the end of a facing region, in a Y direction. | 2015-05-14 |
20150130023 | THREE DIMENSIONAL INTEGRATED CIRCUIT CAPACITOR - A three dimensional integrated circuit capacitor that includes a first conductive layer, a second conductive layer above the first conductive layer and a semiconductor layer above the second conductive layer. The semiconductor layer has an inter layer via (ILV) through the semiconductor layer. A third conductive layer is above the semiconductor layer and a fourth conductive layer is above the third conductive layer. A first conductive plate has fingers on at least two of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer. A second conductive plate has fingers on at least two of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer. An insulating layer is between the first conductive plate and the second conductive plate. | 2015-05-14 |
20150130024 | EMBEDDED SHEET CAPACITOR - A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die. | 2015-05-14 |