20th week of 2009 patent applcation highlights part 59 |
Patent application number | Title | Published |
20090125641 | Method and Apparatus for Managing an Olfactory Device - One embodiment of a method for managing a scent dispensing request made to an olfactory display includes applying one or more filtering criteria to the request and determining whether to provide the request to the olfactory display for fulfillment, in accordance with the filtering criteria. In another embodiment, a system for dispensing scents in response to requests issued by one or more applications running on a computing device includes a filter for determining, in accordance with one or more criteria, which of the requests should be fulfilled and an olfactory display for dispensing at least one scent based on a determination made by the filter. | 2009-05-14 |
20090125642 | HDMI Network Control of A Media Center Computing Device - A software or hardware agent running on a personal computing (PC) device provides allows a consumer electronic device connected to the PC device over a high definition multimedia interface (HDMI) network to control the PC device using standardized commands. This enables a user to control the PC device and other consumer electronic devices that are connected to the HDMI network using a single interface. The agent responds as a consumer electronic device and translates the standardized commands as universal serial bus (USB) human interface device (HID) input reports to the PC device operating system. The agent represents the specific capabilities of the PC device as standard consumer electronic device controls. | 2009-05-14 |
20090125643 | SYSTEM AND METHOD FOR DRIVE RESIZING AND PARTITION SIZE EXCHANGE BETWEEN A FLASH MEMORY CONTROLLER AND A SMART CARD - A system and method to control a device having at least one configurable parameter. Enumerating the device as a first peripheral device and as a second peripheral device wherein the first peripheral device corresponds to a first microcontroller connected to a storage medium and the second peripheral device corresponds to a second microcontroller. Controlling the at least one configurable parameter of the first microcontroller with respect to the storage medium by the second microcontroller. On initialization of the device, transmitting the at least one configurable parameter from the second microcontroller to the first microcontroller. Other systems and methods are disclosed. | 2009-05-14 |
20090125644 | Image processing apparatus and image processing apparatus controlling method - Disclosed herein is an image processing apparatus including an input section, a bus, a memory interface, an output section, and a control section. | 2009-05-14 |
20090125645 | SYSTEM AND METHOD FOR SUPPORTING MULTIPLE TOKENS HAVING A SMART CARD TO CONTROL PARAMETERS OF A FLASH MEMORY DEVICE - A system and method to control a device having at least one configurable parameter. Enumerating the device as a first peripheral device and as a second peripheral device wherein the first peripheral device corresponds to a first microcontroller connected to a storage medium and the second peripheral device corresponds to a second microcontroller. Controlling the at least one configurable parameter of the first microcontroller with respect to the storage medium by the second microcontroller. On initialization of the device, transmitting the at least one configurable parameter from the second microcontroller to the first microcontroller. Other systems and methods are disclosed. | 2009-05-14 |
20090125646 | METHOD AND SYSTEM FOR SECURING INPUT FROM AN EXTERNAL DEVICE TO A HOST - The pureness of a connection between an external device and a host computer can be inspected or monitored to determine the status: connected or disconnected. When it is determined that a disconnection state is entered, an indication can be sent to the host and, in parallel, the data transportation from and/or to the external device may be manipulated. In some embodiments an exemplary connection protector device (CPD) may be added to the connection in between the external device and the host. The CPD can have two connectors one for the host and one for the cable of the external device. The CPD can be adapted to identify any disconnection in the connection with the host and/or the connection with the external device on the other side of the CPD. | 2009-05-14 |
20090125647 | Device And Method For Executing A DMA Task - A method for executing a DMA task, the method includes receiving a request to execute a DMA task; the method characterized by including: defining inter-buffer jumping points at substantially an end of one or more dimensions of each multidimensional buffer out of a plurality of multidimensional buffers; and executing multiple DMA sub-tasks, wherein the executing includes jumping between buffers at the inter-buffer jumping points. A device hat includes at least one memory unit and a DMA controller adapted to access the memory unit; the device is characterized by being adapted to implement multidimensional buffers within the at least one memory unit; wherein the DMA controller is adapted to execute multiple DMA sub-tasks, wherein the execution comprises jumping between buffers at inter-buffer jumping points; and wherein the inter-buffer jumping points are defined at substantially an end of one or more dimensions of each multidimensional buffer out of a plurality of multidimensional buffers. | 2009-05-14 |
20090125648 | DIRECT MEMORY ACCESS SYSTEM AND METHOD - A DMA system includes at lease one read bus, at least one write bus, at least one buffer memory bus, and a DMA controller. The DMA controller comprises a plurality of channels and a bus arbiter. The channels are electrically connected to the read bus, the write bus, and the buffer memory bus. A source address and a destination address of data for each channel are assigned by a control table. The bus arbiter performs bus arbitration and prioritizes data access among the read bus, the write bus, and the buffer memory bus. | 2009-05-14 |
20090125649 | VARIABLE SPEED BUFFER SERVO CONTROL FOR LINEAR TAPE DRIVES - A variable speed linear tape drive includes a driver portion for rotating a supply reel of a tape cartridge having storage media spooled therein, a motor coupled to rotate the driver portion, a controller configured to control the motor in accordance with a control algorithm, an interface for one or more of sending data to and receiving data from a host; and a buffer for storing one or more of data received from the host and data to be transmitted to the host, the buffer operable to supply a buffer fill level indication to the controller, wherein the control algorithm is operable to generate a difference between a target buffer fill level and the buffer fill level indication and adjust at least one of an angular velocity or an acceleration of the motor to reduce the difference. | 2009-05-14 |
20090125650 | Buffer status reporting apparatus, system, and method - An apparatus, system and method for increasing buffer status reporting efficiency and adapting buffer status reporting according to uplink capacity. User equipment is configured a monitor a usage of a plurality of buffers, detect one of a plurality of pre-selected conditions corresponding to at least one of the plurality of buffers, designate one of a plurality of buffer status reporting formats depending on the pre-selected condition detected, communicate a buffer status report to a network device in accordance with the buffer status reporting format designated. The buffer status reporting format is configured to minimize buffer status reporting overhead created by the communicating of the buffer status report. | 2009-05-14 |
20090125651 | Keypad De-Bouncing Apparatus and Method - An apparatus and method for de-bouncing keypad inputs is disclosed including interrupting a processor upon detecting a key press, reading input signals from the key pad to determine an initial port value and starting a timer. A keypad interrupt is disabled and processing resumes until expiration of the timer. The timer interrupts the processor and the input signals are read a second time and combined with the initial port value to determine a key identifier. The timer is started again and processing resumes. Upon expiration of the timer the processor checks for key release. If release is not detected, the timer is again started. If release occurs, the timer is disabled and the keypad interrupt is enabled. | 2009-05-14 |
20090125652 | Physical layer device having a serdes pass through mode - A physical layer device (PLD), comprising: a first serializer-deserializer (SERDES) device having a first parallel port; a second SERDES device having a second parallel port; a third SERDES device having a third parallel port; and a path selector being selectively configurable to provide either (i) a first signal path between the first and second parallel ports, or (ii) a second signal path between the first and third parallel ports. | 2009-05-14 |
20090125653 | ASSOCIATION USING USB VIDEO ADAPTER - Certified Wireless USB 1.0 (CWUSB) defines two different types of association: cable association and numeric association. In the numeric association, the CWUSB host and device use a specific protocol to exchange the security information. At final stage of this information exchange, both host and device need to display a number asking user's feedback. Once this is done, both host and device will be able to generate the connection key as the shared secret for the following secured communication. One problem of this numeric association method is that device needs to be able to display the numbers. For certain class of device that has capability to display an image, there is a natural way to add this function to them. A method for this class of devices is described. Another kind of association, which is not defined in the CWUSB 1.0, is manual association. User needs only to manually type in the Connection Key coming from the CWUSB device. There are many ways to delivery the key, but it is very easy for device that can display an image. | 2009-05-14 |
20090125654 | KVM Switch - A KVM switch which allows a far end console and a near end console to share a single bus is provided. The KVM switch includes a host port, a far end port, a near end port, a video processing module, a far end video processing module, a video switching module, an operation processing module, a far end operation signal module. In order to share the single bus, an additional far end video processing module transmits display signals from the host port to the far end console via the far end port, or displays display signals on a monitor via the video processing module. At the same time, an additional far end operation signal module receives an operation signal from the far end console via the far end port, or transmits the operation signal from an operation device to the host computer via the operation processing module. | 2009-05-14 |
20090125655 | ENABLING SAS EXPANDER LOOPS FOR INCREASED FAIRNESS AND PERFORMANCE - The use of loops in SAS networks is enabled by designating ports connected to loop connections as table loop ports (TLPs). Under normal operating conditions, each TLP is blocked from receiving BCNs, appears to the expander to have nothing connected to it, and is made invisible to initiators. The loop connection and TLPs may be enabled and used to access devices when a problem is detected. In particular, the TLP will now appear in a list of destination ports within the expander to which a BCN should be propagated. In addition, during a subsequent self-configuration, the TLP is allowed to populate its route table with devices accessible through it, and the existence of the TLP is also reported back to initiators. After re-discovery is complete, communications between the initiator and a target can resume, with traffic re-routed through the TLPs as needed, bypassing the failure point. | 2009-05-14 |
20090125656 | Method and Arrangement for the Automatic Configuration of a Master-Slave Field Bus System - A field bus system ( | 2009-05-14 |
20090125657 | SERIAL PERIPHERAL INTERFACE CIRCUIT - An exemplary serial peripheral interface circuit includes a host, a plurality of slaves, and a decoder. A data output terminal, a data input terminal, and a serial clock terminal of the host are connected to a data input terminal, a data output terminal, and a serial clock terminal of each slaves respectively. A slave select terminal of the host is connected to a data receive terminal of the decoder. GPIO pins of the hot are connected to corresponding input terminals of the decoder correspondingly. A select terminal of each slave is connected to a corresponding output terminal of the decoder. The address generated by the GPIO pins controls the decoder, so that the select terminal of the host can be connected to a corresponding slave device via the decoder. | 2009-05-14 |
20090125658 | CWUSB HOST MANAGEMENT SYSTEM - Universal Serial Bus (USB) is a Master/Salve or Host/Device system in which there is only one host and one or more devices connected by cables to the host. To connect a USB device to a different host controller (say another PC), the user unplugs the USB cable and establishes the connection physically by plugging the cable into the new host controller interface. Certified Wireless USB (CWUSB), a logical extension to the USB, preserves the USB connection model, except that the link between the host and the device is now using a wireless technology. A wireless device is usually connected to only one wireless host at a given point of time, even though several wireless hosts may be co-located in the same physical neighborhood. The connection between the wireless host and device is initiated by the device. A device usually selects a wireless host from a stored set of known hosts that have established a trusted relationship with the device. If more than one wireless host is operating in the same neighborhood, there is no well known established procedure for the device to select a particular wireless host to establish a connection. | 2009-05-14 |
20090125659 | Inter-Integrated Circuit (12C) Slave with Read/Write Access to Random Access Memory - A program and device for data access via an inter-integrated circuit (I2C) protocol are provided, which includes receiving an I2C read command at an I2C slave device from an I2C master device, and the I2C read command at the I2C slave device is altered such that the I2C read command causes stored data to be read from a storage device, being external to the I2C slave device, in place of reading from internal memory of I2C slave device. An I2C write command having master data and a slave device register address is intended to write to the internal memory of the I2C slave device, and I2C write command at the I2C slave device is altered such that the I2C write command causes the master data to write to the storage device, being external to the I2C slave device, in place of writing to internal memory of the I2C slave device. | 2009-05-14 |
20090125660 | Interrupt and Exception Handling for Multi-Streaming Digital Processors - A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines. In a synchronous method, no vectoring occurs until all streams to which an interrupt is mapped acknowledge the interrupt. | 2009-05-14 |
20090125661 | SYSTEM FOR SECURE TRANSACTIONS OF CARD-BORNE VALUE UNITS - The invention relates to a system for secure transactions of card-borne value units. The system comprises a card peripheral device for setting up a link with the card and comprising a transparent mode, a terminal linked to the card peripheral device, a host device linked to the terminal. The host device comprises a transactional application suitable for processing the value units on the card and cryptographic means making it possible to read and/or write values units and other information on the card. The card peripheral device operates in transparent mode. The terminal redirects the information originating from or addressed to the card peripheral device to the host device. The host device dialogs with the card via commands and data interchanges. In particular, the invention applies to the topping-up of a chip card, notably from computer means available to the user in possession of said card and an ordinary chip card reader. | 2009-05-14 |
20090125662 | Switch having integrated connectors - A switch having integrated connectors for connecting to computers has a casing, multiple peripheral ports, at least two integrated connectors and a switch unit. The peripheral ports are mounted on the casing and are for connecting respectively to multiple corresponding peripheral devices. Each integrated connector is a peripheral component interconnect express type connector and is for connecting one-to-one to a corresponding computer. The switch unit is mounted in the casing and is connected between the integrated connectors and the peripheral ports to allow a user to select one computer to be connected to the peripheral devices at a time. | 2009-05-14 |
20090125663 | Interface arrangement, especially for a system on a chip, and use thereof - An interface arrangement ( | 2009-05-14 |
20090125664 | SYSTEM CONTROLLER - A system LSI section | 2009-05-14 |
20090125665 | USB DEVICE AND USB SYSTEM INCLUDING THE SAME - A Universal Serial Bus (USB) device includes an internal circuit and an interface circuit. The interface circuit is configured to interface the internal circuit and an external device for wireless USB (WUSB) communication and USB communication. The interface circuit includes a WUSB module enabling the WUSB communication, an on-the-go (OTG) module enabling the USB communication, and an interface module configured to selectively control the WUSB module and the OTG module to interface the internal circuit and the external device for the WUSB communication and the USB communication. | 2009-05-14 |
20090125666 | DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC - A computer program product for implementing a method within a data processing system and a PCI Express protocol for enabling high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding. | 2009-05-14 |
20090125667 | METHOD OF CONTROLLING POWER CONSUMPTION OF A MEMORY ACCORDING TO MAPPING - There is provided a method of controlling power consumption of a memory, which is executed in a computer system including operation server and a management server. The operation server includes one or more memory chips which are units to control the power consumption of the memory, a power control module for controlling power consumption of the memory chips, and a virtualization module for operating one or more virtual servers. The management server manages the mapping between the one or more virtual servers and the one or more memory chips. The method comprises the steps of instructing the operation server to change the power consumption of the one or more memory chips based on whether the obtained access information is capable of achieving predetermined target performance and the mapping information, and changing the power consumption of the one or more memory chips based on the instruction from the management server. | 2009-05-14 |
20090125668 | Management of erased blocks in flash memories - The invention relates to a method for managing the erasure process in a memory system comprising individually erasable memory blocks (SB) that can be addressed with the aid of real memory block addresses (SBA). Said memory blocks are sub-divided into a plurality of writable sectors and can be addressed by means of an address conversion that uses an allocator table (ZT) to convert logical block addresses (LBA) into one of the respective memory block addresses (SBA). According to the invention, the allocator table (ZT) is sub-divided into at least one useful data area (NB) and a buffer block area (BB). The invention is characterised in that a first identifier erased (ER), indicating the physical erasure status and a second identifier content erased (CER), indicating the logical erasure status, is set for each memory block (SB) in the allocator table (ZT). | 2009-05-14 |
20090125669 | PREVENTING DATA LOSS IN A STORAGE SYSTEM - Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to disk when the server reboots (e.g. because the destination mass storage device is unavailable), it is stored in a file. When the disk reappears, the data in the file may be used to restore a file or file system on the disk to a consistent state. | 2009-05-14 |
20090125670 | ERASE BLOCK MANAGEMENT - An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of the floating gate memory cells of the Flash memory device. The Flash memory device of the invention combines the EBM data in a user data erase block by placing it in an EBM data field of the control data section of the erase block sectors. Therefore distributing the EBM data within the Flash memory erase block structure. This allows the Flash memory to update and/or erase the user data and the EBM data in a single operation, to reduce overhead and speed operation. The Flash memory also reduces the process of EBM data structure write fatigue by allowing the EBM data fields to be load leveled by rotating them with the erase blocks they describe. | 2009-05-14 |
20090125671 | APPARATUS, SYSTEM, AND METHOD FOR STORAGE SPACE RECOVERY AFTER REACHING A READ COUNT LIMIT - An apparatus, system, and method are disclosed for storage space recovery after reaching a read count limit. A read module reads data in a storage division of solid-state storage. A read counter module then increments a read counter corresponding to the storage division. A read counter limit module determines if the read count exceeds a maximum read threshold, and if so, a storage division selection module selects the corresponding storage division for recovery. A data recovery module reads valid data packets from the selected storage division, stores the valid data packets in another storage division of the solid-state storage, and updates a logical index with a new physical address of the valid data. | 2009-05-14 |
20090125672 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 2009-05-14 |
20090125673 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 2009-05-14 |
20090125674 | Method for polymorphic and systemic structuring of associative memory via a third-party manager - The present invention relates to a method for polymorphic and systemic structuring of associative memory via a third-party manager that allows a human or electronic operator to manage various families of associative memory for various applications. | 2009-05-14 |
20090125675 | Storage apparatus and logical volume migration method - This storage apparatus includes a first logical volume migration unit for migrating the logical volume of a first storage area targeted for power source shutdown to a second storage area that is not targeted for power source shutdown based on an external command, and a second logical volume migration unit for migrating an expiration date-defined logical volume from the second storage area to a third storage area of a post-expiration migration destination when the expiration date of the expiration date-defined logical volume set with an expiration date for migrating the logical volume is reached. The first logical volume migration unit balances and migrates the expiration date-defined logical volume to the second storage area by referring to the expiration date of the expiration date-defined logical volume and taking into consideration the migration timing to the third storage area. | 2009-05-14 |
20090125676 | INFORMATION HANDLING SYSTEM INCLUDING A LOGICAL VOLUME AND A CACHE AND A METHOD OF USING THE SAME - A system and method of recovering cached data can be used when a particular physical storage device becomes unsuitable for storing data. In one aspect, the method can include providing the information handling system including a logical volume and a cache. The cache includes data that is to be stored within a particular physical storage device. The method can also include persisting the data within a different physical storage device. In one embodiment, the different physical storage device can be used to temporarily store the data when a logical volume is inaccessible. After the particular physical storage device becomes suitable to persist the data, the logical volume can be restored. The method can further include persisting the data within the particular or a replacement physical storage device. In another aspect, a system can be configured to carry out the methods described herein. | 2009-05-14 |
20090125677 | INTELLIGENT CACHING OF MEDIA FILES - A method of receiving and forwarding a multimedia message is provided. The multimedia message is adapted with a first adaptation profile into a first adapted message to be received in a first device. The multimedia message and the first adapted message are stored in a media cache. The message may then be forwarded from the first device to a second device that has a second adaptation profile by retrieving the first adapted message from the media cache and sending it to the second device if the first and second adaptation profiles match, otherwise the multimedia message is retrieved from the media cache and adapted with the second adaptation profile into a second adapted message that is then sent to the second device. In addition, the second adapted message is stored in the media cache. | 2009-05-14 |
20090125678 | METHOD FOR READING DATA WITH STORAGE SYSTEM, DATA MANAGING SYSTEM FOR STORAGE SYSTEM AND STORAGE SYSTEM - Provided is a database management system obtains storage mapping information which associates addresses in a plurality of physical disk drives within the storage system and addresses in logical disk drives including these physical disk drives, to create queues individually for each of the plurality of physical disk drives. The database management system receives a plurality of read requests which request to read data out of the physical disk drives via the logical disk drives provided by the storage system, sorts the read requests by their destination, and accumulates the read requests in the respective queues associated with the request destination physical disk drives. The database management system reallocates the accumulated read requests into an order that shortens the data read time in each physical disk drive, and then issues the read requests to the storage system. | 2009-05-14 |
20090125679 | COMPUTER AND METHOD FOR REFLECTING PATH REDUNDANCY CONFIGURATION OF FIRST COMPUTER SYSTEM IN SECOND COMPUTER SYSTEM - Mapping management information denoting the mapping of a first host and first host volume and a second host and second host volume is prepared beforehand. First-path-redundancy information, which is related to the redundancy of a first path of the first host volume, is acquired, and a second host volume and second host mapped to this first host volume and the first host thereof are specified by referencing the mapping management information. The redundancy of a second path, which links the specified second host volume and a second storage volume, is decided based on the first-path-redundancy information. Second-path-redundancy information, which is related to the decided second-path redundancy, is outputted to configure the decided second-path redundancy in the above-mentioned specified second host. | 2009-05-14 |
20090125680 | Storage System for Restoring Data Stored in Failed Storage Device - The present invention maintains mapping information denoting which real areas have been allocated to which virtual areas for a virtual volume, the capacity of which is dynamically expanded. The present invention also maintains real area management information denoting which real areas have been allocated to which virtual areas. The real area management information is referenced to determine whether or not a low-reliability real area, which is a real area for which reliability has been lowered by the occurrence of a failure in a certain physical storage device, and which belongs to a RAID group comprising this certain physical storage device, has been allocated to a virtual area. A data restore process is not carried out for a low-reliability real area that has not been allocated to a virtual area, but a data restore process is carried out for a low-reliability real area that has been allocated to a virtual area. | 2009-05-14 |
20090125681 | DATA RECORDING APPARATUS, METHOD FOR INTERNAL CONTROL OF DATA RECORDING APPARATUS, AND DATA RECORDING SYSTEM - A data recording apparatus that writes data on/reads data from a hard disk drive in response to a data-write/read command received from an upper control device is provided. The data recording apparatus includes a command-aggregating device and a command-issuing device. The command-aggregating device is configured to generate an aggregate command by aggregating contents of a plurality of commands under the conditions that the plurality of commands are of the same kind continuously received from the control device and logical block addresses designated by the plurality of commands are consecutive addresses. The command-issuing device is configured to issue the aggregate command generated by aggregating the plurality of commands to a hard disk drive controller that controls the hard disk drive. | 2009-05-14 |
20090125682 | Memory Card Programmable Timer Device and Method - A timing device, that may be used in connection with food preparation, holding or service equipment, is programmable via a portable, replaceable media. In particularly, the timing device may be adapted to receive or associate with a media containing a set of instructions to affect operation of the timing device. Upon association with the timing device, transfer of the programming instructions from the media to the timing device occurs affecting programming of the timing device. | 2009-05-14 |
20090125683 | PORTABLE AUXILIARY STORAGE DEVICE - Versatility of a memory card is improved by providing a memory card wherein data protection mode and normal mode can be selected at discretion. | 2009-05-14 |
20090125684 | Timer Device For Monitoring Expiration Of Products - A timer device adapted to monitor time periods associated with foods and other substances which may have a finite time during which they are suitable e for use, comprising a timer unit ( | 2009-05-14 |
20090125685 | SHARED MEMORY SYSTEM FOR A TIGHTLY-COUPLED MULTIPROCESSOR - A shared memory system for a multicore computer system utilizing an interconnection network that furnishes tens of processing cores or more with the ability to refer concurrently to random addresses in a shared memory space with efficiency comparable to the typical efficiency achieved when referring to private memories. The network is essentially a lean and light-weight combinational circuit, although it may also contain non-deep pipelining. The network is generally composed of a sub-network for writing and a separate multicasting sub-network for reading, whose topologies are based on multiple logarithmic multistage networks, e.g. Baseline Networks, connected in parallel. The shared memory system computes paths between processing cores and memory banks anew at every clock cycle, without rearrangement. It returns an approval reply to every core whose initiative of accessing memory leads to the successful establishment of a path and is fulfilled, or a rejection reply to every core whose initiative is not fulfilled. | 2009-05-14 |
20090125686 | IMAGE FORMING APPARATUS AND METHOD OF CONTROLLING THE SAME - An image forming apparatus and method of controlling the same, the image forming apparatus including: an article of consumption including a memory; and a print controller to perform a memory access to read and/or to write data from/to the memory. Addresses for the memory of the article of consumption are changed using access counts updated each time a memory access is requested, so that the memory access can be performed according to the changed addresses. | 2009-05-14 |
20090125687 | METHOD OF CONTROLLING INTERNAL VOLTAGE AND MULTI-CHIP PACKAGE MEMORY PREPARED USING THE SAME - The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device. | 2009-05-14 |
20090125688 | MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION - A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address. | 2009-05-14 |
20090125689 | SYSTEM AND ARTICLE OF MANUFACTURE FOR PROVIDING AN ADDRESS FORMAT COMPATIBLE WITH DIFFERENT ADDRESSING FORMATS USED FOR ADDRESSING DIFFERENT SIZED ADDRESS SPACES - Provided are a system and article of manufacture for providing an address format compatible with different addressing formats used for addressing different sized address spaces. An address format is used in an operating system to address storage space in a storage device comprising a first region and a second region of storage space. A first group of applications uses the address format to only address the storage space in the first region and is not coded to use the address format to access the second region and a second group of applications uses the address format to address the storage space in the first and second regions. | 2009-05-14 |
20090125690 | SYSTEMS AND METHODS FOR PERFORMING STORAGE OPERATIONS IN A COMPUTER NETWORK - Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection logic, a media management component is selected to manage the storage operation. In response to the initiation of a storage operation and according to a second set of selection logic, a network storage device to associate with the storage operation. The selected media management component and the selected network storage device perform the storage operation on the electronic data. | 2009-05-14 |
20090125691 | APPARATUS FOR MANAGING REMOTE COPYING BETWEEN STORAGE SYSTEMS - A resource status value, which shows the resource status of a resource to be utilized in a remote copy that conforms to a copy mode configured for a copy unit created from a first data volume and a second data volume, is acquired either regularly or irregularly. A determination is made as to whether or not the acquired resource status value exceeds a prescribed threshold, and when it is determined that the acquired resource status value exceeds this prescribed threshold, either the resource to be used for a remote copy conforming to a configured copy mode is increased, or the configured copy mode is changed to a different copy mode. | 2009-05-14 |
20090125692 | BACKUP SYSTEM AND METHOD - A storage system, upon receiving a marker from a host computer, executes a generation determination process for determining a generation of a first logical volume that is used by a host computer, and writes information related to the generation determined in this generation determination process to a physical storage device and/or a memory. A backup controller determines whether or not any data or a specified file and/or folder inside the first logical volume of the immediately preceding generation has changed, and when the result of this determination is affirmative, sends a marker insert indication, which induces the issuance of a marker, to the host computer, and when the result of the determination is negative, does not send the marker insert indication to the host computer. | 2009-05-14 |
20090125693 | TECHNIQUES FOR MORE EFFICIENT GENERATION OF XML EVENTS FROM XML DATA SOURCES - One may increase the efficiency of an XML event-generating process by reducing the number of requests to allocate or deallocate system memory. Such reduction may occur as the result of pre-allocating a memory chunk of sufficient size to contain all of the memory buffers required by a particular event-generating process. Instead of allocating new memory chunks for new memory buffers, an application may store any required buffers within the pre-allocated memory chunk. A sufficient memory size may be estimated by performing the event-generating process on a training set of XML documents. Also, an application may re-use buffers during the process or between different iterations of the process, thus avoiding the need to deallocate and reallocate memory that is essentially being used for the same purpose. | 2009-05-14 |
20090125694 | STORAGE CONTROL APPARATUS, STORAGE SYSTEM, AND VIRTUAL VOLUME CONTROL METHOD - The storage control apparatus of the present invention saves a table for managing a virtual volume in a pool and keeps the state of the table in the latest state. A first dynamic mapping table (DMT) that manages a first virtual volume is saved in a first pool. Upon receipt of a write command relating to an unused virtual slot from a write command issuing device, a first virtual volume control unit assigns an unused real slot in the first pool to the virtual slot and updates the first DMT. The first virtual volume control unit discriminates the validity of the received data and, in cases where “0” data are received, releases the assigned real slot, updates the first DMT once again, and discards the received data. In cases where the received data are valid data, de-staging is performed following a DMT update. | 2009-05-14 |
20090125695 | Thermal Control of Memory Modules Using Proximity Information - An information handling system includes a processor having access to a system memory. The system is operable to detect a thermal alert and identify an associated portion of system memory. The system may then modify memory allocation information used by an operating system to allocate system memory. When the thermal alert indicates a rising memory module temperature that exceeds a specified threshold, the modification of the memory allocation information causes the memory to appear to be more “distant” from the system processor(s) and thereby allocated less preferentially than other memory. If the temperature continues to rise beyond a higher threshold, a second modification of the memory allocation information is performed to simulate a “hot eject” of the memory module. As the memory module cools, the memory allocation information can be restored to simulate a hot add of the memory module and to restore the proximity of the memory module. | 2009-05-14 |
20090125696 | METHOD FOR PROCESSING A FILE, STORAGE MEDIUM AND PROCESSING ARRANGEMENT - A method for processing a file, a storage medium, and a processing arrangement. The method includes processing a file, the file being stored in a plurality of memory clusters of a storage medium, a portion of the file being modified and stored in a modification memory cluster, and the modified initial clusters being replaced by the respective modification memory clusters. | 2009-05-14 |
20090125697 | METHOD AND APPARATUS FOR ALLOCATION OF BUFFER - Provided are a method and apparatus for allocating a storage space that is to be used by a plurality of modules sequentially processing data. The method includes acquiring first capacity information regarding the capacity of a storage space needed for data processing of a first module and second capacity information regarding the capacity of a storage space needed for data processing of a second module that processes data consecutively to the first module, and allocating a first storage space to be used by both the first module and the second module based on at least one of the first capacity information and the second capacity information. | 2009-05-14 |
20090125698 | MEMORY CONTROLLER INCLUDING A HARDWARE COMPRESSION AND DECOMPRESSION ENGINE FOR MANAGING SYSTEM MEMORY AND GRAPHICAL OPERATIONS - An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. The IMC preferably uses a lossless data compression and decompression scheme. Data transfers to and from the integrated memory controller of the present invention can thus be in either two formats, these being compressed or normal (non-compressed). The IMC also preferably includes microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data from system I/O peripherals such as the hard drive, floppy drive, or local area network (LAN) are decompressed in the IMC and stored into system memory or saved in the system memory in compressed format. Thus, data can be saved in either a normal or compressed format, retrieved from the system memory for CPU usage in a normal or compressed format, or transmitted and stored on a medium in a normal or compressed format. Internal memory mapping allows for format definition spaces which define the format of the data and the data type to be read or written. Software overrides may be placed in applications software in systems that desire to control data decompression at the software application level. The integrated data compression and decompression capabilities of the IMC remove system bottle-necks and increase performance. This allows lower cost systems due to smaller data storage requirements and reduced bandwidth requirements. This also increases system bandwidth and hence increases system performance. Thus the IMC of the present invention is a significant advance over the operation of current memory controllers. | 2009-05-14 |
20090125699 | Adjustment of Data Storage Capacity Provided by a Storage System - A storage system stores data in at least one partition of a physical storage media in accordance with file system information specifying a plurality of logical blocks having logical block addresses within the partition. The logical blocks include excess logical blocks that are not mapped to space in the physical storage media by the mapping employed by the storage system. Unusable block data marks those excess logical blocks as unusable. This makes it easy to adjust the data storage capacity of the storage system by changing the mapping to map more or less logical block addresses to space in the physical storage media and thereby destroy or create excess logical blocks, and by changing the unusable block data to correspondingly change the excess logical blocks marked as unusable. | 2009-05-14 |
20090125700 | PROCESSING SYSTEM HAVING MEMORY PARTITIONING - Memory resource partitioning code allocates a memory partition in response to a process requesting access to memory storage. Memory partition rules may define attributes of the memory partition. The attributes may include a minimum memory allocation and a maximum memory allocation for the memory partition. | 2009-05-14 |
20090125701 | AGGREGATING DATA FROM DIFFERENT SOURCES - A method and system that aggregates data associated with one or more entities from different data sources are provided. The data sources include documents, web pages, or images that have information about one or more entities. The information is extracted from the data sources based on criteria that define the entities. The extracted information is utilized to generate a hash identifier that corresponds to each entity and one or more storage locations. The one or more storage locations and associated hash identifiers are utilized to store the extracted information corresponding to the entities, and the extracted information for each entity is structured as a virtual page that is stored in an index having references to the data sources. The index storing the virtual pages is notified or updated when the associated data sources are modified. | 2009-05-14 |
20090125702 | SIMD processor and addressing method - A single instruction, multiple data (SIMD) processor including a plurality of addressing register sets, used to flexibly calculate effective operand source and destination memory addresses is disclosed. Two or more address generators calculate effective addresses using the register sets. Each register set includes a pointer register, and a scale register. An address generator forms effective addresses from a selected register set's pointer register and scale register; and an offset. For example, the effective memory address may be formed by multiplying the scale value by an offset value and summing the pointer and the scale value multiplied by the offset value. | 2009-05-14 |
20090125703 | Context Switching on a Network On Chip - Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox, each IP block also including a stack normally used for context switching, the stack access slower than the outbox access, and each IP block further including a processor supporting a plurality of threads of execution, the processor configured to save, upon a context switch, a context of a current thread of execution in memory locations in a memory array in the outbox instead of the stack and lock the memory locations in which the context was saved. | 2009-05-14 |
20090125704 | DESIGN STRUCTURE FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS - A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions. | 2009-05-14 |
20090125705 | DATA PROCESSING METHOD AND APPARATUS WITH RESPECT TO SCALABILITY OF PARALLEL COMPUTER SYSTEMS - A data processing method for scalability of a parallel computer system includes: obtaining a processing time τ(p) that is the longest processing time in a case where a parallel processing is carried out by p processors and a processing time γ | 2009-05-14 |
20090125706 | Software Pipelining on a Network on Chip - A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block. | 2009-05-14 |
20090125707 | System and method for speculative global history prediction updating - A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR. | 2009-05-14 |
20090125708 | INTERNET APPLIANCE - A system, method and apparatus dedicated to accessing certain aspects of the Internet. The system includes a hardware device having a display and firmware associated with the display. The firmware includes a web browser and an operating system, configured to automatically connect to a datacenter server using the web browser, and to receive a frameset template from the datacenter, the frameset including frames, wherein each frame includes a preset content locator, upon boot of the operating system. The data center server may have preconfigured framesets with assigned content locators, and be configured to transmit one or more of the framesets to the device. Each frame may include content from transmitted from a different internet server upon boot of the operating system. | 2009-05-14 |
20090125709 | System And Method For A Remote Information Handling System Boot - In an information handling system (IHS), providing an IHS boot includes forcing the IHS to power on or reboot, retrieving a virtual serial peripheral interface (SPI) boot image using a virtual SPI bus, booting the IHS to the virtual SPI boot image, turning off the virtual SPI boot image, and updating a real SPI boot image. | 2009-05-14 |
20090125710 | METHOD AND APPARATUS FOR BOOTING HOST - Provided are a method and a device for booting a host embodying a downloadable conditional access system (DCAS), wherein one of a plurality of pre-determined booting modes is decided as a booting mode of the host based on first information indicating whether a host can communicate with a broadcasting service provider and second information indicating whether a software-based security client providing information required for decrypting broadcasting data is installed to a hardware-based security module connected to the host, and the host is booted in the decided booting mode. | 2009-05-14 |
20090125711 | Securing unprivileged sessions on posix systems - A method and apparatus for providing security to Portable Operating System Interface (POSIX) system. In one embodiment, a file system with noexec/nodev options is mounted on the POSIX system. The root directory of the mounted file system is changed with a chroot operation to generate a secured system directory structure. The secured system directory structure is assigned to a non-administrative user. | 2009-05-14 |
20090125712 | NETWORK COMMUNICATIONS SECURITY AGENT - One embodiment of an inventive networking environment includes clients called sending clients because they send network content through a network, and clients called receiving clients because they receive the network content from the sending clients through the network. Both sending clients and receiving clients are “clients” in that they rely on a management server to orchestrate the secure transfer of information from sending clients to receiving clients. | 2009-05-14 |
20090125713 | Wireless mesh network with secure automatic key loads to wireless devices - A wireless mesh network provides secure communication by encrypting data using one or more encryption keys. A configuration device in communication with a security manager of the network provides a temporary secure communication path between the security manager and a new field device to be added to the mesh network. Cryptographic material and other configuration data can then be transferred between the security manager of the network and the new field device securely via the configuration device. | 2009-05-14 |
20090125714 | Offline analysis of packets - A network interface and storage medium that, in an embodiment, filter packets received from a network based on rules. The filtering discards a subset of the packets based on the rules and keeps a remaining subset of the packets. The remaining subset is copied to a destination. The rules are created offline in a lower priority process from the filtering and copying by detecting whether symptoms exist in a sample of the remaining subset. In an embodiment, the order that the symptoms are detected is changed based on the frequency of the existence of the symptoms in the sample. In various embodiments, the symptoms may include receiving a threshold number of ping packets within a time period, receiving a threshold number of broadcast packets within a time period, receiving a packet with an invalid source address, and receiving a packet with an invalid header flag. | 2009-05-14 |
20090125715 | METHOD AND APPARATUS FOR REMOTELY AUTHENTICATING A COMMAND - A system that remotely authenticates a command is presented. During operation, an authentication system receives the command from an intermediary system, wherein the command is to be executed on a target system. Next, the authentication system authenticates the intermediary system. If the intermediary system is successfully authenticated, the authentication system authenticates the command using a private key for the authentication system to produce an authenticated command. Next, the authentication system sends the authenticated command to the intermediary system, thereby enabling the intermediary system to send the authenticated command to the target system so that the target system can use a public key for the authentication system to verify and execute the command. | 2009-05-14 |
20090125716 | COMPUTER INITIALIZATION FOR SECURE KERNEL - Dynamic Root of Trust for Measurement (DRTM) mechanisms can be initiated, not by CPU-manufacturer-specific instructions, but by the execution of code in System Management Mode (SMM) that can modify the values stored in specific Platform Configuration Registers (PCRs) of a Trusted Platform Module (TPM). The SMM code can be verified prior to execution and it can be trusted based on the secure mechanisms used to update such code. The SMM code can restore a known, trusted state of the computing device and can initiate the measuring of subsequently executed code. In such a manner the Trusted Computing Base (TCB) can be limited. | 2009-05-14 |
20090125717 | Methods and Apparatus for Secure Data Processing and Transmission - Methods and apparatus provide for placing an apparatus into at least one of a plurality of operational modes, wherein: the apparatus includes a local memory, a bus operable to carry information to and from the local memory, one or more arithmetic processing units operable to process data and operatively coupled to the local memory, and a security circuit operable to place the apparatus into the operational modes; and the plurality of operational modes includes: (i) a first mode whereby the apparatus and an external device are operable to initiate a transfer of information into or out of the memory over the bus, (ii) a second mode whereby neither the apparatus nor the external device are operable to initiate a transfer of information into or out of the memory over the bus, and (iii) a third mode whereby the apparatus is operable to initiate a transfer of information into or out of the local memory over the bus, but the external device is not operable to initiate a transfer of information into or out of the local memory over the bus. | 2009-05-14 |
20090125718 | DOMAIN UPGRADE METHOD IN DIGITAL RIGHTS MANAGEMENT - Disclosed is domain upgrade method in Digital Rights Management (DRM) capable of reducing network resources by simplifying signal procedures at the time of transferring changed domain keys. A device joining after domain upgrade is provided with only a domain key of a domain generation after the domain upgrade, but is not provided with a domain key of the previous domain generation. Accordingly, even if the joining device is mal-operated or is hacked, contents before upgrade are prevented from being illegally used or leaking out. | 2009-05-14 |
20090125719 | METHODS OF ENSURING LEGITIMATE PAY-PER-CLICK ADVERTISING - A method for transferring state information between a client device and a server, the client device being configured to select content, and the server having a memory module and being configured to store referenced content and to transmit referenced content to at least one client device. The method includes receiving a request on the server from the client device, wherein the request includes the state information from the client device; detecting whether the state information has previously been received by the server; updating the state information; and transmitting a response including the updated state information to the client device. | 2009-05-14 |
20090125720 | System Having Secure Access Between IC Entities - A system is provided having first and second integrated circuits. The first integrated circuit implements a first entity which stores an encryption or decryption function, one or more secret keys for use with the function, and an identity of each of the secret keys which are each indicative of an access permission to the first entity associated with each of the secret keys. The second integrated circuit implements a second entity which stores the function and is programmed and configured to issue a request to the first integrated circuit for one or more of the access permissions and associated key identities for one or more of the secret keys stored in the first entity. The first integrated circuit being programmed and configured to respond to the request by outputting the access permissions and key identities to the second entity for use with the function without outputting the secret keys. | 2009-05-14 |
20090125721 | DATA COMMUNICATION METHOD, COMPUTER AND INFORMATION STORING MEDIUM - A computer including at least two processors is used to preferably perform a secure data communication. Data containing a processor ID identifying one of the at least two processors provided for a first computer (computer | 2009-05-14 |
20090125722 | CROSS-PLATFORM DIGITAL RIGHTS MANAGEMENT PROVIDING MULTI-LEVEL SECURITY INFORMATION FLOW TRACKING - A method and system for generating and controlling access to copy-protected digital media files. Digital media content is obtained and encoded in electronic file using a media codec. The encoded media content is encrypted in the electronic file and a multi-format renderer configured to render the encoded, encrypted electronic file is embedded in the electronic file. When the digital file is accessed, the multi-format renderer generates an invocation code identifying an operation-type in response to a requested operation. A transaction ID storing a user-access policy and associated with the electronic file is retrieved and compared to the invocation code. Based on a result of the comparison of the invocation code and the user-access policy, the multi-format renderer selectively allows the invocation code. | 2009-05-14 |
20090125723 | AUTHENTICATION OF AN OBJECT - A method of authenticating an object is disclosed. Coded data portions are provided on a surface of the object. Each coded data portion encodes a position of coded data portion on the surface, an identity associated with the object and a signature fragment. The signature fragment is a fragment of a digital signature of at least part of the identity associated with the object. Next, indicating data is received from a sensing device in response to the sensing device sensing coded data portions. The indicating data is representative of the data encoded in the coded data portions sensed by the sensing device. From the indicating data the identity associate with the object, a plurality of signature fragments encoded in respective coded data portions, and the position of respective coded data portions are determined. A signature fragment identifier for respective signature fragments is determined from the respective positions. Also, a determined signature is determined by arranging the signature fragments according to their respective signature fragment identifiers. The determined signature is decrypted to obtain a determined identity. The object is authenticated by comparing the identity to the determined identity. | 2009-05-14 |
20090125724 | OBJECT AUTHENTICATION - An apparatus for authenticating an object is disclosed. The apparatus receives from a sensing device indicating data. The indicating data is formed by the sensing device in response to sensing a plurality of coded data portions on a surface of the object. Each coded data portion encodes a position of coded data portion on the surface, an identity associated with the object and a signature fragment, the signature fragment being a fragment of a digital signature of at least part of the identity associated with the object. A processor then determines from the indicating data the identity associated with the object, a plurality of signature fragments encoded in respective coded data portions, and the position of respective coded data portions, determines a signature fragment identifier for respective signature fragments from the respective positions, determines a determined signature by arranging the plurality of signature fragments according to their respective signature fragment identifiers, decrypts the determined signature to obtain a determined identity, compares the identity to the determined identity, and then authenticates the object using the result of the comparison. | 2009-05-14 |
20090125725 | EXTERNAL MEMORY ACCESS DEVICE AND METHOD OF ACCESSING EXTERNAL MEMORY - An external memory access device and a method of accessing an external memory are provided. The external memory access device includes an internal memory unit for storing authentication information of at least one external memory and a control unit for extracting the authentication information from the internal memory unit, transmitting the authentication information to an installed external memory, and controlling to display accessibility of the external memory according to the result of a comparison between the stored authentication information and the authentication information of the external memory. Accordingly, a data security function is provided by setting a password to an external memory and enabling an access to the external memory in an authenticated terminal, and convenient access to the external memory is provided by managing a password and an automatic password decrypting function of the corresponding external memory in the terminal without requiring repeated input of the password. | 2009-05-14 |
20090125726 | Method and Apparatus of Providing the Security and Error Correction Capability for Memory Storage Devices - A method and apparatus of configuring the byte structure of a memory storage device, including a flash memory device, to enhance the security and error correction capability is described. In one embodiment, the method includes increasing the security of data stored in the storage device by encrypting data with a unique initialization vector and storing the initialization vector in the storage device. The method also includes using a unique initialization vector for encrypting data, to be stored in each datablock, each time data are encrypted. In one embodiment, the apparatus includes an AES controller that includes encryption and decryption modules to encrypt and decrypt data prior to writing data to or reading from the storage device. The apparatus also includes an encoder module and decoder circuits to encode and decode data prior to writing or reading from memory storage devices. The apparatus optionally includes a state machine that generates and provides the initialization vector and also activates different components of AES controller and ECC module depending on the operation of the device. | 2009-05-14 |
20090125727 | METHOD FOR CRYPTOGRAPHIC PROCESSING OF A MESSAGE - A method for cryptographic processing of a message by a secret key includes the following steps:
| 2009-05-14 |
20090125728 | SECURITY METHOD OF SYSTEM BY ENCODING INSTRUCTIONS - The provided is a method for securing a system by encoding instructions. The method includes encoding instructions composed by a system developer and storing the encoded instructions through an encoding module during a compiling procedure, and decoding the encoded instructions and executing the decoded instructions through a decoding module. In the method, the instructions are encoded using interdependency between instructions in an instruction set which is composed by a system developer. | 2009-05-14 |
20090125729 | Original data circulation method, system, apparatus, and computer readable medium - An original data circulation system for storing or circulating original data which is digital information is provided. The original data circulation system includes an issuer apparatus, a user apparatus and a collector apparatus. The issuer apparatus generates originality information including first information corresponding to the issuer apparatus and second information corresponding to data and sends the originality information. The user apparatus verifies the validity of the source apparatus of the originality information and stores the originality information when the validity is verified. The collector apparatus verifies the validity of the source apparatus of the originality information and processes data corresponding to the second information when the validity is verified. | 2009-05-14 |
20090125730 | Managing Power Consumption In A Computer - Methods, apparatus, and products are disclose for managing power consumption in a computer, the computer including random access memory (‘RAM’) implemented in two or more memory modules, the computer having installed upon it an operating system, the operating system including a power management module, that includes: freeing, by the operating system from one or more of the memory modules, at least the amount of allocated memory in one memory module; selecting, by the operating system, at least one memory module to power down; moving, by the operating system, content of the selected memory module to other memory modules; and powering, by the operating system, down the selected memory module. | 2009-05-14 |
20090125731 | CORE VOLTAGE CONTROLLING APPARATUS - A core voltage controlling apparatus suitable for a center processing unit (CPU) is provided. The apparatus includes a level shifting unit, a time-delay unit and a logic unit. An input terminal of the level shifting unit receives and shifts a first voltage signal, and an output terminal generates a second voltage signal, in which the first voltage signal indicates a power-on stable state, and the second voltage signal indicates a magnitude of the core voltage. The time-delay unit delays the second voltage signal to generate a third voltage signal. The logic unit is coupled to the time-delay unit for performing a logic operation on the third voltage and a fourth voltage signal transmitted by a power supply, and generating a fifth voltage signal for controlling a core voltage generator whether to provide the core voltage to the CPU or not, in which the fourth voltage signal indicates a power state. | 2009-05-14 |
20090125732 | NETWORK-CONNECTABLE DEVICE AND METHOD FOR MANAGING POWER THEREOF - A network-connectable device is configured to communicate with one or more computer-related devices via a network. The network-connectable device includes: a mode selector configured to select a power mode between a first power mode and a second power mode; a power state switching unit operable on the first power mode and configured to: turn on power of the network-connectable device when one of the computer-related devices is connected to the network in a state where no computer-related device has been connected to the network; and shut down the power no computer-related device is connected to the network; and a power state maintaining unit operable on the second power mode and configured to maintain the power of the network connectable device in a same state regardless of whether the computer-related devices are connected to or disconnected from the network. | 2009-05-14 |
20090125733 | METHOD FOR REMOTE POWER CONTROL AND THE CIRCUIT THEREOF - The present invention provides a remote control system for a power supply, comprising a display data channel (DDC); a first control circuit electrically connected to said DDC, coding and sending a control signal through said DDC to control said power supply; a second control circuit electrically connected to said DDC, receiving and decoding said control signal through said DDC to control said power supply. | 2009-05-14 |
20090125734 | Power supply controlling system - A power supply controlling system includes a receiving device, a power supply device, and a transmitting device connected to an information processing apparatus. The receiving device includes a transmitting portion that transmits a switch signal of a power supply switch used for on/off of the power supply device to the transmitting device via second signal lines used for the reception of a second video signal, which are different from first signal lines used for the reception of a first video signal. The transmitting device includes an acquiring portion that acquires the switch signal from the second signal lines on which the second video signal and the switch signal are mixed, and an outputting portion that outputs the switch signal to the power supply device. The receiving device and the transmitting device are connected with a single cable including the first and the second signal lines. | 2009-05-14 |
20090125735 | Active idle communication system - To reduce power consumption and heat generation, an active idle system is proposed that monitors for an idle period and then, after a predetermined time, initiates a silent period. During the silent period data and idle frames are not transmitted. During the silent period, one or more transceiver components may be turned off or forced into some other power saving mode. The predetermined time may be any amount of time and is selected to balance network usage and power savings. Periodically during the silent period, such as at predetermined times, one or more sync or idle frames are transmitted. Received sync or idle frames are processed to maintain receiver settings, synchronization or equalizer adaptation. Restoring active data communication may occur by monitoring the channel during silent periods for a request or only during the predetermined times when sync or idle frames are sent. | 2009-05-14 |
20090125736 | Home appliance and controlling method of the same - The present invention is related to a home appliance such as a dish washer, a laundry machine, a refrigerator, etc. One embodiment of a home appliance according to the present invention comprises a control panel and a controller. The controller panel may include a power switch which allows a user to input a command for switching on or off a power of the appliance and an input device which allows the user to input a command in connection with an operation of the appliance. | 2009-05-14 |
20090125737 | Power Management of an Electronic System - A variable group power limit is enforced to limit the net power consumption of a group of devices in a computer system, and a variable device power limit enforced on each device is independently adjustable to satisfy the current group power limit. The device power limits are dynamically selected according to a power management method that selectively reduces the device power limits of lower-utilization devices and increases the device power limits of higher-utilization devices. | 2009-05-14 |
20090125738 | DATA PROCESSING APPARATUS - An access stop control apparatus is provided in a resource control apparatus so that reception of access from a master apparatus is temporarily stopped during changing of a clock frequency and the clock frequency is changed at safe timing. Thereby, the operation of the master apparatus does not need to be stopped during changing of the clock frequency and a period for which access to a resource is stopped can be suppressed. Therefore, execution of an application requiring real-timeness is not affected. | 2009-05-14 |
20090125739 | APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING INFORMATION - A receiving unit receives data from an external network device through a network. A determining unit determines whether a data processing is needed for the data received by the receiving unit. When the determining unit determines that the data processing is needed for the data, a data processing unit performs the data processing on the data. A power control unit switches, according to the data, a power mode of the information processing apparatus between a normal mode in which power is supplied to all components of the information processing apparatus and a power-saving mode in which power supplying is limited to selected components. | 2009-05-14 |
20090125740 | Dual programmable energy saving timer system - A dual control programmable energy savings timer is described that provides primary control to a utility provider or other supplier of electrical power but a second level of programmable control to an end user that enables additional power savings to end users of electrical energy. | 2009-05-14 |