20th week of 2009 patent applcation highlights part 15 |
Patent application number | Title | Published |
20090121219 | Carbon nanotubes, method of growing the same, hybrid structure and method of growing the hybrid structure, and light emitting device - Provided is a method of growing carbon nanotubes (CNTs) by forming a catalyst layer that is used to facilitate growth of CNTs to have a multi-layer structure; and injecting a carbon-containing gas to the catalyst layer to grow CNTs, and light emitting devices fabricated by incorporating the CNTs grown. | 2009-05-14 |
20090121220 | High performance sub-system design and assembly - A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry. | 2009-05-14 |
20090121221 | High performance sub-system design and assembly - A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry. | 2009-05-14 |
20090121222 | Test Structure - A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads. | 2009-05-14 |
20090121223 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips. | 2009-05-14 |
20090121224 | DUAL GATE OF SEMICONDUCTOR DEVICE CAPABLE OF FORMING A LAYER DOPED IN HIGH CONCENTRATION OVER A RECESSED PORTION OF SUBSTRATE FOR FORMING DUAL GATE WITH RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers. | 2009-05-14 |
20090121225 | Thin film transistor, method for manufacturing the same and display using the same - One embodiment of the present invention is a thin film transistor including a gate electrode formed on an insulating substrate, a gate insulator formed on the gate electrode, a drain electrode and a source electrode formed on the gate insulator, an oxide semiconductor pattern formed between the drain electrode and the source electrode, and a sealing layer formed on the oxide semiconductor pattern. | 2009-05-14 |
20090121226 | ACTIVE-MATRIX DEVICE, ELECTRO-OPTICAL DISPLAY DEVICE, AND ELECTRONIC APPARATUS - An active-matrix device includes a substrate; a plurality of pixel electrodes provided on a first surface of the substrate; a plurality of switching elements provided to correspond to each of the pixel electrodes, each of the switching elements including a fixed electrode connected to the each pixel electrode, a movable electrode mainly made of silicon and displaceably provided so as to contact with and separate from the fixed electrode, and a driving electrode provided to oppose the movable electrode via an electrostatic gap; a first wiring connected to the movable electrode; and a second wiring connected to the driving electrode, wherein a voltage is applied between the movable electrode and the driving electrode to generate an electrostatic attraction between the movable electrode and the driving electrode so as to displace the movable electrode such that the movable electrode contacts with the fixed electrode to electrically connect the first wiring to the pixel electrode. | 2009-05-14 |
20090121227 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY DEVICE - A method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a pattern made of a first conductive film; stacking a gate insulating film, a semiconductor layer, and a resist in the stated order; forming a resist pattern having a step structure in a thickness direction; forming an exposed area of the first conductive film and a pattern of the semiconductor layer by using the resist pattern; forming a pattern made of a second conductive film in contact with the first conductive film in the exposed area of the first conductive film; and forming a pattern made of a third conductive film. The first conductive film forms a gate electrode, and the second conductive film forms each of a source electrode and a drain electrode. The third conductive film forms a pixel electrode, and the second conductive film is coated with an upper-layer film. | 2009-05-14 |
20090121228 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed. | 2009-05-14 |
20090121229 | Display device - In a display device which includes: an insulation substrate; thin film transistors which are formed on the insulation substrate; and terminal portions which are configured to supply voltages to the thin film transistors, the thin film transistor includes a gate electrode and a gate line which is formed of a material equal to a material of the gate electrode, a metal line is connected to the terminal portion, a first insulation film and a second insulation film which is made of a material different from a material of the first insulation film are sequentially stacked on the gate line, an opening which exposes the gate line is formed in the first insulation film and the second insulation film, a side wall surface of the opening is sequentially covered with a protective film, a first transparent conductive film and a third insulation film, the first transparent conductive film and a second transparent conductive film are sequentially stacked on an exposed portion of the gate line, and the second transparent conductive film is connected with the metal line. | 2009-05-14 |
20090121230 | LIGHT EMITTING DEVICE - A light emitting device is disclosed. The light emitting device includes a substrate including a thin film transistor, an insulating film disposed over the thin film transistor, a first electrode disposed over the thin film transistor and connected to the thin film transistor, a function layer including at least one of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, which are sequentially disposed over the first electrode, and a second electrode disposed on the function layer. A thickness of the first electrode is substantially 0.29 to 0.35 times a thickness of the function layer. A thickness of the second electrode is substantially 0.29 to 0.69 times the thickness of the function layer. | 2009-05-14 |
20090121231 | THIN FILM TRANSISTORS, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT-EMITTING DIODE DEVICE USING THE SAME - Aspects of the invention relate to thin film transistors, a method of fabricating the same, and an organic light-emitting diode device using the same. A thin film transistor according to an aspect of the invention includes a semiconductor layer formed from polysilicon in which a grain size deviation is within a range of substantially ±10%. Accordingly, aspects of the invention can improve non-uniformity of image characteristics due to a non-uniform grain size in polysilicon produced by a sequential lateral solidification (SLS) crystallization process. | 2009-05-14 |
20090121232 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY PANEL HAVING THE SAME - An array substrate, a method for manufacturing the array substrate and a display panel having the array substrate are presented. The method includes forming a thin-film transistor (TFT) on a base substrate. A passivation layer covers the TFT. A color filter layer is formed on the passivation layer. An organic protective layer is formed on the color filter layer, and has a type of photoresist that is substantially the same as that of the color filter layer. A contact hole is formed through the organic protective layer, the color filter layer and the passivation layer, partially exposing the TFT. A pixel electrode is formed on the organic protective layer to be electrically connected to a portion of the TFT. The contact hole may be formed through the organic protective layer, the color filter layer and the passivation layer by a single photolithography process, simplifying the array substrate manufacturing process. | 2009-05-14 |
20090121233 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device includes a semiconductor layer, a gate electrode, and a first insulating film, and a second insulating under the semiconductor layer. The first insulating film overlaps a junction region, but not a channel region, of the semiconductor layer. The gate electrode includes a first extended portion that continuously covers an upper and side face and of the first insulating film at the junction region. The gate electrode includes a second extended portion that overlaps and fills a groove in the second insulating that extends along at least the junction region. | 2009-05-14 |
20090121234 | Liquid crystal display device and fabrication method thereof - A liquid crystal display device including a gate electrode and a gate line formed on a first substrate, a first insulating layer formed on the first substrate, an active pattern, an ohmic-contact layer, and a diffusion preventing layer formed on the gate electrode, a data line to cross source and drain electrodes and the gate line formed on the diffusion preventing layer to define a pixel area, a second insulating layer formed on the first substrate, a contact hole formed by removing a portion of the second insulating layer and exposing a portion of the drain electrode, a pixel electrode electrically connected with the drain electrode via the contact hole, and a second substrate attached with the first substrate in a facing manner, wherein the diffusion preventing layer comprises a metal tip protruded to the side of the source and drain electrodes. | 2009-05-14 |
20090121235 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A transistor of a semiconductor device includes a substrate, a gate over the substrate, a source/drain region formed in the substrate to have a channel region therebetween, and an epitaxial layer formed below the channel region to have a different lattice constant from the substrate. The epitaxial layer having a different lattice constant with a substrate material is formed below the channel region to apply a stress to the channel region. Thus, the mobility of carriers of the transistor increases. | 2009-05-14 |
20090121236 | Optocoupler using silicon based LEDs - This invention details how a low cost opto coupler can be made on Silicon On Insulator (SOI) using conventional integrated circuit processing methods. Specifically, metal and deposited insulating materials are use to realize a top reflector for directing light generated by a silicon PN junction diode to a silicon PN junction photo diode detector. The light generator or LED can be operated either in the avalanche mode or in the forward mode. Also, side reflectors are described as a means to contain the light to the LED-photo detector pair. Furthermore, a serpentine junction PN silicon LED is described for the avalanche mode of the silicon LED. For the forward mode, two LED structures are described in which hole and electrons combine in lightly doped regions away from heavily doped regions thereby increasing the LED conversion efficiency. | 2009-05-14 |
20090121237 | LED ARRAY FOR MICRODISPLAYS OR LIKE APPLICATIONS, AND METHOD OF FABRICATION - An array of LEDs are grown by epitaxy on row-connecting conductor strips extending in parallel spaced relationship to one another on the surface of a semiconductor substrate and are thereby electrically interconnected in rows. The row-connecting conductor strips are formed by ion implantation of a p-type dopant into parts of an n-type silicon substrate. Column-connecting conductor strips extend over the light-emitting surfaces of the LEDs for electrically interconnecting them in columns. The LEDs are lit up individually by voltage application between one of the row-connecting conductor strips and one of the column-connecting conductor strips. | 2009-05-14 |
20090121238 | DOUBLE COLLIMATOR LED COLOR MIXING SYSTEM - The present invention is directed to a lighting apparatus. In one embodiment the lighting apparatus includes a plurality of light emitting diode (LED) chips. A first optic is coupled to the plurality of LED chips. A diffuser is coupled to the first optic. In addition, a second optic is coupled to the diffuser. | 2009-05-14 |
20090121239 | DISPLAY DEVICE - A display device includes light emitting elements corresponding to respective colors disposed on a substrate. Each of the light emitting elements corresponding to the respective colors has a cavity structure in which a light emission functioning layer including a light emitting layer is held between a reflecting electrode and a semitransmitting electrode. A cavity order of at least the light emitting element adapted to resonate a light, having the shortest wavelength, of the light emitting elements corresponding to the respective colors is 1, and a cavity order of each of other light emitting elements is 0. The light emission functioning layer except for the light emitting layer is common to the light emitting elements corresponding to the respective colors. | 2009-05-14 |
20090121240 | Nitride Semiconductor Device and Method for Manufacturing the Same - There is provided a nitride semiconductor device with low leakage current and high efficiency in which, while a zinc oxide based compound such as Mg | 2009-05-14 |
20090121241 | Wire bond free wafer level LED - A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device. | 2009-05-14 |
20090121242 | COMPOUND SEMICONDUCTOR LIGHT-EMITTING DIODE AND METHOD FOR FABRICATION THEREOF - A compound semiconductor light-emitting diode includes a light-emitting layer formed of aluminum-gallium-indium phosphide, a light-emitting part | 2009-05-14 |
20090121243 | LIGHT EMITTING DEVICES - Light-emitting devices, and related components, systems and methods are disclosed. | 2009-05-14 |
20090121244 | LED packaging structure and production method thereof - An LED packaging structure and a production method thereof; the LED packaging structure includes an LED die placed on a metal substrate and packed with seal in conjunction with a transparent substrate to deliver advantages of compact, simplified process and long service life and provide significant advancement and industrial value when compared to the prior art. | 2009-05-14 |
20090121245 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip is disclosed which emits electromagnetic radiation from its front side ( | 2009-05-14 |
20090121246 | LED with current confinement structure and surface roughening - An LED having a p-type layer of material with an associated p-contact, an n-type layer of material with an associated n-contact and an active region between the p-type layer and the n-type layer, includes a confinement structure that is formed within one of the p-type layer of material and the n-type layer of material. The confinement structure is generally aligned with the contact on the top and primary emission surface of the LED and substantially prevents the emission of light from the area of the active region that is coincident with the area of the confinement structure and the top-surface contact. The LED may include a roughened emitting-side surface to further enhance light extraction. | 2009-05-14 |
20090121247 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a base portion having a concaved portion; a light emitting element provided in the concaved portion; a resin filled in the concaved portion; and a phosphor contained resin layer containing a wave converting substance and provided to close an opening portion of the concaved portion. The phosphor contained resin layer has a lower thermal expansion coefficient than the resin filled in the concaved portion. | 2009-05-14 |
20090121248 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND PLANAR LIGHT SOURCE - A semiconductor light emitting device includes: a base portion having a concave portion formed in one of major surfaces thereof; and a light emitting element mounted on a bottom surface of the concave portion of the base portion. The base portion comprises a side wall portion that surrounds the light emitting element. The light emitting element is covered with a resin portion filled in the concave portion. At least a part of an upper surface of the resin portion is positioned closer to the bottom surface of the concave portion than an upper surface of the side wall portion. | 2009-05-14 |
20090121249 | PACKAGE STRUCTURE OF A LIGHT EMITTING DIODE DEVICE AND METHOD OF FABRICATING THE SAME - A package structure for light emitting diode devices comprises a substrate having a reflective cavity, a die mounted inside the reflective cavity, a reflective layer disposed on the surface of the reflective cavity, a plurality of electrodes disposed under the surface of the substrate which is opposite to the reflective cavity, and a dual brightness enhancement film overlaid on the reflective cavity. The dual brightness enhancement film efficiently reflects the polarized light that is generated from the die and is not in a transparent direction back to the reflective layer. Subsequently, this light is reflected from the reflective layer to the dual brightness enhancement film. The portions of the reflected light propagating in the same direction as the transparent direction will transmit through the package structure. | 2009-05-14 |
20090121250 | HIGH LIGHT EXTRACTION EFFICIENCY LIGHT EMITTING DIODE (LED) USING GLASS PACKAGING - An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED) combined with a shaped optical element in which the directional light from the ZnO cone or any high refractive index material in contact with the LED surface entering the shaped optical element is extracted to air. | 2009-05-14 |
20090121251 | Siloxane-hydantoin copolymer, optoelectronic device encapsulated therewith and method - The invention provides a siloxane-hydantoin copolymer, an optoelectronic device encapsulated therewith, and methods thereof. The siloxane-hydantoin copolymer comprises a unit selected from the group consisting of Y | 2009-05-14 |
20090121252 | METHOD FOR MANUFACTURING FLIP-CHIP LIGHT EMITTING DIODE PACKAGE - A method for manufacturing flip-chip light emitting diode (LED) package fabricates a silicon submount with at least one groove by wet etching. Two vias are defined on base of the groove, wherein each via has a contact pad thereon and a bottom electrode on bottom thereof. An LED die is flip-chip mounted in the groove with the electrodes thereof electrically connected to the contact pads. A protective glue is applied to fill the groove and provides a flat top face. A phosphor layer is formed on the flat top face by printing. The phosphor layer is formed with excellent uniformity due to the flat top face, and provides uniform wavelength conversion effect. Alternatively, a phosphor plate is manufactured in advance and selected with desired color temperature parameter. The phosphor plate with desired color temperature parameter is attached to the flat top face of the protective glue instead of printing. | 2009-05-14 |
20090121253 | LIGHT-EMITTING APPARATUS AND METHOD OF MANUFACTURING THE SAME - The present invention provides a light-emitting apparatus capable of improving brightness and reducing power consumption and a method of manufacturing the same. The light-emitting apparatus includes: a light-emitting device | 2009-05-14 |
20090121254 | Method for Modification of Built In Potential of Diodes - In broad terms the present invention is a semiconductor junction comprising a first material ( | 2009-05-14 |
20090121255 | RESIN FOR OPTICAL-SEMICONDUCTOR-ELEMENT ENCAPSULATION CONTAINING POLYIMIDE AND OPTICAL SEMICONDUCTOR DEVICE OBTAINED WITH THE SAME - The present invention relates to a resin for optical-semiconductor-element encapsulation containing a polyimide which is produced by imidizing a polyimide precursor obtained by subjecting 5-norbornene-2,3-dicarboxylic anhydride or maleic anhydride, an aliphatic tetracarboxylic dianhydride, and an aliphatic diamine compound to a condensation polymerization reaction. The resin of the invention has excellent heat resistance and excellent light-transmitting properties. In addition, the present invention also relates to an optical semiconductor device containing an optical semiconductor element encapsulated with the resin. | 2009-05-14 |
20090121256 | SEMICONDUCTOR DEVICE WITH IMPROVED SHORT CHANNEL EFFECT OF A PMOS AND STABILIZED CURRENT OF AN NMOS AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area. | 2009-05-14 |
20090121257 | SEMICONDUCTOR SUPERJUNCTION STRUCTURE - Embodiments of semiconductor structures are provided for a semiconductor device employing a superjunction structure. The device includes interleaved regions of first and second semiconductor materials of, respectively, first and second conductivity types and first and second mobilities. The second conductivity type is opposite the first conductivity type and the second mobility exceeds the first mobility for a first carrier type. The first and second semiconductor materials are separated by substantially parallel PN junctions and form a superjunction structure. The device also includes electrical contacts coupled to the first and second materials so that, in response to applied signals, a principal current of the first carrier type flows through the second material. | 2009-05-14 |
20090121258 | FIELD EFFECT TRANSISTOR CONTAINING A WIDE BAND GAP SEMICONDUCTOR MATERIAL IN A DRAIN - A field effect transistor comprising a silicon containing body is provided. After formation of a gate dielectric, gate electrode, and a first gate spacer, a drain side trench is formed and filled with a wide band gap semiconductor material. Optionally, a source side trench may be formed and filled with a silicon germanium alloy to enhance an on-current of the field effect transistor. Halo implantation and source and drain ion implantation are performed to form various doped regions. Since the wide band gap semiconductor material as a wider band gap than that of silicon, impact ionization is reduced due to the use of the wide band gap semiconductor material in the drain, and consequently, a breakdown voltage of the field effect transistor is increased compared to transistors employing silicon in the drain region. | 2009-05-14 |
20090121259 | PAIRED MAGNETIC TUNNEL JUNCTION TO A SEMICONDUCTOR FIELD-EFFECT TRANSISTOR - A magnetic tunnel junction paired to a semiconductor field-effect transistor is described. In one embodiment, there is a circuit that comprises at least one semiconductor field-effect transistor and a magnetic tunnel junction coupled to the at least one semiconductor field-effect transistor. The magnetic tunnel junction has a control line that is configured to control operational characteristics of the at least one semiconductor field-effect transistor. | 2009-05-14 |
20090121260 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 2009-05-14 |
20090121261 | STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETs - A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided. | 2009-05-14 |
20090121262 | SEMICONDUCTOR DEVICE CAPABLE OF IMPROVING CONTACT RESISTANCE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a gate formed over a semiconductor substrate; a junction region formed in a portion of the semiconductor substrate corresponding to both sides of the gate and including a projection, of which at least some portion thereof projects from the surface of the portion of the semiconductor substrate; and a contact plug formed so as to cover the projection. | 2009-05-14 |
20090121263 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device comprises a first conductive film formed downward, perpendicular to a substrate, penetrating through a first insulating film, a second conductive film formed downward along an outer wall of a second insulating film, a third insulating film formed from the bottom of the second conductive film to the top of the substrate in an area sandwiched between the first and second insulating films, contacting with at least the bottom of the second conductive film and an outer wall on a side which does not contact with the second insulating film, and a first impurity diffusion area of a first conductivity type, a second impurity diffusion area of a second conductivity type, a third impurity diffusion area of the first conductivity type and a fourth impurity diffusion area of the first conductivity type in a high concentration layered within the area sandwiched between the first and third insulating films. | 2009-05-14 |
20090121264 | CMOS IMAGE SENSOR AND METHOD OF FORMING THE SAME - A CMOS image sensor is formed utilizing a through-poly implantation process. First, a substrate including a photo-sensing region and a transistor region is provided. Subsequently, at least a gate structure is formed on a surface of the substrate within the transistor region. Thereafter, an ion implantation process is performed on the substrate to form a first conductive type well in the substrate through the gate structure. Since the ion implantation process implants ions into the substrate to a channel region of the transistor through the gate structure, the implant depth of the uncovered parts of the substrate is deeper than the implant depth of the parts of the substrate covered by the gate structure, and defects caused by the energy of the ion implantation process are prevented within the channel region. | 2009-05-14 |
20090121265 | LIGHT MODULATING SENSING MOSFET TRANSISTOR AND PROCESS FOR MANUFACTURING THE SAME - A Light Modulating sensing MOSFET transistor includes: a substrate receiving light radiation, the substrate having two source and drain areas separated by a channel extending along a first direction; a gate conductive beam extending along a second direction being substantially perpendicular to the first direction, the beam being fixed at each of its two opposite ends on at least one supporting area and being located above the channel area, the gate beam being substantially opaque and flexible so as to perform progressive modulation of the light reaching the channel in accordance with its bending controlled by the difference of voltage between the gate and the bulk and causing the beam to bend and to come closer to the surface of the channel. A process for manufacturing a light Modulating sensing MOSFET transistor is also provided. | 2009-05-14 |
20090121266 | METHODS AND STRUCTURES FOR EXCHANGE-COUPLED MAGNETIC MULTI-LAYER STRUCTURE WITH IMPROVED OPERATING TEMPERATURE BEHAVIOR - Exchange-coupled magnetic multilayer structures for use with toggle MRAM devices and the like include a tunnel barrier layer ( | 2009-05-14 |
20090121267 | Spin field effect transistor using half metal and method of manufacturing the same - A spin field effect transistor may include at least one gate electrode, a channel layer, a first stack and a second stack separate from each other on a substrate, wherein the channel layer is formed of a half metal. The half metal may be at least one material selected from the group consisting of chrome oxide (CrO | 2009-05-14 |
20090121268 | Semiconductor Memory Devices Having Vertical Channel Transistors and Related Methods - A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed. | 2009-05-14 |
20090121269 | INTEGRATED CIRCUIT COMPRISING A TRANSISTOR AND A CAPACITOR, AND FABRICATION METHOD - An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell. | 2009-05-14 |
20090121270 | DESIGN STRUCTURE FOR A TRENCH CAPACITOR - A design structure of a trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The design structure resulting from the means for fabricating the trench capacitor includes the methods of forming a trench in the semiconductor substrate; depositing a dielectric layer on a sidewall of the trench; filling the trench with a first layer of undoped polysilicon; etching away the first layer of undoped polysilicon and the dielectric layer from an upper section of the trench whereby the semiconductor substrate is exposed at the sidewall in the upper section of the trench; forming an isolation collar layer on the sidewall in the upper section of the trench; and filling the trench with a second layer of doped polysilicon. | 2009-05-14 |
20090121271 | Vertical-type non-volatile memory devices - In a semiconductor device, and a method of manufacturing thereof, the device comprises a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel. | 2009-05-14 |
20090121272 | FABRICATION METHOD OF NANOPARTICLES BY CHEMICAL CURING - Disclosed is a method of producing nanoparticles by using chemical curing. The method includes depositing a metal thin film on a substrate, applying an insulator precursor on a metal thin film, and adding a curing agent and a catalyst to the insulator precursor to perform the chemical curing. The method also includes mixing metal powder and an insulator precursor, applying a mixture on a substrate, and adding a curing agent and a catalyst to the mixture to perform the chemical curing. Since the chemical curing process is used in the method, it is possible to form nanoparticles by using a simple process at low cost while a high temperature process such as thermal curing is not used. | 2009-05-14 |
20090121273 | Low-voltage memory having flexible gate charging element - In a non-volatile semiconductor memory device including a source region separated from a drain region by a channel region and with an electrically floating gate electrode spaced from and overlying the channel region, a flexible member is spaced from the floating gate and capable of being flexed towards the floating gate for depositing or removing electrical charge on the floating gate in response to a voltage potential between the flexible member and the channel region. In one embodiment, the flexible member comprises a contact gate electrode. In another embodiment, only a single gate electrode is employed without a separate floating gate. | 2009-05-14 |
20090121274 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A salicide treatment is performed on a common source line to reduce surface resistance and contact resistance, thereby improving a cell current characteristic. Therefore, a chip can be reduced in size and chips per wafer can be increased, thereby achieving high yield. In addition, it is possible to overcome the structural limitation of the flash cell when the semiconductor memory device is highly integrated and shrunken. | 2009-05-14 |
20090121275 | Non-Volatile Memory Devices Including Blocking and Interface Patterns Between Charge Storage Patterns and Control Electrodes and Related Methods - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed. | 2009-05-14 |
20090121276 | NONVOLATILE MEMORY DEVICES WITH RECESSED WORD LINES - A nonvolatile memory device includes a substrate, a device isolation region disposed in the substrate and abutting a sidewall of an active region defined in the substrate, the device isolation region having a recessed portion and a word line crossing the active region and the recessed portion of the device isolation region and conforming to the sidewall adjacent the recessed portion of the device isolation region. The nonvolatile memory device may further include a sense line crossing the active region and the device isolation region parallel to the word line, the sense line overlying a portion of the device isolation region having a top surface at substantially the same level as a top surface of the active region. An edge of the active region adjacent the sidewall may be rounded. | 2009-05-14 |
20090121277 | Nonvolatile memory device and method of manufacturing the same - The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer. | 2009-05-14 |
20090121278 | STRUCTURE AND FABRICATION METHOD OF FLASH MEMORY - A method for forming a flash memory cell and the structure thereof is disclosed. The flash memory cell includes a substrate, a first raised source/drain region and a second raised source/drain region separated by a trench in-between, a first charge-trapping spacer and a second charge-trapping spacer respectively on the sidewall of the first and second raised source/drain region, a gate structure covering the first and second spacers, the trench and the first and second raised source/drain regions and a gate oxide layer located between the gate structure and the first and second raised source/drain regions and the substrate. By forming the charge-trapping spacers with less e-distribution, the flash memory affords better erasure efficiency. | 2009-05-14 |
20090121279 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a single crystal silicon substrate an insulating layer partially formed on the single crystal silicon substrate, a single crystal silicon layer formed on the single crystal silicon substrate and the insulating layer, and containing a defect layer resulting from an excessive group IV element, and a plurality of first gate structures for memory cells, each including a first gate insulating film formed on the single crystal silicon layer, a charge storage layer formed on the first gate insulating film, a second gate insulating film formed on the charge storage layer, and a control gate electrode formed on the second gate insulating film. | 2009-05-14 |
20090121280 | SEMICONDUCTOR DEVICES, METHODS OF FORMING THE SEMICONDUCTOR DEVICES AND METHODS OF OPERATING THE SEMICONDUCTOR DEVICES - Described are a semiconductor device, methods of forming the semiconductor device and methods of operating the semiconductor device. The semiconductor device includes a gate electrode and laminated charge trap layers interposed between substrates. The methods of forming the semiconductor device include forming a gate stacked structure including insulating layers having a different etching selectivity, forming spaces on sidewalls of the gate stacked structure using an etching selectivity and forming charge trap layers in the spaces. The methods of operating the semiconductor device include programming trap layers by controlling a voltage applied to a gate electrode. | 2009-05-14 |
20090121281 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has an element isolation region between rewrite units of memory cells. A plurality of memory cells are memory cell groups arranged in a row direction, and each memory cell group consists of (8×N) memory cells arranged in a row direction as a unit to be used as a storage region. The number of a plurality of selection word lines is at least eight, and the number of selection transistors corresponding to at least N is connected to each of the plurality of selection word lines. At least one selection transistor in addition to (8×N) selection transistors are connected in total to the plurality of selection word lines. A plurality of main bit lines includes at least one main bit line in addition to (4×N) main bit lines connected to the common drain of a pair of selection transistors. | 2009-05-14 |
20090121282 | Non-Volatile Memory Device and Method for Manufacturing the Same - An increase of charge storing capacity, prevention of an over-erase, and a reduction of ΔVth may be achieved when a 2-bit/cell non-volatile memory device includes a gate of a predetermined width above a semiconductor substrate, an insulating layer between the gate and the semiconductor substrate and at lateral sides of the gate, having a greater width than the gate, a pair of storage layers at the lateral sides of the gate, a pair of blocking layers at the lateral sides of the gate and covering the pair of storage layers, a source and a drain formed in the semiconductor substrate at first opposed locations external to the gate, and a trap impurity implanted into the insulating layer at second locations external to the gate. | 2009-05-14 |
20090121283 | Semiconductor device and fabrication method of the same - A semiconductor device includes a substrate; a first insulating layer provided on the substrate; a conductive layer buried in the first insulating layer; a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lower diffusion layer being electrically connected to the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer; a gate insulating film provided on a peripheral side surface of the semiconductor layer; a gate electrode provided on the gate insulating film; and a second insulating layer provided such that the gate electrode and a circumference of the semiconductor pillar are buried in the second insulating layer. | 2009-05-14 |
20090121284 | Semiconductor device and method for manufacturing the same - A sacrifice oxide film is formed in a Fin semiconductor substrate portion, and impurities are then implanted in the semiconductor substrate through a mask pattern as a mask. Thereafter, the sacrifice oxide film is removed to expose the semiconductor substrate. A gate insulating film is then formed on the exposed semiconductor substrate. | 2009-05-14 |
20090121285 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer, a first semiconductor region provided on a major surface of the semiconductor layer, a second semiconductor region provided in a surface portion of the first semiconductor region, a trench extending through the second semiconductor region and the first semiconductor region to the semiconductor layer, a first insulating film provided on an inner wall of the trench, a third semiconductor region filling the trench below an interface between the semiconductor layer and the first semiconductor region, a second insulating film provided on the third semiconductor region, a gate electrode filling the trench above the second insulating film. A portion of the first insulating film in contact with the semiconductor layer is opened. The semiconductor layer is in contact with the third semiconductor region through the opened portion. | 2009-05-14 |
20090121286 | Integrated Circuit Comprising a Field Effect Transistor and Method of Fabricating the Same - An integrated circuit includes a field effect transistor including: a gate electrode disposed adjacent to a surface of semiconductor substrate and a source/drain region disposed in the semiconductor substrate and adjacent to the surface. A net dopant concentration of a first section of the source/drain region decreases towards the gate electrode along a direction perpendicular to the surface. | 2009-05-14 |
20090121287 | DUAL WIRED INTEGRATED CIRCUIT CHIPS - A semiconductor device having wiring levels on opposite sides, a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides, and a design structure of a semiconductor device having wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts. | 2009-05-14 |
20090121288 | MULTIPLE GATE FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING SAME - The present invention relates to a Multiple Gate Field Effect Transistor structure and a method for fabricating same. The Multiple Gate Field Effect Transistor structure includes a fin structure made from at least one active semiconductor layer of a silicon on insulator (SOI) structure on a buried insulator of the structure. The Multiple Gate Field Effect Transistor structure also includes an insulator of at least one high-k layer of a material having a dielectric constant that is higher than silicon oxide. This has the advantage that the high-k layer acts as a better etch stop than silicon oxide during formation and cleaning of the fin resulting in a lower recess and undercut effect on the socket of the fin. This leads to a higher stability of the formed fin and enables a smooth finishing of the fin by etching and cleaning steps. | 2009-05-14 |
20090121289 | FIELD EFFECT TRANSISTOR WITH A HETEROSTRUCTURE AND ASSOCIATED PRODUCTION METHOD - A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1 -x),where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized. | 2009-05-14 |
20090121290 | Semiconductor device with high-breakdown-voltage transistor - A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside electrode on a back side of the semiconductor layer. The element portion is configured as a vertical transistor that causes an electric current to flow in a thickness direction of the semiconductor layer between the first wiring and the backside electrode. The backside electrode is elongated to the wiring portion. The wiring portion has a second wiring on the front side of the semiconductor layer. The wiring portion and the backside electrode provide a pulling wire that allows the electric current to flow to the second wiring. | 2009-05-14 |
20090121291 | DENSE CHEVRON NON-PLANAR FIELD EFFECT TRANSISTORS AND METHOD - Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area. | 2009-05-14 |
20090121292 | Fabrication of local damascene finFETs using contact type nitride damascene mask - Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distinguished by the vertical offset from a reference plane defined by the surface of the active regions. These three regions will include a lower surface found in the recessed openings resulting from the damascene etch, an intermediate surface and an upper surface on the remaining portions of the lateral field insulating regions. The general correspondence between the reference plane and the intermediate surface will tend to suppress or eliminate residual gate electrode materials from this region during formation of the gate electrodes, thereby improving the electrical isolation between adjacent active regions and improving the performance of the resulting semiconductor devices. | 2009-05-14 |
20090121293 | Semiconductor device and method for manufacturing same - The semiconductor device includes a semiconductor substrate, a plurality of source regions formed in a stripe shape on the semiconductor substrate, a plurality of gate electrodes formed in a stripe shape between a plurality of the stripe shaped source regions on the semiconductor substrate, an insulating film for covering the source regions and the gate electrodes, the insulating film including a contact hole for partly exposing the source regions in a part of a predetermined region with respect to a longitudinal direction of the source regions; and a source electrode formed on the insulating film and electrically connected to the source region via the contact hole. | 2009-05-14 |
20090121294 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The semiconductor device includes a source offset type MOS transistor in which a source and a drain are formed on a semiconductor substrate by having a predetermined distance between the source and the drain, and a gate electrode is formed on the semiconductor substrate between the source and the drain via a gate insulation film. One end of the drain overlaps or abuts on one end of the gate electrode when viewed from above the gate electrode, and the source is formed by having a distance from the gate electrode when viewed from above the gate electrode. | 2009-05-14 |
20090121295 | METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES - Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET. | 2009-05-14 |
20090121296 | Semiconductor device including dummy gate part and method of fabricating the same - In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions. | 2009-05-14 |
20090121297 | GATE ELECTRODE HAVING A CAPPING LAYER - A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. | 2009-05-14 |
20090121298 | FIELD EFFECT TRANSISTOR - A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode. | 2009-05-14 |
20090121299 | Wafer level sensing package and manufacturing process thereof - A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer. | 2009-05-14 |
20090121300 | MICROELECTRONIC IMAGER PACKAGES AND ASSOCIATED METHODS OF PACKAGING - The microelectronic imager packages include a semiconductor die having a plurality of photo sensors, a cover spaced apart from the semiconductor die and facing the photo sensors, and a coupling structure between the semiconductor die and the cover. The coupling structure has a spacer separating the semiconductor die and the cover and an adhesive proximate to the spacer. The adhesive bonds the spacer, the semiconductor die, and the cover together. | 2009-05-14 |
20090121301 | IMAGE CAPTURE MODULE - An image capture module includes an image sensor and a photochromic glass plate. The image sensor includes a photosensitive area. The photochromic glass plate is positioned in front of the photosensitive area, adjusting light transmittance therethrough according to current ambient light conditions, thereby adjusting exposure value of the image sensor. In addition to the image sensor and the photochromic glass plate, the image capture module may further include a lens unit and a packaging substrate. The substrate defines a cavity therein, in which the image sensor is disposed. The photochromic glass plate seals the cavity. The lens unit is disposed on the photochromic glass plate. During image capture, light enters and is transmitted through the lens unit and the photochromic glass plate, forming an image on the photosensitive area of the image sensor. The image sensor converts the visual image into digital data. | 2009-05-14 |
20090121302 | Chip Package - A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip. | 2009-05-14 |
20090121303 | Semiconductor package - A semiconductor package. The semiconductor package of the invention comprises: a substrate comprising at least one exposed area with photosensitive devices; a cover for isolating the exposed area from the external atmosphere, wherein one of either the substrate or the cover is a base, and the other is a top structure; and a dam formed on the base to form a cavity, wherein the top of the dam has a recess, the dam is attached the top structure by an adhesive, and the cavity corresponds to the exposed area. | 2009-05-14 |
20090121304 | SOLID-STATE IMAGE PICKUP DEVICE, PROCESS FOR PRODUCING THE SAME AND ELECTRONIC DEVICE - A camera module | 2009-05-14 |
20090121305 | Front-Illuminated Avalanche Photodiode - The present invention provides a front-illuminated avalanche photodiode (APD) with improved intrinsic responsivity, as well as a method of fabricating such a front-illuminated APD. The front-illuminated APD comprises an APD body of semiconductor material, which includes a substrate and a layer stack disposed on a front surface of the substrate. The layer stack includes an absorption layer, a multiplication layer, and a field-control layer. Advantageously, a back surface of the APD body is mechanically and chemically polished, and a reflector having a reflectance of greater than 90% at the absorption wavelength band is disposed on the back surface of the APD body. Thus, incident light that is not absorbed in a first pass through the absorption layer is reflected by the reflector for a second pass through the absorption layer, increasing the intrinsic responsivity of the front-illuminated APD. | 2009-05-14 |
20090121306 | Photodiode Array - The present invention provides a photodiode array which can secure a sufficient aperture ratio with respect to light to be detected while restraining crosstalk between photodetecting channels even during operation in Geiger mode. In a photodiode array | 2009-05-14 |
20090121307 | SIMULTANEOUS UNIPOLAR MULTISPECTRAL INTEGRATED TECHNOLOGY (SUMIT) DETECTORS - A multi-color photo sensor having a first photodiode with a first p-type layer and a first n-type layer, the first photodiode generates charge when illuminated with photons of a first wavelength range, a second photodiode with a second p-type layer and a second n-type layer, the second photodiode generates charge when illuminated with photons of a second wavelength range, and a readout integrated circuit electrically coupled to the first n-type layer of the first photodiode via a first metal interconnect and electrically coupled to the second n-type layer of the second photodiode via a second metal interconnect, the second metal interconnect traverses through the first photodiode to contact the second n-type layer of the second photodiode, the second metal interconnect is separated from the first photodiode by a first passivating insulator. | 2009-05-14 |
20090121308 | IMAGE SENSING DEVICE AND METHOD OF - A two-dimensional, temporally modulated electromagnetic wavefield, preferably in the ultraviolet, visible or infrared spectral range, can be locally detected and demodulated with one or more sensing elements. Each sensing element consists of a resistive, transparent electrode (E) on top of an insulated layer (O) that is produced over a semiconducting substrate whose surface is electrically kept in depletion. The electrode (E) is connected with two or more contacts (C | 2009-05-14 |
20090121309 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a device isolation structure on a semiconductor substrate to define an active region. A hard mask pattern defining a recess region is formed over the semiconductor substrate. The semiconductor substrate is selectively etched using the hard mask pattern to form a recess channel structure. The etching process for the semiconductor substrate is performed by two plasma etching methods under different etching conditions. The hard mask pattern is removed to expose the active region including the recess channel structure. A gate electrode is formed to fill the recess channel structure. | 2009-05-14 |
20090121310 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A method for manufacturing a semiconductor device comprising the steps of: forming a first insulating film to be used as a mask for forming a trench region directly above a semiconductor substrate; forming the trench region on the semiconductor substrate using the mask; forming a second insulating film directly above the semiconductor substrate which includes the trench region and the first insulating film so that the second insulating film has a recess above the trench region and a protrusion above the first insulating film; removing the protrusion down to the bottom of the recess as a first removal step; and removing the first insulating film and the second insulating film in accordance with a chemical mechanical polishing method so that the step formed of the recess and protrusion is reduced to 20 nm or less as a second removal step. | 2009-05-14 |
20090121311 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to an embodiment of the invention includes: a semiconductor substrate; a well, having a well contact connection region, formed in the semiconductor substrate; a transistor formed on the well; an isolation region formed between the transistor formed on the well, and the well contact connection region; and a silicide layer formed between a bottom surface of the isolation region, and the semiconductor substrate. | 2009-05-14 |
20090121312 | METHOD AND APPARATUS FOR MAKING COPLANAR ISOLATED REGIONS OF DIFFERENT SEMICONDUCTOR MATERIALS ON A SUBSTRATE - A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers. | 2009-05-14 |
20090121313 | SEMICONDUCTOR DEVICE WITH AT LEAST ONE AIR GAP PROVIDED IN CHIP OUTER AREA - One air gap structure is disposed so as to circle around the outer wall of a seal ring in a loop by arranging, within first insulating films located in a chip outer area corresponding to an outer area of the seal ring, air gaps into a line in parallel to the seal ring, which air gaps are hermetically-closed holes that are provided respectively in wiring layers other than portions corresponding to a global wiring layer and are extended in the thickness direction of first insulating films. When a crack occurs at a chip peripheral edge due to dicing or the like, the advancing direction thereof is changed by the air gaps to an upward direction, thereafter the crack advances toward the uppermost position in the chip outer area along the extending direction of the one air gap structure, so that the crack cannot reach the seal ring. | 2009-05-14 |
20090121314 | Manufacturing method for forming an integrated circuit device and corresponding integrated circuit device - The present invention provides a manufacturing method for forming an integrated circuit device and to a corresponding integrated circuit device. The manufacturing method for forming an integrated circuit device comprises the steps of: forming a first level on a substrate; forming a second level above the first level; forming a cap layer on the second level which covers a first region of the level and leaves a second region uncovered; and simultaneously etching a first contact hole in the first region and a second contact hole in the second region such that the etching is selective to the cap layer in the second region and proceeds to a greater depth in the first region. | 2009-05-14 |
20090121315 | METHOD FOR PRODUCING AN INTEGRATED CIRCUIT AND ARRANGEMENT COMPRISING A SUBSTRATE - Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided. | 2009-05-14 |
20090121316 | Electronic Component with Reactive Barrier and Hermetic Passivation Layer - An electronic component is provided on a substrate. A thin-film capacitor is attached to the substrate, the thin-film capacitor includes a pyrochlore or perovskite dielectric layer between a plurality of electrode layers, the electrode layers being formed from a conductive thin-film material. A reactive barrier layer is deposited over the thin-film capacitor. The reactive barrier layer includes an oxide having an element with more than one valence state, wherein the element with more than one valence state has a molar ratio of the molar amount of the element that is in its highest valence state to its total molar amount in the barrier of 50% to 100%. Optionally layers of other materials may intervene between the capacitor and reactive barrier layer. The reactive barrier layer may be paraelectric and the electronic component may be a tunable capacitor. | 2009-05-14 |
20090121317 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes. | 2009-05-14 |
20090121318 | Semiconductor device, DRAM integrated circuit device, and method of producing the same - A semiconductor device with a multi-layer wiring structure includes a first conductive region: a second conductive region that has an upper surface located in a higher position than the first conductive region with respect to the substrate; an insulating that covers the first and second conductive regions; a wiring groove that is formed in the insulating film so as to expose the second conductive region; a contact hole that is formed in the insulating film so as to expose the first conductive region; and a wiring pattern that fills the wiring groove and the contact hole. In this semiconductor device, the upper surface of the wiring pattern is located on the same plane as the upper surface of the insulating film. | 2009-05-14 |