19th week of 2018 patent applcation highlights part 58 |
Patent application number | Title | Published |
20180130703 | STRUCTURE AND METHOD FOR CAPPING COBALT CONTACTS | 2018-05-10 |
20180130704 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF | 2018-05-10 |
20180130705 | Delayed Via Formation in Electronic Devices | 2018-05-10 |
20180130706 | COBALT DEPOSITION SELECTIVITY ON COPPER AND DIELECTRICS | 2018-05-10 |
20180130707 | BOTTOM-UP FILL (BUF) OF METAL FEATURES FOR SEMICONDUCTOR STRUCTURES | 2018-05-10 |
20180130708 | METHOD FOR FULLY SELF-ALIGNED VIA FORMATION USING A DIRECTED SELF ASSEMBLY (DSA) PROCESS | 2018-05-10 |
20180130709 | METHOD OF PROCESSING WAFER | 2018-05-10 |
20180130710 | FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF | 2018-05-10 |
20180130711 | SEMICONDUCTOR FIN LOOP FOR USE WITH DIFFUSION BREAK | 2018-05-10 |
20180130712 | SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH | 2018-05-10 |
20180130713 | SEMICONDUCTOR DEVICES | 2018-05-10 |
20180130714 | PATTERN INSPECTION METHODS AND METHODS OF FABRICATING RETICLES USING THE SAME | 2018-05-10 |
20180130715 | ION IMPLANTATION METHODS AND STRUCTURES THEREOF | 2018-05-10 |
20180130716 | ELECTRONIC ELEMENT MOUNTING SUBSTRATE, AND ELECTRONIC DEVICE | 2018-05-10 |
20180130717 | INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES, AND METHODS OF MANUFACTURE | 2018-05-10 |
20180130718 | SEMICONDUCTOR ELEMENT PACKAGE, SEMICONDUCTOR DEVICE, AND MOUNTING STRUCTURE | 2018-05-10 |
20180130719 | SEMICONDUCTOR DEVICE PACKAGES AND METHOD OF MANUFACTURING THE SAME | 2018-05-10 |
20180130720 | Substrate Based Fan-Out Wafer Level Packaging | 2018-05-10 |
20180130721 | STACKED COOLER | 2018-05-10 |
20180130722 | SEMICONDUCTOR PACKAGE WITH GROUNDED FENCE TO INHIBIT DENDRITES OF DIE-ATTACH MATERIALS | 2018-05-10 |
20180130723 | LEADFRAME SUBSTRATE WITH ELECTRONIC COMPONENT INCORPORATED THEREIN AND SEMICONDUCTOR ASSEMBLY USING THE SAME | 2018-05-10 |
20180130724 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE | 2018-05-10 |
20180130725 | SEMICONDUCTOR DEVICE | 2018-05-10 |
20180130726 | CASCODE SEMICONDUCTOR PACKAGE AND RELATED METHODS | 2018-05-10 |
20180130727 | FABRICATION METHOD OF ELECTRONIC PACKAGE | 2018-05-10 |
20180130728 | SILICON SUBSTRATE PROCESSING METHOD, ELEMENT EMBEDDED SUBSTRATE, AND CHANNEL FORMING SUBSTRATE | 2018-05-10 |
20180130729 | IC PACKAGE | 2018-05-10 |
20180130730 | METHOD FOR FORMING SEMICONDUCTOR PACKAGE | 2018-05-10 |
20180130731 | ELECTRONICS PACKAGE HAVING A MULTI-THICKNESS CONDUCTOR LAYER AND METHOD OF MANUFACTURING THEREOF | 2018-05-10 |
20180130732 | ELECTRONICS PACKAGE HAVING A MULTI-THICKNESS CONDUCTOR LAYER AND METHOD OF MANUFACTURING THEREOF | 2018-05-10 |
20180130733 | SEPARATION OF INTEGRATED CIRCUIT STRUCTURE FROM ADJACENT CHIP | 2018-05-10 |
20180130734 | TRACE/VIA HYBRID STRUCTURE WITH THERMALLY AND ELECTRICALLY CONDUCTIVE SUPPORT MATERIAL FOR INCREASED THERMAL AND ELECTRICAL PERFORMANCE | 2018-05-10 |
20180130735 | TRACE/VIA HYBRID STRUCTURE AND METHOD OF MANUFACTURE | 2018-05-10 |
20180130736 | TRACE/VIA HYBRID STRUCTURE AND METHOD OF MANUFACTURE | 2018-05-10 |
20180130737 | SEMICONDUCTOR MEMORY DEVICE | 2018-05-10 |
20180130738 | APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME | 2018-05-10 |
20180130739 | WIRING WITH EXTERNAL TERMINAL | 2018-05-10 |
20180130740 | INTEGRATED CIRCUIT COMPRISING AN ANTIFUSE STRUCTURE AND METHOD OF REALIZING | 2018-05-10 |
20180130741 | Electrical Fuse Structure and Method of Formation | 2018-05-10 |
20180130742 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING A PATTERNED METAL LAYER EMBEDDED IN AN INTERLAYER DIELECTRIC LAYER | 2018-05-10 |
20180130743 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS | 2018-05-10 |
20180130744 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME | 2018-05-10 |
20180130745 | PACKAGE SUBSTRATE AND ITS FABRICATION METHOD | 2018-05-10 |
20180130746 | ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN | 2018-05-10 |
20180130747 | STACKED ELECTRONICS PACKAGE AND METHOD OF MANUFACTURING THEREOF | 2018-05-10 |
20180130748 | SEMICONDUCTOR DEVICE | 2018-05-10 |
20180130749 | PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME | 2018-05-10 |
20180130750 | IMAGE SENSOR DEVICE AND IMAGE SENSOR MODULE COMPRISING THE SAME | 2018-05-10 |
20180130751 | INTERCONNECTION STRUCTURES AND METHODS FOR TRANSFER-PRINTED INTEGRATED CIRCUIT ELEMENTS WITH IMPROVED INTERCONNECTION ALIGNMENT TOLERANCE | 2018-05-10 |
20180130752 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures | 2018-05-10 |
20180130753 | SEMICONDUCTOR DEVICE | 2018-05-10 |
20180130754 | VISUAL IDENTIFICATION OF SEMICONDUCTOR DIES | 2018-05-10 |
20180130755 | SYSTEMS AND METHODS FOR PROVIDING ELECTROMAGNETIC INTERFERENCE (EMI) COMPARTMENT SHIELDING FOR COMPONENTS DISPOSED INSIDE OF SYSTEM ELECTRONIC PACKAGES | 2018-05-10 |
20180130756 | SEMICONDUCTOR DEVICE STRUCTURE | 2018-05-10 |
20180130757 | FOLDING THIN SYSTEMS | 2018-05-10 |
20180130758 | SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME | 2018-05-10 |
20180130759 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR MANUFACTURING PROCESS | 2018-05-10 |
20180130760 | CHIP PACKAGE AND CHIP PACKAGING METHOD | 2018-05-10 |
20180130761 | SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC ELEMENT MODULE USING THE SAME | 2018-05-10 |
20180130762 | STACKED ELECTRONICS PACKAGE AND METHOD OF MANUFACTURING THEREOF | 2018-05-10 |
20180130763 | BONDING WIRE FOR SEMICONDUCTOR DEVICE | 2018-05-10 |
20180130764 | HIGH-FREQUENCY CIRCUIT | 2018-05-10 |
20180130765 | METHOD FOR BONDING SEMICONDUCTOR CHIPS TO A LANDING WAFER | 2018-05-10 |
20180130766 | Adhesive with Self-Connecting Interconnects | 2018-05-10 |
20180130767 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH SIDEWALL RECESS AND RELATED DEVICES | 2018-05-10 |
20180130768 | Substrate Based Fan-Out Wafer Level Packaging | 2018-05-10 |
20180130769 | Substrate Based Fan-Out Wafer Level Packaging | 2018-05-10 |
20180130770 | ELECTRONICS PACKAGE HAVING A MULTI-THICKNESS CONDUCTOR LAYER AND METHOD OF MANUFACTURING THEREOF | 2018-05-10 |
20180130771 | PACKAGE SUBSTRATE AND ITS FABRICATION METHOD | 2018-05-10 |
20180130772 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 2018-05-10 |
20180130773 | SEMICONDUCTOR DIE ASSEMBLIES HAVING MOLDED UNDERFILL STRUCTURES AND RELATED TECHNOLOGY | 2018-05-10 |
20180130774 | PACKAGE STACK STRUCTURE | 2018-05-10 |
20180130775 | LED-BASED LIGHT SOURCES FOR LIGHT EMITTING DEVICES AND LIGHTING ARRANGEMENTS WITH PHOTOLUMINESCENCE WAVELENGTH CONVERSION | 2018-05-10 |
20180130776 | LIGHT EMITTING DEVICE | 2018-05-10 |
20180130777 | SEMICONDUCTOR LIGHT-EMITTING DEVICE | 2018-05-10 |
20180130778 | HIGH-FREQUENCY MODULE | 2018-05-10 |
20180130779 | METHOD OF FORMING AN ARRAY OF A MULTI-DEVICE UNIT CELL | 2018-05-10 |
20180130780 | INTERPOSER TRANSMISSION LINE USING MULTIPLE METAL LAYERS | 2018-05-10 |
20180130781 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE | 2018-05-10 |
20180130782 | STACKED SEMICONDUCTOR PACKAGE | 2018-05-10 |
20180130783 | ELECTRONICS PACKAGE HAVING A MULTI-THICKNESS CONDUCTOR LAYER AND METHOD OF MANUFACTURING THEREOF | 2018-05-10 |
20180130784 | ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS | 2018-05-10 |
20180130785 | SEMICONDUCTOR DEVICE INCLUDING A REPEATER/BUFFER AT UPPER METAL ROUTING LAYERS AND METHODS OF MANUFACTURING THE SAME | 2018-05-10 |
20180130786 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 2018-05-10 |
20180130787 | MEMORY CIRCUIT LAYOUT | 2018-05-10 |
20180130788 | ELECTRONIC DEVICE, IN PARTICULAR FOR PROTECTION AGAINST OVERVOLTAGES | 2018-05-10 |
20180130789 | INTEGRATED TRANSISTOR AND PROTECTION DIODE AND FABRICATION METHOD | 2018-05-10 |
20180130790 | Electrostatic Discharge (ESD) Protection for the Metal Oxide Medical Device Products | 2018-05-10 |
20180130791 | ELECTRONIC CIRCUIT, INTEGRATED CIRCUIT AND MOTOR ASSEMBLY | 2018-05-10 |
20180130792 | SYSTEM AND METHOD OF FABRICATING ESD FINFET WITH IMPROVED METAL LANDING IN THE DRAIN | 2018-05-10 |
20180130793 | Electrostatic Discharge Device and Split Multi Rail Network with Symmetrical Layout Design Technique | 2018-05-10 |
20180130794 | ELECTRONIC CIRCUIT, INTEGRATED CIRCUIT AND MOTOR ASSEMBLY | 2018-05-10 |
20180130795 | ULTRASONIC TRANSDUCERS IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) WAFERS AND RELATED APPARATUS AND METHODS | 2018-05-10 |
20180130796 | SEMICONDUCTOR DEVICE | 2018-05-10 |
20180130797 | MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE | 2018-05-10 |
20180130798 | MOSFET TRANSISTORS WITH ROBUST SUBTHRESHOLD OPERATIONS | 2018-05-10 |
20180130799 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A STANDARD CELL WHICH INCLUDES A FIN | 2018-05-10 |
20180130800 | Forming Doped Regions in Semiconductor Strips | 2018-05-10 |
20180130801 | WELL-BASED INTEGRATION OF HETEROEPITAXIAL N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS | 2018-05-10 |
20180130802 | FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE | 2018-05-10 |