19th week of 2019 patent applcation highlights part 70 |
Patent application number | Title | Published |
20190139940 | SEMICONDUCTOR PACKAGES - A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region. | 2019-05-09 |
20190139941 | PIXEL UNIT, PIXEL ARRAY, MULTIMEDIA DEVICE AND MANUFACTURING METHOD THEREOF - A pixel unit, a pixel array, a multimedia device, and a manufacturing method thereof, are provided. The pixel unit includes a display medium module and an active switching element. The display medium module includes at least a pair electrode. The pair electrode includes a first electrode, a second electrode and a display medium. The first electrode and the second electrode are separated from each other, and the display medium is disposed between the first electrode and the second electrode. The active switching element is electrically connected to the first electrode, for allowing the first electrode and the second electrode to change the state of the display medium. The active switching element includes an active switching element substrate portion and a transistor portion, which is form on the active switching element substrate portion. Therefore, the active switching element can be manufactured independently without the restriction from the display medium module. | 2019-05-09 |
20190139942 | PIXEL UNIT STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel unit structure, as well as a manufacturing method thereof, is provided. The pixel unit structure includes a display medium module and an active switching element. The display medium module includes a first electrode, a second electrode and a display medium. The first electrode and the second electrode are separated from each other, and the display medium is disposed between the first electrode and the second electrode. The active switching element is electrically connected to the first electrode, for allowing the first electrode and the second electrode to change the state of the display medium. The active switching element includes a wafer portion and a transistor portion, which is formed on the wafer portion. Therefore, the active switching element can be manufactured independently without the restriction from the display medium module. | 2019-05-09 |
20190139943 | WHITE LIGHT EMITTING DEVICES HAVING HIGH LUMINOUS EFFICIENCY AND IMPROVED COLOR RENDERING THAT INCLUDE PASS-THROUGH VIOLET EMISSIONS - A lighting apparatus a first group of at least one first solid state emitter, each first solid state emitter including a first light emitting diode (“LED”) that, when excited, emits light having a peak wavelength in a range between about 440 nm and about 475 nm, and a second group of at least one second solid state emitter, each second solid state emitter comprising a second LED that, when excited, emits light having a peak wavelength in a range between about 390 nm and about 415 nm. Between about 2% and about 15% of a spectral power of light emitted from the lighting apparatus is light having wavelengths in the range between about 390 nm and about 415 nm. | 2019-05-09 |
20190139944 | LAMP FOR VEHICLE AND VEHICLE - A lamp for a vehicle includes an array module comprising a plurality of micro Light Emitting Diodes (LEDs). The plurality of micro LEDs include a plurality of micro LED pairs, where each micro LED pair includes a first micro LED chip including first electrodes, and a second micro LED chip including second electrodes. One of the second electrodes is configured to contact one of the first electrodes. | 2019-05-09 |
20190139945 | METHOD AND APPARATUS FOR LIGHT DIFFUSION - A display apparatus includes a substrate and a plurality of LEDs. Each LED is attached to the substrate via conductive pads on a side of the LED. A diffuser having light diffusing characteristics is aligned with the plurality LEDs against a surface of the substrate. The diffuser is aligned so as to nest around at least one LED of the plurality of LEDs. | 2019-05-09 |
20190139946 | PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME - A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area. | 2019-05-09 |
20190139947 | ENCAPSULATION COVER FOR AN ELECTRONIC PACKAGE AND METHOD OF FABRICATION - An encapsulation cover for an electronic package includes a cover body having a frontal wall provided with at least one optical element allowing light to pass through. The optical element is inserted into the encapsulation cover by overmolding into a through-passage of the frontal wall. A front face of the optical element is set back with respect to a front face of the frontal wall. The process for fabricating the encapsulation cover includes forming a stack of a sacrificial spacer on top of an optical element, with the stack placed into a cavity of a mold. | 2019-05-09 |
20190139948 | LED LIGHTING APPARATUS - A LED lighting apparatus includes a driver, a substrate, LED chips, a first fluorescent layer and a second fluorescent layer. The driver converts an external power source to a driving current. The substrate is mounted with two electrodes electrically connected to the driver for getting the driving current. The plurality of LED chips are mounted on a first side of the substrate. The first fluorescent layer is disposed on the first side of the substrate covering the plurality of LED chips. The second fluorescent layer is disposed on a second side of the substrate. A part of a light emitted from the plurality of LED chips passing through the first fluorescent layer and then exciting the second fluorescent layer to emit a second light. | 2019-05-09 |
20190139949 | SEMICONDUCTOR STRUCTURE AND ASSOCIATED MANUFACTURING METHOD - A semiconductor structure is disclosed. The semiconductor structure includes: a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side; a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side; and a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; wherein the first color type, the second color type, and the third color type are different from each other. | 2019-05-09 |
20190139950 | OPTICAL MODULATORS - An optoelectronic device. The optoelectronic device operable to provide a PAM-N modulated output, the device comprising: M optical modulators, M being an integer greater than 1, the M optical modulators being arranged in a cascade, the device being configured to operate in N distinct transmittance states, as a PAM-N modulator, wherein, in each transmittance state of the N distinct transmittance states, each of the M optical modulators has applied to it a respective control voltage equal to one of: a first voltage or a second voltage. One or more of the modulators may include a substrate; a crystalline cladding layer, on top of the substrate; and an optically active region, above the crystalline cladding layer. The crystalline cladding layer may have a refractive index which is less than a refractive index of the optically active region. | 2019-05-09 |
20190139951 | IMAGE MODULE PACKAGE - There is provided an image module package including a substrate, a photo sensor chip, a molded transparent layer and a glass filter. The substrate has an upper surface. The photo sensor chip is attached to the upper surface of the substrate and electrically connected to the substrate. The molded transparent layer covers the photo sensor chip and a part of the upper surface of the substrate, wherein a top surface of the molded transparent layer is formed with a receptacle opposite to the photo sensor chip. The glass filter is accommodated in the receptacle. | 2019-05-09 |
20190139952 | CHIP PACKAGING METHOD - A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars. | 2019-05-09 |
20190139953 | ELECTRONIC DEVICE - In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer. | 2019-05-09 |
20190139954 | Threshold Voltage Tuning For Fin-Based Integrated Circuit Device - Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor. | 2019-05-09 |
20190139955 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a fin structure protruding from the substrate in a direction perpendicular to an upper surface of the substrate, the fin structure including first fin regions extending in a first direction and second fin regions extending in a second direction different from the first direction, source/drain regions disposed on the fin structure, a gate structure intersecting the fin structure, a first contact connected to one of the source/drain regions, and a second contact connected to the gate structure and being between the second fin regions in plan view. | 2019-05-09 |
20190139956 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin. | 2019-05-09 |
20190139957 | SELF-ALIGNED GATE EDGE TRIGATE AND FINFET DEVICES - Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins. | 2019-05-09 |
20190139958 | SEMICONDUCTOR DEVICE - The semiconductor device includes a first inserter and a second inverter which is connected thereto in series. Each of the first and the second inserters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of projection semiconductor layers each as the active region, of the channel and the n-channel transistors of the first inverter. | 2019-05-09 |
20190139959 | MANUFACTURING METHOD OF MAGNETIC RANDOM ACCESS MEMORY CELL - A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment. | 2019-05-09 |
20190139960 | Memory Cell, An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor With The Array Comprising Rows Of Access Lines And Columns Of Digit Lines, A 2T-1C Memory Cell, And Methods Of Forming An Array Of Capacitors And Access Transistors There-Above - A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line. Other aspects, including structure independent of method, are disclosed. | 2019-05-09 |
20190139961 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A memory device and a method for manufacturing the memory device are provided. The memory device includes two first gate structures and a multilayer insulating structure. The multilayer insulating structure includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially from bottom to top. The width of the second insulating layer is equal to that of the third insulating layer, and smaller than that of the first insulating layer. The width of the bottom surface of the fourth insulating layer is greater than the width of the top surface of the third insulating layer. The memory device includes a capacitor contact plug formed between the first gate structures. The capacitor contact plug includes a first contact element, a buffering layer, and a second contact element. The second contact element has a top surface wider than its bottom surface. | 2019-05-09 |
20190139962 | Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making - An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. | 2019-05-09 |
20190139963 | MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern. | 2019-05-09 |
20190139964 | TECHNIQUES AND STRUCTURE FOR FORMING DYNAMIC RANDOM ACCESS DEVICE - A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures. | 2019-05-09 |
20190139965 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - One method for manufacturing a semiconductor device includes: forming provisional active regions that are shaped such that active regions that are adjacent in an X direction are connected to each other, forming a sacrificial film, performing etching, including the sacrificial film, so as to form a plurality of first trenches that separate the active regions, embedding element-isolating insulating films in the first trenches and then removing the sacrificial film, forming first side-wall insulating films that cover the exposed side surfaces of the element-isolating insulating films and second side-wall insulating films that cover the side surfaces of the first side-wall insulating films, embedding cap insulating films in second trenches that appear due to the formation of the second side-wall insulating films, and forming a plurality of third trenches at the positions of the second side-wall insulating films and forming word lines thereunder. | 2019-05-09 |
20190139966 | STATIC RANDOM ACCESS MEMORY DEVICE WITH HALO REGIONS HAVING DIFFERENT IMPURITY CONCENTRATIONS - In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other. | 2019-05-09 |
20190139967 | NOVEL SIX-TRANSISTOR (6T) SRAM CELL STRUCTURE - One illustrative 6T SRAM cell structure disclosed herein includes a first active region with a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which are formed in and above the first active region, wherein the first N-type pull-down transistor is positioned laterally between the first N-type pass gate transistor and the first P-type pull-up transistor, and a second active region with a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which are formed in and above the second active region, wherein the second N-type pull-down transistor is positioned laterally between the second N-type pass gate transistor and the second P-type pull-up transistor. | 2019-05-09 |
20190139968 | VERTICAL MEMORY DEVICE INCLUDING SUBSTRATE CONTROL CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction. | 2019-05-09 |
20190139969 | Cutting Metal Gates in Fin Field Effect Transistors - A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode. | 2019-05-09 |
20190139970 | SEMICONDUCTOR STRUCTURE - Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having an N-type logic region including a first and a second N-type threshold voltage region, a P-type logic region including a first and a second P-type threshold voltage region, a pull-up transistor region and an adjacent pull-down transistor region; forming a gate dielectric layer; forming a first work function layer on the gate dielectric layer; removing portions of the first work function layer; forming a second work function layer on remaining first work function layer and exposed portions of the gate dielectric layer; removing a portion of the second work function layer; forming an N-type work function layer on remaining second work function layer and exposed portion of the gate dielectric layer in the second N-type threshold voltage region; and forming a gate electrode layer on the N-type work function layer. | 2019-05-09 |
20190139971 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer. | 2019-05-09 |
20190139972 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A SUBSTRATE, VARIOUS INTERCONNECTIONS, SEMICONDUCTOR MEMBER, CHARGE STORAGE MEMBER AND A CONDUCTIVE MEMBER - According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body. | 2019-05-09 |
20190139973 | THREE-DIMENSIONAL MEMORY DEVICE WITH ANNULAR BLOCKING DIELECTRICS AND METHOD OF MAKING THEREOF - A memory opening is formed through an alternating stack of insulating layers and sacrificial material layers located over a substrate. Annular recesses are formed around the memory opening by laterally recessing the sacrificial material layers with respect to the insulating layers. Annular metal portions are formed over recessed sidewalls of the sacrificial material layers within each of the annular recesses by a selective deposition process. Annular backside blocking dielectrics are formed selectively on inner sidewalls of the annular metal portions employing a layer of a self-assembly material that covers surfaces of the insulating layers and inhibits deposition of a dielectric material thereupon. A memory stack structure is formed in the memory opening, and the sacrificial material layers are replaced with electrically conductive layers. The annular backside blocking dielectrics provide electrical isolation for the annular metal portions, which function as control gate electrodes. | 2019-05-09 |
20190139974 | THREE-DIMENSIONAL MEMORY DEVICE HAVING LEVEL-SHIFTED STAIRCASES AND METHOD OF MAKING THEREOF - A plurality of horizontal top surfaces that are vertically offset is formed on a substrate. An alternating stack of insulating layers and spacer material layers is formed and patterned to provide a plurality of staircase regions that are laterally spaced apart and overlies a respective one of the plurality of horizontal top surfaces of the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. A set of contact via cavities are formed over the electrically conductive layers. | 2019-05-09 |
20190139975 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a first channel layer formed over a substrate and extending in a vertical direction; a first stacked structure comprising a plurality of first interlayer dielectric layers and a plurality of first gate electrode layers which are alternately stacked along the first channel layer; a first memory layer interposed between the first channel layer and the first gate electrode layers; a second channel layer formed over the first channel layer and extending in the vertical direction; a second stacked structure comprising a plurality of second interlayer dielectric layers and a plurality of second gate electrode layers which are alternately stacked along the second channel layer; a second memory layer interposed between the second channel layer and the second gate electrode layers; a first channel connection pattern formed between the first channel layer and the second channel layer and coupling the first and the second channel layers to each other; and a first etch stop pattern formed between the first and second stacked structures and at substantially the same level as the first channel connection pattern, wherein the first etch stop pattern includes the same material as the first channel connection pattern and is isolated from the first channel connection pattern. | 2019-05-09 |
20190139976 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer. | 2019-05-09 |
20190139977 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STAIRCASE STRUCTURES, AND RELATED METHODS - A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and at least one opening extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. The at least one conductive structure of each of the stacked tiers extends continuously from at least one of the steps of the at least one staircase structure and around the at least one opening to form at least one continuous conductive path extending completely across each of the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described. | 2019-05-09 |
20190139978 | NONVOLATILE MEMORY DEVICE - A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region. | 2019-05-09 |
20190139979 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction. | 2019-05-09 |
20190139980 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DETECTING ELECTRICAL FAILURE THEREOF - Disclosed are three-dimensional semiconductor memory devices and methods of detecting electrical failure thereof. The three-dimensional semiconductor memory device includes a substrate with a first conductivity including a cell array region and an extension region having different threshold voltages from each other, a stack structure on the substrate and including stacked electrodes, an electrical vertical channel penetrating the stack structure on the cell array region, and a dummy vertical channel penetrating the stack structure on the extension region. The substrate comprises a pocket well having the first conductivity and provided with the stack structure thereon, and a deep well surrounding the pocket well and having a second conductivity opposite to the first conductivity. | 2019-05-09 |
20190139981 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer, a first conductive layer, a tunneling insulating film, and a charge trapping film. The tunneling insulating film is provided between the semiconductor layer and the first conductive layer. The charge trapping film is provided between the first conductive layer and the tunneling insulating film. The charge trapping film includes a first separation layer, a first trapping layer, and a second trapping layer. The first trapping layer is positioned between the tunneling insulating film and the first separation layer. The second trapping layer is positioned between the first conductive layer and the first separation layer. A trapping efficiency of charge in the first trapping layer is higher than a trapping efficiency of charge in the second trapping layer. | 2019-05-09 |
20190139982 | Three-Dimensional Memory Devices and Fabricating Methods Thereof - Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening. | 2019-05-09 |
20190139983 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern. | 2019-05-09 |
20190139984 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other. | 2019-05-09 |
20190139985 | Three-Dimensional Semiconductor Devices Including Gate Electrodes - A three-dimensional semiconductor device is provided including main separation structures disposed on a substrate, and extending in a first direction, parallel to a surface of the substrate; gate electrodes disposed between the main separation structures; a first secondary separation structure penetrating through the gate electrodes, between the main separation structures, and including a first linear portion and a second linear portion, having end portions opposing each other; and second secondary separation structures disposed between the first secondary separation structure and the main separation structures, and penetrating through the gate electrodes. The second secondary separation structures have end portions opposing each other between the second linear portion and the main separation structures. | 2019-05-09 |
20190139986 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Disclosed are an array substrate and a method of manufacturing the array substrate. The method of manufacturing an array substrate includes: forming a first metal layer on a substrate, and etching the first metal layer; forming an insulating layer on the substrate and the first metal layer; forming an active layer and an ohmic contact layer successively on the insulating layer; etching the active layer and the ohmic contact layer; forming a second metal layer on the ohmic contact layer and the insulating layer, and etching the second metal layer; forming a protective layer on the second metal layer and the insulating layer; forming a photoresist layer on the protective layer, and performing exposure and development; and forming a transparent conducting layer directly on the color filter, and etching the transparent conducting layer to form a pixel electrode layer. | 2019-05-09 |
20190139987 | PIXEL UNIT, ARRAY SUBSTRATE AND DISPLAY PANEL - The present disclosure provides a pixel unit, an array substrate and a display panel. The pixel unit includes a main pixel portion and a secondary pixel portion electrically connected to the main pixel portion, wherein the main pixel portion includes a first horizontal trunk, a first vertical trunk and first branches; the secondary pixel portion includes a second horizontal trunk, a second vertical trunk and second branches; wherein, an acute angle between the first branches and the first horizontal trunk is different from an acute angle between the second branches and the second horizontal trunk. The implementation of the present disclosure may make the liquid crystal molecules in a pixel unit to have different inclination angle so as to improve the side viewing of the display panel. | 2019-05-09 |
20190139988 | TRANSISTOR, LIQUID CRYSTAL DISPLAY DEVICE, AND MANUFACTURING METHOD THEREOF - Photolithography and etching steps for forming an island-shaped semiconductor layer are omitted, and a liquid crystal display device is manufactured with four photolithography steps: a step of forming a gate electrode (including a wiring formed using the same layer as the gate electrode), a step of forming source and drain electrodes (including a wiring formed using the same layer as the source and drain electrodes), a step of forming a contact hole (including the removal of an insulating layer and the like in a region other than the contact hole), and a step of forming a pixel electrode (including a wiring formed using the same layer as the pixel electrode). By the reduction in the number of photolithography steps, a liquid crystal display device can be provided at low cost and high productivity. Formation of a parasitic channel is prevented by an improvement in shape and potential of a wiring. | 2019-05-09 |
20190139989 | Ultra High Density Thin Film Transistor Substrate Having Low Line Resistance Structure and Method for Manufacturing the Same - A display device is described that has reduced resistance in one or more of the gate, common, data electrical lines that control the operation of the pixels of the display device. Reduced resistance is achieved by forming additional metal and/or metal-alloy layers on the gate, common, and/or data lines in such a manner so that the cross-sectional area of those lines is increased. As a consequence, each such line is formed so as to be thicker than could otherwise be achieving without causing defects in the rubbing process of an alignment layer. Additionally, no widening of these lines is needed, thus preserving the aspect ratio of the device. The gate insulating and semiconducting layers that in part make up the thin film transistors that help control the operation of the pixels of the device may also be designed to take into account the increased thickness of the lines. | 2019-05-09 |
20190139990 | DISPLAY DEVICE WITH DIFFERENT CIRCUIT GROUPS - A display device that includes a substrate having a display region and an adjacent peripheral region is provided, including; a plurality of sub-pixels provided within the display region; a plurality of data lines electrically connected to the sub-pixels; and a first electronic circuit group and a second electronic circuit group provided in the peripheral region, connected to the corresponding data lines. The first electronic circuit group includes a plurality of first electronic circuits, and the second electronic circuit group includes a plurality of second electronic circuits. Two adjacent first electronic circuits are arranged with a first interval therebetween, and the first interval has a first width. Two adjacent second electronic circuits are arranged with a second interval therebetween, and the second interval has a second width. The first width and the second width are different. | 2019-05-09 |
20190139991 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes a display panel, a signal generator, a plurality of wires, and a controller. The display panel has a plurality of pixels. The signal generator supplies data signal to the pixels. The wires connect output ends of the signal generator to input ends of the pixels, respectively. The controller varies voltage waveform corresponding to the data signal at the output ends by varying both a voltage level at a rising edge of the voltage waveform and a voltage level at a falling edge of the voltage waveform. | 2019-05-09 |
20190139992 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region. | 2019-05-09 |
20190139993 | DISPLAY PANEL - A display panel is disclosed. The display panel includes a first substrate, a light shielding layer and a color block. The first substrate has a first surface with a first edge and a second edge, and the second edge is connected to the first edge. The second edge substantially extends along a first direction. The light shielding layer is disposed on the first surface and includes a plurality of openings. The color block closest to the second edge is disposed on the light shielding layer and extending along the first direction. The color block does not overlap the plurality of openings. Wherein the color block has a third edge which is closest to the second edge, and the third edge is not aligned evenly. | 2019-05-09 |
20190139994 | STRETCHABLE DISPLAY DEVICE - A stretchable display device includes: a first pixel substrate includes a first body part and a first hinge part connected to the first body part; a second pixel substrate includes a second body part and a second hinge part connected to the second body part. A second direction neighboring cutout pattern is disposed between the first hinge part connected to the first body part and the second hinge part connected to the second body part; a first power line disposed at the first hinge part connected to the first body part and a second power line disposed at a second hinge part is connected to the second body part. The first power line and second power line are disposed at substantially equal distances in the first direction based on a reference line extending in correspondence to the second direction neighboring cutout pattern. | 2019-05-09 |
20190139995 | DISPLAY DEVICE - Provided is a display device including: a capacitor having a first electrode, a first insulating film over the first electrode, and a second electrode over the first insulating film; and a first transistor over the capacitor. The first transistor includes the second electrode, a second insulating film over the second electrode, an oxide semiconductor film over the second insulating film, and a first source electrode and a first drain electrode over the oxide semiconductor film. The first source electrode and the first drain electrode are electrically connected to the oxide semiconductor film. | 2019-05-09 |
20190139996 | TRANSPARENT SUBSTRATE AND PROCESS FOR PRODUCING IT - To provide a transparent substrate with excellent appearance and with high visibility when observed from a predetermined direction, and a process for producing it. | 2019-05-09 |
20190139997 | SEMICONDUCTOR IMAGE SENSOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor image sensor device includes a semiconductor substrate, a radiation-sensing region, and a first isolation structure. The radiation-sensing region is in the semiconductor substrate. The first isolation structure is in the semiconductor substrate and adjacent to the radiation-sensing region. The first isolation structure includes a bottom isolation portion in the semiconductor substrate, an upper isolation portion in the semiconductor substrate, and a diffusion barrier layer surrounding a sidewall of the upper isolation portion. | 2019-05-09 |
20190139998 | ISOLATION STRUCTURE AND IMAGE SENSOR - An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a dielectric post. The first dielectric layer includes a trench portion located in a trench of the semiconductor substrate. The second dielectric layer includes a trench portion covering the trench portion of the first dielectric layer and located in the trench of the semiconductor substrate. The third dielectric layer includes a trench portion covering the trench portion of the second dielectric layer and located in the trench of the semiconductor substrate. The dielectric post is disposed in the trench of the semiconductor substrate and covering the trench portion of the third dielectric layer. | 2019-05-09 |
20190139999 | IMPLANT DAMAGE FREE IMAGE SENSOR AND METHOD OF THE SAME - An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalls form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalls and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal. | 2019-05-09 |
20190140000 | BACKSIDE-ILLUMINATED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR SENSOR AND THE MANUFACTURING METHOD THEREOF - A backside-illumination complementary metal oxide semiconductor (CMOS) image sensor, comprises a semiconductor substrate including a first side for receiving incident light and a second side opposite to the first side; and a reflector disposed at the second side of the semiconductor substrate, wherein the reflector is configured to reflect incident light that transmits through the semiconductor substrate back into the semiconductor substrate. | 2019-05-09 |
20190140001 | Semiconductor Image Sensor Device Having Back Side Illuminated Image Sensors with Embedded Color Filters - Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed. | 2019-05-09 |
20190140002 | ENERGY RAY DETECTOR, DETECTION APPARATUS, AND EQUIPMENT - A detector includes a semiconductor layer included in a detection region and a peripheral region, and having a first surface and a second surface opposite to the first surface, and a wiring structure included in at least the detection region, and disposed between a space on the first surface side with respect to the semiconductor layer and a space on the second surface side with respect to the semiconductor layer, wherein a thickness of the semiconductor layer in at least a part of the detection region is smaller than a thickness of the peripheral region including the semiconductor layer, and the thickness of the semiconductor layer is larger than a distance between the first surface in the detection region and the space on the first surface side, and a distance between the second surface in the detection region and the space on the second surface side. | 2019-05-09 |
20190140003 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - An image sensor includes a photosensitive device, a storage device, and a driving circuit. The storage device is adjacent to the photosensitive device and includes a storage node, a gate dielectric layer, a storage gate electrode, and etch stop layer, a shielding layer, and a protection layer. The gate dielectric layer is over the storage node. The storage gate electrode is over the gate dielectric layer. The etch stop layer covers the gate dielectric layer and the storage gate electrode. The shielding layer is over the storage gate electrode. The protection layer is sandwiched between the etch stop layer and the shielding layer. The driving circuit is adjacent to the storage device. | 2019-05-09 |
20190140004 | Semiconductor Devices Having Reduced Noise - Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode. | 2019-05-09 |
20190140005 | Chip Scale Package for An Image Sensor - A chip scale package (CSP) structure for an image sensor comprises an image sensor chip, wherein the image sensor chip comprises a semiconductor substrate having a top surface to receive light, a plurality of color filters disposed over the top surface, and a plurality of micro lenses disposed on the plurality of color filters. A low refractive index material is disposed over the image sensor chip, wherein the low refractive index material covers the plurality of micro lenses, and wherein a refractive index of the low refractive index material is lower than a refractive index of the plurality of micro lenses. A cover glass is disposed directly on the low refractive index material, wherein no air gap is between the cover glass and the low refractive index material, and between the low refractive index material and the image sensor chip. Therefore, the cover glass is fully supported by the low refractive index material without any dams. | 2019-05-09 |
20190140006 | IMAGE SENSOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming an image sensor device is provided. The method includes forming a first trench in a semiconductor substrate. The semiconductor substrate has a front surface and a back surface, and the first trench extends from the front surface into the semiconductor substrate. The method includes forming a first isolation structure in the first trench. The method includes forming a light-sensing region in the semiconductor substrate. The first isolation structure surrounds the light-sensing region. The method includes forming a second trench in the semiconductor substrate. The second trench extends from the back surface into the semiconductor substrate and exposes the first isolation structure. The method includes forming a second isolation structure in the second trench. The second isolation structure includes a light-blocking structure to absorb or reflect incident light. | 2019-05-09 |
20190140007 | ELECTRIC FIELD IMAGING DEVICE - An electric field imaging device is provided with which it is possible to visualize as a dynamic state an electromagnetic field intensity distribution and a phase delay/advance distribution in the vicinity of a product, using a sample of the actual product without lead-out lines. The electric field imaging device includes: an antenna which accepts a high-frequency signal emitted by the sample as an input; an electrooptic (EO) crystal plate which is a frequency f | 2019-05-09 |
20190140008 | METHOD FOR PRODUCING CURVED ELECTRONIC CIRCUITS - Method for collectively producing several curved electronic circuits, including:
| 2019-05-09 |
20190140009 | BACKSIDE ILLUMINATION IMAGE SENSOR AND IMAGE-CAPTURING DEVICE - A backside illumination image sensor that includes a semiconductor substrate with a plurality of photoelectric conversion elements and a read circuit formed on a front surface side of the semiconductor substrate, and captures an image by outputting, via the read circuit, electrical signals generated as incident light having reached a back surface side of the semiconductor substrate is received at the photoelectric conversion elements includes: a light shielding film formed on a side where incident light enters the photoelectric conversion elements, with an opening formed therein in correspondence to each photoelectric conversion element; and an on-chip lens formed at a position set apart from the light shielding film by a predetermined distance in correspondence to each photoelectric conversion element. The light shielding film and an exit pupil plane of the image forming optical system achieve a conjugate relation to each other with regard to the on-chip lens. | 2019-05-09 |
20190140010 | CMOS SENSORS AND METHODS OF FORMING THE SAME - CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region. | 2019-05-09 |
20190140011 | FAN-OUT SENSOR PACKAGE AND CAMERA MODULE - The fan-out sensor package includes: a core member having a through-hole; an integrated circuit (IC) for a sensor disposed in the through-hole and having a first surface having a sensor region and first connection pads disposed thereon, a second surface opposing the first surface and having second connection pads disposed thereon, and through-silicon vias (TSVs) penetrating between the first and second surfaces and electrically connecting the first and second connection pads to each other; an encapsulant covering the core member and the second surface of the IC for a sensor and filling at least portions of the through-hole; a redistribution layer disposed on the encapsulant; and vias penetrating through at least portions of the encapsulant and electrically connecting the redistribution layer and the second connection pads to each other. | 2019-05-09 |
20190140012 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening. | 2019-05-09 |
20190140013 | IMAGE-CAPTURING UNIT - Provided is an image-capturing unit including an image-capturing chip that includes a first surface having a pixel and a second surface that is on an opposite side of the first surface and has provided thereon an output section that outputs a pixel signal read from the pixel; a transparent substrate that is arranged facing the first surface and includes a wire pattern; a mounting substrate that is arranged facing the second surface and supports the image-capturing chip; and a relay section that is arranged on the mounting substrate and relays, to the wire pattern, the pixel signal output from the output section. Also provided is an image-capturing apparatus including the image-capturing unit described above. | 2019-05-09 |
20190140014 | IMAGING DEVICE AND CAMERA SYSTEM - An imaging device includes a first pixel and a second pixel, each of the first pixel and the second pixel including a photoelectric converter that includes a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode and that converts incident light into charge, an amplifier transistor that has a gate electrode coupled to the first electrode and that outputs a signal corresponding to an amount of the charge, and a light attenuator that is layered on the photoelectric conversion layer and that attenuates light toward the photoelectric conversion layer. A transmittance of the light attenuator of the first pixel is different from a transmittance of the light attenuator of the second pixel. | 2019-05-09 |
20190140015 | HORTICULTURAL LIGHTING DEVICES AND METHODS - Horticultural lighting devices and methods are disclosed herein. The methods include generating an LED-based horticultural light spectrum at a radiant flux. The horticultural lighting devices include a light fixture configured to receive and to operate plural light-emitting diodes (LEDs). The horticultural lighting device also includes a plurality of LEDs, coupled to the light fixture, that generate a radiant flux. For both the methods and the horticultural lighting devices, 7%-15% of the radiant flux is from light with wavelengths in a blue light band of 400 nanometers (nm) to less than 500 nm, 20%-40% of the radiant flux is from light with wavelengths in a green light band of 500 nm to less than 600 nm, and 45%-60% of the radiant flux is from light with wavelengths in a red light band of 600 nm to less than 700 nm. | 2019-05-09 |
20190140016 | HIGH RESOLUTION DISPLAY DEVICE - A display device is provided. The display device includes a substrate, an emission layer configured to emit light, the emission layer including a first semiconductor layer provided on the substrate, an active layer provided on the first semiconductor layer, and a second semiconductor layer provided on the active layer, and a plurality of color converting layers provided on the emission layer and configured to emit light of certain colors from light emitted from the emission layer. | 2019-05-09 |
20190140017 | MICRO LED COLOR DISPLAY DEVICE - A Micro LED color display device is provided, which uses a second blue LED (B | 2019-05-09 |
20190140018 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present disclosure provides a method for manufacturing the semiconductor structure. The method includes forming an N | 2019-05-09 |
20190140019 | APPARATUS AND METHODS FOR INTEGRATING MAGNETORESISTIVE DEVICES - An integrated circuit device includes a memory portion and a logic portion. The memory portion may include a plurality of magnetoresistive devices and the logic portion may include logic circuits. The memory portion may include a plurality of metal conductors separated by a first interlayer dielectric material (ILD), wherein the first ILD is a low-k ILD or an ultra low-k ILD. And, the logic portion may include a plurality of metal conductors separated by a second interlayer dielectric material (ILD). | 2019-05-09 |
20190140020 | MAGNETIC DETECTION CIRCUIT, MRAM AND OPERATION METHOD THEREOF - A magnetic detection circuit for a magnetic random access memory (MRAM) is provided. The magnetic detection circuit includes a sensing array including a plurality of sensing cells and a controller. Each of the sensing cells includes a first magnetic tunnel junction (MTJ) device. The controller is configured to access the first MRAM cells to detect the external magnetic field strength of the MRAM. The controller determines whether to stop the write operation of a plurality of memory cells of the MRAM according to the external magnetic field strength of the MRAM, and each of the memory cells includes a second MTJ device. The first MTJ device is smaller than the second MTJ device. | 2019-05-09 |
20190140021 | SEMICONDUCTOR MEMORY DEVICE - A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate. | 2019-05-09 |
20190140022 | MEMORY DEVICES HAVING CROSSPOINT MEMORY ARRAYS THEREIN WITH MULTI-LEVEL WORD LINE AND BIT LINE STRUCTURES - A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact. | 2019-05-09 |
20190140023 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner. | 2019-05-09 |
20190140024 | ORGANIC LIGHT-EMITTING DIODE TOUCH DISPLAY OPERATING METHOD - An OLED touch display operation method is disclosed. The OLED touch display operation method includes the following steps: controlling a touch scan transition timing and a display multiplexer switching timing to maintain a specific equidistant relationship; when the OLED touch display performs display function, the OLED touch display performs touch scanning only for a part of display time, and stops touch scanning or performs touch voltage compensation scanning for another part of display time; and when being interfered by external noise, the OLED touch display performs touch scanning only in a blanking period out of the display time and the touch scanning frequency can be adjusted to avoid interference of external noise. | 2019-05-09 |
20190140025 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel and a display device are provided. By simplifying the design of a part of a pixel drive circuit on a drive array substrate in a bending region of the display panel, the number of a drive transistor and other switching control tubes having the largest area in a partial region of the pixel drive circuit are reduced. Moreover, by removing an inorganic insulation layer having a larger stress, an organic buffer layer having a larger elastic modulus is filled. Therefore, the bending region has good bendability or foldability. | 2019-05-09 |
20190140026 | DISPLAY PANEL - To prevent the display quality from being degraded as a result of (i) a boundary portion of an edge region of the display region being visibly in the shape of stairs and/or (ii) emitted light having an unintended color, a display panel includes a light-shielding section including, for each pixel ( | 2019-05-09 |
20190140027 | Light-Emitting Element, Display Module, Lighting Module, Light-Emitting Device, Display Device, Electronic Appliance, and Lighting Device - A multicolor light-emitting element that utilizes fluorescence and phosphorescence and is advantageous for practical application is provided. The light-emitting element has a stacked-layer structure of a first light-emitting layer containing a host material and a fluorescent substance and a second light-emitting layer containing two kinds of organic compounds and a substance that can convert triplet excitation energy into luminescence. Note that light emitted from the first light-emitting layer has an emission peak on the shorter wavelength side than light emitted from the second light-emitting layer. | 2019-05-09 |
20190140028 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a first switching element electrically connected to a gate line extending in a first direction and a data line extending in a second direction crossing the first direction, an organic layer disposed on the first switching element, a shielding electrode disposed on the organic layer and overlapping the data line, a pixel electrode disposed on the same layer as the shielding electrode and a light-blocking pattern disposed on the shielding electrode and adjacent to a corner of the pixel electrode | 2019-05-09 |
20190140029 | DISPLAY DEVICE - A display device includes a substrate including a display area and a non-display area, a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels displaying a different color from a color of the first pixel column, and data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column, wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines. | 2019-05-09 |
20190140030 | PIXEL ARRANGEMENT STRUCTURE AND DRIVING METHOD THEREOF, DISPLAY SUBSTRATE AND DISPLAY DEVICE - A pixel arrangement structure, including a plurality of repeating units, wherein each of the plurality of repeating units includes one first sub-pixel, one second sub-pixel, and two third sub-pixels; in each of the plurality of repeating units, the two third sub-pixels are arranged in one of a first direction and a second direction, and the first sub-pixel and the second sub-pixel are arranged in the other one of the first direction and the second direction; the plurality of repeating units are arranged in the first direction to form a plurality of repeating unit groups, the plurality of repeating unit groups are arranged in the second direction; and the first direction and the second direction are different directions. | 2019-05-09 |
20190140031 | Display-Integrated Infrared Emitter and Sensor Structures - In one embodiment, an electronic display includes a first plurality of hexagon-shaped pixels and a second plurality of hexagon-shaped pixels that are coplanar with the first plurality of hexagon-shaped pixels. The first plurality of hexagon-shaped pixels each include an infrared (IR) emitter subpixel that is operable to emit IR light. The second plurality of hexagon-shaped pixels each include an IR detector subpixel that is operable to detect IR light. Each IR emitter subpixel and each IR detector subpixel includes an anode layer and a cathode layer. Each particular IR emitter subpixel includes an IR emissive layer located between the anode layer and the cathode layer of the particular IR emitter subpixel. Each particular IR detector subpixel includes an IR detector layer located between the anode layer and the cathode layer of the particular IR detector subpixel. | 2019-05-09 |
20190140032 | IDENTIFYING POTENTIALLY-DEFECTIVE PICTURE ELEMENTS IN AN ACTIVE-MATRIX DISPLAY PANEL - An example process includes: powering, via a power supply, an active-matrix display panel comprised of picture elements; and identifying, based on an output of the power supply, one or more picture elements in the active-matrix display panel that are potentially defective. The example process may also include identifying, among one or more of the picture elements that are potentially-defective, one or more picture elements that actually are defective. | 2019-05-09 |
20190140033 | OLED DISPLAY AND MAUNFACTURE METHOD THEREOF - An OLED display and manufacture method thereof are provided. The OLED display includes a TFT substrate, the TFT substrate having a plurality of light-blocked pixel isolation layers and a plurality of OLED emissive layers on a surface thereof, and each OLED emissive layer having cathode on a surface thereof. The light-blocked pixel isolation layer includes a wall portion, and the wall portion having a light-blocked portion on a surface thereof. The TFT substrate has a plurality of pixel regions surrounded by the wall portions of the light-blocked pixel isolation layers on the surface thereof. Each pixel region respectively has the OLED emissive layer therein. The OLED display and method avoid light leakage caused by the oblique light of each pixel region emitted into adjacent pixel regions while the OLED emissive layer lighting. | 2019-05-09 |
20190140034 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - Provided are an organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes: a substrate on which a display area is defined, wherein an image is displayed on the display area; a thin film transistor arranged on the display area of the substrate; a via-insulating layer covering the thin film transistor; a pixel electrode arranged on the via-insulating layer and electrically connected to the thin film transistor; a pixel-defining layer including an opening exposing a central portion of the pixel electrode, and covering an edge of the pixel electrode; a counter electrode facing the pixel electrode; an organic emission layer arranged between the pixel electrode and the counter electrode; a wire arranged on the via-insulating layer to be spaced apart from the pixel electrode and including a spacer area and a non-spacer area; and a spacer arranged on the spacer area. | 2019-05-09 |
20190140035 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus including: a substrate including a display area and a peripheral area at an outer side of the display area; a pixel electrode disposed in the display area of the substrate; a pixel-defining layer disposed on the pixel electrode and exposing at least a portion of the pixel electrode; an intermediate layer disposed on the pixel electrode; an opposite electrode disposed on the intermediate layer; a first conductive layer disposed in the peripheral area of the substrate and including at least one opening; a first block structure and a second block structure disposed on the first conductive layer and separated from each other with the at least one opening therebetween; and an encapsulation structure disposed on the opposite electrode in the display area and the peripheral area. | 2019-05-09 |
20190140036 | DISPLAY DEVICE - A display device includes a substrate including a display area and a peripheral area, a pixel area, a data driver, a data divider, and coupling lines that couple the data driver to the data divider. The pixel area includes first pixel lines in a first area of the display area and coupled to first area data lines, and second pixel lines disposed in a second area of the display area and coupled to second area data lines. The data driver outputs data signals corresponding to the first and second pixel lines. The data divider includes first selectors that transfer the data signals corresponding to the first pixel lines to the first area data lines, and second selectors that transfer the data signals corresponding to the second pixel lines to the second area data lines. A distance between adjacent second selectors is shorter than a distance between adjacent first selectors. | 2019-05-09 |
20190140037 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display is disclosed. The organic light emitting diode display includes a first substrate, a second substrate, and a conductive filler layer between the first substrate and the second substrate. The first substrate includes an auxiliary electrode, a first barrier disposed on the auxiliary electrode, a cathode physically divided by the first barrier and exposing at least a portion of the auxiliary electrode, and a protective layer disposed on the cathode, physically divided by the first barrier, and exposing at least a portion of the auxiliary electrode. The second substrate includes a spacer protruding toward the first substrate and disposed adjacent to the auxiliary electrode and a power line covering at least a portion of the spacer and supplied with a power voltage. | 2019-05-09 |
20190140038 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display is disclosed. The organic light emitting diode display includes a first substrate on which a power electrode supplied with a power voltage and an organic light emitting diode are disposed, a second substrate on which a power line is disposed, the second substrate facing the first substrate, a conductive filler layer interposed between the first substrate and the second substrate, the conductive filler layer including a conductive medium electrically connecting a cathode of the organic light emitting diode to the power line, and a conductive sealant disposed at an edge of the first substrate and an edge of the second substrate, the conductive filler layer being accommodated inside the conductive sealant. The conductive sealant electrically connects the power electrode to the power line. | 2019-05-09 |
20190140039 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display is disclosed. The organic light emitting diode display includes a first substrate including an organic light emitting diode, a second substrate including a power line supplied with a power voltage and facing the first substrate, and a conductive filler layer between the first substrate and the second substrate. The first substrate includes an auxiliary electrode, a first barrier on the auxiliary electrode, a cathode physically divided by the first barrier and exposing at least a portion of the auxiliary electrode, a contact electrode disposed on the cathode, physically divided by the first barrier, and exposing at least a portion of the auxiliary electrode, and a protective layer between the cathode and the contact electrode. One end of the cathode directly contacts the auxiliary electrode, and one end of the contact electrode directly contacts the auxiliary electrode. | 2019-05-09 |