19th week of 2013 patent applcation highlights part 59 |
Patent application number | Title | Published |
20130117501 | GARBAGE COLLECTION METHOD FOR NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory area having free segments and first to fourth regions having used segments. The garbage collection method includes selecting a target segment from the used segments, moving a valid data block from the selected target segment to the used segments, and erasing data of all data blocks in the selected target segment and making the selected target segment into a free segment. When the number of free segments is greater than a predefined value, the target segment is selected by a first method and valid data blocks in the target segment are moved by a second method. When the number of free segments is less than the predefined value, the target segment is selected by a third method and valid data blocks in the target segment are moved by a fourth method. | 2013-05-09 |
20130117502 | METHOD FOR MANAGING SYSTEM FIRMWARE IN NAS SERVER - A method for managing system firmware in a network attached storage (NAS) server comprises: synchronizing system firmware stored one or more of two or more hard disks (HDDs) and system firmware stored in a nonvolatile memory with each other; and confirming whether or not at least one valid HDD in which the system firmware is stored exists, when an HDD is replaced; and copying the system firmware stored in the nonvolatile memory into the replaced HDD, when it is confirmed that the valid HDD does not exist. In the method, when a watch dog timer is reset, the system firmware stored in the nonvolatile memory is synchronized, based on the system firmware stored in the HDD, by confirming whether or not the system firmware of the HDD and the system firmware of the nonvolatile memory are synchronized with each other. | 2013-05-09 |
20130117503 | SERVICING NON-BLOCK STORAGE REQUESTS - An apparatus, system, and method are disclosed for servicing storage requests for a non-volatile memory device. An interface module is configured to receive a storage request for a data set of a non-volatile memory device from a client. The data set is different from a block of the non-volatile memory device, and may have a length different from a block size of the non-volatile memory device. A block load module is configured to load data of at least the block size of the non-volatile memory device. A fulfillment module is configured to service the storage request using at least a portion of the loaded data. | 2013-05-09 |
20130117504 | EMBEDDED MEMORY AND DEDICATED PROCESSOR STRUCTURE WITHIN AN INTEGRATED CIRCUIT - An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory. | 2013-05-09 |
20130117505 | SETTING OPTIMAL SPACE ALLOCATION POLICY FOR CREATING DEPENDENT SNAPSHOTS TO ENHANCE APPLICATION WRITE PERFORMANCE AND REDUCE RESOURCE USAGE - In one embodiment, a system includes a network storage controller having logic adapted for receiving a request to duplicate at least a portion of a volume stored on the first disk array, logic adapted for creating at least one dependent volume on the first disk array, and logic adapted for duplicating the at least the portion of the volume to the at least one dependent volume on the first disk array to create a snapshot. Other systems, computer program products, and methods are described according to more embodiments. | 2013-05-09 |
20130117506 | INTEGRATED CIRCUIT DEVICE, DATA STORAGE ARRAY SYSTEM AND METHOD THEREFOR - An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command. | 2013-05-09 |
20130117507 | MEMORY STORAGE APPARATUS, MEMORY CONTROLLER, AND METHOD FOR TRANSMITTING AND IDENTIFYING DATA STREAM - A memory storage apparatus, a memory controller and method for transmitting and identifying data streams are provided. The memory controller passes at least a portion of a data stream received from a host system to a smart card chip of the memory storage apparatus. Then, the host system accurately receives a response message from the smart card chip by executing a plurality of read commands. The memory controller is capable of adding a first verification code to a response data stream sent to the host system, and is capable of adding a write token to each of data segments of the response data stream. The host system confirms the accuracy of the response data stream by verifying the first verification code or by verifying the write token of each of the data segments. | 2013-05-09 |
20130117508 | ELECTRONIC DEVICE SYSTEM, ELECTRONIC DEVICE, AND STORAGE MEDIUM - An electronic device system, an electronic device and a storage device that prevent the processing by a program stored in a non-certified storage medium are provided. | 2013-05-09 |
20130117509 | TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS - A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device. | 2013-05-09 |
20130117510 | SYSTEM AND METHOD FOR MANAGING AN OBJECT CACHE - In order to optimize efficiency of deserialization, a serialization cache is maintained at an object server. The serialization cache is maintained in conjunction with an object cache and stores serialized forms of objects cached within the object cache. When an inbound request is received, a serialized object received in the request is compared to the serialization cache. If the serialized byte stream is present in the serialization cache, then the equivalent object is retrieved from the object cache, thereby avoiding deserialization of the received serialized object. If the serialized byte stream is not present in the serialization cache, then the serialized byte stream is deserialized, the deserialized object is cached in the object cache, and the serialized object is cached in the serialization cache. | 2013-05-09 |
20130117511 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus has a cache having a normal mode and a retention mode in which the cache consumes less power than in the normal mode. An interconnect receives, from at least one other device, coherency access requests for data stored in the cache. In the normal mode, the data in the cache is accessible and the cache generates coherency responses in response to the coherency access requests, while in the retention mode the data is retained in the cache but inaccessible in response to the coherency access requests. A coherency controller is provided to monitor the coherency access requests and coherency responses. Switching of the cache from the normal mode to the retention mode is deferred until the coherency controller has detected coherency responses for all coherency access requests passed to said cache. | 2013-05-09 |
20130117512 | PROGRAM CONVERTING APPARATUS, PROGRAM CONVERTING METHOD, AND MEDIUM - According to one embodiment, a program converting device includes an access attribute determining unit, a non-sharing target classifying unit, and a converting unit. The access attribute determining unit calculates exclusive accesses from memory accesses by threads forming a source program and determines a memory access using a cache memory among the calculated exclusive accesses. The non-sharing target classifying unit determines an access data item that does not share a cache line with another access data item among the access data items that are accessed using the cache memories. The converting unit inserts a process that does not share the cache line into the source program based on the determination result of the non-sharing target classifying unit. | 2013-05-09 |
20130117513 | MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH LATENCY MEMORY OPERATIONS - Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations. | 2013-05-09 |
20130117514 | Addressing Cross-Allocated Blocks in a File System - A mechanism is provided for cross-allocated block repair in a mounted file system. A set of cross-allocated blocks are identified from a plurality of blocks within an inode of the mounted file system, based on a corresponding bit associated with each cross-allocated block in a duplicated block information bitmap being in a first identified state. The set of cross-allocated blocks are repaired using a user-defined repair process. Then one or more of the set of cross-allocated blocks are deallocated based on results of the user-defined repair process. | 2013-05-09 |
20130117515 | Primary Data Storage System with Data Tiering - The invention is directed to a primary data storage system for use in a computer network in which a network allows user computers to transfer data to/from the primary data storage system. In one embodiment, the primary data storage system implements a tiering strategy to move data between stores with different characteristics so as to match the characteristics of the data to the characteristics of one of the stores. | 2013-05-09 |
20130117516 | Primary Data Storage System with Staged Deduplication - The invention is directed to a primary data storage system for use in a computer network in which a network allows user computers to transfer data to and/or from the primary data storage system. In one embodiment of the invention, the storage processor operates to analyze the data associated with write block commands that relate to different storage locations in a data store system that is associated with the primary data storage system so as to identify the potential writing of the block(s) of the same data to the data store system and prevent the writing of such blocks of data. | 2013-05-09 |
20130117517 | DATA ALLOCATION SYSTEM - A data control system facilitates transfer of a virtual disk from a primary storage system to a secondary storage system. The data control system, responsive to an instruction to transfer the virtual disk, wherein the virtual disk comprises a plurality of data blocks, determines whether each of the plurality of data blocks is allocated or unallocated; for each data block of the plurality of data blocks determined to be allocated, the data control system reads the data block from memory in the primary storage system and transfers the data block for storage in the secondary storage system; and for each data block of the plurality of data blocks determined to be unallocated, the data control system refrains from reading the data block from memory in the primary storage system. | 2013-05-09 |
20130117518 | SYSTEM CONTROLLER, INFORMATION PROCESSING SYSTEM AND METHOD OF SAVING AND RESTORING DATA IN THE INFORMATION PROCESSING SYSTEM - A system controller ( | 2013-05-09 |
20130117519 | Memory Management In Multi-Threaded Multi-Processor Computing System - Allocators are instantiated for each of a plurality of processors in a multi-threaded multi-processor computing system. The allocators selectively allocate and deallocate memory to threads executing on the associated processor. Related apparatus, systems, techniques and articles are also described. | 2013-05-09 |
20130117520 | METHOD AND APPARATUS FOR RELOCATING DATA - Disclosed are an apparatus and method for recycling areas of a data storage device by relocating data. In one embodiment, a method may comprise selecting a first storage area based on a quantity of obsolete data in the first storage area, moving valid data from the first storage area to a second storage area, and setting memory spaces corresponding to the first storage area as available memory for storing other data. Another embodiment may further comprise selecting a physical address-based move operation or a logical address-based move operation based on a number of sets of contiguous valid memory spaces in the first storage area, wherein the physical address-based move comprises moving data based on physical data addresses, and logical address-based moved comprises moving data based on logical block addresses. | 2013-05-09 |
20130117521 | Managing Chip Multi-Processors Through Virtual Domains - A chip multi-processor (CMP) with virtual domain management. The CMP has a plurality of tiles each including a core and a cache, a mapping storage, a plurality of memory controllers, a communication bus interconnecting the tiles and the memory controllers, and machine-executable instructions. The tiles and memory controllers are responsive to the instructions to group the tiles into a plurality of virtual domains, each virtual domain associated with at least one memory controller, and to store a mapping unique to each virtual domain in the mapping storage. | 2013-05-09 |
20130117522 | Inter-Process Memory Management - A memory allocator assigns temporary memory limits to each of a plurality of processes requiring memory. Thereafter, at least one assigned temporary memory limit is changed during execution of a corresponding process. Related apparatus, systems, techniques and articles are also described. | 2013-05-09 |
20130117523 | DATA COPYING METHOD AND APPARATUS IN A THIN PROVISIONED SYSTEM - Data migration includes copying between normal volumes and thin provisioned volumes. Data in a normal volume can be copied to a thin provisioned volume. Alternatively, data structures can be provided to facilitate converting a normal volume into a thin provisioned volume without actual copying of data. Copying from a thin provisioned volume to a normal volume is also disclosed. | 2013-05-09 |
20130117524 | MANAGEMENT OF RECYCLING BIN FOR THINLY-PROVISIONED LOGICAL VOLUMES - A method for data storage includes representing logical volumes by respective sets of pointers to physical partitions in which data used by the logical volumes is stored. One or more of the logical volumes are defined as provisionally deleted. A subset of the provisionally-deleted logical volumes is selected such that each logical volume in the subset has one or more private physical partitions whose data is used exclusively by that logical volume. One or more of the private physical partitions of the logical volumes in the subset are released for reallocation to another logical volume. | 2013-05-09 |
20130117525 | METHOD FOR IMPLEMENTING PRE-EMPTIVE READ RECONSTRUCTION - The present invention is directed to a method for pre-emptive read reconstruction. In the method(s) disclosed herein, when a pre-emptive read reconstruction timer times out, if one or more drive read operations for providing requested stripe read data are still pending; and if stripe read data corresponding to the pending drive read operations may be constructed (ex.—reconstructed) based on the stripe read data received before the expiration of the timer, the pending drive read operations are classified as stale, but the pending drive read operations are still allowed to complete rather than being aborted, thereby promoting efficiency of the data storage system in situations when the data storage system includes an abnormal disk drive (ex.—a disk drive which endures random cycles of low read performance). | 2013-05-09 |
20130117526 | SHARED TEMPORARY STORAGE MANAGEMENT IN A SHARED DISK DATABASE CLUSTER - System, method, computer program product embodiments and combinations and sub-combinations thereof for temporary storage management in a shared disk database cluster are provided. Included is the reserving of units on-demand and of variable size from shared temporary storage space in the SDC. The utilization of the reserved units of the shared temporary storage space is tracked, and the shared temporary storage space is administered based on the tracking. | 2013-05-09 |
20130117527 | METHOD AND APPARATUS FOR THIN PROVISIONING - Embodiments of the present invention provide a method and an apparatus for thin provisioning. The method includes: receiving a write IO instruction sent by a host; when the write IO instruction is not allocated a logical space and a pre-allocated space in an LUN is insufficient to be allocated to the write IO instruction, requesting a PVG for a first logical space having first allocation granularity, and in the first logical space, adopting second allocation granularity to allocate a second logical space to the write IO instruction, where the first allocation granularity is larger than the second allocation granularity; and sending the write IO instruction to the PVG, so that the PVG allocates a corresponding physical space to the write IO instruction according to the second logical space and preconfigured correspondence between logical spaces and physical spaces. In the embodiments of the present invention, the storage performance can be provided. | 2013-05-09 |
20130117528 | Partitioning Data Within A Distributed Data Storage System Using Virtual File Links - A record within a destination virtual file is generated on a destination node of a distributed data storage system. The record comprises (i) a link directed to a partition of a source virtual file stored on a source node and (ii) partition criteria characterizing the partition. The source virtual file is mapped to a chain of linked pages stored in a page buffer of the distributed data storage system and the partitioning criteria is used by at least one of the source node and the destination node to identify data associated with the partition. A request is later received at the destination node to access data defined by the destination virtual file. Data is provided, in response to the request, from the partition of the source virtual file stored on the source node using the link and the partitioning criteria. Related apparatus, systems, techniques and articles are also described. | 2013-05-09 |
20130117529 | DISPERSED STORAGE UNIT AND METHOD FOR CONFIGURATION THEREOF - A dispersed storage (DS) unit for use within a dispersed storage network is capable of self-configuring using registry information provided to the DS unit. The registry information includes a slice name assignment indicating a range of slice names corresponding to a plurality of potential data slices of potential data objects to be stored in the DS unit. Based on the registry information, the DS unit allocates a portion of physical memory to store the potential data slices. | 2013-05-09 |
20130117530 | APPARATUS FOR TRANSLATING VIRTUAL ADDRESS SPACE - The apparatus includes a virtual address space generation unit generating a virtual address space of a guest operating system, the guest operating system being executed in the virtual address space, and a virtual address space of a virtual machine monitor, the virtual machine monitor being executed in the virtual address space; a gateway page generation unit generating a gateway page allocated to a predetermined region of an actual memory region and mapped to the virtual address space of the guest operating system and the virtual address space of the guest machine monitor; and a memory management unit executing the gateway page to map a kernel region of the guest operating system to the predetermined region of the virtual address space of the virtual machine monitor to perform translation between the virtual address space of the guest operating system and the virtual address space of the virtual machine monitor. | 2013-05-09 |
20130117531 | METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION - A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed. | 2013-05-09 |
20130117532 | INTERLEAVING ADDRESS MODIFICATION - An apparatus having a plurality of memory blocks and a circuit is disclosed. The circuit may be configured to (i) generate a second address by removing one or more first bits of a first address from one or more first locations defined by a first value, (ii) generate a third address by adding an offset value to the second address and (iii) generate a fourth address by inserting a selected one of a plurality of modifiers into the third address. The selected modifier may be inserted into the third address at the first locations. Each modifier is generally associated with a respective one of a plurality of buffers formed in the memory blocks. The circuit may also be configured to access the respective buffer of the fourth address. | 2013-05-09 |
20130117533 | COPROCESSOR HAVING TASK SEQUENCE CONTROL - A coprocessor has: a processing unit for processing tasks in a data-processing system subject to at least one master processor; at least one storage module having memory areas, assignable in each case to the tasks, for storing data assigned to the tasks; and a buffer area for buffering instructions assigned to the tasks, the instructions including processing instructions, and upon retrieval of the processing instructions from the buffer area, the data stored in the storage module being processed on the basis of the processing instructions. | 2013-05-09 |
20130117534 | INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS - Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively. | 2013-05-09 |
20130117535 | Selective Writing of Branch Target Buffer - A method includes executing a branch instruction and determining if a branch is taken. The method further includes evaluating a number of instructions associated with the branch instruction. Upon determining that the branch is taken, the method includes selectively writing an entry into a branch target buffer that corresponds to the taken branch responsive to determining that the number of instructions is less than a threshold. | 2013-05-09 |
20130117536 | RECONFIGURABLE INSTRUCTION ENCODING METHOD AND PROCESSOR ARCHITECTURE - A reconfigurable instruction encoding method includes the followings. An instruction distribution of an application is counted, and multiple instruction pairs with higher utilization rates are accordingly found. Multiple instructions of the instruction pairs are duplicately encoded according to multiple reserved sections of an original instruction table, so that the instructions have corresponding reconfigured codes and a reconfigured instruction table extended from the original instruction table and including the reconfigured codes is obtained. A compiler is utilized to generate multiple machine codes according to the reconfigured instruction table and consecutive execution instructions. Hamming distance of the machine codes corresponding to the reconfigured instruction table and the execution instructions are not longer than Hamming distance of the machine codes generated according to the original instruction table and the execution instructions. | 2013-05-09 |
20130117537 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 2013-05-09 |
20130117538 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 2013-05-09 |
20130117539 | Method and Apparatus for Packing Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 2013-05-09 |
20130117540 | METHOD AND APPARATUS FOR UNPACKING PACKED DATA - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 2013-05-09 |
20130117541 | SPECULATIVE EXECUTION AND ROLLBACK - One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of other instructions. A scheduler circuit issues instructions for execution assuming that, several cycles later, when the instructions reach multithreaded execution units, that dependencies between the instructions will be resolved, resources will be available, operand data will be available, and other conditions will not prevent execution of the instructions. When a rollback condition exists at the point of execution for an instruction for a particular thread group, the instruction is not dispatched to the multithreaded execution units. However, other instructions issued by the scheduler circuit for execution by different thread groups, and for which a rollback condition does not exist, are executed by the multithreaded execution units. The instruction incurring the rollback condition is reissued after the rollback condition no longer exists. | 2013-05-09 |
20130117542 | CODE COVERAGE FRAMEWORK - A method, information processing system, and computer program product record an execution of a program instruction. A determination is made that a thread has entered a program unit. Another determination is made that that the thread is associated with at least one attribute that matches a set of thread recording criteria. An instruction recording mechanism for the thread is dynamically activated in response to the at least one attribute of the thread matching the set of thread recording criteria. | 2013-05-09 |
20130117543 | LOW OVERHEAD OPERATION LATENCY AWARE SCHEDULER - A method and apparatus for processing multi-cycle instructions include picking a multi-cycle instruction and directing the picked multi-cycle instruction to a pipeline. The pipeline includes a pipeline control configured to detect a latency and a repeat rate of the picked multi-cycle instruction and to count clock cycles based on the detected latency and the detected repeat rate. The method and apparatus further include detecting the repeat rate and the latency of the picked multi-cycle instruction, and counting clock cycles based on the detected repeat rate and the latency of the picked multi-cycle instruction. | 2013-05-09 |
20130117544 | METHOD AND APPARATUS FOR RUN-TIME STATISTICS DEPENDENT PROGRAM EXECUTION USING SOURCE-CODING PRINCIPLES - Disclosed are a method and system for optimized, dynamic data-dependent program execution. The disclosed system comprises a statistics computer which computes statistics of the incoming data at the current time instant, where the said statistics include the probability distribution of the incoming data, the probability distribution over program modules induced by the incoming data, the probability distribution induced over program outputs by the incoming data, and the time-complexity of each program module for the incoming data, wherein the said statistics are computed on as a function of current and past data, and previously computed statistics; a plurality of alternative execution path orders designed prior to run-time by the use of an appropriate source code; a source code selector which selects one of the execution path orders as a function of the statistics computed by the statistics computer; a complexity measurement which measures the time-complexity of the currently selected execution path-order. | 2013-05-09 |
20130117545 | High-Word Facility for Extending the Number of General Purpose Registers Available to Instructions - A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed. | 2013-05-09 |
20130117546 | Load Pair Disjoint Facility and Instruction Therefore - A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers. | 2013-05-09 |
20130117547 | Method and Apparatus for Unpacking and Moving Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 2013-05-09 |
20130117548 | ALGORITHM FOR VECTORIZATION AND MEMORY COALESCING DURING COMPILING - One embodiment of the present invention sets forth a technique for reducing the number of assembly instructions included in a computer program. The technique involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, where each node includes an assembly instruction of the computer program, hierarchically parsing the plurality of nodes to identify at least two assembly instructions that are vectorizable and can be replaced by a single vectorized assembly instruction, and replacing the at least two assembly instructions with the single vectorized assembly instruction. | 2013-05-09 |
20130117549 | METHOD FOR EXECUTING MULTIPLE OPERATING SYSTEMS AND ELECTRONIC APPARATUS - A method for executing multiple operating systems (OSs) and an electronic apparatus are provided. Current hardware resources of the electronic apparatus are obtained after executing a boot process. The hardware resources are allocated to each of the OSs according to a resource allocation ratio, so as to load each of the OSs. | 2013-05-09 |
20130117550 | ACCESSING SECURE VOLUMES - A system and method for reading data from or writing data to a secure volume of a secure peripheral device. The secure peripheral device is communicatively coupled with a first host computer. The secure peripheral device includes an unsecure first volume, a secure second volume, and a secure third volume. Data is read from or written to the secure third volume either via an operating system stored on the first host computer or via an operating system stored on the secure peripheral device. | 2013-05-09 |
20130117551 | SECURITY METHOD - A security method for verifying a client device comprising: loading and executing a boot loader at the client device which establishes a connection to a boot compliance server; sending a first cryptographic element from the boot compliance server to the client device; generating a first cryptographic response with the first cryptographic element based on at least part of the boot loader and sending the first cryptographic response to the boot compliance server for verification; and continuing the boot process upon successful verification of the first cryptographic response. | 2013-05-09 |
20130117552 | METHOD FOR CHANGING RECEIVING MODE IN MOBILE TERMINAL AND MOBILE TERMINAL THEREOF - Disclosed herein are a method of changing a receiving mode in a mobile terminal, and a mobile terminal thereof. The method includes entering a charging ready mode when the mobile terminal is positioned adjacent to an external wireless power transmitting module; determining whether the receiving mode of the mobile terminal is a vibration mode; and, when the receiving mode of the mobile terminal is the vibration mode, changing the receiving mode of the mobile terminal to a non-vibration mode. | 2013-05-09 |
20130117553 | Method and Apparatus for Increasing the Output of a Cryptographic System - The rate at which packets are provided to a cryptographic engine of a cryptographic system is adjusted using a feedback mechanism to increase the output of the cryptographic system. Data is classified and queued on a per class/flow basis and stored in input queues prior to being processed. A class based queue scheduler is implemented to select data from the input queues to be transmitted to the cryptographic engine. The cryptographic engine operates in processing cycles. At each cycle, an amount of data is transferred from the input queues to a cryptographic engine input queue. A cryptographic accelerator in the cryptographic engine processes the data on the cryptographic engine input queue during the cycle. The output rate of the cryptographic accelerator is measured during the cycle and this value is used as feedback to determine how much data should be passed to the cryptographic engine for a subsequent cycle. | 2013-05-09 |
20130117554 | User key management for the Secure Shell (SSH) - Management of user keys for public key authentication using the SSH in large SSH deployments is automated by deploying a management system in the environment, discovering SSH identity keys and authorized keys, analyzing authorized connections between user accounts, and automatically managing the authorized connections and the key pairs used for authentication. | 2013-05-09 |
20130117555 | METHOD AND SYSTEM FOR DATA ENCRYPTION AND DECRYPTION IN DATA TRANSMISSION THROUGH THE WEB - This invention provides a method and system for data encryption and decryption in data transmission through the web. The method includes: a browser sends a cryptographic information acquisition request to a cryptographic information providing equipment; the cryptographic information providing equipment sends cryptographic information back to the browser via an HTTPS channel; the cryptographic information includes a cryptographic algorithm and a cryptographic index; the browser uses the cryptographic algorithm to encrypt the data to be transmitted, and sends the encrypted data and the cryptographic index to the web server via an HTTP channel; the web server obtains the cryptographic algorithm corresponding to the cryptographic index from the cryptographic information providing equipment, then decrypts the encrypted data. Embodiments of the present invention can alleviate the load in the HTTPS channel, and improve the overall performance. | 2013-05-09 |
20130117556 | AUTHENTICATED SENSOR INTERFACE DEVICE - A system and method for the secure storage and transmission of data is provided. A data aggregate device can be configured to receive secure data from a data source, such as a sensor, and encrypt the secure data using a suitable encryption technique, such as a shared private key technique, a public key encryption technique, a Diffie-Hellman key exchange technique, or other suitable encryption technique. The encrypted secure data can be provided from the data aggregate device to different remote devices over a plurality of segregated or isolated data paths. Each of the isolated data paths can include an optoisolator that is configured to provide one-way transmission of the encrypted secure data from the data aggregate device over the isolated data path. External data can be received through a secure data filter which, by validating the external data, allows for key exchange and other various adjustments from an external source. | 2013-05-09 |
20130117557 | CLOUD COMPUTING SYSTEM AND CLOUD SERVER MANAGING METHOD THEREOF - A cloud computing system is disclosed. The cloud computing system includes a management server that manages a plurality of servers and distributes service resources. Each of the servers corresponds to one of a secure server type and a general server type, and the secure server type of server decrypts an encrypted code provided from a client. | 2013-05-09 |
20130117558 | METHOD AND APPARATUS FOR AUTHENTICATING A DIGITAL CERTIFICATE STATUS AND AUTHORIZATION CREDENTIALS - A relying party obtains a certificate of a certificate subject and acquires a status information object for the certificate. The relying party validates the certificate using information in the status information object and compares authorization attributes present in the status information object with policy attributes associated with the requested service. A policy attribute is a set of constraints used by the relying party to determine if the authorization attributes associated with the certificate subject are sufficient to allow the certificate subject to access the requested service. If the authorization attributes present in the status information object match the policy attributes associated with the requested service, the relying party may grant the certificate subject access to the requested service. | 2013-05-09 |
20130117559 | System and Method for Multi-Certificate and Certificate Authority Strategy - Operations or functions on a device may require an operational certificate to ensure that the user of the device or the device itself is permitted to carry out the operations or functions. A system and a method are provided for providing an operational certificate to a device, whereby the operational certificate is associated with one or more operations of the device. A manufacturing certificate authority, during the manufacture of the device, obtains identity information associated with the device and provides a manufacturing certificate to the device. An operational certificate authority obtains and authenticates at least a portion of the identity information associated with the device from the manufacturing certificate and, if at least the portion of the identity information is authenticated, the operational certificate is provided to the device. | 2013-05-09 |
20130117560 | PROCESSING A DISPERSED STORAGE NETWORK ACCESS REQUEST UTILIZING CERTIFICATE CHAIN VALIDATION INFORMATION - A method begins by a processing module receiving a dispersed storage network (DSN) access request that includes a requester identifier (ID), wherein the requester ID is associated with a certificate chain. When the certificate chain is valid, the method continues with the processing module accessing registry information for the DSN. The method continues with the processing module identifying one of a plurality of access control lists based on at least one of information associated with the requester ID and information associated with the certificate chain, identifying one or more entries of the one of the plurality of access control lists based on the information associated with the certificate chain to produce one or more identified entries, and generating, for the DSN access request, permissions from one or more sets of permissions associated with the one or more identified entries. | 2013-05-09 |
20130117561 | SECURE DESKTOP APPLICATIONS FOR AN OPEN COMPUTING PLATFORM - Example secure desktop applications for an open computing platform are disclosed. An example secure desktop method for a computing platform disclosed herein comprises establishing a secure communication connection between a secure desktop provided by the computing platform and a trusted entity, the secure communication connection being accessible to a trusted application authenticated with the secure desktop, the secure communication connection being inaccessible to an untrusted application not authenticated with the secure desktop, and securing data that is stored by the secure desktop in local storage associated with the computing platform, the stored data being accessible to the trusted application and inaccessible to the untrusted application. | 2013-05-09 |
20130117562 | SECURITY METHOD, ASSOCIATED CHIP CARD, MODULE AND TERMINAL - A security method in a terminal comprising a chip card offering secure functions, a user interface, a module for interfacing with the chip card and suitable for shutting down or introducing the electrical supply to the chip card. After shutdown of the chip card with the terming being kept on, the interface module introduces the electrical supply to the chip card, encrypts a command for resumption of utilization of the secure functions with a negotiated key stored by the interfacing module, and dispatches the encrypted command to the chip card. The interface module utilizes the secure functions of the chip card when the resumption command decrypted by the chip card is recognized as a resumption command by the chip card. | 2013-05-09 |
20130117563 | SECURING INFORMATION IN A CLOUD COMPUTING SYSTEM - The method and system for secure data (information) inside a cloud computing system, allow data to be encrypted everywhere in the cloud on storage devices and in communication lines so that only the information owner has the encryption key and may decrypt the data. The main idea is using software filter technology inside the cloud virtual machine for encrypting and decrypting data and keeping the encryption key(s) only in the hand of the owner of the information outside the cloud. The encryption key is loaded into the appropriate filter only by permission of the information owner or an allowed user. The method allows combination of data encryption with application control and user control. | 2013-05-09 |
20130117564 | MANAGING SECURITY FOR COMPUTER SERVICES - A system or computer usable program product for providing security for a business application including receiving a request from a server including a server public key and a security token, deploying a virtual node implementing the business application in response to the request, using the security token in a bootstrap process by the virtual node to provide authentication to the server, and authenticating a message from the server using a server public key. | 2013-05-09 |
20130117565 | Peer-to-peer device management, monitor and control - The present invention provides a method, system and program product for peer-to-peer device management, monitor and control. Communication devices connected by communication networks can manage, monitor and control each other; they can be in both managing and managed roles. In one aspect, communication devices can send request messages comprising management, monitor and control commands to peers and receive response messages comprising results and statuses to the request messages from peers. In another aspect, communication devices can send notification messages to peers for management, monitor and control when their monitored contents or states meet predefined criteria. | 2013-05-09 |
20130117566 | MEMORY SYSTEM - A memory system comprises: a memory device including an authentication data area storing authentication unit information and a verification value, and a contents data area storing contents; and a host device configured to receive the authentication unit information and the verification value from the memory device, and perform secure authentication of the memory device based on whether a result of decoding the verification value is equal to the authentication unit information. | 2013-05-09 |
20130117567 | MANAGING SECURITY FOR COMPUTER SERVICES - A method for providing security for a business application including receiving a request from a server including a server public key and a security token, deploying a virtual node implementing the business application in response to the request, using the security token in a bootstrap process by the virtual node to provide authentication to the server, and authenticating a message from the server using a server public key. | 2013-05-09 |
20130117568 | CRYPTOGRAPHIC TECHNIQUES FOR A COMMUNICATIONS NETWORK - Techniques are described for enabling authentication and/or key agreement between communications network stations and service networks. The techniques described include the negotiation and use of a cryptographic primitive shared between a service network and a home environment of a station. The techniques described also feature a key usage indicator, such as a sequence number, maintained by the service network and a station. Comparison of the key usage indicators can, for example, permit efficient authentication of the service network. | 2013-05-09 |
20130117569 | METHOD AND APPARATUS FOR IMPROVING DIGITAL SIGNATURES - Systems and methods are provided for enchancing pseudo random number generation to thwart various security attacks to a system that relies on digital signature security measures. For example, a random number may be bound to a message that is to be signed using a digital signature. Alternatively, a random number may be bound to a secret seed value, which may be updated subsequent to each signing. Alternatively still, a random number may be bound to both the message to be signed using a digital signature and a secret seed value. | 2013-05-09 |
20130117570 | WATERMARK EXTRACTION BASED ON TENTATIVE WATERMARKS - Methods, devices and computer program products facilitate the extraction of embedded watermarks in the presence of content distortions. Pre-distorted synchronization templates are used to detect synchronization portions of embedded watermark frames. A pre-distorted synchronization template that best matches the synchronization portion of the embedded watermark frame produces an estimation of one or more distortions that are present in the content. The remainder of watermark frame can be evaluated based on the outcome of the comparison. | 2013-05-09 |
20130117571 | EXTRACTION OF EMBEDDED WATERMARKS FROM A HOST CONTENT BASED ON EXTRAPOLATION TECHNIQUES - Methods, devices and computer program products facilitate the extraction of embedded watermarks in the presence of content distortions. Subsequent to the detection of a tentative watermark, particular sections of the content are examined to form one or more extrapolated watermarks or watermark segments. Weights are assigned to the extrapolated watermarks or watermark segments, and used in combination with the detected tentative watermark to collectively assess if a desired probability of false detection is satisfied. | 2013-05-09 |
20130117572 | Portable electronic device, system and method for authenticating a document associated with a geographical location - In a portable electronic device, a method of authenticating a document associated with a geographical location is disclosed. A document is provided in the form of digital data, and a hash value is generated from the digital data of said document. Raw GPS data are received from at least one GPS satellite, and then digitally signed by a first private key of the portable electronic device. From the raw GPS data, exact GPS coordinates are calculated. A request for an authentic location stamp is sent to a certification unit, the request containing at least the hash value of the document, the raw GPS data and the exact GPS coordinates, wherein said request is digitally signed by a private key of the portable electronic device. In response to said location stamp request, a nonce value from the certification unit is received, said nonce value being digitally signed by a private key of the certification unit. A certification request is then sent to the certification unit, said request containing at least the hash value of the document, the raw GPS data, the exact GPS coordinates and the nonce value, wherein the certification request is digitally signed with said private key of the portable electronic device. In response to said certification request, a certified location stamp containing said certification request and a piece of time information is received, said location stamp being digitally signed by a private key of the certification unit. The certified location stamp is verified by using the corresponding public key of the certification unit, and if it is determined that the certified location stamp is signed by the certification unit, the certified location stamp will be assigned to the document. | 2013-05-09 |
20130117573 | METHOD FOR VERIFYING A PASSWORD - A method for verifying a password in a computing device, wherein the computing device comprises: a user input interface; a trusted hardware module having a trusted application stored therein, the trusted hardware module arranged to provide the trusted application with access to at least said user input interface; and a secure verification application for verifying the password; the method comprising: the trusted application receiving a request to obtain a user password; the trusted hardware module providing the trusted application with access to the user input interface; the user entering a password using the user input interface; the trusted application encoding the entered password; passing the encoded password to the secure transaction application; and decoding the password. | 2013-05-09 |
20130117574 | MEMORY DEVICE AND SYSTEM WITH SECURE KEY MEMORY AND ACCESS LOGIC - A memory device includes a first memory area that stores a secure key, a second memory area that stores content data, memory secure logic configured to exclusively access the secure key in the first memory area, and a memory controller, physically separate from the memory secure logic, that accesses the content data in response to externally provided command, address and data (CAD) information and the secure key as accessed through the memory secure logic. | 2013-05-09 |
20130117575 | ENCRYPTION APPARATUS, ENCRYPTION METHOD, DECRYPTION APPARATUS, DECRYPTION METHOD AND SYSTEM - An encryption method includes encrypting a first portion and second portion each of which is included in data to be encrypted, encrypting first information used for decryption of the first data portion, and associating second information used for decryption of the second portion with a predetermined part of the first data portion. | 2013-05-09 |
20130117576 | CONVERTING APPARATUS, CONVERTING METHOD, AND RECORDING MEDIUM OF CONVERTING PROGRAM - A converting method includes storing correspondence of each of first-type coded information, included in a first-type coded information group, and one of second-type coded information, included in a second-type coded information group, based on input information, by a processor, and converting, when input data includes the first-type coded information, first-type coded information in the input data into second-type coded information, based on the correspondence. | 2013-05-09 |
20130117577 | Secure Memory Transaction Unit - A method for providing security for plaintext data being transferred between units in a computer system includes steps of dividing a memory into a series of addressable locations, each of the addressable locations having an address at which can be stored version information, a data authentication tag, and ciphertext corresponding to the plaintext. The system retrieves the ciphertext, the version information, and the data authentication tag, and generates encryption keys for decrypting the information stored at the address. If the data authentication tag indicates the plaintext data are valid, then the system provides the decrypted plaintext to the requestor, or encrypts new plaintext data and stores the corresponding ciphertext with new authentication and version information at the first address. | 2013-05-09 |
20130117578 | METHOD FOR VERIFYING A MEMORY BLOCK OF A NONVOLATILE MEMORY - In a method for verifying a memory block of a nonvolatile memory, at a first point in time, a first authentication code for the memory block is determined while using a secret keyword and is stored in an authentication code memory table, and at a second point in time, for the verification, a second authentication code for the memory block is determined while using the secret keyword and is compared to the first authentication code and the memory block is verified if the first authentication code and the second authentication code agree. | 2013-05-09 |
20130117579 | APPARATUS AND METHOD OF PORTABLE TERMINAL FOR APPLICATION DATA PROTECTION - A method of operating a portable terminal for encrypting application data is provided. The method includes receiving data input to an application, encrypting the received data by using at least one of an application unique key and a combination of a device unique key of the portable terminal and an application IDentification (ID) that is globally unique, and storing the encrypted data. | 2013-05-09 |
20130117580 | COMPACT UNIVERSAL WIRELESS ADAPTER - A universal wireless adapter, which includes a power source, a power management element, a main processing unit, at least two serial connections, a wireless transceiver coupled to one of the at least two serial connections, wherein the transceiver is operable according to IEEE Standards 802.11b/g/n, and is capable of operating in one of an infrastructure mode and an ad hoc mode. The adapter also includes a volatile memory chip and a single non-volatile memory chip. The adapter also includes a synchronous boost voltage converter, wherein the input voltage from the battery is boosted to a higher, second voltage output. The second of at least two serial connections is a Universal Serial Bus (USB) serial connection; and a display coupled to the main processing unit, and the power source is a 2600 mAh, 3.7 volt battery. Mass-storage device couples to adapter to provide wireless access thereto. | 2013-05-09 |
20130117581 | POWER NEGOTIATION PROTOCOL - In one embodiment, a method includes a first device providing a first power to a second device using a first set of conductors out of a plurality of conductors. The method includes the first device providing, in response to receiving a notification, a second power to the second device using the first and a second set of conductors out of a plurality of conductors. The notification indicates that the second device can be supplied with a second power using the first set of conductors and a second set of conductors out of the plurality of conductors, and can also specify the configuration for enabling the second power. | 2013-05-09 |
20130117582 | OFFLINE COMMUNICATION IN A VOLTAGE SCALING SYSTEM - The subject matter of this application is embodied in an apparatus that includes a data processor, and a hardware monitor. The hardware monitor can be configured to emulate a critical path of the data processor, measure a parameter associated with the emulated critical path, process the measurement value, and generate an interrupt signal if the processing result meets a criterion. The apparatus also includes a power supply to provide power to the data processor and the hardware monitor, and a controller to control the power supply to adjust an output voltage level of the power supply. The controller upon receiving an interrupt signal from the hardware monitor queries the hardware monitor to obtain a measurement of the parameter and controls the power supply to adjust the output voltage level according to the measurement value. | 2013-05-09 |
20130117583 | METHOD FOR MANAGING THE SUPPLY VOLTAGE OF A MICROCONTROLLER FOR AN ELECTRONIC COMPUTER OF A MOTOR VEHICLE - A method for managing the power supply voltage (V | 2013-05-09 |
20130117584 | METHOD AND SYSTEM FOR ISOLATING LOCAL AREA NETWORKS OVER A CO-AXIAL WIRING FOR ENERGY MANAGEMENT - An energy management system. The system includes a coax controller apparatus comprising an exterior housing and plurality of coax modules numbered from 2 through N, where N is an integer greater than 3. In a specific embodiment, each of the coax modules comprises a powerline chip (PLC) module coupled to an analog front end, which is coupled to a coaxial connector. The system also has an electromagnetic shield configured to each of the coax modules. In a specific embodiment, the electromagnetic shield is configured to substantially maintain the coax module substantially free from interference noise or other disturbances. The system has a power meter coupled to one or more ports of the coax controller apparatus. | 2013-05-09 |
20130117585 | POWER SUPPLY DEVICE FOR SUPPLYING POWER VIA INTERNET NETWORK - A power supply device for supplying power via internet network comprises a power supply unit and a power consumption unit. The power supply unit comprises a power source unit and a first processing unit. The power source unit provides a first voltage with a first power and a second voltage with a second power. The first processing unit detects a connection status of the power supply unit for controlling the power source unit to provide the first voltage, and controlling the power source unit to provide the second voltage according to a control signal. The power consumption unit comprises a connecting unit and a second processing unit. The connecting unit is for connecting the power source unit and the first processing unit. The second processing unit receives the first voltage via the connecting unit and provides the control signal according to the first voltage. | 2013-05-09 |
20130117586 | NETWORK ACCESS DEVICE WITH FLEXIBLE PRECISE LOW-POWER REMOTE WAKE-UP MECHANISM APPLICABLE IN VARIOUS APPLICATION LAYER HANDSHAKE PROTOCOLS - A network access device is disclosed, having a transceiving circuit, a demodulation circuit, and a control circuit. The transceiving circuit is used to receive network signals. The demodulation circuit is coupled with the transceiving circuit and used to generate data frames according to the network signals. The control circuit is coupled with the demodulation circuit and used to wake up one or more components of an electronic device when at least two fields of the data frame match predetermined values, or when the data frames are received in a predetermined order. | 2013-05-09 |
20130117587 | SERVICE PROCESSING METHOD AND SERVER - The present invention provides a service processing method and a server, which belong to the field of mobile terminals. The method includes: installing, on a server, a service application same as that of a mobile terminal; running the service application on the server, and executing, in place of the mobile terminal, a service corresponding to the service application; determining, by the server according to a result of executing the service, whether the mobile terminal needs to be woken up; and when the service needs to wake up the mobile terminal, instructing the mobile terminal to process the service. The server executes a service in place of a mobile terminal, and when the mobile terminal needs to be woken up, instructs the mobile terminal to process the service, thereby reducing the power consumption of the mobile terminal, and extending the standby time and service life of the mobile terminal. | 2013-05-09 |
20130117588 | Run-Time Task-Level Dynamic Energy Management - A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator. | 2013-05-09 |
20130117589 | STABILITY CONTROL IN A VOLTAGE SCALING SYSTEM - The subject matter of this application is embodied in an apparatus that includes a data processor, and a hardware monitor to emulate a critical path of the data processor and measure a parameter associated with the emulated critical path, process the measurement value, and generate an interrupt signal if the processing result meets a criterion. The apparatus also includes a power supply to provide power to the data processor and the hardware monitor, and a controller to receive the interrupt signal from the hardware monitor and in response to the interrupt signal, controls the power supply to adjust an output voltage level of the power supply. | 2013-05-09 |
20130117590 | Minimizing Aggregate Cooling and Leakage Power with Fast Convergence - A mechanism is provided for minimizing system power in the data processing system with fast convergence. A current aggregate system power value is determined using a current thermal threshold value. For each potential thermal threshold value in a set of potential thermal threshold values, a determination is made as to whether there is a potential thermal threshold value that results in a potential aggregate system power value that is lower than the current aggregate system power value. Responsive to identifying an optimal potential thermal threshold value from the set of potential thermal threshold values that results in minimum aggregate system power value that is lower than the current aggregate system power value, the optimal potential thermal threshold value is set as a new thermal threshold value. | 2013-05-09 |
20130117591 | ELECTRONIC DEVICE - Manipulation receiving unit receives an operation input by a user manipulation. In case the manipulation receiving unit does not receive an input operation for a predetermined time period, a state control unit sets an operation state to a power saving state. However, if the voice receiving unit receives voice input before a non-operation time period reaches the predetermined time period, the status control unit does not set the operation state to the power saving state even if the manipulation receiving unit does not receive an input operation during the predetermined time period. The non-operation time period is defined as a time period during which the manipulation receiving unit does not receive an input operation. | 2013-05-09 |
20130117592 | POWER CAPPING SYSTEM - A method for power capping is disclosed. The power supplied to a load from a power supply is compared to a power capping limit | 2013-05-09 |
20130117593 | Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects - A System-on-a-Chip (SoC) comprising a controller, an activity counter, a reference pattern detection logic, a master pattern detection logic, an arbiter, a comparator, a tracker circuit, a delay cell circuit, and a request mask circuit coupled to a bus. The bus is configured to support master control. The controller is configured to cause components to enter a low power state. The activity counter is configured to monitor activity. The detection logics are configured to operate on an activity based clock or always on clock. The arbiter is configured to select an initiator. The comparator is configured to compare the output of the detection logics. The tracker circuit is configured to track selection of components. The delay cell circuit is configured to store output of components. The request mask circuit is configured to prevent request to arbiter or any arbiter selected request made from a previous clock cycle. | 2013-05-09 |
20130117594 | CONFIGURABLE THERMAL AND POWER MANAGEMENT FOR PORTABLE COMPUTERS - Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device. | 2013-05-09 |
20130117595 | SYSTEM AND METHOD FOR POWER MANAGEMENT OF MOBILE DEVICES - A method and system of managing power usage of devices including selectively executing a program application on a plurality of battery powered devices. Battery usage data is generated for a battery in one or more of the devices during execution of the work application. The battery usage data includes the run-time of the battery for the work application being executed. The data is aggregated and stored for the plurality of devices in memory. An application specific battery profile is generated using the stored battery usage data. The application specific battery profile is associated with the work application being run by the client devices. | 2013-05-09 |
20130117596 | METHOD OF ANALYZING A USAGE AMOUNT OF INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM AND COMPUTER READABLE RECORDING MEDIUM - The processing unit calculates usage amount of a program from a used amount of the processing unit and a power amount of the processing unit. The processing unit initializes a performance counter at a start of a execution of the program, calculates power amount of the program from the measured power consumption stored in the storage unit and the number of times of each event counted by the performance counter at a completion of execution of the program, and calculates usage of the program from the usage amount of the processing unit and calculated the power amount. | 2013-05-09 |
20130117597 | TIME SYNCHRONIZATION OF MULTIPLE TIME-BASED DATA STREAMS WITH INDEPENDENT CLOCKS - Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data streams are determined, and based on these relationships, times in at least one of the time-based data streams may be translated to times in any of the other time-based data streams despite the data streams having independent clocks. | 2013-05-09 |
20130117598 | GLITCHLESS PROGRAMMABLE CLOCK SHAPER - In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge. | 2013-05-09 |
20130117599 | SEMICONDUCTOR DEVICE OPERATING ACCORDING TO LATENCY VALUE - Disclosed herein is a device that includes a first register temporarily storing first information indicative of a reference latency, a second register temporarily storing second information indicative of an offset latency, a third register temporarily storing third information indicative of one of first and second operation modes, and a logic circuit configured to produce latency information in response to the first information when the third information is indicative of the first operation mode and to both of the first information and the second information when the third information is indicative of the second operation mode. | 2013-05-09 |
20130117600 | MEMORY MANAGEMENT IN A NON-VOLATILE SOLID STATE MEMORY DEVICE - A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes monitoring an occurrence of an error during a read operation in a memory unit of the device, where the error is correctable by error-correcting code, and programming the memory unit according to the monitored occurrence of the error, where the step of monitoring the occurrence of an error is carried out for at least one block, and wherein said step of programming includes wear-leveling the monitored block according the error monitored for the monitored block. | 2013-05-09 |