| 19th week of 2013 patent applcation highlights part 19 |
| Patent application number | Title | Published |
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| 20130113471 | ROTATION ANGLE DETECTION DEVICE AND TORQUE SENSOR - A torque sensor computes a steering torque applied to a steering wheel on the basis of a difference between a rotation angle of an input shaft, which is detected using a first resolver, and a rotation angle of a lower shaft, which is detected using a second resolver. A planetary gear mechanism that includes a sun gear that rotates together with the input shaft, a planetary gear that is made of a magnetic material and that revolves around the sun gear and an internal gear that is in mesh with the planetary gear is provided. A rotation angle of the input shaft and a position of the planetary gear are detected on the basis of voltage signals output from the first resolver, and a steering angle of the steering wheel is obtained on the basis of the detected rotation angle and the detected position. | 2013-05-09 |
| 20130113472 | METHOD AND APPARATUS FOR MAGNETIC CRACK DEPTH PREDICTION - A method of magnetic crack depth prediction for a magnetisable component of a first geometry comprising determining a measure of remnant magnetic flux leakage for a section of the component and, converting the remnant magnetic flux leakage to a predicted crack depth for that section of the component using an empirically determined relationship between remnant magnetic flux leakage and crack depth for a previously tested in service component of the first geometry. | 2013-05-09 |
| 20130113473 | MAGNETIC SENSOR WITH SHUNTING LAYERS AND MANUFACTURING METHOD THEREOF - The present invention directs a magnetic sensor with shunting layers, and the magnetic sensor includes a magnetic sensor bar which having an integral structure; and a plurality of shunting layers whose resistivity is lower than the magnetic sensor bar, respectively forming on the magnetic sensor bar in length direction without any physical separation therebetween, with spaces between every two adjacent shunting layers; and two electrode pads respectively forming on two ends of the magnetic sensor bar. The present invention also provides manufacturing method of the magnetic sensor. | 2013-05-09 |
| 20130113474 | Magnetic Sensor Device - A magnetic sensor device includes a magnet configured to generate a bias magnetic field. A plurality of electrical wires extend through the magnet. A magnetic sensor chip is attached to an end face of a first electrical wire of the plurality of electrical wires. | 2013-05-09 |
| 20130113475 | Magnetic Sensor Device and a Method for Fabricating the Same - A magnetic sensor device includes a plurality of electrical wires, a magnetic sensor chip, and a magnet. The magnet is formed from a material composition of a polymer and magnetic particles and attached to at least one of the electrical wires. | 2013-05-09 |
| 20130113476 | CIRCUIT ASSEMBLY AND METHOD FOR PROGRAMMING A HALL SENSOR HAVING AN UPSTREAM CONTROLLER - A circuit assembly having a controller in which the Hall sensor or a programmable circuit component integrated therein is programmed by clocking or modulating a Hall sensor power supply voltage. A clocked or modulated controller power supply voltage is applied to the controller in clocked or modulated form; and where the clock or modulated Hall sensor power supply voltage is applied to the Hall sensor by the controller as a function of the clocked or modulated controller power supply voltage. | 2013-05-09 |
| 20130113477 | CURRENT SENSORS - Embodiments relate to magnetic field current sensors having sensor elements for sensing at least two magnetic field components, for example Bx and By. The current in a conductor is estimated by Bx and Bx/By, wherein Bx is the primary measurement and Bx/By is a corrective term used to account for position tolerances between the sensor and the conductor. In other embodiments, the corrective term can be dBx/By, where dBx is a difference in between components sensed at different sensor elements. The particular field components can vary in embodiments; for example, the current can be estimated by By and By/Bx, or dBy/Bx or some other arrangement | 2013-05-09 |
| 20130113478 | METHOD OF USING A MAGNETORESISTIVE SENSOR IN SECOND HARMONIC DETECTION MODE FOR SENSING WEAK MAGNETIC FIELDS - A method to measure a magnetic field is provided. The method includes applying an alternating drive current to a drive strap overlaying a magnetoresistive sensor to shift an operating point of the magnetoresistive sensor to a low noise region. An alternating magnetic drive field is generated in the magnetoresistive sensor by the alternating drive current. When the magnetic field to be measured is superimposed on the alternating magnetic drive field in the magnetoresistive sensor, the method further comprises extracting a second harmonic component of an output of the magnetoresistive sensor. The magnetic field to be measured is proportional to a signed amplitude of the extracted second harmonic component. | 2013-05-09 |
| 20130113479 | METHOD FOR CORRECTING NMR AND NUCLEAR LOGS IN FORMATE MUD FILTRATE INVADED FORMATONS - A method of calculating a porosity of a geological formation includes determining a bulk pore volume and a movable fluid pore volume in the geological formation in which drilling mud including a mud filtrate is introduced, calculating a porosity of the formation based on a bulk pore volume, and correcting the porosity based on the movable fluid volume in the geological formation. | 2013-05-09 |
| 20130113480 | MULTIPHYSICS NMR LOGGING TECHNIQUES FOR THE DETERMINATION OF IN SITU TOTAL GAS IN GAS RESERVOIRS - Methods for the determination of the Total Gas in Place (TGiP) in gas-bearing formations are provided. Aspects of the subject disclosure also relate to the determination of the TGiP from nuclear magnetic resonance (NMR) logs alone or in combination other well logs. | 2013-05-09 |
| 20130113481 | APPARATUS AND METHOD FOR COMPENSATING ARTIFACT IN HIGHER ORDER DIFFUSION MAGNETIC RESONANCE IMAGING (MRI) - An apparatus and method for compensating for an artifact of higher order diffusion Magnetic Resonance Imaging (MRI) are provided. The apparatus includes a construction unit configured to construct a diffusion q-space matrix, a correction unit configured to correct an image shift in a phase encoding direction in the constructed diffusion q-space matrix, a reconstruction processing unit configured to reconstruct a q-space of a Diffusion Spectrum Imaging (DSI) based on the corrected image shift, and a tracking processing unit to process a DSI fiber tracking using the reconstructed q-space of the DSI. | 2013-05-09 |
| 20130113482 | METHOD TO GENERATE AN MR IMAGE, AND CORRESPONDING MAGNETIC RESONANCE SYSTEM - To generate an MR image, acquired MR data are entered into k-space on multiple uniform trajectories in k-space within a predetermined time period. The trajectories are acquired chronologically in a predetermined order before a predetermined point in time, and in a different order after the point in time. The i-th trajectory after the point in time in the different order is adjacent to the (n−i+1)-th trajectory in the predetermined order (n is the number of trajectories acquired before and after the point in time). Two trajectories are adjacent if a distance between them is less than a predetermined threshold. Except for the (n−i+1)-th trajectory, none of the trajectories acquired before the point in time has a distance from the i-th trajectory that is less than the threshold. The predetermined time period is set to be at a middle of a time period after an RF excitation pulse, such that a contrast change within the predetermined time period proceeds as linearly as possible over time. | 2013-05-09 |
| 20130113483 | MAGNETIC RESONANCE IMAGING APPARATUS AND CONTROL METHOD THEREOF - The magnetic resonance imaging apparatus includes a main magnet to generate a static magnetic field in an imaging region, a gradient coil assembly to form a gradient in the static magnetic field, a radio frequency (RF) coil assembly to apply a first RF pulse and second RF pulse with respect to n (n≧2) slice regions located at different positions in the imaging region, to excite atomic nuclei of the slice regions, and a controller to control the RF coil assembly to apply a first RF pulse and second RF pulse having a first center frequency f | 2013-05-09 |
| 20130113484 | APPARATUS FOR AUTOMATICALLY TESTING AND TUNING RADIO FREQUENCY COIL - In one embodiment, an apparatus for automatically testing and tuning a RF coil is provided. The apparatus comprises a digital frequency generator for generating a stimulus, the stimulus comprising a range of radio frequency signals having different frequencies, a radio frequency coupler configured for applying the stimulus to the RF coil so as to enable the RF coil to generate a reflected signal in response to the stimulus applied, a radio frequency detector for detecting the reflected signal and a signal processing unit for processing the reflected signal, so as to identify the tuned resonant frequency of the RF coil and further configured for calculating return loss at the RF coil based on the reflected signal. | 2013-05-09 |
| 20130113485 | Stacked Coil for Magnetic Resonance Imaging - A receive coil for MRI includes a stacked pair of coil elements to communicate the respective MR signals therein to the signal processing system in separate channels. This greatly increases image SNR and penetration depth and in parallel imaging. The coils are arranged in a stacked relationship so as to be at least partly and preferably wholly overlapped and lying in the same or closely adjacent planes. The coils include tuning capacitors to a common resonant frequency. The coils are connected by a conductor arranged such that the signals of the first and second coils are decoupled. The conductor can form a common portion of the coils including a capacitance of in the common portion arranged. The coils can be connected by two conductors one of which is a short and the other contains a capacitor. In both cases the connection conductors provide the decoupling. | 2013-05-09 |
| 20130113486 | MAGNETIC RESONANCE IMAGING APPARATUS - In one embodiment, an MRI apparatus ( | 2013-05-09 |
| 20130113487 | INSTRUMENTED CORE BARRELS AND METHODS OF MONITORING A CORE WHILE THE CORE IS BEING CUT - A formation core analysis system can include an inner barrel and a toroidal electromagnetic antenna which transmits electromagnetic signals into a formation core when the core is received in the inner barrel. Another formation core analysis system can include an inner barrel and multiple longitudinally spaced apart electrodes which electrically contact a formation core when the core is received in the inner barrel. A speed of displacement of the core into the inner barrel may be indicated by differences between measurements taken via the electrodes as the core displaces into the inner barrel. A method of measuring resistivity of a formation core as the core is being cut can include transmitting electromagnetic signals into the core from a toroidal electromagnetic antenna as the core is being cut by a coring bit. | 2013-05-09 |
| 20130113488 | APPARATUS AND METHODS FOR MONITORING A CORE DURING CORING OPERATIONS - One method of monitoring a formation core during coring operations can include measuring resistivities of a formation internal and external to a core barrel assembly, comparing the resistivities of the formation internal and external to the core barrel assembly, and determining a displacement of the core into the core barrel assembly, based at least in part on the comparing, while the core is being cut. A formation core analysis system can include multiple longitudinally spaced apart sets of transmitters and receivers which measure resistivity of a core while the core displaces into a core barrel assembly, and multiple longitudinally spaced apart sets of transmitters and receivers which measure resistivity of a formation external to the core barrel assembly while a coring bit penetrates the formation. A speed of displacement of the core may be indicated by differences in time between measurements taken via the different sets as the core displaces. | 2013-05-09 |
| 20130113489 | STATIONARY STAR-SHAPED ANTENNA METHOD FOR MANIPULATING FOCUSED BEAMFORMED, SHAPED FIELDS AND BEAMSTEERED ELECTROMAGNETIC SIGNAL FROM SUBTEL SEDIMENTARY STRATIGRAPHIC FORMATIONS DEEP IN THE EARTH - A method for electromagnetic geophysical surveying according to one aspect of the invention includes disposing a plurality of electromagnetic receivers in a selected pattern above an area of the Earth's subsurface to be evaluated. An electromagnetic source is repeatedly actuated proximate the electromagnetic receivers. Signals generated by the receivers, indexed in time with respect to each actuation of the at least one electromagnetic energy source, are recorded. The recorded signals are processed to generate an image corresponding to at least one point in the subsurface. The processing includes stacking recordings from each receiver for a plurality of actuations of the sources and beam steering a response of the receivers such that the at least one point is equivalent to a focal point of a response of the plurality of receivers. | 2013-05-09 |
| 20130113490 | APPARATUS AND METHOD FOR DIRECTIONAL RESISTIVITY MEASUREMENT WHILE DRILLING USING INCOMPLETE CIRCULAR ANTENNA - An apparatus for making directional resistivity measurements of a subterranean formation includes a resistivity tool body with a longitudinal axis and an outer surface, a first antenna with two open ends deployed below the outer surface, a second antenna deployed below the outer surface and spaced at an axial distance from the first antenna, and at least one slot formed on the outer surface. A corresponding method for making directional resistivity measurements includes rotating a resistivity tool in a borehole, utilizing a transmitter-receiver antenna group formed in the resistivity tool to process an electromagnetic wave, and computing a resistivity-related measurement from the electromagnetic wave received on the receiver antenna. | 2013-05-09 |
| 20130113491 | DRILLING DYNAMICS MONITOR - Procedures are described for monitoring dynamics along a drill string during the drilling process using only surface instrumentation or using a combination of surface and downhole instrumentation. Events such as drill collar whirl may be identified from signatures found in signals generated by an electromagnetic sensor such as a magnetometer and/or from a mechanical sensor such as accelerometer. Additional embodiments are described. | 2013-05-09 |
| 20130113492 | STORAGE BATTERY DETERIORATION DIAGNOSIS SYSTEM AND METHOD THEREOF - There is provided a storage battery deterioration diagnosis system, including: a cell-list creator configured to select diagnosis target cells from among a plurality of cells in a storage battery system, and create a list of the diagnosis target cells; a cell deterioration diagnoser configured to obtain degradation degrees of the diagnosis target cells; a temperature distribution estimator configured to estimate degradation degrees of non-target cells other than the diagnosis target cells, based on a distance between the non-target cell and the diagnosis target cells, and obtain temperature distribution of a whole of the plurality of cells based on degradation degrees of the diagnosis target cells and the degradation degrees of the non-target cells; and a cell-list updater configured to update the list of the diagnosis target cells based on the temperature distribution. | 2013-05-09 |
| 20130113493 | PROTECTIVE SEMICONDUCTOR APPARATUS FOR AN ASSEMBLED BATTERY, A BATTERY PACK INCLUDING THE PROTECTIVE SEMICONDUCTOR APPARATUS, AND AN ELECTRONIC DEVICE - A protective semiconductor apparatus for protecting an assembled battery including N secondary cells connected in series includes a disconnection detecting circuit including, for each of the N secondary cells, a voltage-sensing resistor dividing a voltage of a corresponding one of the secondary cells, a reference voltage, and a first comparator comparing a voltage obtained by the voltage-sensing resistor with the reference voltage. The protection semiconductor apparatus also includes a circuit connecting an internal resistor having a resistance value smaller than a resistance value of a corresponding one of the voltage-sensing resistors in parallel to the corresponding voltage-sensing resistors successively and selectively at predetermined time intervals. The disconnection detecting circuit detects disconnection between the N secondary cells and the protective semiconductor apparatus based on an output from the first comparator when the internal resistor is connected in parallel to the corresponding voltage-sensing resistor. | 2013-05-09 |
| 20130113494 | CHUCK MECHANISM OF CHARGE-DISCHARGE TEST DEVICE FOR THIN SECONDARY BATTERY - The present invention relates to a chuck mechanism of a charge-discharge test device for a thin secondary battery, and aims to provide a chuck mechanism having excellent action controllability. The chuck mechanism includes: a chuck drive part which is movable in a direction toward a battery container housing a thin secondary battery; and a chuck activation part which is located away from the chuck drive part in the direction toward the battery container and whose movement in the same direction is restricted. In the chuck mechanism, when the chuck unit is moved in the direction toward the battery container, the chuck drive part activates a chuck member of the chuck activation part whose movement in the same direction is restricted. | 2013-05-09 |
| 20130113495 | Fail-Safe Designs for Large Capacity Battery Systems - Fail-safe systems and design methodologies for large capacity battery systems are disclosed. The disclosed systems and methodologies serve to locate a faulty cell in a large capacity battery, such as a cell having an internal short circuit, determine whether the fault is evolving, and electrically isolate the faulty cell from the rest of the battery, preventing further electrical energy from feeding into the fault. | 2013-05-09 |
| 20130113496 | Testing Electrical Connections Between Cardiac Resuscitation Devices and External Electrodes - Testing integrity of electrical connections between cardiac resuscitation devices and electrodes connected thereto while the electrodes remain stored within a sealed package. Each electrode comprises a skin-contacting gel layer, a current-spreading layer, and an adhesive layer for adhering the electrode to the patient. An electrical lead for delivering a therapy pulse extends from the current-spreading layer of each electrode to the exterior of the package. A jumper element located within the package and connected to the current-spreading layer of each electrode provides a self-test electrical connection between the first and second electrical leads while the electrodes are adhered to a substrate within the package to permit testing the integrity of the electrical connection between the electrodes and cardiac resuscitation device prior to use of the electrodes. The jumper is configured so that the self-test electrical connection is broken when the user removes the electrodes from the substrate. | 2013-05-09 |
| 20130113497 | FAULT POSITION ANALYSIS METHOD AND FAULT POSITION ANALYSIS DEVICE FOR SEMICONDUCTOR DEVICE - A fault position analysis method and a fault position analysis device for a semiconductor device, through which a fault position of a SiC semiconductor device can be analyzed and specified by an OBI RCH method, are disclosed. The fault position analysis method for the semiconductor device scans and irradiates a device and a circuit on a front surface of a substrate with a laser beam from a rear surface side of the substrate of the semiconductor device to heat the device and the circuit. It causes a current to flow to the device and the circuit while being heated, detects a change in a resistance value caused by a change in a current, and analyzes the fault position. The semiconductor device is a semiconductor device which uses an N-doped SiC substrate. Laser beams having wavelengths of 650 to 810 nm are used. | 2013-05-09 |
| 20130113498 | TEST DEVICE WITH UNINTERRUPTIBLE POWER SUPPLY - A test device with uninterruptible power supply supplies external power to a product under test (PUT) and performing electric power tests thereon. The PUT has a processing unit, a power input end, a battery connection end, and a charging and discharging circuit. The device includes a first test port, a second test port, and a power-storing unit. The PUT is electrically connected to the first and second test ports to receive the external power through the first test port and be switchable to the second test port to selectively receive power from the power-storing unit, thereby preventing interruption of operation of the PUT. A charging voltage from the charging and discharging circuit is applied to the power-storing unit via the second test port to charge the power-storing unit. An operation-required power level of the PUT can be maintained, even if the test device receives no power. | 2013-05-09 |
| 20130113499 | METHOD AND APPARATUS FOR DETERMINING PLANAR IMPEDANCE TOMOGRAPHY - A method and apparatus for determining planar impedance tomography of a sample comprising a measurement head unit comprising an impedance sensor; a three-axis actuator assembly, coupled to the measurement head unit, for positioning the impedance sensor relative to a sample; a controller, coupled to the three-axis actuator assembly, for controlling the three-axis actuator assembly to position the impedance sensor at a plurality of locations relative to the sample; and an impedance analyzer, coupled to the impedance sensor, for determining an impedance value at each location in the plurality of locations. | 2013-05-09 |
| 20130113500 | FILL-LEVEL MEASURING DEVICE FOR ASCERTAINING AND MONITORING FILL LEVEL OF A MEDIUM LOCATED IN THE PROCESS SPACE OF A CONTAINER BY MEANS OF A MICROWAVE TRAVEL TIME MEASURING METHOD - A fill-level measuring device for ascertaining and monitoring fill level of a medium located in the process space of a container by means of a microwave travel time measuring method. The device comprises a measurement transmitter and an antenna unit, which is constructed at least of a hollow conductor and a radiating element A microwave transmissive, process isolating element is inserted for process isolation into the hollow conductor between the measurement transmitter and the horn shaped radiating element contacting the process space. The process isolating element is embodied as a hollow body having at least one tubular hollow body region matched to the shape of the hollow conductor, and a pointed hollow body region neighboring the hollow body region in the direction of the radiating element and having a wall thickness selected based on reflection, or lack thereof, of the microwave signals, | 2013-05-09 |
| 20130113501 | DOUBLE PISTON ROD - A distance measuring apparatus for detecting the position of a reflection body in a line structure is provided that includes a sensor device, which has at least one antenna for feeding a transmission signal as an electromagnetic wave into the line structure and for receiving the electromagnetic wave reflected on the reflection body. The sensor device also includes evaluation electronics which are configured to determine the position of the reflection body from the phase difference between the transmitted and the received wave. | 2013-05-09 |
| 20130113502 | Randomizing One or More Micro-Features of a Touch Sensor - In one embodiment, an apparatus includes a touch sensor with one or more meshes of conductive material. Each of the meshes includes multiple mesh cells defined by multiple mesh segments. Each of the mesh cells includes a centroid and multiple vertices. The mesh segments are made of the conductive material, and the centroids or vertices of the mesh cells have a substantially random distribution within an area of the touch sensor. The apparatus also includes one or more computer-readable non-transitory storage media coupled to the touch sensor that embody logic that is configured when executed to control the touch sensor. | 2013-05-09 |
| 20130113503 | METHOD AND DEVICE FOR MEASURING THE LOCATION OF A PARTICLE BEAM PRESENT IN PACKETS IN A LINEAR ACCELERATOR - The invention relates to a method and device for measuring the location of a particle beam ( | 2013-05-09 |
| 20130113504 | VEHICLE DOOR HANDLE APPARATUS - A vehicle door handle apparatus is provided with a handle main body formed by coupling a first cover and a second cover and a capacitance sensor accommodated in a hollow space in the handle main body. One of the first cover and the second cover is formed with an accommodation recess defined by partition walls. The capacitance sensor is accommodated in the accommodation recess and fixed by a potting agent. | 2013-05-09 |
| 20130113505 | SENSOR FOR DETECTING LIQUID SPILLING - Present invention concerns generally to a sensor or a sensor system for detecting spilling of aqueous liquids, for instance in confined spaces were such is critical such in an airplane. The system of present invention is an early warning system or sentinel for the prevention of corrosion by corrosive liquids. Corrosion caused by corrosive liquids can rapidly change the surface properties of components in engineering structures, and that will finally endanger the functionality of structural parts. However, if monitoring technologies are in place providing continuous information on the presence of corrosive liquids, corrosion treatment and even corrosion prevention can start at a very early stage. Present invention provides such by early detection of corrosive liquids by extended sensors based on the collapse of percolation conductivity (COPC). The term collapse refers to the fact that the transition into the non-conducting state must not necessarily have the properties of a thermodynamically well-defined transition. | 2013-05-09 |
| 20130113506 | SYSTEM AND METHOD FOR SENSING HUMAN ACTIVITY BY MONITORING IMPEDANCE - A system for sensing human activity by monitoring impedance includes a signal generator for generating an alternating current (AC) signal, the AC signal applied to an object, a reactance altering element coupled to the AC signal, an envelope generator for converting a returned AC signal to a time-varying direct current (DC) signal, and an analog-to-digital converter for determining a defined impedance parameter of the time-varying DC signal, where the defined impedance parameter defines an electromagnetic resonant attribute of the object. | 2013-05-09 |
| 20130113507 | VOLTAGE MEASUREMENT - The present invention relates to voltage measurement apparatus. The voltage measurement apparatus comprises a potential attenuator configured to be electrically connected between first and second conductors, which are electrically coupled to a source. The potential attenuator comprises a first impedance and a reference impedance arrangement in series with each other. The reference impedance arrangement has an electrical characteristic which is changed in a known fashion. The voltage measurement apparatus further comprises a processing arrangement configured: to acquire at least one signal from the reference impedance arrangement, the at least one signal reflecting change of the electrical characteristic in the known fashion; and to determine a voltage between the first and second conductors in dependence on the fashion in which the electrical characteristic is changed being known and the at least one signal. | 2013-05-09 |
| 20130113508 | ELECTRONIC TEST SYSTEM AND ASSOCIATED METHOD - Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal. | 2013-05-09 |
| 20130113509 | Temperature Control System for IC Tester - A temperature control system for IC tester, comprising: a test socket; a compressing device including a heat exchanger and a thermoelectric cooler (TEC); and a test head having a temperature sensor. The test head is configured at the front end of the compressing device such that, upon placing at least one device under test (DUT) onto the test socket, the test head coerces tightly one of the DUTs through downward pressure from the compressing device thereby allowing the temperature sensor to detect the surface temperature of the DUT to obtain a temperature signal, and then feed such a temperature signal back to a control processing unit for operations to generate a linear control signal thus that, through the control of the linear control signal, the heat absorption and heat discharge functions of the TEC are enabled to further control the temperature of the DUT within a determined range. | 2013-05-09 |
| 20130113510 | SYSTEM AND METHOD FOR MODULATION MAPPING - An apparatus for providing modulation mapping is disclosed. The apparatus includes a laser source, a motion mechanism providing relative motion between the laser beam and the DUT, signal collection mechanism, which include a photodetector and appropriate electronics for collecting modulated laser light reflected from the DUT, and a display mechanism for displaying a spatial modulation map which consists of the collected modulated laser light over a selected time period and a selected area of the IC. | 2013-05-09 |
| 20130113511 | DC-AC PROBE CARD TOPOLOGY - A DC-AC probe card for testing a DUT includes: a plurality of probe needles, each probe needle having a distal end for contacting said DUT; and a plurality of connection pathways operable to connect test instrumentation to the probe needles, wherein each connection pathway provides both a desired characteristic impedance for AC measurements and a guarded pathway for DC measurements between respective test instrument connections and probe needles. | 2013-05-09 |
| 20130113512 | PROBE BLOCK, PROBE CARD AND PROBE APPARATUS BOTH HAVING THE PROBE BLOCK - The present invention provides a probe block, which comprises 1) a conductive base on which a first groove is formed, 2) a pair of signal transmitting probes which have dielectric covers and are placed parallel to each other in the first groove, and 3) a ground probe which is in contact with the conductive base, wherein front portions of the signal transmitting probes and the ground probe protrude from the conductive base to form signal transmitting probe needles and a ground probe needle, respectively. The probe block of the present invention has excellent high frequency responses characteristics and is easy for maintenance. | 2013-05-09 |
| 20130113513 | TEST APPARATUS OF SEMICONDUCTOR PACKAGE AND METHODS OF TESTING THE SEMICONDUCTOR PACKAGE USING THE SAME - A semiconductor package testing apparatus and testing a semiconductor package, the apparatus including a test circuit substrate that electrically tests a semiconductor package having connection terminals; a socket electrically connecting the test circuit substrate with the semiconductor package; a socket guide having an open region delimiting the socket; an insert that fixes the semiconductor package and positions the semiconductor package in the open region of the socket guide; a pusher that presses the semiconductor package to make contact between the socket and the semiconductor package; and an alignment part that aligns the semiconductor package with the open region, wherein the alignment part is configured to selectively apply a magnetic force to align keys of the semiconductor package, the align keys being formed of a magnetic material. | 2013-05-09 |
| 20130113514 | SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL - A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data. | 2013-05-09 |
| 20130113516 | TERMINATION CIRCUIT AND DC BALANCE METHOD THEREOF - A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers. | 2013-05-09 |
| 20130113517 | IMPEDANCE CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An impedance control circuit includes a pull-up code generator configured to generate pull-up impedance control codes using a voltage of a first node, a pull-up impedance unit configured to pull-up-drive the first node in response to the pull-up impedance control codes, a plurality of dummy impedance units enabled in response to respective select signals and each configured to pull-up-drive a second node in response to the pull-up impedance control codes, a pull-down code generator configured to generate pull-down impedance control codes using a voltage of the second node, and a plurality of pull-down impedance units enabled in response to the respective select signals and each configured to pull-down-drive the second node in response to the pull-down impedance control codes. | 2013-05-09 |
| 20130113518 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 2013-05-09 |
| 20130113519 | ASYNCHRONOUS DIGITAL CIRCUITS INCLUDING ARBITRATION AND ROUTING PRIMATIVES FOR ASYNCHRONOUS AND MIXED-TIMING NETWORKS - Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data. | 2013-05-09 |
| 20130113520 | METHOD AND APPARATUS FOR IMPROVED MULTIPLEXING USING TRI-STATE INVERTER - A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively. | 2013-05-09 |
| 20130113521 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a main driving unit configured to receive an output data and to drive the received data to a data output pad; a pre-emphasis data generation unit configured to compare a delayed data obtained by delaying the output data by one data period with the output data, to delay the comparison result by one data period, and to output the delayed data as pre-emphasis data; and a pre-emphasis driving unit configured to receive the pre-emphasis data and to drive the received data to the data output pad. | 2013-05-09 |
| 20130113522 | ASYNCHRONOUS-LOGIC CIRCUIT FOR FULL DYNAMIC VOLTAGE CONTROL - Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation. | 2013-05-09 |
| 20130113523 | SEMICONDUCTOR DEVICE - A semiconductor device includes a main driving unit configured to serialize first and second data applied in parallel and output the serialized data to a data output pad, and an auxiliary driving unit configured to drive the data output pad in a period when the first and second data have different logic levels. | 2013-05-09 |
| 20130113524 | FLEXIBLE LOW POWER SLEW-RATE CONTROLLED OUTPUT BUFFER - An output buffer includes a pullup driver, a pulldown driver, and an output stage. The pullup driver has a drive control input, and an output for providing a pullup drive signal in a push-pull mode in response to receiving a first drive control signal on the drive control input, and in a current limited mode in response to receiving a second drive control signal on said drive control input. The pulldown driver has a drive control input, and an output for providing a pulldown drive signal in the push-pull mode in response to receiving a third drive control signal on the drive control input, and in the current limited mode in response to receiving a fourth drive control signal on the drive control input. The output stage provides a voltage on an output terminal in response to the pullup and pulldown drive signals. | 2013-05-09 |
| 20130113525 | SEMICONDUCTOR DEVICE AND OPERATION MODE SWITCH METHOD - A semiconductor device includes a first internal terminal, a first transistor, a second transistor, an oscillator including an output terminal to output a clock signal, and a comparator coupled to a first internal terminal, and that compares a potential of the first internal terminal when the first internal terminal is coupled to the first reference potential with a potential of the first internal terminal when the first internal terminal is coupled to a second reference potential, an external terminal being connectable to the first internal terminal, and a second internal terminal being coupled to the external terminal, and that receives an input signal through the external terminal. Each of the first control terminal and the second control terminal is coupled to the output terminal to commonly receive the clock signal. The first transistor and the second transistor exclusively operate according to the clock signal. | 2013-05-09 |
| 20130113526 | CONTROL SIGNAL GENERATION CIRCUIT, CHARGE PUMP DRIVE CIRCUIT, CLOCK DRIVER, AND DRIVE METHOD OF CHARGE PUMP - A control signal generation circuit which generates a control signal for controlling a gate of an MOS transistor, comprises a first switching part connected to a current source and the gate and controlled based on an input signal; and a second switching part connected to the current source and the gate and controlled based on an input signal and control signal, wherein a voltage value of the control signal changes based on the input signal, and a slant of the voltage value with respect to time is switched to become smaller after the voltage value exceeds a threshold voltage of the MOS transistor compared with when the voltage value equals to or less than the threshold voltage of the MOS transistor. | 2013-05-09 |
| 20130113527 | CLOCK CIRCUIT FOR PROVIDING AN ELECTRONIC DEVICE WITH A CLOCK SIGNAL, ELECTRONIC DEVICE WITH A CLOCK CIRCUIT AND METHOD FOR PROVIDING AN ELECTRONIC DEVICE WITH A CLOCK SIGNAL - This invention relates to a clock circuit for providing an electronic device with a clock signal having an adjustable clock frequency. The clock circuit is adapted to receive information regarding a context level of the electronic device and to dynamically control the clock frequency of the clock signal according to the context level. The dynamical control of the clock circuit output frequency based on the context level enables automated power-to-performance control of the electronic device. The invention also relates to an electronic device comprising a context setting unit adapted to set a context level in which the electronic device is operated and a clock circuit. Furthermore, it relates to a method of providing an electronic device with a clock signal having an adjustable clock frequency, wherein a clock circuit receives information regarding a context level of the electronic device; and wherein the clock circuit dynamically controls the clock frequency of the clock signal according to the context level. | 2013-05-09 |
| 20130113528 | Digital Phase-Locked Loop with Wide Capture Range, Low Phase Noise, and Reduced Spurs - The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancelation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancelation technique to reduce phase noise introduced by the MMD. | 2013-05-09 |
| 20130113529 | Signal Generator - A signal generator for coupling to a concealed conductor including a first oscillator configured to generate a first waveform having a first frequency, a first terminal coupled to the first oscillator through a first band pass filter configured to pass signals of the first frequency, a second oscillator configured to generate a second waveform having a second frequency, and a second terminal coupled to the second oscillator through a second band pass filter configured to pass signals of the second frequency. | 2013-05-09 |
| 20130113530 | Oscillator Based Frequency Locked Loop - A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator. | 2013-05-09 |
| 20130113531 | ELECTRONIC CIRCUIT, SAFETY CRITICAL SYSTEM, AND METHOD FOR PROVIDING A RESET SIGNAL - An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available. | 2013-05-09 |
| 20130113532 | PROCESSING SYSTEM AND POWER CONTROL DEVICE THEREOF - A power control device is provided. The power control device includes a power supply unit, a reset unit, and a power control unit. The power supply unit determines whether a supplied voltage from an external voltage supply source is being provided to the power supply unit to generate a determination signal. The power supply unit further generates an operation voltage and a standby voltage according to the supplied voltage. The reset unit receives the determination signal and the standby voltage and generates a reset signal according to the determination signal and the standby voltage to activate a reset operation. The power control unit receives the reset signal and generates a power enabling signal according to the reset signal. The power supply unit outputs the operation voltage or does not according to the power enabling signal. | 2013-05-09 |
| 20130113533 | TEMPERATURE COMPENSATED FREQUENCY REFERENCE COMPRISING TWO MEMS OSCILLATORS - A temperature compensated frequency reference comprising first MEMS oscillator (MEMS | 2013-05-09 |
| 20130113534 | CLOCK DATA RECOVERY CIRCUIT AND TRANSCEIVER SEMICONDUCTOR INTEGRATED CIRCUIT CONTAINING THE SAME - A clock data recovery circuit which has a high degree of jitter tolerance and can alleviate increase in the phase number of a multi-phase clock, power consumption, and a semiconductor chip area is provided. Each circuit of plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit. The first detection circuit detects that a data edge leads in phase more than −1 phase from an edge detection phase, the second detection circuit detects that the data edge laggs in phase more than +1 phase from the edge detection phase. In response to the first output signal or the second output signal, the edge detection phase is changed by the amount of −1 phase or +1 phase. When the data edge is detected in the range of ±1 phase, a next edge detection phase is maintained in the current state. | 2013-05-09 |
| 20130113535 | Apparatus and Method for Fast Phase Locked Loop (PLL) Settling for Cellular Time-Division Duplex (TDD) Communications Systems - A communications device is disclosed that adjusts a target signal to allow a reference phase locked loop (PLL) to lock onto a reference signal that is related to a desired operating frequency in a first mode of operation. The reference PLL locks onto the reference signal when the target signal is calibrated to be proportional to the reference signal. As the communications device transitions between the first mode of operation and a second mode of operation, the communications device performs a shorten calibration cycle on the reference PLL. The reference phase locked loop (PLL) locks onto the reference signal in response to the shorten calibration cycle in the second mode of operation. | 2013-05-09 |
| 20130113536 | FRACTIONAL-N PHASE LOCKED LOOP BASED ON BANG-BANG DETECTOR - The present disclosure is directed to a fractional-N digital phase locked loop (DPLL) that replaces the conventionally used time-to-digital converter (TDC) based phase detector with a bang-bang phase detector (BBPD). Compared to the TDC based phase detector, the BBPD has an often superior resolution for the same or similar amount of power and/or area consumption. Therefore, replacing the TDC based phase detector with a BBPD can reduce, or even eliminate, the common problem of spurs being added to the output signal generated by the DPLL because of the limited resolution of the TDC based phase detector. This can allow the DPLL to be used for the most demanding applications, such as in generating local oscillator signals for down-converting and demodulating weak signals received by a communication device, such as a cellular phone. | 2013-05-09 |
| 20130113537 | PULSE GENERATOR - A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal. | 2013-05-09 |
| 20130113538 | DISCRETE SIGNAL CONSOLIDATION DEVICE AND METHOD AND AIRCRAFT WITH SAID DEVICE - A device and a method for eliminating transitions in discrete signals. The working of the device and method is based on allowing the charge of a capacitor with one state when the state opposite the state to which it has been assigned is produced and allowing their discharge through a corresponding capacitor when their state is active. The signal is advantageously consolidated without needing processors or programmes, is very simple, there is increased reliability, and the device can very easily be integrated in any sensor, such as those used in aircraft. | 2013-05-09 |
| 20130113539 | CLOCK CIRCUIT FOR A MICROPROCESSOR - A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output. | 2013-05-09 |
| 20130113540 | ELECTRONIC DEVICE AND METHOD FOR PROVIDING A DIGITAL SIGNAL AT A LEVEL SHIFTER OUTPUT - An electronic device comprising a level shifter and a method. The level shifter includes an input adapted to receive an input signal switching between a low input voltage level and a high input voltage level and a first switch and a second switch coupled in series between a low output voltage supply and a high output voltage supply. An output is coupled to an interconnection node between the first and the second switch and is adapted to be coupled to a load. The first and second switches are controlled by the input signal. The level shifter further includes a third switch which is coupled between the interconnection node and an auxiliary voltage supply which has a voltage level between the low output voltage level and the high output voltage level. | 2013-05-09 |
| 20130113541 | LOW POWER LEVEL SHIFTER WITH OUTPUT SWING CONTROL - A level shifter comprising a first driver transistor receiving an input signal. A gate-controlled transistor coupled to the first driver transistor. A second driver transistor coupled to the gate controlled transistor. An output coupled to the second driver transistor, wherein the gate-controlled transistor is for receiving a predetermined gate voltage when the output voltage exceeds a predetermined value. | 2013-05-09 |
| 20130113542 | OUTPUT BUFFER, OPERATING METHOD THEREOF AND DEVICES INCLUDING THE SAME - A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals. | 2013-05-09 |
| 20130113543 | MULTIPLICATION DYNAMIC RANGE INCREASE BY ON THE FLY DATA SCALING - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) receive two input signals. Each input signal generally carries a respective data value. Each data value may have a respective sign bit and a respective at least one guard bit. The first circuit may also be configured to (ii) scale each data value independently such that all of the respective guard bits have a same value as the respective sign bit and (iii) generate a product value in an output signal by adjusting an intermediate value based on the scaling of the data values. The second circuit may be configured to generate the intermediate value by multiplying the two data values as scaled. | 2013-05-09 |
| 20130113544 | PROXIMITY SWITCH HAVING WRONG TOUCH FEEDBACK - A proximity switch assembly and method are provided having wrong touch feedback. The switch includes a plurality of proximity switches each including proximity sensors providing a sense activation field. Control circuitry processes the activation field of each proximity switch to sense activation, detects an allowed activation of one of the proximity switches and further detects an attempted activation that is not allowed. The switch further includes an output coupled to a device to perform a function when an allowed activation is detected. The switch includes one or more user perceived feedback devices for generating user perceived feedback when an attempted activation that is not allowed is detected. | 2013-05-09 |
| 20130113545 | METHOD FOR CONTROLLING THE SUPPLY VOLTAGE FOR AN INTEGRATED CIRCUIT AND AN APPARATUS WITH A VOLTAGE REGULATION MODULE AND AN INTEGRATED CIRCUIT - The present invention relates to a method for controlling the supply voltage for an integrated circuit, which is connected to a voltage regulation module via a sense line, a voltage supply line and a bus wherein the supply voltage is provided by the voltage regulation module ( | 2013-05-09 |
| 20130113546 | Master-slave low-noise charge pump circuit and method - Charge pump circuitry ( | 2013-05-09 |
| 20130113547 | Method and apparatus for floating or applying voltage to a well of an integrated circuit - In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well. | 2013-05-09 |
| 20130113548 | METHODS AND CIRCUITS FOR GENERATING REFERENCE VOLTAGE - A circuit for generating a reference voltage includes a first reference voltage generating circuit disposed outside a chip and a second reference voltage generating circuit disposed inside the chip. The first and second reference voltage generating circuits output first and second reference voltages to first and second output terminals, respectively. The second reference voltage generating circuit includes at least one pull-up resistor and at least one pull-down resistor. The pull-up resistor is coupled between a first node where an internal power supply voltage is coupled and the second output terminal. The pull-down resistor is coupled between a second node and the second output terminal, wherein a voltage at the second node is relatively lower than a voltage at the first node. A third reference voltage is outputted from a node where the first output terminal is coupled to the second output terminal. | 2013-05-09 |
| 20130113549 | Variable Capacitor Circuit and Method - A variable capacitor circuit is disclosed. The variable capacitor circuit includes a plurality of MOS capacitors, each MOS capacitor being implemented by a MOS transistor with the gate terminal connected to a first voltage signal and with the drain terminal shorted with the source terminal and connected to a second voltage signal, said MOS capacitors being connected in parallel through the gate terminal connected to the first voltage signal, and being operated in a cut-off region in which the equivalent capacitance of each MOS capacitor remains substantially constant for variations of the first voltage signal. | 2013-05-09 |
| 20130113550 | SWITCHED-CAPACITOR FILTER - A filter is implemented as cascaded stages, and in at least one stage all resistances are implemented as double-sampled switched-capacitor circuits. In a variation, at least one resistance is implemented as a double-sampled switched-capacitor T-network. In a variation, in an integrator stage, a resistance is implemented as a transconductance, and the cutoff frequency of the integrator stage scales with a switching frequency of a DC-DC voltage converter. | 2013-05-09 |
| 20130113551 | ENVELOPE DETECTOR - The envelope detector for detecting an envelope of a digital modulation signal in accordance with an embodiment of the present invention, includes: a mixer configured to receive the digital modulation signal and output a square signal squaring the digital modulation signal when being applied with bias voltage; a bias voltage applying unit configured to apply the bias voltage to the mixer; and a DC blocking capacitor configured to be connected to the mixer to block DC component included in the square signal. In accordance with the embodiment of the present invention, it is possible to provide the envelope detector having the simple structure while having the good receiving sensitivity and the wide dynamic range characteristics and detect the envelope of the modulated signal without transmitting the carrier signal in the transmitter and generating the separate signal in the receiver, thereby saving the costs consumed to implement the transceiver. | 2013-05-09 |
| 20130113552 | OFFSET COMPENSATION FOR SENSE AMPLIFIERS - A method of re-offsetting a plurality of amplifier is provided. The method includes testing the plurality of amplifiers based on a re-offset value at bulks of compensation transistors of the plurality of amplifiers; identifying a first group of first amplifiers of the plurality of amplifiers favoring reading a first logic level and/or a second group of second amplifiers of the plurality of amplifiers favoring reading a second logic level different from the first logic level, based on results of the testing step; changing the re-offset value to a new re-offset value; re-offsetting the first group of first amplifiers and/or the second group of second amplifiers based on the new re-offset value; and re-testing the first group of first amplifiers and the second group of second amplifiers. | 2013-05-09 |
| 20130113553 | Chopper - A chopper comprises a differential difference amplifier, a first switch, and a second switch. The differential difference amplifier comprises a first input stage and a second input stage. The first input stage comprises a non-inverting input terminal and an inverting input terminal. The second input stage comprises a non-inverting input terminal and an inverting input terminal. The first switch is operable to receive a first input voltage and a second input voltage and selectively transfer the first input voltage to one of the non-inverting input terminal of the first input stage and the non-inverting input terminal of the second input stage. The second switch is operable to receive a third input voltage and a fourth input voltage and selectively transfer the third input voltage to one of the inverting input terminal of the first input stage and the inverting input terminal of the second input stage. | 2013-05-09 |
| 20130113554 | SIGNAL SPLITTING APPARATUS SUITABLE FOR USE IN A POWER AMPLIFIER - Disclosed is a signal splitting apparatus useable in a power amplifier having two or more power amplifiers. The apparatus includes a direct gain component; and a derived gain component connected to the direct gain component. The derived gain component derives the derived gain from the direct gain by imposing a constraint which is valid over the entire dynamic range of the input signal, e.g. the sum of the power of the direct split signal and the derived split signal are constrained to be substantially equal to the power of the input signal. The use of combining additional direct gain and derived gain components, as well as a delay element, are disclosed so as to enable n-component splitting that for adaptation to different applications by the use of suitable coefficients. | 2013-05-09 |
| 20130113555 | POWER AMPLIFIER WITH IMPROVED POWER EFFICIENCY - Provided is a power amplifier used in a transmitter of a communication system. The power amplifier may include a power amplifier module to amplify power of a transmitting signal, an energy converter module to receive thermal energy generated by the power amplifier module and to convert the received thermal energy into electric energy, and a direct current (DC)-DC converter module to produce DC power using the electric energy generated by the energy converter module and to supply the produced DC power to the power amplifier module. | 2013-05-09 |
| 20130113556 | VOLTAGE, CURRENT, AND SATURATION PREVENTION - In one embodiment, saturation of the control system of a power amplifier is limited by comparing a control voltage at a first control node against a scaled battery voltage, and then drawing an error current away from the first control node when the control voltage exceeds the scaled battery voltage. The first control node may be located after a trans-conductance amplifier in a feedback control system. | 2013-05-09 |
| 20130113557 | AMPLIFYING DEVICE - An efficient amplifying device is achieved. An amplifying device that amplifies a signal subject to amplification is configured as follows. That is, an amplifier (PA | 2013-05-09 |
| 20130113558 | AMPLIFIER THERMAL MANAGEMENT - A thermally regulated amplifier system includes an amplifier unit, a temperature-sensing unit and a controller. The amplifier unit includes a power amplifier that has an adjustable gain function. The controller receives temperature readings from the temperature-sensing unit, computes the gain G(n) of the amplifier unit, and provides the computed gain of the amplifier G(n) to the power amplifier unit. | 2013-05-09 |
| 20130113559 | DEVICE AND METHOD FOR PRE-DISTORTING AND AMPLIFYING A SIGNAL BASED ON AN ERROR ATTRIBUTE - A method and a device may be provided. The device may include a non-linear amplifying circuit arranged to apply a non-linear gain function on an analog signal to provide an amplified signal; an input circuit, arranged to clip I channel and Q channel digital input signals supplied from a digital transmitter, to provide clipped I-channel and Q-channel digital signals; a pre-distortion circuit, arranged to pre distort the clipped I channel and Q channel digital signals such as to at least partially compensate for a non linearity of the non linear gain function, to provide pre-distorted I-channel and Q-channel digital signals; a mixed signal circuit for converting the pre-distorted I-channel and Q-channel digital signals to the analog signal; a reconstruction circuit, arranged to receive at least a portion of the amplified signal and to generate reconstructed I-channel and Q-channel signals; and a control circuit, arranged to: calculate an error attribute based on (a) the clipped I-channel and Q-channel digital signals, and (b) the reconstructed digital I-channel and Q-channel signals; and to affect at least one operational parameter of the non-linear amplifying circuit in response to the error attribute. | 2013-05-09 |
| 20130113560 | POWER AMPLIFYING CIRCUIT AND HIGH-FREQUENCY MODULE - A high-frequency module including a power amplifying circuit includes a high-frequency power amplifying element, a matching circuit, and a driving power-supply circuit. The high-frequency power amplifying element includes a high-frequency amplifying circuit and a directional coupler. A first end of a main line of the directional coupler is connected to an output terminal of a latter-stage amplifying circuit of the high-frequency amplifying circuit. A second end of the main line of the directional coupler is connected through an output matching circuit to a high-frequency signal output terminal of the high-frequency power amplifying element. The output terminal of the latter-stage amplifying circuit is also connected to a second driving power-supply voltage application terminal of the high-frequency power amplifying element. The second driving power-supply voltage application terminal is connected to the high-frequency signal output terminal by a connecting conductor. | 2013-05-09 |
| 20130113561 | OUTPUT MODE SWITCHING AMPLIFIER - An output mode switching amplifier, including: a transistor for signal amplification connected between a first node on an input side and a second node on an output side; a bypass path for bypassing the transistor between the first node and the second node; a voltage control circuit for switching whether to apply a bias voltage to the transistor so that a transmission signal is amplified by the transistor or to output a transmission signal via the bypass path without amplifying the transmission signal by the transistor; and a second-harmonic reflection circuit connected to the bypass path, for reflecting a second harmonic of the transmission signal. | 2013-05-09 |
| 20130113562 | CURRENT REUSE ELECTRONIC DEVICE BASED ON MAGNETIC COUPLING COMPONENTS - A current reuse device including a first stage provided with a first input for a first input signal and a first output for a first output signal; a second stage comprising a second input for a second input signal and a direct current terminal operating as a ground terminal for alternate signals; a first inductor connected to a first output and to the direct current terminal so that the first and second stages share a direct current; a second inductor reciprocally coupled to the first inductor and connected to the second input in order to generate the second input signal as a function of the first output signal. | 2013-05-09 |
| 20130113563 | GAIN ENHANCEMENT FOR CASCODE STRUCTURE - Aspects of the present invention provide apparatuses and methods to provide significant gain enhancement for a cascode structure for a differential amplifier. The cascode structure of the differential amplifier can include first and second pairs of output transistors. The second pair of output transistors can be configured to approximately cancel modulation effects of the first pair of output transistors induced by changes in a differential output of differential amplifier, thereby resulting in conditions for providing enhanced gain. | 2013-05-09 |
| 20130113564 | FAST SETTLING LOW POWER LOW NOISE AMPLIFIER - Aspects of the present invention provide apparatuses and methods to provide slew rate enhancement during an initial stage of operation of an amplifier and processing of an input signal with low noise introduction during a subsequent amplification stage of operation. During the initial stage, a high bandwidth component of the amplifier can be engaged to provide slew rate enhancement of the overall amplifier. The adaptive slew rate enhancement can be based on a detected imbalance of an output of a low bandwidth component of the amplifier. Once a desired operating state of the amplifier is achieved, the high bandwidth component can be disengaged. The low bandwidth component can then solely operate on a received input signal during the amplification stage. The low bandwidth component can be low power and can introduce low levels of noise, thereby ensuring minimal noise introduction and corruption of the amplified output signal of the amplifier. | 2013-05-09 |
| 20130113565 | LINEAR DIFFERENTIAL AMPLIFIER WITH HIGH INPUT IMPEDANCE - A differential amplifier provides an amplifier circuit including two differential pairs. A first differential pair is connected in series to a second differential pair. The second differential pair is connected in a crosswise manner at least indirectly to a differential output signal of the first differential pair. The first differential pair and the second differential pair form a first differential current path and a second differential current path. A first emulation device is connected in parallel to the first current path. A second emulation device is connected in parallel to the second current path. | 2013-05-09 |
| 20130113566 | VARIABLE GAIN AMPLIFIER - An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage). | 2013-05-09 |
| 20130113567 | SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECEPTION APPARATUS AND RADIO COMMUNICATION TERMINAL INCLUDING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a first capacitance element and a second capacitance element; a first amplification circuit that amplifies a potential difference of a first voltage signal and a second voltage signal supplied via the first capacitance element and the second capacitance element, respectively, to output a first amplification signal and a second amplification signal; a first resistance element that feeds back the first amplification signal to one input terminal of the first amplification circuit; a second resistance element that feeds back the second amplification signal to another input terminal of the first amplification circuit; a voltage generator that generates a predetermined voltage; and a third resistance element that transmits the predetermined voltage generated by the voltage generator to each input terminal of the first amplification circuit. | 2013-05-09 |
| 20130113568 | PUSH-PULL LOW-NOISE AMPLIFIER WITH AREA-EFFICIENT IMPLEMENTATION - An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric. | 2013-05-09 |
| 20130113569 | CROSS-COUPLED MULTIPATH FEEDFORWARD OPERATIONAL AMPLIFIERS - An operational amplifier can include a plurality of amplifiers connected to form a plurality of amplification paths extending from an input terminal to an output terminal of the operational amplifier. An amplifier in one of the amplification paths can include an intrinsic amplification-transistor capacitance connected between a first amplifier input and a first amplifier output, and a cross-coupling capacitor connected between the first amplifier input and a second amplifier output. A plurality of the amplification paths can include series-connected amplifiers connected in parallel with the cross-coupled amplifier. The cross-coupling capacitor can have a capacitance value selected as a function of the intrinsic capacitance and a gain experienced between the amplifier inputs and outputs. The operational amplifier can include an AC coupling capacitor connected in series with the cross-coupled amplifier. The operational amplifier can be arranged in feedback configuration. | 2013-05-09 |
| 20130113570 | Method and Device for Controlling Power Amplification - A method and network equipment for controlling power amplification are disclosed. The method for controlling power amplification includes outputting a voltage signal according to the state of an NE. The voltage signal is applied to a grid electrode or a base electrode of at least one power amplifier transistor in a power amplifier. | 2013-05-09 |
| 20130113571 | ANTENNA LNA FILTER FOR GNSS DEVICES - A low-noise amplifier (LNA) filter for use with global navigation satellite system (GNSS) devices is disclosed. A first LNA stage, which is configured to connect to an antenna configured to receive GNSS signals, includes an LNA. A second LNA stage, which is connected to the output of the first LNA stage, has a surface acoustic wave (SAW) filter and an LNA. A third LNA stage, which is connected to the output of the second LNA stage, also has a SAW filter and an LNA. | 2013-05-09 |
