| 19th week of 2013 patent applcation highlights part 14 |
| Patent application number | Title | Published |
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| 20130112968 | SEMICONDUCTOR DEVICE - A semiconductor device which achieves miniaturization with favorable characteristics maintained is provided. In addition, a miniaturized semiconductor device is provided with high yield. In a semiconductor device including an oxide semiconductor, the contact resistance between the oxide semiconductor and the source electrode or the drain electrode is reduced with miniaturization advanced. Specifically, an oxide semiconductor film is processed to be an island-shaped oxide semiconductor film whose side surface has a tapered shape. Further, the side surface has a taper angle greater than or equal to 1° and less than 10°, and at least part of the source electrode and the drain electrode is in contact with the side surfaces of the oxide semiconductor film. With such a structure, the contact region of the oxide semiconductor film and the source electrode or the drain electrode is increased, whereby the contact resistance is reduced. | 2013-05-09 |
| 20130112969 | METHOD OF MANUFACTURING P-TYPE ZNO NANOWIRES AND METHOD OF MANUFACTURING ENERGY CONVERSION DEVICE - A method of manufacturing silver (Ag)-doped zinc oxide (ZnO) nanowires and a method of manufacturing an energy conversion device are provided. In the method of manufacturing Ag-doped ZnO nanowires, the Ag-doped nanowires are grown by a low temperature hydrothermal synthesis method using a Ag-containing aqueous solution. | 2013-05-09 |
| 20130112970 | THIN FILM TRANSISTOR SUBSTRATE AND FABRICATION METHOD FOR THE SAME - A TFT substrate ( | 2013-05-09 |
| 20130112971 | COMPOSITE OXIDE SINTERED BODY AND SPUTTERING TARGET COMPRISING SAME - A composite oxide sintered body includes In, Zn, and Sn, and has a relative density of 90% or more, an average crystal grain size of 10 μm or less, and a bulk resistance of 30 mΩcm or less, the number of tin oxide aggregate particles having a diameter of 10 μm or more being 2.5 or less per mm | 2013-05-09 |
| 20130112972 | THIN-FILM TRANSISTOR - Making it possible to improve adhesion between the semiconductor layer and the electrodes, realize high-speed operation of the thin-film transistor by enhancing ohmic contact between these members, reliably prevent oxidation of the electrode surfaces, and realize an electrode fabrication process with few processing steps. The thin-film transistor | 2013-05-09 |
| 20130112973 | PRECURSOR COMPOSITION AND METHOD FOR FORMING AMORPHOUS CONDUCTIVE OXIDE FILM - The present invention provides a precursor composition for forming a conductive oxide film having high conductivity and a stable amorphous structure maintained even after heated at high temperature by a simple liquid phase process. The precursor composition of the present invention contains at least one selected from the group consisting of carboxylates, nitrates and sulfates of lanthanoids (but, except for cerium); at least one selected from the group consisting of carboxylates, nitrosyl carboxylates, nitrosyl nitrates and nitrosyl sulfates of ruthenium, iridium or rhodium; and a solvent containing at least one selected from the group consisting of carboxylic acids, alcohols and ketones. | 2013-05-09 |
| 20130112974 | METHOD FOR DETERMINING THE LOCAL STRESS INDUCED IN A SEMICONDUCTOR MATERIAL WAFER BY THROUGH VIAS - A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer. | 2013-05-09 |
| 20130112975 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT EMITTING DISPLAY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A TFT array substrate including: a thin-film transistor including an active layer, gate, source and drain electrodes, a first insulation layer between the active layer and the gate electrode, and a second insulation layer between the gate and the source and drain electrodes; a pixel electrode on the first and second insulation layers, and connected to one of the source and drain electrodes; a capacitor including a first electrode on the same layer as the gate electrode, a second electrode formed of the same material as the pixel electrode, a first protection layer on the second electrode, and a second protection layer on the first protection layer; a third insulation layer between the second insulation layer and the pixel electrode, and between the first electrode and the second electrode; and a fourth insulation layer covering the source and drain electrodes and the second protection layer, and exposing the pixel electrode. | 2013-05-09 |
| 20130112976 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT-EMITTING DISPLAY INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A thin-film transistor array substrate is disclosed. In one embodiment, the substrate includes: i) a thin-film transistor including an active layer, and gate, source and drain electrodes, ii) a lower electrode of a capacitor, iii) an upper electrode of the capacitor formed on the lower electrode iv) a first insulation layer between the lower and upper electrodes, and between the active layer and the gate electrode, and having a gap outside the lower electrode. The substrate may further include i) a second insulation layer formed on the first insulation layer and having the same etching surface as the first insulation layer in the gap, ii) a bridge formed of the same material as the source and drain electrodes, and filling a part of the gap and iii) a third insulation layer covering the source and drain electrodes and exposing a pixel electrode. | 2013-05-09 |
| 20130112977 | PIXEL STRUCTURE, ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - The present invention provides a pixel structure including a substrate, a first metal pattern layer, an insulating layer, a second metal pattern layer, a passivation layer, and a conductive protection layer. The substrate has at least one pixel region. The first patterned metal layer is disposed on the substrate, and has a top surface. The insulating layer is disposed on the first patterned metal layer and the substrate, and is in contact with the top surface of the first patterned metal layer. The second patterned metal layer is disposed on the insulating layer in the pixel region, and includes a source and a drain. The passivation layer is disposed on the second patterned metal layer and the insulating layer. A top surface of the source is in contact with the passivation layer, and the conductive protection layer is disposed on the drain. | 2013-05-09 |
| 20130112978 | WIRING STRUCTURE, THIN FILM TRANSISTOR ARRAY SUBSTRATE INCLUDING THE SAME, AND DISPLAY DEVICE - On each of wiring conversion parts connected to a first conductive film and a second conductive film each functioning as a wiring, a first transparent conductive film does not cover an end surface of the second conductive film in proximity to a corner of the first transparent conductive film, and has a portion covering the end surface of the second conductive film on a portion other than the proximity of the corners. A second transparent conductive film as an upper layer of the first transparent conductive film is connected to the first conductive film and the second conductive film, so that the first conductive film and the second conductive film are electrically connected. | 2013-05-09 |
| 20130112979 | FRINGE FIELD SWITCHING LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A fringe field switching (FFS) liquid crystal display (LCD) device which uses an organic insulating layer and consumes less power, in which film quality of an upper layer of a low temperature protective film is changed to improve undercut within a pad portion contact hole, and a method for fabricating the same is provided. | 2013-05-09 |
| 20130112980 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a bright and highly reliable light-emitting device. An anode ( | 2013-05-09 |
| 20130112981 | Semiconductor Device, and Method of Forming the Same - In order to realize a semiconductor device of enhanced TFT characteristics, a semiconductor thin film is selectively irradiated with a laser beam at the step of crystallizing the semiconductor thin film by the irradiation with the laser beam. By way of example, only driver regions ( | 2013-05-09 |
| 20130112982 | METHOD FOR FORMING NANOFIN TRANSISTORS - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin is formed from a crystalline substrate. A first source/drain region is formed in the substrate beneath the fin. A surrounding gate insulator is formed around the fin. A surrounding gate is formed around the fin and separated from the fin by the surrounding gate insulator. A second source/drain region is formed in a top portion of the fin. Various embodiments etch a hole in a layer over the substrate, form sidewall spacers in the hole, form a fin pattern from the sidewall spacers, and etch into the crystalline substrate to form the fin from the substrate using a mask corresponding to the fin pattern. Other aspects are provided herein. | 2013-05-09 |
| 20130112983 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure and a method for manufacturing the same are disclosed. The pixel structure of the present invention is a pixel structure implemented by combining an in-plane switching (IPS) technique and a fringe field switching (FFS) technique. In each pixel structure, two transparent conductive layers are utilized to form a storage capacitor (Cst) such that the capacitance of the storage capacitor can be increased without decreasing an aperture ratio of a display panel, and thereby a feedthrough voltage can be reduced so as to prevent a screen from blinking. | 2013-05-09 |
| 20130112984 | FLEXIBLE DISPLAY APPARATUS - A flexible display apparatus is disclosed. The flexible display apparatus includes: a substrate on which a display unit for displaying an image, a non-display area formed outside the display unit, and at least one pad for inputting an electrical signal to the display unit are located; and a circuit board including circuit terminals to be electrically connected to the at least one pad. A stiffener including a plurality of reinforcement lines that are patterned to reduce or prevent thermal deformation of the substrate is formed on the substrate. | 2013-05-09 |
| 20130112985 | MONOLITHICALLY INTEGRATED VERTICAL JFET AND SCHOTTKY DIODE - An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction. | 2013-05-09 |
| 20130112986 | Gallium Nitride Semiconductor Devices and Method Making Thereof - The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device. | 2013-05-09 |
| 20130112987 | LIGHT EMITTING DIODE AND FABRICATING METHOD THEREOF - A light emitting diode including a GaN substrate, a first type semiconductor layer, a light emitting layer, a second type semiconductor layer, a first electrode, and a second electrode is provided. The GaN substrate has a first surface and a second surface opposite thereto, and the second surface has a plurality of protuberances, the height of the protuberance is h μm and the distribution density of the protuberance on the second surface is d cm | 2013-05-09 |
| 20130112988 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND WAFER - A semiconductor light emitting device includes a first layer including at least one of n-type GaN and n-type AlGaN; a second layer including Mg-containing p-type AlGaN; and a light emitting section provided between the first and second layers. The light emitting section includes barrier layers of Si-containing Al | 2013-05-09 |
| 20130112989 | BROAD-AREA LIGHTING SYSTEMS - In accordance with certain embodiments, illumination systems are formed by aligning light-emitting elements with optical elements and/or disposing light-conversion materials on the light-emitting elements, as well as by providing electrical connectivity to the light-emitting elements | 2013-05-09 |
| 20130112990 | Gallium Nitride Devices with Compositionally-Graded Transition Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of o semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 2013-05-09 |
| 20130112991 | SILICON CARBIDE SCHOTTKY-BARRIER DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n− epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n− epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n− epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer. | 2013-05-09 |
| 20130112992 | HIGH TEMPERATURE TRANSDUCER USING SOI, SILICON CARBIDE OR GALLIUM NITRIDE ELECTRONICS - There is disclosed a high temperature pressure sensing system which includes a SOI, silicon carbide, or gallium nitride Wheatstone bridge including piezoresistors. The bridge provides an output which is applied to an analog to digital converter also fabricated using SOI, silicon carbide, or gallium nitride materials. The output of the analog to digital converter is applied to microprocessor, which microprocessor processes the data or output of the bridge to produce a digital output indicative of bridge value. The microprocessor also receives an output from another analog to digital converter indicative of the temperature of the bridge as monitored by a span resistor coupled to the bridge. The microprocessor has a separate memory coupled thereto which is also fabricated from SOI, silicon carbide, or gallium nitride materials and which memory stores various data indicative of the microprocessor also enabling the microprocessor test and system test to be performed. | 2013-05-09 |
| 20130112993 | SEMICONDUCTOR DEVICE AND WIRING SUBSTRATE - A semiconductor device according to one embodiment of the present invention includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate and having a conductive property, and a semiconductor element mounted on the wiring layer. In the semiconductor device, the insulating substrate is composed of cBN or diamond. | 2013-05-09 |
| 20130112994 | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE - The semiconductor module includes a base and at least one circuit substrate. The at least one circuit substrate has a supporting substrate and a semiconductor element supported by the supporting substrate. The base and/or the supporting substrate has a structure for fitting the at least one circuit substrate with the base. | 2013-05-09 |
| 20130112995 | SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME - An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon. | 2013-05-09 |
| 20130112996 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type. | 2013-05-09 |
| 20130112997 | SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE, AND SOI WAFER - Disclosed is a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate (S) is provided with a first silicon carbide layer ( | 2013-05-09 |
| 20130112998 | SOLID STATE LIGHT EMITTING SEMICONDUCTOR DEVICE - A solid state light emitting semiconductor device including a substrate, a mesa epitaxy stacking structure, an insulating layer, a first type electrode and a second type electrode is provided. The mesa epitaxy stacking structure includes a first type semiconductor layer, an active layer and a second type semiconductor layer arranged in order. A concave area is formed in the middle of the mesa epitaxy stacking structure to expose a portion of the first type semiconductor layer. The insulating layer covers the exposed surface of the first type semiconductor layer around the mesa epitaxy structure, sidewalls of the mesa epitaxy stacking structure and a portion of surface of the second type semiconductor layer. The first type electrode is located on the exposed first type semiconductor layer in the concave area, and is surrounded by the second type electrode located on the insulating layer around the mesa epitaxy stacking structure. | 2013-05-09 |
| 20130112999 | LIGHT EMITTING DIODE AND LIGHT EMITTING DIODE LAMP - A light emitting diode is provided by the present invention which includes a pn junction-type light emitting unit having a light emitting layer ( | 2013-05-09 |
| 20130113000 | DISPLAY SUBSTRATES AND METHODS OF FABRICATING THE SAME - Display substrates are disclosed. In one aspect, display substrates include a first signal line, a second signal line, a first detour signal line and a second detour signal line. The first signal line includes a first region and a pair of second regions disposed on opposite sides of the first region. The pair of second regions are spaced apart from the first region. The second signal line crosses the first signal line. The second signal line includes a third region and a pair of fourth regions disposed on opposite sides of the third region. The pair of fourth regions are spaced apart from the third region. The first detour signal line electrically connects the pair of second regions to each other. The second detour signal line electrically connects the pair of fourth regions to each other. Related methods are also disclosed. | 2013-05-09 |
| 20130113001 | LED PACKAGE MODULE - An LED package module includes a circuit board, a metal board, a plurality of chips, a plurality of wires and a molding component. The metal board directly covers the whole upper surface of the circuit board, wherein the metal board is provided with a plurality of chip-mounting pads and a plurality of openings arranged adjacent to the chip-mounting pads so as to expose the wiring area of the circuit board. The chips are respectively arranged on each of the chip-mounting pads. The wires electrically connect chips and the wiring area of the circuit board. The molding component respectively covers each chip, wires and the wiring area. | 2013-05-09 |
| 20130113002 | LOW COST MOUNTING OF LEDs IN TL-RETROFIT TUBES - This invention relates to a lighting device comprising a light transmissive light outlet unit ( | 2013-05-09 |
| 20130113003 | LUMINESCENT LIGHT SOURCE AND DISPLAY PANEL HAVING THE SAME - A luminescent light source including a blue light emitting diode (LED) chip, a red LED chip, and a wavelength converting material is provided. The blue LED chip and the red LED chip respectively emit a first light and a second light. A ratio of peak intensity of the second light to peak intensity of the first light ranges from 0.36 to 0.56. The wavelength converting material is disposed around the blue LED chip or the red LED chip and emits a third light. A wavelength of the third light ranges from a wavelength of the first light to a wavelength of the second light. | 2013-05-09 |
| 20130113004 | LIGHT-EMITTING DEVICE WITH HEAD-TO-TAIL P-TYPE AND N-TYPE TRANSISTORS - A light-emitting microelectronic device including a first N-type transistor (T | 2013-05-09 |
| 20130113005 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION METHOD THEREOF - A semiconductor light emitting device and a fabrication method thereof are provided. The semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A reflective structure is formed on the light emitting structure and includes a nano-rod layer comprised of a plurality of nano-rods and air filling space between the plurality of nano-rods and a reflective metal layer formed on the nano-rod layer. | 2013-05-09 |
| 20130113006 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION METHOD THEREOF - A semiconductor light emitting device include an n-type semiconductor layer, an active layer disposed on the n-type semiconductor layer, and a first p-type semiconductor layer disposed on the active layer. The first p-type semiconductor layer has an uneven structure formed on a surface thereof. A second p-type semiconductor layer has an impurity concentration higher than that of the first p-type semiconductor layer. The second p-type semiconductor layer is disposed on the first p-type semiconductor layer and has an uneven structure formed on a surface thereof. A reflective metal layer is formed on the second p-type semiconductor layer. | 2013-05-09 |
| 20130113007 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device including a light emitting structure including a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, a first electrode layer, a second electrode layer disposed between the light emitting structure and the first electrode layer, and an insulating layer surrounding the edge of the second electrode layer under the second conductive type semiconductor layer, the insulating layer being disposed between the second electrode layer and the first electrode layer, wherein the first electrode layer passes through the second electrode layer, the second conductive type semiconductor layer and the active layer, and contacts the first conductive type semiconductor layer, and the second electrode layer comprises a plurality of first reflective layers that contact the second conductive type semiconductor layer and are spaced from one another by a predetermined distance. | 2013-05-09 |
| 20130113008 | WAVELENGTH CONVERSION SHEET FILLED WITH LARGE AMOUNT OF PHOSPHOR, METHOD OF PRODUCING LIGHT EMITTING SEMICONDUCTOR DEVICE USING THE SHEET, AND LIGHT EMITTING SEMICONDUCTOR DEVICE - A wavelength conversion sheet filled with a large amount of phosphor, enabling the phosphor to be easily dispersed uniformly and in a large amount near the surface of an LED element. Specifically, the sheet includes: a layer formed from a heat-curable resin composition, which contains 100 parts by mass of a resin component and 100 to 2,000 parts by mass of a particulate phosphor in which the proportion of particles having a sphericity of 0.7 to 1.0 is not less than 60% of all the particles, and which exists in a plastic solid or semisolid state in an uncured state at normal temperature, wherein the average particle diameter of the phosphor is not more than 60% of the thickness of the layer formed from the heat-curable resin composition, and the maximum particle diameter thereof is not more than 90% thereof. | 2013-05-09 |
| 20130113009 | METHOD OF MANUFACTURING LIGHT EMITTING DEVICE PACKAGE - A method of manufacturing a light emitting device (LED) package includes forming a reflector using nano-imprinting to increase an intensity of light extracted toward an external environment by increasing an angle of a reflector. | 2013-05-09 |
| 20130113010 | Optoelectronic Component and Method for Producing an Optoelectronic Component - An optoelectronic component comprising an optoelectronic semiconductor chip ( | 2013-05-09 |
| 20130113011 | FULL SPECTRUM SOLID STATE WHITE LIGHT SOURCE, METHOD FOR MANUFACTURING AND APPLICATIONS - A method of manufacturing a down-conversion substrate for use in a light system includes forming a first crystallography layer including one or more phosphor materials and, optionally, applying at least one activator to the crystallography layer, heating the crystallography layer at high temperature to promote crystal growth in the crystallography layer, and drawing out the crystallography layer and allowing the crystallography layer to cool to form the down-conversion substrate. A light system includes an excitation source for emitting short wavelength primary emissions; and a down-conversion substrate disposed in the path of at least some of the primary emissions from the excitation source to convert at least a portion of the primary emissions into longer-wavelength secondary emissions, wherein the substrate includes one or more crystallography layers, wherein each crystallography layer includes one or more phosphor materials, and optionally at least one activator. Down-converted secondary light may be produced by the system. | 2013-05-09 |
| 20130113012 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT, LAMP, ELECTRONIC DEVICE AND MACHINE - A semiconductor light-emitting element ( | 2013-05-09 |
| 20130113013 | METAL FOIL LAMINATE, SUBSTRATE FOR MOUNTING LED, AND LIGHT SOURCE DEVICE - Provided is a metal foil laminate that: has heat resistance; has high reflectance in the visible light range; has little decrease in reflectance in environments with a high-temperature thermal load; is compatible with large surface areas; and can be used for printed circuit boards for mounting LEDs that have excellent adhesion with metals. The metal foil laminate is characterized in that: a laminate has metal foil on at least one side of a resin layer (A) containing a polyorganosiloxane and an inorganic filler; the 90° peel strength between said resin layer (A) and said metal foil is at least 0.95 kN/m, and the mean reflectance at wavelengths of 400 to 800 nm on the surface that is exposed when the resin layer (A) is exposed by peeling and removing said metal foil is at least 80%; and the decrease in the reflectance at a wavelength of 470 nm after being treated with heat for 10 minutes at 260° C. is not more than 5%. | 2013-05-09 |
| 20130113014 | OPTOELECTRONIC DEVICE - The application provides an optoelectronic device structure, comprising a semiconductor stack, comprising a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; a first electrode electrically connecting with the first conductivity type semiconductor layer, and further comprising a first extension electrode; a second electrode electrically connecting with the second conductivity type semiconductor layer; and a plurality of electrical restraint contact areas between the semiconductor stack and the first extension electrode, wherein the plurality of electrical restraint contact areas is distributed in a variable interval. | 2013-05-09 |
| 20130113015 | Substrate, Light Emitting Device and Method for Manufacturing Substrate - A substrate includes a first lead frame, a second lead frame, and a resin layer. The first lead frame includes a heat sink and a plurality of electrodes for external connection. The second lead frame is laminated on the first lead frame and includes a plurality of wirings for mounting light emitting elements. The resin layer is filled between the first lead frame and the second lead frame. The plurality of wirings are arranged above the heat sink. The plurality of electrodes and part of the plurality of wirings are joined with each other. | 2013-05-09 |
| 20130113016 | PACKAGING PHOTON BUILDING BLOCKS WITH TOP SIDE CONNECTIONS AND INTERCONNECT STRUCTURE - Standardized photon building blocks are used to make both discrete light emitters as well as array products. Each photon building block has one or more LED chips mounted on a substrate. No electrical conductors pass between the top and bottom surfaces of the substrate. The photon building blocks are supported by an interconnect structure that is attached to a heat sink. Landing pads on the top surface of the substrate of each photon building block are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors on the interconnect structure are electrically coupled to the LED dice in the photon building blocks through the contact pads and landing pads. The bottom surface of the interconnect structure is coplanar with the bottom surfaces of the substrates of the photon building blocks. | 2013-05-09 |
| 20130113017 | ELECTRONIC DEVICE FOR PROTECTING FROM ELECTROSTATIC DISCHARGE - A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor. | 2013-05-09 |
| 20130113018 | FIELD EFFECT TRANSISTOR - A first group III nitride semiconductor layer has a low carbon concentration region having a carbon concentration of less than 1×10 | 2013-05-09 |
| 20130113019 | SEMICONDUCTOR DEVICE WITH REDUCED THRESHOLD VARIABILITY HAVING A THRESHOLD ADJUSTING SEMICONDUCTOR ALLOY IN THE DEVICE ACTIVE REGION - Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length. Additionally, the disclosed semiconductor device includes a gate electrode structure that is positioned above the threshold adjusting semiconductor alloy material layer, the gate electrode structure including a high-k dielectric material and a metal-containing electrode material formed above the high-k dielectric material. | 2013-05-09 |
| 20130113020 | SIGE HBT AND METHOD OF MANUFACTURING THE SAME - A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed. | 2013-05-09 |
| 20130113021 | SIGE HBT HAVING DEEP PSEUDO BURIED LAYER AND MANUFACTURING METHOD THEREOF - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) having a deep pseudo buried layer is disclosed. The SiGe HBT includes isolation structures formed in trenches, first pseudo buried layers and second pseudo buried layers, and a collector region. The first pseudo buried layers are formed under the respective trenches and the second pseudo buried layers are formed under the first pseudo buried layers, with each first pseudo buried layer vertically contacting with a second pseudo buried layer. The second pseudo buried layers are laterally connected to each other, and the collector region is surrounded by the trenches, the first pseudo buried layers and the second pseudo buried layers. The cross section of each of the trenches has a regular trapezoidal shape, namely, each trench's width of its top is smaller than that of its bottom. A manufacturing method of the SiGe HBT is also disclosed. | 2013-05-09 |
| 20130113022 | SIGE HBT AND MANUFACTURING METHOD THEREOF - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, which includes: two isolation structures each being formed in a trench; a set of three or more pseudo buried layers formed under each trench with every adjacent two pseudo buried layers of the set being vertically contacted with each other; and a collector region. In this design, the lowermost pseudo buried layers of the two sets are laterally in contact with each other, and the collector region is surrounded by the two isolation structures and the two sets of pseudo buried layers. As the breakdown voltage of a SiGe HBT according to the present invention is determined by the distance between an uppermost pseudo buried layer and the edge of an active region, SiGe HBTs having different breakdown voltages can be achieved. A manufacturing method of the SiGe HBT is also disclosed. | 2013-05-09 |
| 20130113023 | Multi-Fin Device by Self-Aligned Castle Fin Formation - The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W | 2013-05-09 |
| 20130113024 | SOLID-STATE IMAGE PICKUP DEVICE, IMAGE PICKUP SYSTEM INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SAME - A solid-state image pickup device including a photoelectric conversion element, a floating diffusion, and an element isolation region that are disposed above a first semiconductor region has a second semiconductor region of a first conductivity type disposed on the first semiconductor region. An interface between the first semiconductor region and a portion of the second semiconductor region corresponding to the photoelectric conversion element is located at a first depth, whereas the interface between the first semiconductor region and a portion of the second semiconductor region disposed under the element isolation region and the floating diffusion is located at a second depth smaller than the first depth. | 2013-05-09 |
| 20130113025 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor device structure and a method for manufacturing the same. The method comprises: providing a semiconductor substrate, forming a first insulating layer on the surface of the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a stripe-type trench embedded in the first insulating layer and the semiconductor substrate; forming a channel region in the trench; forming a gate stack line on the channel region and source/drain regions on opposite sides of the channel region. Embodiments of the present invention are applicable to manufacture of semiconductor devices. | 2013-05-09 |
| 20130113026 | FIN FIELD EFFECT TRANSISTOR GATE OXIDE - The present disclosure provides for methods of fabricating a semiconductor device and such a device. A method includes providing a substrate including at least two isolation features, forming a fin substrate above the substrate and between the at least two isolation features, forming a silicon liner over the fin substrate, and oxidizing the silicon liner to form a silicon oxide liner over the fin substrate. | 2013-05-09 |
| 20130113027 | Metal Oxide Semiconductor Transistor and Manufacturing Method Thereof - The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface. The present invention further provides a manufacturing method of the MOS transistor. | 2013-05-09 |
| 20130113028 | SEMICONDUCTOR DEVICE AND FIELD EFFECT TRANSISTOR - A semiconductor device comprises a substrate | 2013-05-09 |
| 20130113029 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHODS OF FABRICATING THE SAME - A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between | 2013-05-09 |
| 20130113030 | SEMICONDUCTOR DEVICE - The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well. | 2013-05-09 |
| 20130113031 | KINK POLY STRUCTURE FOR IMPROVING RANDOM SINGLE BIT FAILURE - A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure. | 2013-05-09 |
| 20130113032 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device includes a substrate, a conductive layer provided on a major surface of the substrate, a stacked body, a memory film, and a channel body. The stacked body includes multiple insulating layers alternately stacked with multiple electrode layers on the conductive layer. The memory film includes a charge storage film provided on side walls of holes made to pierce the stacked body. The channel body includes a pair of columnar portions and a linking portion. The pair of columnar portions is provided on an inner side of the memory film inside the holes. The linking portion is provided inside the conductive layer to link lower ends of the pair of columnar portions. The electrode layers are tilted with respect to the major surface of the substrate. The columnar portions of the channel body and the memory film pierce the tilted portion of the electrode layers. | 2013-05-09 |
| 20130113033 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers. | 2013-05-09 |
| 20130113034 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, PRODUCTION METHOD FOR SAME, AND CHARGE STORAGE FILM - A non-volatile semiconductor memory device comprises a tunnel insulating film on a semiconductor substrate, a charge storage film on the tunnel insulating film, a blocking insulating film on the charge storage film, a control gate electrode arranged on the blocking insulating film, and source/drain regions formed on the semiconductor substrate on the both sides of the control gate electrode, that the charge storage film is a silicon nitride film produced according to the catalytic chemical vapor deposition technique and that the ratio between the constituent elements: N/Si falls within the range of from 1.2 to 1.4. | 2013-05-09 |
| 20130113035 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force. | 2013-05-09 |
| 20130113036 | Transistor Assembly as an ESD Protection Measure | 2013-05-09 |
| 20130113037 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact. | 2013-05-09 |
| 20130113038 | TRENCH MOSFET WITH SPLIT TRENCHED GATE STRUCTURES IN CELL CORNERS FOR GATE CHARGE REDUCTION - A trench MOSFET with closed cells having split trenched gates structure in trenched gates intersection area in cell corner is disclosed. The invented split trenched gates structure comprises an insulation layer between said split trenched gates with thick thermal oxide layer in center portion of the trenched gates intersection area, therefore further reducing Qgd of the trench MOSFET without increasing additional Rds. | 2013-05-09 |
| 20130113039 | SEMICONDUCTOR DEVICE - A semiconductor device provides a MOSFET having first and second regions. In the first region, a plurality of unit cells of the MOSFET device are provided. At the end of the plurality of the unit cells, a termination cell is provided. An n type layer underlies the unit cells, between the unit cells and an underlying electrode. In the unit cell region, this n doped layer is dually doped with impurities at two different densities, whereas, adjacent the termination cell, a different paradigm is provided. In one aspect, only one of the two n doped layers extends along a side of the termination cell. In a second aspect, the termination unit is in contact with an oppositely doped layer as compared to the impurities in the dual doped layer. In this way, breakdown voltage may be maintained while on-resistance is simultaneously reduced. | 2013-05-09 |
| 20130113040 | Semiconductor Device Comprising Transistor Structures and Methods for Forming Same - A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described. | 2013-05-09 |
| 20130113041 | SEMICONDUCTOR TRANSISTOR DEVICE WITH OPTIMIZED DOPANT PROFILE - Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel. | 2013-05-09 |
| 20130113042 | MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin. | 2013-05-09 |
| 20130113043 | RADIATION HARDENED MEMORY CELL AND DESIGN STRUCTURES - A radiation hardened static memory cell, methods of manufacture and design structures are provided. The method includes forming one or more first gate stacks and second gate stacks on a substrate. The method further includes providing a shallow implant process for the one or more first gate stacks such that diffusion regions of the one or more first gate stacks are non-butted junction regions. The method further includes providing a deep implant process for the one or more second gates stack such that diffusions regions of the one or more second gate stacks are butted junction regions. | 2013-05-09 |
| 20130113044 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed. | 2013-05-09 |
| 20130113045 | ELECTROSTATIC DISCHARGE (ESD) DEVICE AND SEMICONDUCTOR STRUCTURE - An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs. | 2013-05-09 |
| 20130113046 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - Semiconductor devices and methods of forming the same are provided. The semiconductor device may include a semiconductor element disposed on a substrate and including an insulating layer and a gate electrode, a doped region having a first conductivity-type on the substrate, a conductive interconnection electrically connected to the gate electrode, and a first contact plug having a second conductivity-type and electrically connecting the conductive interconnection and the doped region to each other and constituting a Zeiler diode by junction with the doped region. | 2013-05-09 |
| 20130113047 | MOSFET STRUCTURE WITH T-SHAPED EPITAXIAL SILICON CHANNEL - A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized. | 2013-05-09 |
| 20130113048 | HIGH VOLTAGE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively. | 2013-05-09 |
| 20130113049 | FUSE CIRCUIT FOR FINAL TEST TRIMMING OF INTEGRATED CIRCUIT CHIP - The present invention discloses a fuse circuit for final test trimming of an integrated circuit (IC) chip. The fuse circuit includes at least one electrical fuse, at least one control switch corresponding to the electrical fuse, and a resistant device. The electrical fuse is connected with the control switch in series between a predetermined pin and a grounding pin. The control switch receives a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse. The resistant device is coupled between a bulk terminal and a source terminal to increase a resistance of a parasitic channel, such that an electrostatic discharge (ESD) protection is enhanced, and errors of final test trimming of an IC chip are avoided. | 2013-05-09 |
| 20130113050 | BLANKET SHORT CHANNEL ROLL-UP IMPLANT WITH NON-ANGLED LONG CHANNEL COMPENSATING IMPLANT THROUGH PATTERNED OPENING - A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers. | 2013-05-09 |
| 20130113051 | HIGH PERFORMANCE LOW POWER BULK FET DEVICE AND METHOD OF MANUFACTURE - A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer. | 2013-05-09 |
| 20130113052 | METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The MOSFET includes a substrate, a well region formed in the substrate, a shallow channel layer, a channel, a gate oxide layer, a gate region, a source region, and a drain region. The shallow channel layer is formed on a portion of the well region and includes a first shallow channel region and a second shallow channel region. The channel is arranged between the first shallow channel region and the second shallow channel region and connects the first shallow channel region and the second shallow channel region. Further, the gate oxide layer is formed on a portion of the well region between the first shallow channel region and the second shallow channel region and includes a first gate oxide region and a second gate oxide region arranged on different sides of the channel. The gate region is formed on the channel and the gate oxide layer; the source region is formed in the first shallow channel region and vertically extends into the well region under the first shallow channel region; and the drain region is formed in the second shallow channel region and vertically extends into the well region under the second shallow channel region. | 2013-05-09 |
| 20130113053 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure. | 2013-05-09 |
| 20130113054 | SEMICONDUCTOR SENSOR DEVICE AND METHOD OF PACKAGING SAME - A packaged semiconductor device with a cavity formed by a cover or lid mounted to a substrate. The lid covers one or more semiconductor sensor dies mounted on the substrate. The dies are coated with a gel or spray on coating, and the lid is encapsulated with a mold compound. A hole or passage may be formed through the cover and mold compound to expose the sensor dies to selected environmental conditions. | 2013-05-09 |
| 20130113055 | SENSOR DEVICE MANUFACTURING METHOD AND SENSOR DEVICE - A method for manufacturing a sensor device is provided. The method prevents corrosion of metal electrodes of a sensor due to outside air with high humidity and preventing the occurrence of warpage of the sensor due to resin sealing of the sensor, thereby reducing the influence on sensor characteristics, and provides the sensor device. The method includes arranging a sensor on a substrate, the sensor having a fixed part, a movable part positioned inside the fixed part, a flexible part connecting the fixed part and the movable part, and a plurality of metal electrodes, electrically connecting the plurality of metal electrodes of the sensor and a plurality of terminals of the substrate with bonding wires, and covering portions of the plurality of metal electrodes of the sensor connected to the bonding wires with a resin so that a part of the bonding wires between the plurality of metal electrodes and the plurality of terminals is exposed. | 2013-05-09 |
| 20130113056 | DYNAMIC QUANTITY SENSOR - The present invention provides a dynamic quantity device which reduces stress received by a sensor due to resin packaging and reduces variation in sensor characteristics due to stress. The dynamic quantity sensor includes a semiconductor substrate including a fixing part and a flexible part and a movable part positioned on an interior side of the fixing part, and a cap component configured to cover the flexible part and the movable part, wherein the fixing part includes an interior frame configured to enclose the flexible part and the movable part and an exterior part positioned on a periphery of the interior frame, a slit configured to divide the interior frame and the exterior frame, and a linking part configured to link the interior frame and the exterior frame. | 2013-05-09 |
| 20130113057 | FORCE SENSING SHEET - A force sensing array includes multiple layers of material that are arranged to define an elastically stretchable sensing sheet. The sensing sheet may be placed underneath a patient to detect interface forces or pressures between the patient and the support structure that the patient is positioned on. The force sensing array includes a plurality of force sensors. The force sensors are defined where a row conductor and a column conductor approach each other on opposite sides of a force sensing material, such as a piezoresistive material. In order to reduce electrical cross talk between the plurality of sensors, a semiconductive material is included adjacent the force sensing material to create a PN junction with the force sensing material. This PN junction acts as a diode, limiting current flow to essentially one direction, which, in turn, reduces cross talk between the multiple sensors. | 2013-05-09 |
| 20130113058 | MAGNETIC MEMORY ELEMENT, MAGNETIC MEMORY AND MANUFACTURING METHOD OF THE SAME - A magnetic memory element includes: a first magnetization free layer configured to be composed of ferromagnetic material with perpendicular magnetic anisotropy; a reference layer configured to be provided near the first magnetization free layer; a non-magnetic layer configured to be provided adjacent to the reference layer; and a step formation layer configured to be provided under the first magnetization free layer. The first magnetization free layer includes: a first magnetization fixed region of which magnetization is fixed, a second magnetization fixed region of which magnetization is fixed, and a magnetization free region configured to be connected with the first magnetization fixed region and the second magnetization fixed region. The first magnetization free layer has at least one of a step, a groove and a protrusion inside. | 2013-05-09 |
| 20130113059 | PHOTOVOLTAIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A photovoltaic device includes a semiconductor substrate; an amorphous first conductive semiconductor layer on a first region of a first surface of the semiconductor substrate and containing a first impurity; an amorphous second conductive semiconductor layer on a second region of the first surface of the semiconductor substrate and containing a second impurity; and a gap passivation layer located between the first region and the second region on the semiconductor substrate, wherein the first conductive semiconductor layer is also on the gap passivation layer. | 2013-05-09 |
| 20130113060 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device including unit pixel cells, each having a photoelectric conversion film and a pixel electrode which are formed above a silicon substrate, an amplification transistor which is formed on the silicon substrate and outputs a voltage according to a potential of the pixel electrode, and a reset transistor which is formed on the silicon substrate and resets a potential of a gate electrode of the amplification transistor, the imaging device including a vertical signal line which is disposed correspondingly to a column of the unit pixel cells, and transmits a voltage of the unit pixel cells of the corresponding column, and a vertical scanning unit which selects a row of the unit pixel cells having a voltage to be outputted to the vertical signal line, wherein the vertical signal line is located below the pixel electrode of the unit pixel cells corresponding to the vertical signal line. | 2013-05-09 |
| 20130113061 | IMAGE SENSOR TRENCH ISOLATION WITH CONFORMAL DOPING - Provided is a semiconductor image sensor device. The image sensor device includes a substrate. The image sensor device includes a first pixel and a second pixel disposed in the substrate. The first and second pixels are neighboring pixels. The image sensor device includes an isolation structure disposed in the substrate and between the first and second pixels. The image sensor device includes a doped isolation device disposed in the substrate and between the first and second pixels. The doped isolation device surrounds the isolation structure in a conformal manner. | 2013-05-09 |
| 20130113062 | Lens Holder, Method for Manufacturing the Same and Image Capturing Device Thereof - A lens holder, a method for manufacturing the same and an image capturing device thereof. The lens holder comprises a hollow substrate, a filter, a hollow elastomer and a photodetector module. The hollow substrate comprises a photodetector accommodating space and a plurality of fixing mechanisms disposed around the photodetector accommodating space. The filter is disposed inside the photodetector accommodating space and covers a hollow section of the hollow substrate. The hollow elastomer is disposed on the filter. The photodetector module is disposed on the hollow elastomer and comprises a photodetector and a substrate. The substrate can be fixed onto the hollow substrate through the plurality of fixing mechanisms. Wherein, a plurality of protrusion parts extends from the hollow elastomer for holding the substrate. The aforementioned lens holder structure can be used to perform a tilt alignment of the photodetector efficiently. | 2013-05-09 |
| 20130113063 | HIGH BANDWIDTH, MONOLITHIC TRAVELING WAVE PHOTODIODE ARRAY - The monolithic application of a high speed TWPDA with impedance matching. Use of the high speed monolithic TWPDA will allow for more efficient transfer of optical signals within analog circuits and over distances. | 2013-05-09 |
| 20130113064 | PHOTODETECTOR, OPTICAL COMMUNICATION DEVICE EQUIPPED WITH THE SAME, METHOD FOR MAKING OF PHOTODETECTOR, AND METHOD FOR MAKING OF OPTICAL COMMUNICATION DEVICE - The present invention provides a photodetector which solves the problem of low sensitivity of a photodetector, an optical communication device equipped with the same, and a method for making the photodetector, and a method for making the optical communication device. The photodetector includes a substrate, a lower cladding layer arranged on the substrate, an optical waveguide arranged on the lower cladding layer, an intermediate layer arranged on the optical waveguide, a optical absorption layer arranged on the intermediate layer, a pair of electrodes arranged on the optical absorption layer, and wherein the optical absorption layer includes a IV-group or III-V-group single-crystal semiconductor, and the optical absorption layer absorbs an optical signal propagating through the optical waveguide. | 2013-05-09 |
| 20130113065 | PAD DESIGN FOR CIRCUIT UNDER PAD IN SEMICONDUCTOR DEVICES - Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via. | 2013-05-09 |
| 20130113066 | UTBB CMOS IMAGER - An image sensor device comprising at least one transistor lying on a semiconductor-on-insulator substrate, the substrate comprising a thin semi-conducting layer wherein a channel area of said transistor is made, an insulating layer separating the thin semi-conducting layer with a semi-conducting support layer, the device being characterized in that the semi-conducting support layer comprises at least one photosensitive area including at least one P-doped region and at least one N-doped region forming a junction provided facing the channel area of said transistor. | 2013-05-09 |
| 20130113067 | THERMAL WARP COMPENSATION IC PACKAGE - An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments, the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art. | 2013-05-09 |
